Commit | Line | Data |
---|---|---|
b8422dcb LC |
1 | /* |
2 | * This file is part of wl18xx | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __WL18XX_ACX_H__ | |
23 | #define __WL18XX_ACX_H__ | |
24 | ||
25 | #include "../wlcore/wlcore.h" | |
8c0ea102 | 26 | #include "../wlcore/acx.h" |
b8422dcb | 27 | |
f74ea74b | 28 | enum { |
b6acb4e0 EP |
29 | ACX_NS_IPV6_FILTER = 0x0050, |
30 | ACX_PEER_HT_OPERATION_MODE_CFG = 0x0051, | |
31 | ACX_CSUM_CONFIG = 0x0052, | |
32 | ACX_SIM_CONFIG = 0x0053, | |
33 | ACX_CLEAR_STATISTICS = 0x0054, | |
34 | ACX_AUTO_RX_STREAMING = 0x0055, | |
6d5a748d RA |
35 | ACX_PEER_CAP = 0x0056, |
36 | ACX_INTERRUPT_NOTIFY = 0x0057, | |
e2f1e50f | 37 | ACX_RX_BA_FILTER = 0x0058, |
d1c54096 GM |
38 | ACX_AP_SLEEP_CFG = 0x0059, |
39 | ACX_DYNAMIC_TRACES_CFG = 0x005A, | |
f74ea74b LC |
40 | }; |
41 | ||
b8422dcb LC |
42 | /* numbers of bits the length field takes (add 1 for the actual number) */ |
43 | #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15 | |
44 | ||
e59bec16 LC |
45 | #define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ |
46 | WL1271_ACX_INTR_INIT_COMPLETE | \ | |
47 | WL1271_ACX_INTR_EVENT_A | \ | |
48 | WL1271_ACX_INTR_EVENT_B | \ | |
49 | WL1271_ACX_INTR_CMD_COMPLETE | \ | |
50 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
51 | WL1271_ACX_INTR_DATA | \ | |
52 | WL1271_ACX_SW_INTR_WATCHDOG) | |
53 | ||
54 | #define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ | |
55 | WL1271_ACX_INTR_EVENT_A | \ | |
56 | WL1271_ACX_INTR_EVENT_B | \ | |
57 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
58 | WL1271_ACX_INTR_DATA | \ | |
59 | WL1271_ACX_SW_INTR_WATCHDOG) | |
f5755fe9 | 60 | |
b8422dcb LC |
61 | struct wl18xx_acx_host_config_bitmap { |
62 | struct acx_header header; | |
63 | ||
64 | __le32 host_cfg_bitmap; | |
65 | ||
66 | __le32 host_sdio_block_size; | |
67 | ||
68 | /* extra mem blocks per frame in TX. */ | |
69 | __le32 extra_mem_blocks; | |
70 | ||
71 | /* | |
72 | * number of bits of the length field in the first TX word | |
73 | * (up to 15 - for using the entire 16 bits). | |
74 | */ | |
75 | __le32 length_field_size; | |
76 | ||
77 | } __packed; | |
78 | ||
2fc28de5 AN |
79 | enum { |
80 | CHECKSUM_OFFLOAD_DISABLED = 0, | |
81 | CHECKSUM_OFFLOAD_ENABLED = 1, | |
82 | CHECKSUM_OFFLOAD_FAKE_RX = 2, | |
83 | CHECKSUM_OFFLOAD_INVALID = 0xFF | |
84 | }; | |
85 | ||
86 | struct wl18xx_acx_checksum_state { | |
87 | struct acx_header header; | |
88 | ||
89 | /* enum acx_checksum_state */ | |
90 | u8 checksum_state; | |
91 | u8 pad[3]; | |
92 | } __packed; | |
93 | ||
8dd8e53c IR |
94 | |
95 | struct wl18xx_acx_error_stats { | |
c48276cb EP |
96 | u32 error_frame_non_ctrl; |
97 | u32 error_frame_ctrl; | |
98 | u32 error_frame_during_protection; | |
99 | u32 null_frame_tx_start; | |
100 | u32 null_frame_cts_start; | |
101 | u32 bar_retry; | |
102 | u32 num_frame_cts_nul_flid; | |
103 | u32 tx_abort_failure; | |
104 | u32 tx_resume_failure; | |
105 | u32 rx_cmplt_db_overflow_cnt; | |
106 | u32 elp_while_rx_exch; | |
107 | u32 elp_while_tx_exch; | |
108 | u32 elp_while_tx; | |
109 | u32 elp_while_nvic_pending; | |
110 | u32 rx_excessive_frame_len; | |
111 | u32 burst_mismatch; | |
112 | u32 tbc_exch_mismatch; | |
8dd8e53c IR |
113 | } __packed; |
114 | ||
c48276cb | 115 | #define NUM_OF_RATES_INDEXES 30 |
8c0ea102 | 116 | struct wl18xx_acx_tx_stats { |
8dd8e53c IR |
117 | u32 tx_prepared_descs; |
118 | u32 tx_cmplt; | |
8c0ea102 LC |
119 | u32 tx_template_prepared; |
120 | u32 tx_data_prepared; | |
121 | u32 tx_template_programmed; | |
122 | u32 tx_data_programmed; | |
123 | u32 tx_burst_programmed; | |
124 | u32 tx_starts; | |
c48276cb | 125 | u32 tx_stop; |
8c0ea102 LC |
126 | u32 tx_start_templates; |
127 | u32 tx_start_int_templates; | |
128 | u32 tx_start_fw_gen; | |
129 | u32 tx_start_data; | |
130 | u32 tx_start_null_frame; | |
131 | u32 tx_exch; | |
132 | u32 tx_retry_template; | |
133 | u32 tx_retry_data; | |
c48276cb | 134 | u32 tx_retry_per_rate[NUM_OF_RATES_INDEXES]; |
8c0ea102 LC |
135 | u32 tx_exch_pending; |
136 | u32 tx_exch_expiry; | |
8c0ea102 LC |
137 | u32 tx_done_template; |
138 | u32 tx_done_data; | |
139 | u32 tx_done_int_template; | |
c48276cb EP |
140 | u32 tx_cfe1; |
141 | u32 tx_cfe2; | |
c5d94169 LC |
142 | u32 frag_called; |
143 | u32 frag_mpdu_alloc_failed; | |
144 | u32 frag_init_called; | |
145 | u32 frag_in_process_called; | |
146 | u32 frag_tkip_called; | |
147 | u32 frag_key_not_found; | |
148 | u32 frag_need_fragmentation; | |
149 | u32 frag_bad_mblk_num; | |
150 | u32 frag_failed; | |
151 | u32 frag_cache_hit; | |
152 | u32 frag_cache_miss; | |
8c0ea102 LC |
153 | } __packed; |
154 | ||
155 | struct wl18xx_acx_rx_stats { | |
8dd8e53c IR |
156 | u32 rx_beacon_early_term; |
157 | u32 rx_out_of_mpdu_nodes; | |
8c0ea102 | 158 | u32 rx_hdr_overflow; |
8c0ea102 | 159 | u32 rx_dropped_frame; |
c5d94169 | 160 | u32 rx_done_stage; |
8c0ea102 LC |
161 | u32 rx_done; |
162 | u32 rx_defrag; | |
163 | u32 rx_defrag_end; | |
8c0ea102 LC |
164 | u32 rx_cmplt; |
165 | u32 rx_pre_complt; | |
166 | u32 rx_cmplt_task; | |
167 | u32 rx_phy_hdr; | |
168 | u32 rx_timeout; | |
c48276cb | 169 | u32 rx_rts_timeout; |
8dd8e53c | 170 | u32 rx_timeout_wa; |
c5d94169 LC |
171 | u32 defrag_called; |
172 | u32 defrag_init_called; | |
173 | u32 defrag_in_process_called; | |
174 | u32 defrag_tkip_called; | |
175 | u32 defrag_need_defrag; | |
176 | u32 defrag_decrypt_failed; | |
177 | u32 decrypt_key_not_found; | |
178 | u32 defrag_need_decrypt; | |
8dd8e53c | 179 | u32 rx_tkip_replays; |
c48276cb | 180 | u32 rx_xfr; |
8c0ea102 LC |
181 | } __packed; |
182 | ||
183 | struct wl18xx_acx_isr_stats { | |
184 | u32 irqs; | |
185 | } __packed; | |
186 | ||
8c0ea102 LC |
187 | #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10 |
188 | ||
189 | struct wl18xx_acx_pwr_stats { | |
190 | u32 missing_bcns_cnt; | |
191 | u32 rcvd_bcns_cnt; | |
192 | u32 connection_out_of_sync; | |
193 | u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD]; | |
194 | u32 rcvd_awake_bcns_cnt; | |
c48276cb EP |
195 | u32 sleep_time_count; |
196 | u32 sleep_time_avg; | |
197 | u32 sleep_cycle_avg; | |
198 | u32 sleep_percent; | |
199 | u32 ap_sleep_active_conf; | |
200 | u32 ap_sleep_user_conf; | |
201 | u32 ap_sleep_counter; | |
8c0ea102 LC |
202 | } __packed; |
203 | ||
8c0ea102 LC |
204 | struct wl18xx_acx_rx_filter_stats { |
205 | u32 beacon_filter; | |
206 | u32 arp_filter; | |
207 | u32 mc_filter; | |
208 | u32 dup_filter; | |
209 | u32 data_filter; | |
210 | u32 ibss_filter; | |
211 | u32 protection_filter; | |
8dd8e53c IR |
212 | u32 accum_arp_pend_requests; |
213 | u32 max_arp_queue_dep; | |
8c0ea102 LC |
214 | } __packed; |
215 | ||
c5d94169 LC |
216 | struct wl18xx_acx_rx_rate_stats { |
217 | u32 rx_frames_per_rates[50]; | |
218 | } __packed; | |
219 | ||
8dd8e53c | 220 | #define AGGR_STATS_TX_AGG 16 |
8dd8e53c | 221 | #define AGGR_STATS_RX_SIZE_LEN 16 |
c5d94169 LC |
222 | |
223 | struct wl18xx_acx_aggr_stats { | |
c48276cb EP |
224 | u32 tx_agg_rate[AGGR_STATS_TX_AGG]; |
225 | u32 tx_agg_len[AGGR_STATS_TX_AGG]; | |
c5d94169 LC |
226 | u32 rx_size[AGGR_STATS_RX_SIZE_LEN]; |
227 | } __packed; | |
228 | ||
8dd8e53c IR |
229 | #define PIPE_STATS_HW_FIFO 11 |
230 | ||
c5d94169 LC |
231 | struct wl18xx_acx_pipeline_stats { |
232 | u32 hs_tx_stat_fifo_int; | |
233 | u32 hs_rx_stat_fifo_int; | |
c5d94169 LC |
234 | u32 enc_tx_stat_fifo_int; |
235 | u32 enc_rx_stat_fifo_int; | |
236 | u32 rx_complete_stat_fifo_int; | |
237 | u32 pre_proc_swi; | |
238 | u32 post_proc_swi; | |
239 | u32 sec_frag_swi; | |
240 | u32 pre_to_defrag_swi; | |
fc645df0 | 241 | u32 defrag_to_rx_xfer_swi; |
c5d94169 LC |
242 | u32 dec_packet_in; |
243 | u32 dec_packet_in_fifo_full; | |
244 | u32 dec_packet_out; | |
8dd8e53c | 245 | u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO]; |
c48276cb | 246 | u16 padding; |
c5d94169 LC |
247 | } __packed; |
248 | ||
fc645df0 GM |
249 | #define DIVERSITY_STATS_NUM_OF_ANT 2 |
250 | ||
251 | struct wl18xx_acx_diversity_stats { | |
252 | u32 num_of_packets_per_ant[DIVERSITY_STATS_NUM_OF_ANT]; | |
253 | u32 total_num_of_toggles; | |
8c0ea102 LC |
254 | } __packed; |
255 | ||
c48276cb EP |
256 | struct wl18xx_acx_thermal_stats { |
257 | u16 irq_thr_low; | |
258 | u16 irq_thr_high; | |
259 | u16 tx_stop; | |
260 | u16 tx_resume; | |
261 | u16 false_irq; | |
262 | u16 adc_source_unexpected; | |
263 | } __packed; | |
264 | ||
265 | #define WL18XX_NUM_OF_CALIBRATIONS_ERRORS 18 | |
266 | struct wl18xx_acx_calib_failure_stats { | |
267 | u16 fail_count[WL18XX_NUM_OF_CALIBRATIONS_ERRORS]; | |
268 | u32 calib_count; | |
269 | } __packed; | |
270 | ||
271 | struct wl18xx_roaming_stats { | |
272 | s32 rssi_level; | |
273 | } __packed; | |
274 | ||
275 | struct wl18xx_dfs_stats { | |
276 | u32 num_of_radar_detections; | |
277 | } __packed; | |
278 | ||
8c0ea102 LC |
279 | struct wl18xx_acx_statistics { |
280 | struct acx_header header; | |
281 | ||
8dd8e53c | 282 | struct wl18xx_acx_error_stats error; |
8c0ea102 LC |
283 | struct wl18xx_acx_tx_stats tx; |
284 | struct wl18xx_acx_rx_stats rx; | |
8c0ea102 | 285 | struct wl18xx_acx_isr_stats isr; |
8c0ea102 | 286 | struct wl18xx_acx_pwr_stats pwr; |
8c0ea102 | 287 | struct wl18xx_acx_rx_filter_stats rx_filter; |
c5d94169 LC |
288 | struct wl18xx_acx_rx_rate_stats rx_rate; |
289 | struct wl18xx_acx_aggr_stats aggr_size; | |
290 | struct wl18xx_acx_pipeline_stats pipeline; | |
fc645df0 | 291 | struct wl18xx_acx_diversity_stats diversity; |
c48276cb EP |
292 | struct wl18xx_acx_thermal_stats thermal; |
293 | struct wl18xx_acx_calib_failure_stats calib; | |
294 | struct wl18xx_roaming_stats roaming; | |
295 | struct wl18xx_dfs_stats dfs; | |
8c0ea102 LC |
296 | } __packed; |
297 | ||
f74ea74b LC |
298 | struct wl18xx_acx_clear_statistics { |
299 | struct acx_header header; | |
300 | }; | |
301 | ||
5f9b6777 AN |
302 | enum wlcore_bandwidth { |
303 | WLCORE_BANDWIDTH_20MHZ, | |
304 | WLCORE_BANDWIDTH_40MHZ, | |
305 | }; | |
306 | ||
307 | struct wlcore_peer_ht_operation_mode { | |
308 | struct acx_header header; | |
309 | ||
310 | u8 hlid; | |
311 | u8 bandwidth; /* enum wlcore_bandwidth */ | |
312 | u8 padding[2]; | |
313 | }; | |
314 | ||
530abe19 EP |
315 | /* |
316 | * ACX_PEER_CAP | |
317 | * this struct is very similar to wl1271_acx_ht_capabilities, with the | |
318 | * addition of supported rates | |
319 | */ | |
320 | struct wlcore_acx_peer_cap { | |
321 | struct acx_header header; | |
322 | ||
323 | /* bitmask of capability bits supported by the peer */ | |
324 | __le32 ht_capabilites; | |
325 | ||
326 | /* rates supported by the remote peer */ | |
327 | __le32 supported_rates; | |
328 | ||
329 | /* Indicates to which link these capabilities apply. */ | |
330 | u8 hlid; | |
331 | ||
332 | /* | |
333 | * This the maximum A-MPDU length supported by the AP. The FW may not | |
334 | * exceed this length when sending A-MPDUs | |
335 | */ | |
336 | u8 ampdu_max_length; | |
337 | ||
338 | /* This is the minimal spacing required when sending A-MPDUs to the AP*/ | |
339 | u8 ampdu_min_spacing; | |
340 | ||
341 | u8 padding; | |
342 | } __packed; | |
343 | ||
6d5a748d RA |
344 | /* |
345 | * ACX_INTERRUPT_NOTIFY | |
346 | * enable/disable fast-link/PSM notification from FW | |
347 | */ | |
348 | struct wl18xx_acx_interrupt_notify { | |
349 | struct acx_header header; | |
350 | u32 enable; | |
351 | }; | |
352 | ||
353 | /* | |
354 | * ACX_RX_BA_FILTER | |
355 | * enable/disable RX BA filtering in FW | |
356 | */ | |
357 | struct wl18xx_acx_rx_ba_filter { | |
358 | struct acx_header header; | |
359 | u32 enable; | |
360 | }; | |
361 | ||
e2f1e50f K |
362 | struct acx_ap_sleep_cfg { |
363 | struct acx_header header; | |
364 | /* Duty Cycle (20-80% of staying Awake) for IDLE AP | |
365 | * (0: disable) | |
366 | */ | |
367 | u8 idle_duty_cycle; | |
368 | /* Duty Cycle (20-80% of staying Awake) for Connected AP | |
369 | * (0: disable) | |
370 | */ | |
371 | u8 connected_duty_cycle; | |
372 | /* Maximum stations that are allowed to be connected to AP | |
373 | * (255: no limit) | |
374 | */ | |
375 | u8 max_stations_thresh; | |
376 | /* Timeout till enabling the Sleep Mechanism after data stops | |
377 | * [unit: 100 msec] | |
378 | */ | |
379 | u8 idle_conn_thresh; | |
380 | } __packed; | |
381 | ||
d1c54096 GM |
382 | /* |
383 | * ACX_DYNAMIC_TRACES_CFG | |
384 | * configure the FW dynamic traces | |
385 | */ | |
386 | struct acx_dynamic_fw_traces_cfg { | |
387 | struct acx_header header; | |
388 | __le32 dynamic_fw_traces; | |
389 | } __packed; | |
390 | ||
b8422dcb LC |
391 | int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap, |
392 | u32 sdio_blk_size, u32 extra_mem_blks, | |
393 | u32 len_field_size); | |
2fc28de5 | 394 | int wl18xx_acx_set_checksum_state(struct wl1271 *wl); |
f74ea74b | 395 | int wl18xx_acx_clear_statistics(struct wl1271 *wl); |
5f9b6777 | 396 | int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide); |
530abe19 EP |
397 | int wl18xx_acx_set_peer_cap(struct wl1271 *wl, |
398 | struct ieee80211_sta_ht_cap *ht_cap, | |
399 | bool allow_ht_operation, | |
400 | u32 rate_set, u8 hlid); | |
6d5a748d RA |
401 | int wl18xx_acx_interrupt_notify_config(struct wl1271 *wl, bool action); |
402 | int wl18xx_acx_rx_ba_filter(struct wl1271 *wl, bool action); | |
e2f1e50f | 403 | int wl18xx_acx_ap_sleep(struct wl1271 *wl); |
d1c54096 | 404 | int wl18xx_acx_dynamic_fw_traces(struct wl1271 *wl); |
b8422dcb | 405 | |
8c0ea102 | 406 | #endif /* __WL18XX_ACX_H__ */ |