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wlcore/wl18xx: fw logger over sdio
[deliverable/linux.git] / drivers / net / wireless / ti / wl18xx / main.c
CommitLineData
9a1a6990
LC		 1/*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/platform_device.h>
2fc28de5 24#include <linux/ip.h>
640dfb9b 25#include <linux/firmware.h>
bc2ab3b8 26#include <linux/etherdevice.h>
bd763482 27#include <linux/irq.h>
9a1a6990
LC		 28
29#include "../wlcore/wlcore.h"
30#include "../wlcore/debug.h"
46a1d512
LC		 31#include "../wlcore/io.h"
32#include "../wlcore/acx.h"
fb0f2e4a 33#include "../wlcore/tx.h"
9c809f88 34#include "../wlcore/rx.h"
46a1d512 35#include "../wlcore/boot.h"
9a1a6990 36
5d4a9fa6 37#include "reg.h"
46a1d512 38#include "conf.h"
fcab1890 39#include "cmd.h"
b8422dcb 40#include "acx.h"
872b345f 41#include "tx.h"
274c66cd 42#include "wl18xx.h"
be65202a 43#include "io.h"
78e28062 44#include "scan.h"
c50a2825 45#include "event.h"
8c0ea102 46#include "debugfs.h"
1349c421 47
169da04f
AN		 48#define WL18XX_RX_CHECKSUM_MASK 0x40
49
c68cc0f6
YS		 50static char *ht_mode_param = NULL;
51static char *board_type_param = NULL;
3d62eb5a 52static bool checksum_param = false;
09aad14f 53static int num_rx_desc_param = -1;
17d97719
AN		 54
55/* phy paramters */
56static int dc2dc_param = -1;
57static int n_antennas_2_param = -1;
58static int n_antennas_5_param = -1;
59static int low_band_component_param = -1;
60static int low_band_component_type_param = -1;
61static int high_band_component_param = -1;
62static int high_band_component_type_param = -1;
63static int pwr_limit_reference_11_abg_param = -1;
3a8ddb61 64
f648eab7
AN		 65static const u8 wl18xx_rate_to_idx_2ghz[] = {
66 /* MCS rates are used only with 11n */
67 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
68 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
69 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
70 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
71 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
72 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
73 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
74 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
75 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
76 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
77 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
78 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
79 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
80 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
81 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
82 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
83
84 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
85 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
86 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
87 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
88
89 /* TI-specific rate */
90 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
91
92 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
93 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
94 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
95 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
96 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
97 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
98 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
99 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
100};
101
102static const u8 wl18xx_rate_to_idx_5ghz[] = {
103 /* MCS rates are used only with 11n */
104 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
105 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
106 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
107 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
108 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
109 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
110 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
111 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
112 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
113 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
114 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
115 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
116 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
117 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
118 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
119 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
120
121 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
122 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
123 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
124 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
125
126 /* TI-specific rate */
127 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
128
129 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
130 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
131 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
132 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
133 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
134 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
135 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
136 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
137};
138
139static const u8 *wl18xx_band_rate_to_idx[] = {
140 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
141 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
142};
143
144enum wl18xx_hw_rates {
145 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
146 WL18XX_CONF_HW_RXTX_RATE_MCS14,
147 WL18XX_CONF_HW_RXTX_RATE_MCS13,
148 WL18XX_CONF_HW_RXTX_RATE_MCS12,
149 WL18XX_CONF_HW_RXTX_RATE_MCS11,
150 WL18XX_CONF_HW_RXTX_RATE_MCS10,
151 WL18XX_CONF_HW_RXTX_RATE_MCS9,
152 WL18XX_CONF_HW_RXTX_RATE_MCS8,
153 WL18XX_CONF_HW_RXTX_RATE_MCS7,
154 WL18XX_CONF_HW_RXTX_RATE_MCS6,
155 WL18XX_CONF_HW_RXTX_RATE_MCS5,
156 WL18XX_CONF_HW_RXTX_RATE_MCS4,
157 WL18XX_CONF_HW_RXTX_RATE_MCS3,
158 WL18XX_CONF_HW_RXTX_RATE_MCS2,
159 WL18XX_CONF_HW_RXTX_RATE_MCS1,
160 WL18XX_CONF_HW_RXTX_RATE_MCS0,
161 WL18XX_CONF_HW_RXTX_RATE_54,
162 WL18XX_CONF_HW_RXTX_RATE_48,
163 WL18XX_CONF_HW_RXTX_RATE_36,
164 WL18XX_CONF_HW_RXTX_RATE_24,
165 WL18XX_CONF_HW_RXTX_RATE_22,
166 WL18XX_CONF_HW_RXTX_RATE_18,
167 WL18XX_CONF_HW_RXTX_RATE_12,
168 WL18XX_CONF_HW_RXTX_RATE_11,
169 WL18XX_CONF_HW_RXTX_RATE_9,
170 WL18XX_CONF_HW_RXTX_RATE_6,
171 WL18XX_CONF_HW_RXTX_RATE_5_5,
172 WL18XX_CONF_HW_RXTX_RATE_2,
173 WL18XX_CONF_HW_RXTX_RATE_1,
174 WL18XX_CONF_HW_RXTX_RATE_MAX,
175};
176
23ee9bf8
LC		 177static struct wlcore_conf wl18xx_conf = {
178 .sg = {
179 .params = {
133b7326
GM		 180 [WL18XX_CONF_SG_PARAM_0] = 0,
181 /* Configuartion Parameters */
182 [WL18XX_CONF_SG_ANTENNA_CONFIGURATION] = 0,
183 [WL18XX_CONF_SG_ZIGBEE_COEX] = 0,
184 [WL18XX_CONF_SG_TIME_SYNC] = 0,
185 [WL18XX_CONF_SG_PARAM_4] = 0,
186 [WL18XX_CONF_SG_PARAM_5] = 0,
187 [WL18XX_CONF_SG_PARAM_6] = 0,
188 [WL18XX_CONF_SG_PARAM_7] = 0,
189 [WL18XX_CONF_SG_PARAM_8] = 0,
190 [WL18XX_CONF_SG_PARAM_9] = 0,
191 [WL18XX_CONF_SG_PARAM_10] = 0,
192 [WL18XX_CONF_SG_PARAM_11] = 0,
193 [WL18XX_CONF_SG_PARAM_12] = 0,
194 [WL18XX_CONF_SG_PARAM_13] = 0,
195 [WL18XX_CONF_SG_PARAM_14] = 0,
196 [WL18XX_CONF_SG_PARAM_15] = 0,
197 [WL18XX_CONF_SG_PARAM_16] = 0,
198 [WL18XX_CONF_SG_PARAM_17] = 0,
199 [WL18XX_CONF_SG_PARAM_18] = 0,
200 [WL18XX_CONF_SG_PARAM_19] = 0,
201 [WL18XX_CONF_SG_PARAM_20] = 0,
202 [WL18XX_CONF_SG_PARAM_21] = 0,
203 [WL18XX_CONF_SG_PARAM_22] = 0,
204 [WL18XX_CONF_SG_PARAM_23] = 0,
205 [WL18XX_CONF_SG_PARAM_24] = 0,
206 [WL18XX_CONF_SG_PARAM_25] = 0,
207 /* Active Scan Parameters */
208 [WL18XX_CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
209 [WL18XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
210 [WL18XX_CONF_SG_PARAM_28] = 0,
211 /* Passive Scan Parameters */
212 [WL18XX_CONF_SG_PARAM_29] = 0,
213 [WL18XX_CONF_SG_PARAM_30] = 0,
214 [WL18XX_CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
215 /* Passive Scan in Dual Antenna Parameters */
216 [WL18XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
217 [WL18XX_CONF_SG_BEACON_HV3_COLL_TH_IN_PASSIVE_SCAN] = 0,
218 [WL18XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN] = 0,
219 /* General Parameters */
220 [WL18XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
221 [WL18XX_CONF_SG_PARAM_36] = 0,
222 [WL18XX_CONF_SG_BEACON_MISS_PERCENT] = 60,
223 [WL18XX_CONF_SG_PARAM_38] = 0,
224 [WL18XX_CONF_SG_RXT] = 1200,
225 [WL18XX_CONF_SG_UNUSED] = 0,
226 [WL18XX_CONF_SG_ADAPTIVE_RXT_TXT] = 1,
227 [WL18XX_CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
228 [WL18XX_CONF_SG_HV3_MAX_SERVED] = 6,
229 [WL18XX_CONF_SG_PARAM_44] = 0,
230 [WL18XX_CONF_SG_PARAM_45] = 0,
231 [WL18XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
232 [WL18XX_CONF_SG_GEMINI_PARAM_47] = 0,
233 [WL18XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 0,
234 /* AP Parameters */
235 [WL18XX_CONF_SG_AP_BEACON_MISS_TX] = 3,
236 [WL18XX_CONF_SG_PARAM_50] = 0,
237 [WL18XX_CONF_SG_AP_BEACON_WINDOW_INTERVAL] = 2,
238 [WL18XX_CONF_SG_AP_CONNECTION_PROTECTION_TIME] = 30,
239 [WL18XX_CONF_SG_PARAM_53] = 0,
240 [WL18XX_CONF_SG_PARAM_54] = 0,
241 /* CTS Diluting Parameters */
242 [WL18XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
243 [WL18XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
244 [WL18XX_CONF_SG_TEMP_PARAM_1] = 0,
245 [WL18XX_CONF_SG_TEMP_PARAM_2] = 0,
246 [WL18XX_CONF_SG_TEMP_PARAM_3] = 0,
247 [WL18XX_CONF_SG_TEMP_PARAM_4] = 0,
248 [WL18XX_CONF_SG_TEMP_PARAM_5] = 0,
249 [WL18XX_CONF_SG_TEMP_PARAM_6] = 0,
250 [WL18XX_CONF_SG_TEMP_PARAM_7] = 0,
251 [WL18XX_CONF_SG_TEMP_PARAM_8] = 0,
252 [WL18XX_CONF_SG_TEMP_PARAM_9] = 0,
253 [WL18XX_CONF_SG_TEMP_PARAM_10] = 0,
23ee9bf8
LC		 254 },
255 .state = CONF_SG_PROTECTIVE,
256 },
257 .rx = {
258 .rx_msdu_life_time = 512000,
259 .packet_detection_threshold = 0,
260 .ps_poll_timeout = 15,
261 .upsd_timeout = 15,
262 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
263 .rx_cca_threshold = 0,
264 .irq_blk_threshold = 0xFFFF,
265 .irq_pkt_threshold = 0,
266 .irq_timeout = 600,
267 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
268 },
269 .tx = {
270 .tx_energy_detection = 0,
271 .sta_rc_conf = {
272 .enabled_rates = 0,
273 .short_retry_limit = 10,
274 .long_retry_limit = 10,
275 .aflags = 0,
276 },
277 .ac_conf_count = 4,
278 .ac_conf = {
279 [CONF_TX_AC_BE] = {
280 .ac = CONF_TX_AC_BE,
281 .cw_min = 15,
282 .cw_max = 63,
283 .aifsn = 3,
284 .tx_op_limit = 0,
285 },
286 [CONF_TX_AC_BK] = {
287 .ac = CONF_TX_AC_BK,
288 .cw_min = 15,
289 .cw_max = 63,
290 .aifsn = 7,
291 .tx_op_limit = 0,
292 },
293 [CONF_TX_AC_VI] = {
294 .ac = CONF_TX_AC_VI,
295 .cw_min = 15,
296 .cw_max = 63,
297 .aifsn = CONF_TX_AIFS_PIFS,
298 .tx_op_limit = 3008,
299 },
300 [CONF_TX_AC_VO] = {
301 .ac = CONF_TX_AC_VO,
302 .cw_min = 15,
303 .cw_max = 63,
304 .aifsn = CONF_TX_AIFS_PIFS,
305 .tx_op_limit = 1504,
306 },
307 },
308 .max_tx_retries = 100,
309 .ap_aging_period = 300,
310 .tid_conf_count = 4,
311 .tid_conf = {
312 [CONF_TX_AC_BE] = {
313 .queue_id = CONF_TX_AC_BE,
314 .channel_type = CONF_CHANNEL_TYPE_EDCF,
315 .tsid = CONF_TX_AC_BE,
316 .ps_scheme = CONF_PS_SCHEME_LEGACY,
317 .ack_policy = CONF_ACK_POLICY_LEGACY,
318 .apsd_conf = {0, 0},
319 },
320 [CONF_TX_AC_BK] = {
321 .queue_id = CONF_TX_AC_BK,
322 .channel_type = CONF_CHANNEL_TYPE_EDCF,
323 .tsid = CONF_TX_AC_BK,
324 .ps_scheme = CONF_PS_SCHEME_LEGACY,
325 .ack_policy = CONF_ACK_POLICY_LEGACY,
326 .apsd_conf = {0, 0},
327 },
328 [CONF_TX_AC_VI] = {
329 .queue_id = CONF_TX_AC_VI,
330 .channel_type = CONF_CHANNEL_TYPE_EDCF,
331 .tsid = CONF_TX_AC_VI,
332 .ps_scheme = CONF_PS_SCHEME_LEGACY,
333 .ack_policy = CONF_ACK_POLICY_LEGACY,
334 .apsd_conf = {0, 0},
335 },
336 [CONF_TX_AC_VO] = {
337 .queue_id = CONF_TX_AC_VO,
338 .channel_type = CONF_CHANNEL_TYPE_EDCF,
339 .tsid = CONF_TX_AC_VO,
340 .ps_scheme = CONF_PS_SCHEME_LEGACY,
341 .ack_policy = CONF_ACK_POLICY_LEGACY,
342 .apsd_conf = {0, 0},
343 },
344 },
345 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
346 .tx_compl_timeout = 350,
347 .tx_compl_threshold = 10,
348 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
349 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
350 .tmpl_short_retry_limit = 10,
351 .tmpl_long_retry_limit = 10,
352 .tx_watchdog_timeout = 5000,
0e810479
AN		 353 .slow_link_thold = 3,
354 .fast_link_thold = 30,
23ee9bf8
LC		 355 },
356 .conn = {
357 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
358 .listen_interval = 1,
359 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
360 .suspend_listen_interval = 3,
361 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
186b5a7c 362 .bcn_filt_ie_count = 3,
23ee9bf8
LC		 363 .bcn_filt_ie = {
364 [0] = {
365 .ie = WLAN_EID_CHANNEL_SWITCH,
366 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
367 },
368 [1] = {
369 .ie = WLAN_EID_HT_OPERATION,
370 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
186b5a7c
EP		 371 },
372 [2] = {
373 .ie = WLAN_EID_ERP_INFO,
374 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
23ee9bf8
LC		 375 },
376 },
7b052214
IC		 377 .synch_fail_thold = 12,
378 .bss_lose_timeout = 400,
23ee9bf8
LC		 379 .beacon_rx_timeout = 10000,
380 .broadcast_timeout = 20000,
381 .rx_broadcast_in_ps = 1,
382 .ps_poll_threshold = 10,
383 .bet_enable = CONF_BET_MODE_ENABLE,
384 .bet_max_consecutive = 50,
385 .psm_entry_retries = 8,
386 .psm_exit_retries = 16,
387 .psm_entry_nullfunc_retries = 3,
0fc1d2e9 388 .dynamic_ps_timeout = 1500,
23ee9bf8
LC		 389 .forced_ps = false,
390 .keep_alive_interval = 55000,
391 .max_listen_interval = 20,
66340e5b 392 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
6d5a748d 393 .suspend_rx_ba_activity = 0,
23ee9bf8
LC		 394 },
395 .itrim = {
396 .enable = false,
397 .timeout = 50000,
398 },
399 .pm_config = {
400 .host_clk_settling_time = 5000,
648f6ed9 401 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
23ee9bf8
LC		 402 },
403 .roam_trigger = {
404 .trigger_pacing = 1,
405 .avg_weight_rssi_beacon = 20,
406 .avg_weight_rssi_data = 10,
407 .avg_weight_snr_beacon = 20,
408 .avg_weight_snr_data = 10,
409 },
410 .scan = {
411 .min_dwell_time_active = 7500,
412 .max_dwell_time_active = 30000,
5d3a1603
ES		 413 .min_dwell_time_active_long = 25000,
414 .max_dwell_time_active_long = 50000,
7c482c10
EP		 415 .dwell_time_passive = 100000,
416 .dwell_time_dfs = 150000,
23ee9bf8
LC		 417 .num_probe_reqs = 2,
418 .split_scan_timeout = 50000,
419 },
420 .sched_scan = {
421 /*
422 * Values are in TU/1000 but since sched scan FW command
423 * params are in TUs rounding up may occur.
424 */
425 .base_dwell_time = 7500,
426 .max_dwell_time_delta = 22500,
427 /* based on 250bits per probe @1Mbps */
428 .dwell_time_delta_per_probe = 2000,
429 /* based on 250bits per probe @6Mbps (plus a bit more) */
430 .dwell_time_delta_per_probe_5 = 350,
431 .dwell_time_passive = 100000,
432 .dwell_time_dfs = 150000,
433 .num_probe_reqs = 2,
434 .rssi_threshold = -90,
435 .snr_threshold = 0,
8698a3a4
EP		 436 .num_short_intervals = SCAN_MAX_SHORT_INTERVALS,
437 .long_interval = 30000,
23ee9bf8
LC		 438 },
439 .ht = {
9ae48aea 440 .rx_ba_win_size = 32,
3507efa0 441 .tx_ba_win_size = 64,
23ee9bf8
LC		 442 .inactivity_timeout = 10000,
443 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
444 },
445 .mem = {
446 .num_stations = 1,
447 .ssid_profiles = 1,
448 .rx_block_num = 40,
449 .tx_min_block_num = 40,
450 .dynamic_memory = 1,
451 .min_req_tx_blocks = 45,
452 .min_req_rx_blocks = 22,
453 .tx_min = 27,
454 },
455 .fm_coex = {
456 .enable = true,
457 .swallow_period = 5,
458 .n_divider_fref_set_1 = 0xff, /* default */
459 .n_divider_fref_set_2 = 12,
461b958f
VG		 460 .m_divider_fref_set_1 = 0xffff,
461 .m_divider_fref_set_2 = 148, /* default */
23ee9bf8
LC		 462 .coex_pll_stabilization_time = 0xffffffff, /* default */
463 .ldo_stabilization_time = 0xffff, /* default */
464 .fm_disturbed_band_margin = 0xff, /* default */
465 .swallow_clk_diff = 0xff, /* default */
466 },
467 .rx_streaming = {
468 .duration = 150,
469 .queues = 0x1,
470 .interval = 20,
471 .always = 0,
472 },
473 .fwlog = {
9d8146d4 474 .mode = WL12XX_FWLOG_CONTINUOUS,
3719c17e 475 .mem_blocks = 0,
23ee9bf8
LC		 476 .severity = 0,
477 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
9d8146d4 478 .output = WL12XX_FWLOG_OUTPUT_DBG_PINS,
23ee9bf8
LC		 479 .threshold = 0,
480 },
481 .rate = {
482 .rate_retry_score = 32000,
483 .per_add = 8192,
484 .per_th1 = 2048,
485 .per_th2 = 4096,
486 .max_per = 8100,
487 .inverse_curiosity_factor = 5,
488 .tx_fail_low_th = 4,
489 .tx_fail_high_th = 10,
490 .per_alpha_shift = 4,
491 .per_add_shift = 13,
492 .per_beta1_shift = 10,
493 .per_beta2_shift = 8,
494 .rate_check_up = 2,
495 .rate_check_down = 12,
496 .rate_retry_policy = {
497 0x00, 0x00, 0x00, 0x00, 0x00,
498 0x00, 0x00, 0x00, 0x00, 0x00,
499 0x00, 0x00, 0x00,
500 },
501 },
502 .hangover = {
503 .recover_time = 0,
504 .hangover_period = 20,
505 .dynamic_mode = 1,
506 .early_termination_mode = 1,
507 .max_period = 20,
508 .min_period = 1,
509 .increase_delta = 1,
510 .decrease_delta = 2,
511 .quiet_time = 4,
512 .increase_time = 1,
513 .window_size = 16,
514 },
7230341f
YS		 515 .recovery = {
516 .bug_on_recovery = 0,
517 .no_recovery = 0,
518 },
23ee9bf8
LC		 519};
520
521static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
c68cc0f6 522 .ht = {
50e4c905 523 .mode = HT_MODE_WIDE,
c68cc0f6 524 },
46a1d512
LC		 525 .phy = {
526 .phy_standalone = 0x00,
527 .primary_clock_setting_time = 0x05,
528 .clock_valid_on_wake_up = 0x00,
529 .secondary_clock_setting_time = 0x05,
c68cc0f6 530 .board_type = BOARD_TYPE_HDK_18XX,
46a1d512
LC		 531 .auto_detect = 0x00,
532 .dedicated_fem = FEM_NONE,
e1c497c3 533 .low_band_component = COMPONENT_3_WAY_SWITCH,
50e4c905 534 .low_band_component_type = 0x05,
46a1d512
LC		 535 .high_band_component = COMPONENT_2_WAY_SWITCH,
536 .high_band_component_type = 0x09,
46a1d512
LC		 537 .tcxo_ldo_voltage = 0x00,
538 .xtal_itrim_val = 0x04,
539 .srf_state = 0x00,
540 .io_configuration = 0x01,
541 .sdio_configuration = 0x00,
542 .settings = 0x00,
543 .enable_clpc = 0x00,
544 .enable_tx_low_pwr_on_siso_rdl = 0x00,
545 .rx_profile = 0x00,
d88949b7
YS		 546 .pwr_limit_reference_11_abg = 0x64,
547 .per_chan_pwr_limit_arr_11abg = {
548 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
549 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
550 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
551 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
552 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
553 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
554 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
555 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
556 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
557 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
558 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
559 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
560 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
561 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
562 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
563 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
564 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
565 .pwr_limit_reference_11p = 0x64,
1d614665
VG		 566 .per_chan_bo_mode_11_abg = { 0x00, 0x00, 0x00, 0x00,
567 0x00, 0x00, 0x00, 0x00,
568 0x00, 0x00, 0x00, 0x00,
569 0x00 },
570 .per_chan_bo_mode_11_p = { 0x00, 0x00, 0x00, 0x00 },
d88949b7
YS		 571 .per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
572 0xff, 0xff, 0xff },
16ea4733 573 .psat = 0,
17d97719 574 .external_pa_dc2dc = 0,
d88949b7 575 .number_of_assembled_ant2_4 = 2,
17d97719 576 .number_of_assembled_ant5 = 1,
50e4c905
IC		 577 .low_power_val = 0xff,
578 .med_power_val = 0xff,
579 .high_power_val = 0xff,
580 .low_power_val_2nd = 0xff,
581 .med_power_val_2nd = 0xff,
582 .high_power_val_2nd = 0xff,
ec4f4b76 583 .tx_rf_margin = 1,
46a1d512 584 },
e2f1e50f
K		 585 .ap_sleep = { /* disabled by default */
586 .idle_duty_cycle = 0,
587 .connected_duty_cycle = 0,
588 .max_stations_thresh = 0,
589 .idle_conn_thresh = 0,
590 },
46a1d512 591};
5d4a9fa6 592
82b890cd
LC		 593static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
594 [PART_TOP_PRCM_ELP_SOC] = {
bd763482 595 .mem = { .start = 0x00A00000, .size = 0x00012000 },
82b890cd
LC		 596 .reg = { .start = 0x00807000, .size = 0x00005000 },
597 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
3719c17e 598 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
82b890cd
LC		 599 },
600 [PART_DOWN] = {
601 .mem = { .start = 0x00000000, .size = 0x00014000 },
602 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
603 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
604 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
605 },
606 [PART_BOOT] = {
607 .mem = { .start = 0x00700000, .size = 0x0000030c },
608 .reg = { .start = 0x00802000, .size = 0x00014578 },
609 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
610 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
611 },
612 [PART_WORK] = {
613 .mem = { .start = 0x00800000, .size = 0x000050FC },
614 .reg = { .start = 0x00B00404, .size = 0x00001000 },
615 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
3719c17e 616 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
82b890cd
LC		 617 },
618 [PART_PHY_INIT] = {
e3b8bbb9
IR		 619 .mem = { .start = WL18XX_PHY_INIT_MEM_ADDR,
620 .size = WL18XX_PHY_INIT_MEM_SIZE },
82b890cd
LC		 621 .reg = { .start = 0x00000000, .size = 0x00000000 },
622 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
623 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
624 },
625};
626
5d4a9fa6
LC		 627static const int wl18xx_rtable[REG_TABLE_LEN] = {
628 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
629 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
630 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
631 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
632 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
633 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
634 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
1c351da6 635 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
5d4a9fa6
LC		 636 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
637 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
638
639 /* data access memory addresses, used with partition translation */
640 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
641 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
642
643 /* raw data access memory addresses */
644 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
645};
646
ef47d328
VG		 647static const struct wl18xx_clk_cfg wl18xx_clk_table_coex[NUM_CLOCK_CONFIGS] = {
648 [CLOCK_CONFIG_16_2_M] = { 8, 121, 0, 0, false },
649 [CLOCK_CONFIG_16_368_M] = { 8, 120, 0, 0, false },
650 [CLOCK_CONFIG_16_8_M] = { 8, 117, 0, 0, false },
651 [CLOCK_CONFIG_19_2_M] = { 10, 128, 0, 0, false },
652 [CLOCK_CONFIG_26_M] = { 11, 104, 0, 0, false },
653 [CLOCK_CONFIG_32_736_M] = { 8, 120, 0, 0, false },
654 [CLOCK_CONFIG_33_6_M] = { 8, 117, 0, 0, false },
655 [CLOCK_CONFIG_38_468_M] = { 10, 128, 0, 0, false },
656 [CLOCK_CONFIG_52_M] = { 11, 104, 0, 0, false },
657};
658
be65202a
LC		 659static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
660 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
661 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
662 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
663 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
664 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
665 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
666 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
667 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
668 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
669};
670
0cd6543f 671/* TODO: maybe move to a new header file? */
750e9d15 672#define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-4.bin"
0cd6543f
LC		 673
674static int wl18xx_identify_chip(struct wl1271 *wl)
675{
676 int ret = 0;
677
678 switch (wl->chip.id) {
73395a79
IR		 679 case CHIP_ID_185x_PG20:
680 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
681 wl->chip.id);
682 wl->sr_fw_name = WL18XX_FW_NAME;
683 /* wl18xx uses the same firmware for PLT */
684 wl->plt_fw_name = WL18XX_FW_NAME;
2718bf40 685 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
bf7c46a7 686 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
01b3c0e4 687 WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
78e28062 688 WLCORE_QUIRK_TX_PAD_LAST_FRAME |
6b70e7eb 689 WLCORE_QUIRK_REGDOMAIN_CONF |
78e28062 690 WLCORE_QUIRK_DUAL_PROBE_TMPL;
4a1ccce8 691
8675f9ab
LC		 692 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
693 WL18XX_IFTYPE_VER, WL18XX_MAJOR_VER,
694 WL18XX_SUBTYPE_VER, WL18XX_MINOR_VER,
695 /* there's no separate multi-role FW */
696 0, 0, 0, 0);
73395a79 697 break;
0cd6543f 698 case CHIP_ID_185x_PG10:
e59bec16
LC		 699 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
700 wl->chip.id);
701 ret = -ENODEV;
702 goto out;
7ae25da3 703
0cd6543f
LC		 704 default:
705 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
706 ret = -ENODEV;
707 goto out;
708 }
709
c83cb803
IC		 710 wl->fw_mem_block_size = 272;
711 wl->fwlog_end = 0x40000000;
712
78e28062
EP		 713 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
714 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
715 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
716 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
0a1c720c 717 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
d21553f8 718 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS;
0cd6543f
LC		 719out:
720 return ret;
721}
722
6134323f 723static int wl18xx_set_clk(struct wl1271 *wl)
46a1d512 724{
6134323f
IY		 725 u16 clk_freq;
726 int ret;
d5b59276 727
b0f0ad39
IY		 728 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
729 if (ret < 0)
730 goto out;
be65202a
LC		 731
732 /* TODO: PG2: apparently we need to read the clk type */
733
6134323f
IY		 734 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
735 if (ret < 0)
736 goto out;
737
be65202a
LC		 738 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
739 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
740 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
741 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
742
ef47d328
VG		 743 /* coex PLL configuration */
744 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N,
745 wl18xx_clk_table_coex[clk_freq].n);
746 if (ret < 0)
747 goto out;
748
749 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M,
750 wl18xx_clk_table_coex[clk_freq].m);
751 if (ret < 0)
752 goto out;
753
754 /* bypass the swallowing logic */
755 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
756 PLLSH_COEX_PLL_SWALLOW_EN_VAL1);
757 if (ret < 0)
758 goto out;
759
6134323f
IY		 760 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
761 wl18xx_clk_table[clk_freq].n);
762 if (ret < 0)
763 goto out;
764
765 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
766 wl18xx_clk_table[clk_freq].m);
767 if (ret < 0)
768 goto out;
be65202a
LC		 769
770 if (wl18xx_clk_table[clk_freq].swallow) {
771 /* first the 16 lower bits */
6134323f
IY		 772 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
773 wl18xx_clk_table[clk_freq].q &
774 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
775 if (ret < 0)
776 goto out;
777
be65202a 778 /* then the 16 higher bits, masked out */
6134323f
IY		 779 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
780 (wl18xx_clk_table[clk_freq].q >> 16) &
781 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
782 if (ret < 0)
783 goto out;
be65202a
LC		 784
785 /* first the 16 lower bits */
6134323f
IY		 786 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
787 wl18xx_clk_table[clk_freq].p &
788 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
789 if (ret < 0)
790 goto out;
791
be65202a 792 /* then the 16 higher bits, masked out */
6134323f
IY		 793 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
794 (wl18xx_clk_table[clk_freq].p >> 16) &
795 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
be65202a 796 } else {
6134323f
IY		 797 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
798 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
be65202a 799 }
6134323f 800
ef47d328
VG		 801 /* choose WCS PLL */
802 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL,
803 PLLSH_WL_PLL_SEL_WCS_PLL);
804 if (ret < 0)
805 goto out;
806
807 /* enable both PLLs */
808 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1);
809 if (ret < 0)
810 goto out;
811
812 udelay(1000);
813
814 /* disable coex PLL */
815 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2);
816 if (ret < 0)
817 goto out;
818
819 /* reset the swallowing logic */
820 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
821 PLLSH_COEX_PLL_SWALLOW_EN_VAL2);
822 if (ret < 0)
823 goto out;
824
6134323f
IY		 825out:
826 return ret;
46a1d512
LC		 827}
828
b0f0ad39 829static int wl18xx_boot_soft_reset(struct wl1271 *wl)
46a1d512 830{
b0f0ad39
IY		 831 int ret;
832
46a1d512 833 /* disable Rx/Tx */
b0f0ad39
IY		 834 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
835 if (ret < 0)
836 goto out;
46a1d512
LC		 837
838 /* disable auto calibration on start*/
b0f0ad39
IY		 839 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
840
841out:
842 return ret;
46a1d512
LC		 843}
844
845static int wl18xx_pre_boot(struct wl1271 *wl)
846{
6134323f
IY		 847 int ret;
848
849 ret = wl18xx_set_clk(wl);
850 if (ret < 0)
851 goto out;
46a1d512
LC		 852
853 /* Continue the ELP wake up sequence */
b0f0ad39
IY		 854 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
855 if (ret < 0)
856 goto out;
857
46a1d512
LC		 858 udelay(500);
859
b0f0ad39
IY		 860 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
861 if (ret < 0)
862 goto out;
46a1d512
LC		 863
864 /* Disable interrupts */
b0f0ad39
IY		 865 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
866 if (ret < 0)
867 goto out;
46a1d512 868
b0f0ad39 869 ret = wl18xx_boot_soft_reset(wl);
46a1d512 870
6134323f
IY		 871out:
872 return ret;
46a1d512
LC		 873}
874
6134323f 875static int wl18xx_pre_upload(struct wl1271 *wl)
46a1d512
LC		 876{
877 u32 tmp;
6134323f 878 int ret;
bd763482 879 u16 irq_invert;
46a1d512 880
e3b8bbb9
IR		 881 BUILD_BUG_ON(sizeof(struct wl18xx_mac_and_phy_params) >
882 WL18XX_PHY_INIT_MEM_SIZE);
883
b0f0ad39
IY		 884 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
885 if (ret < 0)
886 goto out;
46a1d512
LC		 887
888 /* TODO: check if this is all needed */
b0f0ad39
IY		 889 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
890 if (ret < 0)
891 goto out;
46a1d512 892
6134323f
IY		 893 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
894 if (ret < 0)
895 goto out;
46a1d512
LC		 896
897 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
898
6134323f 899 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
e3b8bbb9
IR		 900 if (ret < 0)
901 goto out;
902
903 /*
904 * Workaround for FDSP code RAM corruption (needed for PG2.1
905 * and newer; for older chips it's a NOP). Change FDSP clock
906 * settings so that it's muxed to the ATGP clock instead of
907 * its own clock.
908 */
909
910 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
911 if (ret < 0)
912 goto out;
913
914 /* disable FDSP clock */
915 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
916 MEM_FDSP_CLK_120_DISABLE);
917 if (ret < 0)
918 goto out;
919
920 /* set ATPG clock toward FDSP Code RAM rather than its own clock */
921 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
922 MEM_FDSP_CODERAM_FUNC_CLK_SEL);
923 if (ret < 0)
924 goto out;
925
926 /* re-enable FDSP clock */
927 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
928 MEM_FDSP_CLK_120_ENABLE);
bd763482
ER		 929 if (ret < 0)
930 goto out;
931
932 ret = irq_get_trigger_type(wl->irq);
933 if ((ret == IRQ_TYPE_LEVEL_LOW) || (ret == IRQ_TYPE_EDGE_FALLING)) {
934 wl1271_info("using inverted interrupt logic: %d", ret);
935 ret = wlcore_set_partition(wl,
936 &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
937 if (ret < 0)
938 goto out;
939
940 ret = wl18xx_top_reg_read(wl, TOP_FN0_CCCR_REG_32, &irq_invert);
941 if (ret < 0)
942 goto out;
943
944 irq_invert |= BIT(1);
945 ret = wl18xx_top_reg_write(wl, TOP_FN0_CCCR_REG_32, irq_invert);
946 if (ret < 0)
947 goto out;
948
949 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
950 }
6134323f
IY		 951
952out:
953 return ret;
46a1d512
LC		 954}
955
eb96f841 956static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
46a1d512 957{
23ee9bf8 958 struct wl18xx_priv *priv = wl->priv;
45777c49 959 struct wl18xx_mac_and_phy_params *params;
eb96f841 960 int ret;
46a1d512 961
45777c49
AN		 962 params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
963 if (!params) {
964 ret = -ENOMEM;
965 goto out;
966 }
967
b0f0ad39
IY		 968 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
969 if (ret < 0)
970 goto out;
971
45777c49
AN		 972 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
973 sizeof(*params), false);
eb96f841 974
b0f0ad39 975out:
45777c49 976 kfree(params);
eb96f841 977 return ret;
46a1d512
LC		 978}
979
b0f0ad39 980static int wl18xx_enable_interrupts(struct wl1271 *wl)
46a1d512 981{
f5755fe9 982 u32 event_mask, intr_mask;
b0f0ad39 983 int ret;
f5755fe9 984
e59bec16
LC		 985 event_mask = WL18XX_ACX_EVENTS_VECTOR;
986 intr_mask = WL18XX_INTR_MASK;
f5755fe9 987
b0f0ad39
IY		 988 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
989 if (ret < 0)
990 goto out;
46a1d512
LC		 991
992 wlcore_enable_interrupts(wl);
b0f0ad39
IY		 993
994 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
995 WL1271_ACX_INTR_ALL & ~intr_mask);
a8311c8a
IY		 996 if (ret < 0)
997 goto disable_interrupts;
998
999 return ret;
1000
1001disable_interrupts:
1002 wlcore_disable_interrupts(wl);
b0f0ad39
IY		 1003
1004out:
1005 return ret;
46a1d512
LC		 1006}
1007
1008static int wl18xx_boot(struct wl1271 *wl)
1009{
1010 int ret;
1011
1012 ret = wl18xx_pre_boot(wl);
1013 if (ret < 0)
1014 goto out;
1015
6134323f
IY		 1016 ret = wl18xx_pre_upload(wl);
1017 if (ret < 0)
1018 goto out;
46a1d512
LC		 1019
1020 ret = wlcore_boot_upload_firmware(wl);
1021 if (ret < 0)
1022 goto out;
1023
eb96f841
IY		 1024 ret = wl18xx_set_mac_and_phy(wl);
1025 if (ret < 0)
1026 goto out;
46a1d512 1027
c50a2825
EP		 1028 wl->event_mask = BSS_LOSS_EVENT_ID |
1029 SCAN_COMPLETE_EVENT_ID |
750e9d15 1030 RADAR_DETECTED_EVENT_ID |
c50a2825
EP		 1031 RSSI_SNR_TRIGGER_0_EVENT_ID |
1032 PERIODIC_SCAN_COMPLETE_EVENT_ID |
0b70078c 1033 PERIODIC_SCAN_REPORT_EVENT_ID |
c50a2825
EP		 1034 DUMMY_PACKET_EVENT_ID |
1035 PEER_REMOVE_COMPLETE_EVENT_ID |
1036 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1037 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1038 INACTIVE_STA_EVENT_ID |
6b70e7eb 1039 CHANNEL_SWITCH_COMPLETE_EVENT_ID |
e93e15fb
EP		 1040 DFS_CHANNELS_CONFIG_COMPLETE_EVENT |
1041 SMART_CONFIG_SYNC_EVENT_ID |
6d5c8987 1042 SMART_CONFIG_DECODE_EVENT_ID |
3719c17e
SP		 1043 TIME_SYNC_EVENT_ID |
1044 FW_LOGGER_INDICATION;
c50a2825 1045
71e996be
EP		 1046 wl->ap_event_mask = MAX_TX_FAILURE_EVENT_ID;
1047
46a1d512
LC		 1048 ret = wlcore_boot_run_firmware(wl);
1049 if (ret < 0)
1050 goto out;
1051
b0f0ad39 1052 ret = wl18xx_enable_interrupts(wl);
46a1d512
LC		 1053
1054out:
1055 return ret;
1056}
1057
eb96f841 1058static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
274c66cd
LC		 1059 void *buf, size_t len)
1060{
1061 struct wl18xx_priv *priv = wl->priv;
1062
1063 memcpy(priv->cmd_buf, buf, len);
1064 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
1065
eb96f841
IY		 1066 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
1067 WL18XX_CMD_MAX_SIZE, false);
274c66cd
LC		 1068}
1069
b0f0ad39 1070static int wl18xx_ack_event(struct wl1271 *wl)
274c66cd 1071{
b0f0ad39
IY		 1072 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1073 WL18XX_INTR_TRIG_EVENT_ACK);
274c66cd
LC		 1074}
1075
624845b3
AN		 1076static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1077{
1078 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
1079 return (len + blk_size - 1) / blk_size + spare_blks;
1080}
1081
fb0f2e4a
AN		 1082static void
1083wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1084 u32 blks, u32 spare_blks)
1085{
1086 desc->wl18xx_mem.total_mem_blocks = blks;
fb0f2e4a
AN		 1087}
1088
d2361c51
AN		 1089static void
1090wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1091 struct sk_buff *skb)
1092{
1093 desc->length = cpu_to_le16(skb->len);
1094
9fccc82e
IR		 1095 /* if only the last frame is to be padded, we unset this bit on Tx */
1096 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
1097 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
1098 else
1099 desc->wl18xx_mem.ctrl = 0;
1100
d2361c51
AN		 1101 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
1102 "len: %d life: %d mem: %d", desc->hlid,
1103 le16_to_cpu(desc->length),
1104 le16_to_cpu(desc->life_time),
1105 desc->wl18xx_mem.total_mem_blocks);
1106}
1107
9c809f88
AN		 1108static enum wl_rx_buf_align
1109wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1110{
1111 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
1112 return WLCORE_RX_BUF_PADDED;
1113
1114 return WLCORE_RX_BUF_ALIGNED;
1115}
1116
30e2dd79
AN		 1117static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1118 u32 data_len)
1119{
1120 struct wl1271_rx_descriptor *desc = rx_data;
1121
1122 /* invalid packet */
1123 if (data_len < sizeof(*desc))
1124 return 0;
1125
1126 return data_len - sizeof(*desc);
1127}
9c809f88 1128
872b345f
AN		 1129static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
1130{
1131 wl18xx_tx_immediate_complete(wl);
1132}
1133
a1c597f2 1134static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
b8422dcb
LC		 1135{
1136 int ret;
b8422dcb 1137 u32 sdio_align_size = 0;
a1c597f2
AN		 1138 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
1139 HOST_IF_CFG_ADD_RX_ALIGNMENT;
f2baf075 1140
b8422dcb
LC		 1141 /* Enable Tx SDIO padding */
1142 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
1143 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1144 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1145 }
1146
1147 /* Enable Rx SDIO padding */
1148 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1149 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
1150 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1151 }
1152
1153 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
a1c597f2 1154 sdio_align_size, extra_mem_blk,
b8422dcb
LC		 1155 WL18XX_HOST_IF_LEN_SIZE_FIELD);
1156 if (ret < 0)
1157 return ret;
1158
a1c597f2
AN		 1159 return 0;
1160}
1161
1162static int wl18xx_hw_init(struct wl1271 *wl)
1163{
1164 int ret;
1165 struct wl18xx_priv *priv = wl->priv;
1166
1167 /* (re)init private structures. Relevant on recovery as well. */
1168 priv->last_fw_rls_idx = 0;
2fd8a3bb 1169 priv->extra_spare_key_count = 0;
a1c597f2
AN		 1170
1171 /* set the default amount of spare blocks in the bitmap */
1172 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1173 if (ret < 0)
1174 return ret;
1175
d1c54096
GM		 1176 /* set the dynamic fw traces bitmap */
1177 ret = wl18xx_acx_dynamic_fw_traces(wl);
1178 if (ret < 0)
1179 return ret;
1180
102165c6
LC		 1181 if (checksum_param) {
1182 ret = wl18xx_acx_set_checksum_state(wl);
1183 if (ret != 0)
1184 return ret;
1185 }
2fc28de5 1186
b8422dcb
LC		 1187 return ret;
1188}
1189
75fb4df7
EP		 1190static void wl18xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1191 struct wl_fw_status *fw_status)
1192{
1193 struct wl18xx_fw_status *int_fw_status = raw_fw_status;
1194
1195 fw_status->intr = le32_to_cpu(int_fw_status->intr);
1196 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1197 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1198 fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1199 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1200
1201 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1202 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1203 fw_status->link_fast_bitmap =
1204 le32_to_cpu(int_fw_status->link_fast_bitmap);
1205 fw_status->total_released_blks =
1206 le32_to_cpu(int_fw_status->total_released_blks);
1207 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1208
1209 fw_status->counters.tx_released_pkts =
1210 int_fw_status->counters.tx_released_pkts;
1211 fw_status->counters.tx_lnk_free_pkts =
1212 int_fw_status->counters.tx_lnk_free_pkts;
1213 fw_status->counters.tx_voice_released_blks =
1214 int_fw_status->counters.tx_voice_released_blks;
1215 fw_status->counters.tx_last_rate =
1216 int_fw_status->counters.tx_last_rate;
1217
1218 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1219
1220 fw_status->priv = &int_fw_status->priv;
1221}
1222
2fc28de5
AN		 1223static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1224 struct wl1271_tx_hw_descr *desc,
1225 struct sk_buff *skb)
1226{
1227 u32 ip_hdr_offset;
1228 struct iphdr *ip_hdr;
1229
102165c6
LC		 1230 if (!checksum_param) {
1231 desc->wl18xx_checksum_data = 0;
1232 return;
1233 }
1234
2fc28de5
AN		 1235 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1236 desc->wl18xx_checksum_data = 0;
1237 return;
1238 }
1239
1240 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1241 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1242 desc->wl18xx_checksum_data = 0;
1243 return;
1244 }
1245
1246 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1247
1248 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
1249 ip_hdr = (void *)skb_network_header(skb);
1250 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1251}
1252
169da04f
AN		 1253static void wl18xx_set_rx_csum(struct wl1271 *wl,
1254 struct wl1271_rx_descriptor *desc,
1255 struct sk_buff *skb)
1256{
1257 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1258 skb->ip_summed = CHECKSUM_UNNECESSARY;
1259}
1260
cc31a3c9
AN		 1261static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1262{
1263 struct wl18xx_priv *priv = wl->priv;
1264
c80daad6
AN		 1265 /* only support MIMO with multiple antennas, and when SISO
1266 * is not forced through config
1267 */
1268 return (priv->conf.phy.number_of_assembled_ant2_4 >= 2) &&
1269 (priv->conf.ht.mode != HT_MODE_WIDE) &&
1270 (priv->conf.ht.mode != HT_MODE_SISO20);
cc31a3c9
AN		 1271}
1272
7ae25da3
LC		 1273/*
1274 * TODO: instead of having these two functions to get the rate mask,
1275 * we should modify the wlvif->rate_set instead
1276 */
f13af348
AN		 1277static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1278 struct wl12xx_vif *wlvif)
1279{
1280 u32 hw_rate_set = wlvif->rate_set;
1281
1282 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1283 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1284 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1285 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1286
1287 /* we don't support MIMO in wide-channel mode */
1288 hw_rate_set &= ~CONF_TX_MIMO_RATES;
cc31a3c9
AN		 1289 } else if (wl18xx_is_mimo_supported(wl)) {
1290 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1291 hw_rate_set |= CONF_TX_MIMO_RATES;
f13af348
AN		 1292 }
1293
1294 return hw_rate_set;
1295}
1296
ebc7e57d
AN		 1297static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1298 struct wl12xx_vif *wlvif)
1299{
0344dcd3
AN		 1300 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1301 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
ebc7e57d 1302 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
0344dcd3
AN		 1303
1304 /* sanity check - we don't support this */
1305 if (WARN_ON(wlvif->band != IEEE80211_BAND_5GHZ))
1306 return 0;
1307
ebc7e57d 1308 return CONF_TX_RATE_USE_WIDE_CHAN;
cc31a3c9 1309 } else if (wl18xx_is_mimo_supported(wl) &&
0344dcd3 1310 wlvif->band == IEEE80211_BAND_2GHZ) {
ebc7e57d 1311 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
0344dcd3
AN		 1312 /*
1313 * we don't care about HT channel here - if a peer doesn't
1314 * support MIMO, we won't enable it in its rates
1315 */
ebc7e57d 1316 return CONF_TX_MIMO_RATES;
174a7303
LC		 1317 } else {
1318 return 0;
ebc7e57d
AN		 1319 }
1320}
1321
1f8a1890
VG		 1322static const char *wl18xx_rdl_name(enum wl18xx_rdl_num rdl_num)
1323{
1324 switch (rdl_num) {
1325 case RDL_1_HP:
1326 return "183xH";
1327 case RDL_2_SP:
1328 return "183x or 180x";
1329 case RDL_3_HP:
1330 return "187xH";
1331 case RDL_4_SP:
1332 return "187x";
1333 case RDL_5_SP:
1334 return "RDL11 - Not Supported";
1335 case RDL_6_SP:
1336 return "180xD";
1337 case RDL_7_SP:
1338 return "RDL13 - Not Supported (1893Q)";
1339 case RDL_8_SP:
1340 return "18xxQ";
1341 case RDL_NONE:
1342 return "UNTRIMMED";
1343 default:
1344 return "UNKNOWN";
1345 }
1346}
1347
6134323f 1348static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
54956294
AN		 1349{
1350 u32 fuse;
1f8a1890 1351 s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0, package_type = 0;
6134323f 1352 int ret;
54956294 1353
b0f0ad39
IY		 1354 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1355 if (ret < 0)
1356 goto out;
54956294 1357
1f8a1890
VG		 1358 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1359 if (ret < 0)
1360 goto out;
1361
1362 package_type = (fuse >> WL18XX_PACKAGE_TYPE_OFFSET) & 1;
1363
6134323f
IY		 1364 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1365 if (ret < 0)
1366 goto out;
1367
f9ae0852
VG		 1368 pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1369 rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET;
1370
1f8a1890 1371 if ((rom <= 0xE) && (package_type == WL18XX_PACKAGE_TYPE_WSP))
f9ae0852
VG		 1372 metal = (fuse & WL18XX_METAL_VER_MASK) >>
1373 WL18XX_METAL_VER_OFFSET;
1374 else
1375 metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >>
1376 WL18XX_NEW_METAL_VER_OFFSET;
1377
1378 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1379 if (ret < 0)
1380 goto out;
1381
1382 rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET;
f9ae0852 1383
1f8a1890
VG		 1384 wl1271_info("wl18xx HW: %s, PG %d.%d (ROM 0x%x)",
1385 wl18xx_rdl_name(rdl_ver), pg_ver, metal, rom);
f9ae0852 1386
6134323f 1387 if (ver)
f9ae0852 1388 *ver = pg_ver;
54956294 1389
b0f0ad39 1390 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
54956294 1391
6134323f
IY		 1392out:
1393 return ret;
54956294
AN		 1394}
1395
640dfb9b 1396#define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
6f157edb
EP		 1397
1398static int wl18xx_load_conf_file(struct device *dev, struct wlcore_conf *conf,
1399 struct wl18xx_priv_conf *priv_conf)
23ee9bf8 1400{
640dfb9b
LC		 1401 struct wlcore_conf_file *conf_file;
1402 const struct firmware *fw;
1403 int ret;
1404
1405 ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1406 if (ret < 0) {
1407 wl1271_error("could not get configuration binary %s: %d",
1408 WL18XX_CONF_FILE_NAME, ret);
6f157edb 1409 return ret;
640dfb9b
LC		 1410 }
1411
1412 if (fw->size != WL18XX_CONF_SIZE) {
41844076
LC		 1413 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1414 WL18XX_CONF_SIZE, fw->size);
640dfb9b 1415 ret = -EINVAL;
6f157edb 1416 goto out_release;
640dfb9b
LC		 1417 }
1418
1419 conf_file = (struct wlcore_conf_file *) fw->data;
1420
1421 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1422 wl1271_error("configuration binary file magic number mismatch, "
1423 "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1424 conf_file->header.magic);
1425 ret = -EINVAL;
6f157edb 1426 goto out_release;
640dfb9b
LC		 1427 }
1428
1429 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1430 wl1271_error("configuration binary file version not supported, "
1431 "expected 0x%08x got 0x%08x",
1432 WL18XX_CONF_VERSION, conf_file->header.version);
1433 ret = -EINVAL;
6f157edb 1434 goto out_release;
640dfb9b
LC		 1435 }
1436
6f157edb
EP		 1437 memcpy(conf, &conf_file->core, sizeof(*conf));
1438 memcpy(priv_conf, &conf_file->priv, sizeof(*priv_conf));
640dfb9b 1439
6f157edb
EP		 1440out_release:
1441 release_firmware(fw);
1442 return ret;
1443}
640dfb9b 1444
6f157edb
EP		 1445static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1446{
1447 struct wl18xx_priv *priv = wl->priv;
23ee9bf8 1448
6f157edb
EP		 1449 if (wl18xx_load_conf_file(dev, &wl->conf, &priv->conf) < 0) {
1450 wl1271_warning("falling back to default config");
640dfb9b 1451
6f157edb
EP		 1452 /* apply driver default configuration */
1453 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl->conf));
1454 /* apply default private configuration */
1455 memcpy(&priv->conf, &wl18xx_default_priv_conf,
1456 sizeof(priv->conf));
1457 }
640dfb9b 1458
6f157edb 1459 return 0;
23ee9bf8
LC		 1460}
1461
be42aee6
LC		 1462static int wl18xx_plt_init(struct wl1271 *wl)
1463{
b0f0ad39
IY		 1464 int ret;
1465
16bc10c3
YS		 1466 /* calibrator based auto/fem detect not supported for 18xx */
1467 if (wl->plt_mode == PLT_FEM_DETECT) {
1468 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1469 return -EINVAL;
1470 }
1471
b0f0ad39
IY		 1472 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1473 if (ret < 0)
1474 return ret;
be42aee6
LC		 1475
1476 return wl->ops->boot(wl);
1477}
1478
6134323f 1479static int wl18xx_get_mac(struct wl1271 *wl)
a5114d9c
LC		 1480{
1481 u32 mac1, mac2;
6134323f 1482 int ret;
a5114d9c 1483
b0f0ad39
IY		 1484 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1485 if (ret < 0)
1486 goto out;
a5114d9c 1487
6134323f
IY		 1488 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1489 if (ret < 0)
1490 goto out;
1491
1492 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1493 if (ret < 0)
1494 goto out;
a5114d9c
LC		 1495
1496 /* these are the two parts of the BD_ADDR */
1497 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1498 ((mac1 & 0xff000000) >> 24);
1499 wl->fuse_nic_addr = (mac1 & 0xffffff);
1500
bc2ab3b8
LC		 1501 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) {
1502 u8 mac[ETH_ALEN];
1503
1504 eth_random_addr(mac);
1505
1506 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2];
1507 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5];
1508 wl1271_warning("MAC address from fuse not available, using random locally administered addresses.");
1509 }
1510
b0f0ad39 1511 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
6134323f
IY		 1512
1513out:
1514 return ret;
a5114d9c
LC		 1515}
1516
283e8c42
LC		 1517static int wl18xx_handle_static_data(struct wl1271 *wl,
1518 struct wl1271_static_data *static_data)
1519{
1520 struct wl18xx_static_data_priv *static_data_priv =
1521 (struct wl18xx_static_data_priv *) static_data->priv;
1522
1defbeb0
YS		 1523 strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1524 sizeof(wl->chip.phy_fw_ver_str));
1525
1526 /* make sure the string is NULL-terminated */
1527 wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0';
1528
283e8c42
LC		 1529 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1530
1531 return 0;
1532}
1533
32bb2c03
AN		 1534static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1535{
a1c597f2
AN		 1536 struct wl18xx_priv *priv = wl->priv;
1537
2fd8a3bb
AN		 1538 /* If we have keys requiring extra spare, indulge them */
1539 if (priv->extra_spare_key_count)
a1c597f2
AN		 1540 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1541
1542 return WL18XX_TX_HW_BLOCK_SPARE;
1543}
1544
1545static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1546 struct ieee80211_vif *vif,
1547 struct ieee80211_sta *sta,
1548 struct ieee80211_key_conf *key_conf)
1549{
1550 struct wl18xx_priv *priv = wl->priv;
2fd8a3bb 1551 bool change_spare = false, special_enc;
a1c597f2
AN		 1552 int ret;
1553
2fd8a3bb
AN		 1554 wl1271_debug(DEBUG_CRYPT, "extra spare keys before: %d",
1555 priv->extra_spare_key_count);
1556
1557 special_enc = key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1558 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP;
1559
1560 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1561 if (ret < 0)
1562 goto out;
1563
a1c597f2 1564 /*
2fd8a3bb 1565 * when adding the first or removing the last GEM/TKIP key,
a1c597f2
AN		 1566 * we have to adjust the number of spare blocks.
1567 */
2fd8a3bb
AN		 1568 if (special_enc) {
1569 if (cmd == SET_KEY) {
1570 /* first key */
1571 change_spare = (priv->extra_spare_key_count == 0);
1572 priv->extra_spare_key_count++;
1573 } else if (cmd == DISABLE_KEY) {
1574 /* last key */
1575 change_spare = (priv->extra_spare_key_count == 1);
1576 priv->extra_spare_key_count--;
1577 }
1578 }
a1c597f2 1579
2fd8a3bb
AN		 1580 wl1271_debug(DEBUG_CRYPT, "extra spare keys after: %d",
1581 priv->extra_spare_key_count);
a1c597f2 1582
2fd8a3bb 1583 if (!change_spare)
a1c597f2
AN		 1584 goto out;
1585
1586 /* key is now set, change the spare blocks */
2fd8a3bb 1587 if (priv->extra_spare_key_count)
a1c597f2
AN		 1588 ret = wl18xx_set_host_cfg_bitmap(wl,
1589 WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
2fd8a3bb 1590 else
a1c597f2
AN		 1591 ret = wl18xx_set_host_cfg_bitmap(wl,
1592 WL18XX_TX_HW_BLOCK_SPARE);
a1c597f2
AN		 1593
1594out:
a1c597f2 1595 return ret;
32bb2c03
AN		 1596}
1597
9fccc82e
IR		 1598static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1599 u32 buf_offset, u32 last_len)
1600{
1601 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1602 struct wl1271_tx_hw_descr *last_desc;
1603
1604 /* get the last TX HW descriptor written to the aggr buf */
1605 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1606 buf_offset - last_len);
1607
1608 /* the last frame is padded up to an SDIO block */
1609 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1610 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1611 }
1612
1613 /* no modifications */
1614 return buf_offset;
1615}
1616
5f9b6777 1617static void wl18xx_sta_rc_update(struct wl1271 *wl,
7d3b29e5 1618 struct wl12xx_vif *wlvif)
5f9b6777 1619{
7d3b29e5 1620 bool wide = wlvif->rc_update_bw >= IEEE80211_STA_RX_BW_40;
5f9b6777
AN		 1621
1622 wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update wide %d", wide);
1623
5f9b6777
AN		 1624 /* sanity */
1625 if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS))
7d3b29e5 1626 return;
5f9b6777
AN		 1627
1628 /* ignore the change before association */
1629 if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags))
7d3b29e5 1630 return;
5f9b6777
AN		 1631
1632 /*
1633 * If we started out as wide, we can change the operation mode. If we
1634 * thought this was a 20mhz AP, we have to reconnect
1635 */
1636 if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS ||
1637 wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS)
1638 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1639 else
1640 ieee80211_connection_loss(wl12xx_wlvif_to_vif(wlvif));
5f9b6777
AN		 1641}
1642
530abe19
EP		 1643static int wl18xx_set_peer_cap(struct wl1271 *wl,
1644 struct ieee80211_sta_ht_cap *ht_cap,
1645 bool allow_ht_operation,
1646 u32 rate_set, u8 hlid)
1647{
1648 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1649 rate_set, hlid);
1650}
5f9b6777 1651
f1626fd8
AN		 1652static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1653 struct wl1271_link *lnk)
1654{
1655 u8 thold;
1656 struct wl18xx_fw_status_priv *status_priv =
75fb4df7 1657 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
5e74b3aa 1658 unsigned long suspend_bitmap;
9bccb8ae
EP		 1659
1660 /* if we don't have the link map yet, assume they all low prio */
1661 if (!status_priv)
1662 return false;
f1626fd8
AN		 1663
1664 /* suspended links are never high priority */
9bccb8ae 1665 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
5e74b3aa 1666 if (test_bit(hlid, &suspend_bitmap))
f1626fd8
AN		 1667 return false;
1668
1669 /* the priority thresholds are taken from FW */
5e74b3aa
EP		 1670 if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1671 !test_bit(hlid, &wl->ap_fw_ps_map))
f1626fd8
AN		 1672 thold = status_priv->tx_fast_link_prio_threshold;
1673 else
1674 thold = status_priv->tx_slow_link_prio_threshold;
1675
1676 return lnk->allocated_pkts < thold;
1677}
1678
1679static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1680 struct wl1271_link *lnk)
1681{
1682 u8 thold;
1683 struct wl18xx_fw_status_priv *status_priv =
75fb4df7 1684 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
5e74b3aa 1685 unsigned long suspend_bitmap;
9bccb8ae
EP		 1686
1687 /* if we don't have the link map yet, assume they all low prio */
1688 if (!status_priv)
1689 return true;
f1626fd8 1690
9bccb8ae 1691 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
5e74b3aa 1692 if (test_bit(hlid, &suspend_bitmap))
f1626fd8 1693 thold = status_priv->tx_suspend_threshold;
5e74b3aa
EP		 1694 else if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1695 !test_bit(hlid, &wl->ap_fw_ps_map))
f1626fd8
AN		 1696 thold = status_priv->tx_fast_stop_threshold;
1697 else
1698 thold = status_priv->tx_slow_stop_threshold;
1699
1700 return lnk->allocated_pkts < thold;
1701}
1702
c83cb803
IC		 1703static u32 wl18xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1704{
1705 return hwaddr & ~0x80000000;
1706}
1707
3992eb2b
IY		 1708static int wl18xx_setup(struct wl1271 *wl);
1709
0cd6543f 1710static struct wlcore_ops wl18xx_ops = {
3992eb2b 1711 .setup = wl18xx_setup,
46a1d512
LC		 1712 .identify_chip = wl18xx_identify_chip,
1713 .boot = wl18xx_boot,
be42aee6 1714 .plt_init = wl18xx_plt_init,
274c66cd
LC		 1715 .trigger_cmd = wl18xx_trigger_cmd,
1716 .ack_event = wl18xx_ack_event,
c50a2825
EP		 1717 .wait_for_event = wl18xx_wait_for_event,
1718 .process_mailbox_events = wl18xx_process_mailbox_events,
624845b3 1719 .calc_tx_blocks = wl18xx_calc_tx_blocks,
fb0f2e4a 1720 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
d2361c51 1721 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
9c809f88 1722 .get_rx_buf_align = wl18xx_get_rx_buf_align,
30e2dd79 1723 .get_rx_packet_len = wl18xx_get_rx_packet_len,
872b345f
AN		 1724 .tx_immediate_compl = wl18xx_tx_immediate_completion,
1725 .tx_delayed_compl = NULL,
b8422dcb 1726 .hw_init = wl18xx_hw_init,
75fb4df7 1727 .convert_fw_status = wl18xx_convert_fw_status,
2fc28de5 1728 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
54956294 1729 .get_pg_ver = wl18xx_get_pg_ver,
169da04f 1730 .set_rx_csum = wl18xx_set_rx_csum,
f13af348 1731 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
ebc7e57d 1732 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
a5114d9c 1733 .get_mac = wl18xx_get_mac,
ad62d81a 1734 .debugfs_init = wl18xx_debugfs_add_files,
78e28062
EP		 1735 .scan_start = wl18xx_scan_start,
1736 .scan_stop = wl18xx_scan_stop,
78e28062
EP		 1737 .sched_scan_start = wl18xx_sched_scan_start,
1738 .sched_scan_stop = wl18xx_scan_sched_scan_stop,
283e8c42 1739 .handle_static_data = wl18xx_handle_static_data,
32bb2c03 1740 .get_spare_blocks = wl18xx_get_spare_blocks,
a1c597f2 1741 .set_key = wl18xx_set_key,
fcab1890 1742 .channel_switch = wl18xx_cmd_channel_switch,
9fccc82e 1743 .pre_pkt_send = wl18xx_pre_pkt_send,
5f9b6777 1744 .sta_rc_update = wl18xx_sta_rc_update,
530abe19 1745 .set_peer_cap = wl18xx_set_peer_cap,
c83cb803 1746 .convert_hwaddr = wl18xx_convert_hwaddr,
f1626fd8
AN		 1747 .lnk_high_prio = wl18xx_lnk_high_prio,
1748 .lnk_low_prio = wl18xx_lnk_low_prio,
ccb1df94
EP		 1749 .smart_config_start = wl18xx_cmd_smart_config_start,
1750 .smart_config_stop = wl18xx_cmd_smart_config_stop,
1751 .smart_config_set_group_key = wl18xx_cmd_smart_config_set_group_key,
6d5a748d
RA		 1752 .interrupt_notify = wl18xx_acx_interrupt_notify_config,
1753 .rx_ba_filter = wl18xx_acx_rx_ba_filter,
e2f1e50f 1754 .ap_sleep = wl18xx_acx_ap_sleep,
750e9d15 1755 .set_cac = wl18xx_cmd_set_cac,
830513ab 1756 .dfs_master_restart = wl18xx_cmd_dfs_master_restart,
0cd6543f
LC		 1757};
1758
93fb19bb
AN		 1759/* HT cap appropriate for wide channels in 2Ghz */
1760static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
0e0f5a3b 1761 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
0330ee1f
EP		 1762 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40 |
1763 IEEE80211_HT_CAP_GRN_FLD,
0e0f5a3b
AN		 1764 .ht_supported = true,
1765 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1766 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1767 .mcs = {
1768 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1769 .rx_highest = cpu_to_le16(150),
1770 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1771 },
1772};
1773
93fb19bb
AN		 1774/* HT cap appropriate for wide channels in 5Ghz */
1775static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1776 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
0330ee1f
EP		 1777 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1778 IEEE80211_HT_CAP_GRN_FLD,
93fb19bb
AN		 1779 .ht_supported = true,
1780 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1781 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1782 .mcs = {
1783 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1784 .rx_highest = cpu_to_le16(150),
1785 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1786 },
1787};
1788
83342718
LC		 1789/* HT cap appropriate for SISO 20 */
1790static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
0330ee1f
EP		 1791 .cap = IEEE80211_HT_CAP_SGI_20 |
1792 IEEE80211_HT_CAP_GRN_FLD,
83342718
LC		 1793 .ht_supported = true,
1794 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1795 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1796 .mcs = {
1797 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1798 .rx_highest = cpu_to_le16(72),
1799 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1800 },
1801};
1802
3a8ddb61 1803/* HT cap appropriate for MIMO rates in 20mhz channel */
bfb92ca1 1804static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
0330ee1f
EP		 1805 .cap = IEEE80211_HT_CAP_SGI_20 |
1806 IEEE80211_HT_CAP_GRN_FLD,
3a8ddb61
AN		 1807 .ht_supported = true,
1808 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1809 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1810 .mcs = {
1811 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1812 .rx_highest = cpu_to_le16(144),
1813 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1814 },
1815};
1816
abf0b249
EP		 1817static const struct ieee80211_iface_limit wl18xx_iface_limits[] = {
1818 {
7845af35 1819 .max = 2,
abf0b249
EP		 1820 .types = BIT(NL80211_IFTYPE_STATION),
1821 },
1822 {
1823 .max = 1,
1824 .types = BIT(NL80211_IFTYPE_AP) |
1825 BIT(NL80211_IFTYPE_P2P_GO) |
1826 BIT(NL80211_IFTYPE_P2P_CLIENT),
1827 },
7845af35
EP		 1828 {
1829 .max = 1,
1830 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1831 },
abf0b249
EP		 1832};
1833
1834static const struct ieee80211_iface_limit wl18xx_iface_ap_limits[] = {
1835 {
1836 .max = 2,
1837 .types = BIT(NL80211_IFTYPE_AP),
1838 },
7845af35
EP		 1839 {
1840 .max = 1,
1841 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1842 },
1843};
1844
1845static const struct ieee80211_iface_limit wl18xx_iface_ap_cl_limits[] = {
1846 {
1847 .max = 1,
1848 .types = BIT(NL80211_IFTYPE_STATION),
1849 },
1850 {
1851 .max = 1,
1852 .types = BIT(NL80211_IFTYPE_AP),
1853 },
1854 {
1855 .max = 1,
1856 .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
1857 },
1858 {
1859 .max = 1,
1860 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1861 },
1862};
1863
1864static const struct ieee80211_iface_limit wl18xx_iface_ap_go_limits[] = {
1865 {
1866 .max = 1,
1867 .types = BIT(NL80211_IFTYPE_STATION),
1868 },
1869 {
1870 .max = 1,
1871 .types = BIT(NL80211_IFTYPE_AP),
1872 },
1873 {
1874 .max = 1,
1875 .types = BIT(NL80211_IFTYPE_P2P_GO),
1876 },
1877 {
1878 .max = 1,
1879 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1880 },
abf0b249
EP		 1881};
1882
1883static const struct ieee80211_iface_combination
1884wl18xx_iface_combinations[] = {
1885 {
1886 .max_interfaces = 3,
1887 .limits = wl18xx_iface_limits,
1888 .n_limits = ARRAY_SIZE(wl18xx_iface_limits),
1889 .num_different_channels = 2,
1890 },
1891 {
1892 .max_interfaces = 2,
1893 .limits = wl18xx_iface_ap_limits,
1894 .n_limits = ARRAY_SIZE(wl18xx_iface_ap_limits),
1895 .num_different_channels = 1,
86f2db86
EP		 1896 .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
1897 BIT(NL80211_CHAN_HT20) |
1898 BIT(NL80211_CHAN_HT40MINUS) |
1899 BIT(NL80211_CHAN_HT40PLUS),
abf0b249
EP		 1900 }
1901};
1902
3992eb2b 1903static int wl18xx_setup(struct wl1271 *wl)
9a1a6990 1904{
3992eb2b 1905 struct wl18xx_priv *priv = wl->priv;
640dfb9b 1906 int ret;
9a1a6990 1907
da08fdfa 1908 BUILD_BUG_ON(WL18XX_MAX_LINKS > WLCORE_MAX_LINKS);
32f0fd5b 1909 BUILD_BUG_ON(WL18XX_MAX_AP_STATIONS > WL18XX_MAX_LINKS);
133b7326 1910 BUILD_BUG_ON(WL18XX_CONF_SG_PARAMS_MAX > WLCORE_CONF_SG_PARAMS_MAX);
da08fdfa 1911
5d4a9fa6 1912 wl->rtable = wl18xx_rtable;
f1c434df 1913 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
c91ec5f3 1914 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS;
da08fdfa 1915 wl->num_links = WL18XX_MAX_LINKS;
32f0fd5b 1916 wl->max_ap_stations = WL18XX_MAX_AP_STATIONS;
abf0b249
EP		 1917 wl->iface_combinations = wl18xx_iface_combinations;
1918 wl->n_iface_combinations = ARRAY_SIZE(wl18xx_iface_combinations);
f4afbed9 1919 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
f648eab7
AN		 1920 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1921 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1922 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
75fb4df7 1923 wl->fw_status_len = sizeof(struct wl18xx_fw_status);
1fab39dc 1924 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
8c0ea102 1925 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
283e8c42 1926 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
83342718 1927
09aad14f
AN		 1928 if (num_rx_desc_param != -1)
1929 wl->num_rx_desc = num_rx_desc_param;
1930
3992eb2b 1931 ret = wl18xx_conf_init(wl, wl->dev);
640dfb9b 1932 if (ret < 0)
3992eb2b 1933 return ret;
776f030a 1934
c68cc0f6
YS		 1935 /* If the module param is set, update it in conf */
1936 if (board_type_param) {
1937 if (!strcmp(board_type_param, "fpga")) {
1938 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1939 } else if (!strcmp(board_type_param, "hdk")) {
1940 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1941 } else if (!strcmp(board_type_param, "dvp")) {
1942 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1943 } else if (!strcmp(board_type_param, "evb")) {
1944 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1945 } else if (!strcmp(board_type_param, "com8")) {
1946 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1947 } else {
1948 wl1271_error("invalid board type '%s'",
1949 board_type_param);
3992eb2b 1950 return -EINVAL;
c68cc0f6
YS		 1951 }
1952 }
1953
e1c497c3 1954 if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
c68cc0f6
YS		 1955 wl1271_error("invalid board type '%d'",
1956 priv->conf.phy.board_type);
3992eb2b 1957 return -EINVAL;
a9c130d5
LC		 1958 }
1959
17d97719
AN		 1960 if (low_band_component_param != -1)
1961 priv->conf.phy.low_band_component = low_band_component_param;
1962 if (low_band_component_type_param != -1)
858403ab 1963 priv->conf.phy.low_band_component_type =
17d97719
AN		 1964 low_band_component_type_param;
1965 if (high_band_component_param != -1)
1966 priv->conf.phy.high_band_component = high_band_component_param;
1967 if (high_band_component_type_param != -1)
858403ab 1968 priv->conf.phy.high_band_component_type =
17d97719
AN		 1969 high_band_component_type_param;
1970 if (pwr_limit_reference_11_abg_param != -1)
7b03c306 1971 priv->conf.phy.pwr_limit_reference_11_abg =
17d97719
AN		 1972 pwr_limit_reference_11_abg_param;
1973 if (n_antennas_2_param != -1)
1974 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1975 if (n_antennas_5_param != -1)
1976 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1977 if (dc2dc_param != -1)
1978 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
7b03c306 1979
c68cc0f6
YS		 1980 if (ht_mode_param) {
1981 if (!strcmp(ht_mode_param, "default"))
1982 priv->conf.ht.mode = HT_MODE_DEFAULT;
1983 else if (!strcmp(ht_mode_param, "wide"))
1984 priv->conf.ht.mode = HT_MODE_WIDE;
1985 else if (!strcmp(ht_mode_param, "siso20"))
1986 priv->conf.ht.mode = HT_MODE_SISO20;
1987 else {
1988 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
3992eb2b 1989 return -EINVAL;
c68cc0f6
YS		 1990 }
1991 }
1992
1993 if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
fa2adfcd
AN		 1994 /*
1995 * Only support mimo with multiple antennas. Fall back to
8c5dab1a 1996 * siso40.
fa2adfcd 1997 */
cc31a3c9 1998 if (wl18xx_is_mimo_supported(wl))
fa2adfcd
AN		 1999 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
2000 &wl18xx_mimo_ht_cap_2ghz);
2001 else
2002 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
8c5dab1a 2003 &wl18xx_siso40_ht_cap_2ghz);
fa2adfcd
AN		 2004
2005 /* 5Ghz is always wide */
2006 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
93fb19bb 2007 &wl18xx_siso40_ht_cap_5ghz);
c68cc0f6 2008 } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
fa2adfcd 2009 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
93fb19bb 2010 &wl18xx_siso40_ht_cap_2ghz);
fa2adfcd 2011 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
93fb19bb 2012 &wl18xx_siso40_ht_cap_5ghz);
c68cc0f6 2013 } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
fa2adfcd
AN		 2014 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
2015 &wl18xx_siso20_ht_cap);
2016 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
2017 &wl18xx_siso20_ht_cap);
fa2adfcd
AN		 2018 }
2019
102165c6
LC		 2020 if (!checksum_param) {
2021 wl18xx_ops.set_rx_csum = NULL;
2022 wl18xx_ops.init_vif = NULL;
2023 }
2024
e166de55
YS		 2025 /* Enable 11a Band only if we have 5G antennas */
2026 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
1ddbc7d4 2027
3992eb2b
IY		 2028 return 0;
2029}
2030
b74324d1 2031static int wl18xx_probe(struct platform_device *pdev)
3992eb2b
IY		 2032{
2033 struct wl1271 *wl;
2034 struct ieee80211_hw *hw;
2035 int ret;
2036
2037 hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
c50a2825
EP		 2038 WL18XX_AGGR_BUFFER_SIZE,
2039 sizeof(struct wl18xx_event_mailbox));
3992eb2b
IY		 2040 if (IS_ERR(hw)) {
2041 wl1271_error("can't allocate hw");
2042 ret = PTR_ERR(hw);
2043 goto out;
2044 }
2045
2046 wl = hw->priv;
2047 wl->ops = &wl18xx_ops;
2048 wl->ptable = wl18xx_ptable;
2049 ret = wlcore_probe(wl, pdev);
2050 if (ret)
2051 goto out_free;
2052
2053 return ret;
83342718
LC		 2054
2055out_free:
2056 wlcore_free_hw(wl);
640dfb9b
LC		 2057out:
2058 return ret;
9a1a6990
LC		 2059}
2060
b74324d1 2061static const struct platform_device_id wl18xx_id_table[] = {
9a1a6990
LC		 2062 { "wl18xx", 0 },
2063 { } /* Terminating Entry */
2064};
2065MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
2066
2067static struct platform_driver wl18xx_driver = {
2068 .probe = wl18xx_probe,
b74324d1 2069 .remove = wlcore_remove,
9a1a6990
LC		 2070 .id_table = wl18xx_id_table,
2071 .driver = {
2072 .name = "wl18xx_driver",
9a1a6990
LC		 2073 }
2074};
2075
77e7b30b 2076module_platform_driver(wl18xx_driver);
3a8ddb61 2077module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
fa2adfcd 2078MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
3a8ddb61 2079
a9c130d5 2080module_param_named(board_type, board_type_param, charp, S_IRUSR);
4b9d2365
LC		 2081MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
2082 "dvp");
a9c130d5 2083
102165c6 2084module_param_named(checksum, checksum_param, bool, S_IRUSR);
3d62eb5a 2085MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
102165c6 2086
17d97719
AN		 2087module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
2088MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
2089
2090module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
2091MODULE_PARM_DESC(n_antennas_2,
2092 "Number of installed 2.4GHz antennas: 1 (default) or 2");
2093
2094module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
2095MODULE_PARM_DESC(n_antennas_5,
2096 "Number of installed 5GHz antennas: 1 (default) or 2");
2097
2098module_param_named(low_band_component, low_band_component_param, int,
2099 S_IRUSR);
858403ab
LC		 2100MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
2101 "(default is 0x01)");
2102
17d97719
AN		 2103module_param_named(low_band_component_type, low_band_component_type_param,
2104 int, S_IRUSR);
858403ab
LC		 2105MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
2106 "(default is 0x05 or 0x06 depending on the board_type)");
2107
17d97719
AN		 2108module_param_named(high_band_component, high_band_component_param, int,
2109 S_IRUSR);
858403ab
LC		 2110MODULE_PARM_DESC(high_band_component, "High band component: u8, "
2111 "(default is 0x01)");
2112
17d97719
AN		 2113module_param_named(high_band_component_type, high_band_component_type_param,
2114 int, S_IRUSR);
858403ab
LC		 2115MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
2116 "(default is 0x09)");
2117
17d97719
AN		 2118module_param_named(pwr_limit_reference_11_abg,
2119 pwr_limit_reference_11_abg_param, int, S_IRUSR);
7b03c306
LC		 2120MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
2121 "(default is 0xc8)");
2122
09aad14f
AN		 2123module_param_named(num_rx_desc,
2124 num_rx_desc_param, int, S_IRUSR);
2125MODULE_PARM_DESC(num_rx_desc_param,
2126 "Number of Rx descriptors: u8 (default is 32)");
2127
9a1a6990
LC		 2128MODULE_LICENSE("GPL v2");
2129MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
0cd6543f 2130MODULE_FIRMWARE(WL18XX_FW_NAME);
76ea6fdb 2131MODULE_FIRMWARE(WL18XX_CONF_FILE_NAME);
Linux kernel - Deliverables
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