projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5d4a9fa6 LC |
1 | /* |
| 2 | * This file is part of wlcore | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Texas Instruments Inc. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License | |
| 8 | * version 2 as published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, but | |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 13 | * General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
| 18 | * 02110-1301 USA | |
| 19 | * | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __REG_H__ | |
| 23 | #define __REG_H__ | |
| 24 | ||
| 25 | #define WL18XX_REGISTERS_BASE 0x00800000 | |
| 26 | #define WL18XX_CODE_BASE 0x00000000 | |
| 27 | #define WL18XX_DATA_BASE 0x00400000 | |
| 28 | #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000 | |
| 29 | #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000 | |
| 30 | #define WL18XX_PHY_BASE 0x00900000 | |
| 31 | #define WL18XX_TOP_OCP_BASE 0x00A00000 | |
| 32 | #define WL18XX_PACKET_RAM_BASE 0x00B00000 | |
| 33 | #define WL18XX_HOST_BASE 0x00C00000 | |
| 34 | ||
| 35 | #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000 | |
| 36 | ||
| 37 | #define WL18XX_REG_BOOT_PART_START 0x00802000 | |
| 38 | #define WL18XX_REG_BOOT_PART_SIZE 0x00014578 | |
| 39 | ||
| 40 | #define WL18XX_PHY_INIT_MEM_ADDR 0x80926000 | |
| 41 | ||
| 42 | #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE) | |
| 43 | #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000) | |
| 44 | #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000) | |
| 45 | #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000) | |
| 46 | #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000) | |
| 47 | #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000) | |
| 48 | #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000) | |
| 49 | #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000) | |
| 50 | #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000) | |
| 51 | #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000) | |
| 52 | #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800) | |
| 53 | #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00) | |
| 54 | #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000) | |
| 55 | #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400) | |
| 56 | ||
| 57 | #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004) | |
| 58 | #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8) | |
| 59 | #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0) | |
| 60 | #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074) | |
| 61 | #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078) | |
| 62 | #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC) | |
| 63 | ||
| 64 | #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C) | |
| 65 | ||
| 66 | #define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018) | |
| 67 | #define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008) | |
| 68 | ||
| 69 | /* Scratch Pad registers*/ | |
| 70 | #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC) | |
| 71 | #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0) | |
| 72 | #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4) | |
| 73 | #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8) | |
| 74 | #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC) | |
| 75 | #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504) | |
| 76 | #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500) | |
| 77 | #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508) | |
| 78 | #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510) | |
| 79 | #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C) | |
| 80 | #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514) | |
| 81 | #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518) | |
| 82 | #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C) | |
| 83 | #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520) | |
| 84 | ||
| 85 | /* Spare registers*/ | |
| 86 | #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194) | |
| 87 | #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198) | |
| 88 | #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C) | |
| 89 | #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0) | |
| 90 | #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4) | |
| 91 | #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8) | |
| 92 | #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC) | |
| 93 | #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0) | |
| 94 | #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524) | |
| 95 | #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528) | |
| 96 | #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C) | |
| 97 | #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530) | |
| 98 | #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534) | |
| 99 | #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538) | |
| 100 | #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C) | |
| 101 | #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540) | |
| 102 | ||
| 103 | #define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0) | |
| 104 | #define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1) | |
| 46a1d512 LC |
105 | #define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4) |
| 106 | ||
| 107 | #define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100) | |
| 108 | #define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C) | |
| 5d4a9fa6 LC |
109 | |
| 110 | #define WL18XX_CMD_MBOX_ADDRESS 0xB007B4 | |
| 111 | ||
| 112 | #define WL18XX_FW_STATUS_ADDR 0x50F8 | |
| 113 | ||
| 114 | #define CHIP_ID_185x_PG10 (0x06030101) | |
| 115 | ||
| 274c66cd LC |
116 | /* |
| 117 | * Host Command Interrupt. Setting this bit masks | |
| 118 | * the interrupt that the host issues to inform | |
| 119 | * the FW that it has sent a command | |
| 120 | * to the Wlan hardware Command Mailbox. | |
| 121 | */ | |
| 122 | #define WL18XX_INTR_TRIG_CMD BIT(28) | |
| 123 | ||
| 124 | /* | |
| 125 | * Host Event Acknowlegde Interrupt. The host | |
| 126 | * sets this bit to acknowledge that it received | |
| 127 | * the unsolicited information from the event | |
| 128 | * mailbox. | |
| 129 | */ | |
| 130 | #define WL18XX_INTR_TRIG_EVENT_ACK BIT(29) | |
| 131 | ||
| 46a1d512 LC |
132 | /* TODO: maybe move elsewhere? */ |
| 133 | #define NUM_OF_CHANNELS_11_ABG 150 | |
| 134 | #define NUM_OF_CHANNELS_11_P 7 | |
| 135 | #define WL18XX_NUM_OF_SUB_BANDS 9 | |
| 136 | #define SRF_TABLE_LEN 16 | |
| 137 | #define PIN_MUXING_SIZE 2 | |
| 138 | ||
| 139 | enum { | |
| 140 | COMPONENT_NO_SWITCH = 0x0, | |
| 141 | COMPONENT_2_WAY_SWITCH = 0x1, | |
| 142 | COMPONENT_3_WAY_SWITCH = 0x2, | |
| 143 | COMPONENT_MATCHING = 0x3, | |
| 144 | }; | |
| 145 | ||
| 146 | enum { | |
| 147 | FEM_NONE = 0x0, | |
| 148 | FEM_VENDOR_1 = 0x1, | |
| 149 | FEM_VENDOR_2 = 0x2, | |
| 150 | FEM_VENDOR_3 = 0x3, | |
| 151 | }; | |
| 152 | ||
| 153 | enum { | |
| 154 | BOARD_TYPE_FPGA_18XX = 0, | |
| 155 | BOARD_TYPE_HDK_18XX = 1, | |
| 156 | BOARD_TYPE_DVP_EVB_18XX = 2, | |
| 157 | }; | |
| 158 | ||
| 159 | struct wl18xx_mac_and_phy_params { | |
| 160 | u8 phy_standalone; | |
| 161 | u8 rdl; | |
| 162 | u8 enable_clpc; | |
| 163 | u8 enable_tx_low_pwr_on_siso_rdl; | |
| 164 | u8 auto_detect; | |
| 165 | u8 dedicated_fem; | |
| 166 | ||
| 167 | u8 low_band_component; | |
| 168 | ||
| 169 | /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ | |
| 170 | u8 low_band_component_type; | |
| 171 | ||
| 172 | u8 high_band_component; | |
| 173 | ||
| 174 | /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ | |
| 175 | u8 high_band_component_type; | |
| 176 | u8 number_of_assembled_ant2_4; | |
| 177 | u8 number_of_assembled_ant5; | |
| 178 | u8 pin_muxing_platform_options[PIN_MUXING_SIZE]; | |
| 179 | u8 external_pa_dc2dc; | |
| 180 | u8 tcxo_ldo_voltage; | |
| 181 | u8 xtal_itrim_val; | |
| 182 | u8 srf_state; | |
| 183 | u8 srf1[SRF_TABLE_LEN]; | |
| 184 | u8 srf2[SRF_TABLE_LEN]; | |
| 185 | u8 srf3[SRF_TABLE_LEN]; | |
| 186 | u8 io_configuration; | |
| 187 | u8 sdio_configuration; | |
| 188 | u8 settings; | |
| 189 | u8 rx_profile; | |
| 190 | u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG]; | |
| 191 | u8 pwr_limit_reference_11_abg; | |
| 192 | u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P]; | |
| 193 | u8 pwr_limit_reference_11p; | |
| 194 | u8 per_sub_band_tx_trace_loss[WL18XX_NUM_OF_SUB_BANDS]; | |
| 195 | u8 per_sub_band_rx_trace_loss[WL18XX_NUM_OF_SUB_BANDS]; | |
| 196 | u8 primary_clock_setting_time; | |
| 197 | u8 clock_valid_on_wake_up; | |
| 198 | u8 secondary_clock_setting_time; | |
| 199 | u8 board_type; | |
| 200 | u8 padding[1]; | |
| 201 | } __packed; | |
| 202 | ||
| 5d4a9fa6 | 203 | #endif /* __REG_H__ */ |