Commit | Line | Data |
---|---|---|
f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
1937e742 | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
f5fc0f86 LC |
6 | * |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
00d20100 SL |
25 | #ifndef __ACX_H__ |
26 | #define __ACX_H__ | |
f5fc0f86 | 27 | |
c31be25a | 28 | #include "wlcore.h" |
00d20100 | 29 | #include "cmd.h" |
f5fc0f86 LC |
30 | |
31 | /************************************************************************* | |
32 | ||
33 | Host Interrupt Register (WiLink -> Host) | |
34 | ||
35 | **************************************************************************/ | |
36 | /* HW Initiated interrupt Watchdog timer expiration */ | |
37 | #define WL1271_ACX_INTR_WATCHDOG BIT(0) | |
38 | /* Init sequence is done (masked interrupt, detection through polling only ) */ | |
39 | #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1) | |
40 | /* Event was entered to Event MBOX #A*/ | |
41 | #define WL1271_ACX_INTR_EVENT_A BIT(2) | |
42 | /* Event was entered to Event MBOX #B*/ | |
43 | #define WL1271_ACX_INTR_EVENT_B BIT(3) | |
44 | /* Command processing completion*/ | |
45 | #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4) | |
46 | /* Signaling the host on HW wakeup */ | |
47 | #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5) | |
48 | /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ | |
49 | #define WL1271_ACX_INTR_DATA BIT(6) | |
e8a8b252 | 50 | /* Trace message on MBOX #A */ |
f5fc0f86 | 51 | #define WL1271_ACX_INTR_TRACE_A BIT(7) |
e8a8b252 | 52 | /* Trace message on MBOX #B */ |
f5fc0f86 | 53 | #define WL1271_ACX_INTR_TRACE_B BIT(8) |
f5755fe9 IR |
54 | /* SW FW Initiated interrupt Watchdog timer expiration */ |
55 | #define WL1271_ACX_SW_INTR_WATCHDOG BIT(9) | |
f5fc0f86 | 56 | |
f5755fe9 | 57 | #define WL1271_ACX_INTR_ALL 0xFFFFFFFF |
f5fc0f86 | 58 | |
f5755fe9 IR |
59 | /* all possible interrupts - only appropriate ones will be masked in */ |
60 | #define WLCORE_ALL_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ | |
61 | WL1271_ACX_INTR_EVENT_A | \ | |
62 | WL1271_ACX_INTR_EVENT_B | \ | |
63 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
64 | WL1271_ACX_INTR_DATA | \ | |
65 | WL1271_ACX_SW_INTR_WATCHDOG) | |
f5fc0f86 LC |
66 | |
67 | /* Target's information element */ | |
68 | struct acx_header { | |
69 | struct wl1271_cmd_header cmd; | |
70 | ||
71 | /* acx (or information element) header */ | |
d0f63b20 | 72 | __le16 id; |
f5fc0f86 LC |
73 | |
74 | /* payload length (not including headers */ | |
d0f63b20 | 75 | __le16 len; |
ba2d3587 | 76 | } __packed; |
f5fc0f86 LC |
77 | |
78 | struct acx_error_counter { | |
79 | struct acx_header header; | |
80 | ||
81 | /* The number of PLCP errors since the last time this */ | |
82 | /* information element was interrogated. This field is */ | |
83 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 84 | __le32 PLCP_error; |
f5fc0f86 LC |
85 | |
86 | /* The number of FCS errors since the last time this */ | |
87 | /* information element was interrogated. This field is */ | |
88 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 89 | __le32 FCS_error; |
f5fc0f86 LC |
90 | |
91 | /* The number of MPDUs without PLCP header errors received*/ | |
92 | /* since the last time this information element was interrogated. */ | |
93 | /* This field is automatically cleared when it is interrogated.*/ | |
d0f63b20 | 94 | __le32 valid_frame; |
f5fc0f86 LC |
95 | |
96 | /* the number of missed sequence numbers in the squentially */ | |
97 | /* values of frames seq numbers */ | |
d0f63b20 | 98 | __le32 seq_num_miss; |
ba2d3587 | 99 | } __packed; |
f5fc0f86 | 100 | |
7f097988 EP |
101 | enum wl12xx_role { |
102 | WL1271_ROLE_STA = 0, | |
103 | WL1271_ROLE_IBSS, | |
104 | WL1271_ROLE_AP, | |
105 | WL1271_ROLE_DEVICE, | |
106 | WL1271_ROLE_P2P_CL, | |
107 | WL1271_ROLE_P2P_GO, | |
108 | ||
109 | WL12XX_INVALID_ROLE_TYPE = 0xff | |
110 | }; | |
111 | ||
f5fc0f86 LC |
112 | enum wl1271_psm_mode { |
113 | /* Active mode */ | |
114 | WL1271_PSM_CAM = 0, | |
115 | ||
116 | /* Power save mode */ | |
117 | WL1271_PSM_PS = 1, | |
118 | ||
119 | /* Extreme low power */ | |
120 | WL1271_PSM_ELP = 2, | |
26b5858a LC |
121 | |
122 | WL1271_PSM_MAX = WL1271_PSM_ELP, | |
66340e5b AN |
123 | |
124 | /* illegal out of band value of PSM mode */ | |
125 | WL1271_PSM_ILLEGAL = 0xff | |
f5fc0f86 LC |
126 | }; |
127 | ||
128 | struct acx_sleep_auth { | |
129 | struct acx_header header; | |
130 | ||
131 | /* The sleep level authorization of the device. */ | |
132 | /* 0 - Always active*/ | |
133 | /* 1 - Power down mode: light / fast sleep*/ | |
134 | /* 2 - ELP mode: Deep / Max sleep*/ | |
135 | u8 sleep_auth; | |
136 | u8 padding[3]; | |
ba2d3587 | 137 | } __packed; |
f5fc0f86 LC |
138 | |
139 | enum { | |
140 | HOSTIF_PCI_MASTER_HOST_INDIRECT, | |
141 | HOSTIF_PCI_MASTER_HOST_DIRECT, | |
142 | HOSTIF_SLAVE, | |
143 | HOSTIF_PKT_RING, | |
144 | HOSTIF_DONTCARE = 0xFF | |
145 | }; | |
146 | ||
147 | #define DEFAULT_UCAST_PRIORITY 0 | |
148 | #define DEFAULT_RX_Q_PRIORITY 0 | |
f5fc0f86 LC |
149 | #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ |
150 | #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ | |
151 | #define TRACE_BUFFER_MAX_SIZE 256 | |
152 | ||
153 | #define DP_RX_PACKET_RING_CHUNK_SIZE 1600 | |
154 | #define DP_TX_PACKET_RING_CHUNK_SIZE 1600 | |
155 | #define DP_RX_PACKET_RING_CHUNK_NUM 2 | |
156 | #define DP_TX_PACKET_RING_CHUNK_NUM 2 | |
157 | #define DP_TX_COMPLETE_TIME_OUT 20 | |
f5fc0f86 LC |
158 | |
159 | #define TX_MSDU_LIFETIME_MIN 0 | |
160 | #define TX_MSDU_LIFETIME_MAX 3000 | |
161 | #define TX_MSDU_LIFETIME_DEF 512 | |
162 | #define RX_MSDU_LIFETIME_MIN 0 | |
163 | #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF | |
164 | #define RX_MSDU_LIFETIME_DEF 512000 | |
165 | ||
166 | struct acx_rx_msdu_lifetime { | |
167 | struct acx_header header; | |
168 | ||
169 | /* | |
170 | * The maximum amount of time, in TU, before the | |
171 | * firmware discards the MSDU. | |
172 | */ | |
d0f63b20 | 173 | __le32 lifetime; |
ba2d3587 | 174 | } __packed; |
f5fc0f86 | 175 | |
f5fc0f86 LC |
176 | enum acx_slot_type { |
177 | SLOT_TIME_LONG = 0, | |
178 | SLOT_TIME_SHORT = 1, | |
179 | DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, | |
180 | MAX_SLOT_TIMES = 0xFF | |
181 | }; | |
182 | ||
183 | #define STATION_WONE_INDEX 0 | |
184 | ||
185 | struct acx_slot { | |
186 | struct acx_header header; | |
187 | ||
7f097988 | 188 | u8 role_id; |
f5fc0f86 LC |
189 | u8 wone_index; /* Reserved */ |
190 | u8 slot_time; | |
7f097988 | 191 | u8 reserved[5]; |
ba2d3587 | 192 | } __packed; |
f5fc0f86 LC |
193 | |
194 | ||
c87dec9f JO |
195 | #define ACX_MC_ADDRESS_GROUP_MAX (8) |
196 | #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX) | |
f5fc0f86 LC |
197 | |
198 | struct acx_dot11_grp_addr_tbl { | |
199 | struct acx_header header; | |
200 | ||
7f097988 | 201 | u8 role_id; |
f5fc0f86 LC |
202 | u8 enabled; |
203 | u8 num_groups; | |
7f097988 | 204 | u8 pad[1]; |
f5fc0f86 | 205 | u8 mac_table[ADDRESS_GROUP_MAX_LEN]; |
ba2d3587 | 206 | } __packed; |
f5fc0f86 | 207 | |
f5fc0f86 LC |
208 | struct acx_rx_timeout { |
209 | struct acx_header header; | |
210 | ||
7f097988 EP |
211 | u8 role_id; |
212 | u8 reserved; | |
d0f63b20 LC |
213 | __le16 ps_poll_timeout; |
214 | __le16 upsd_timeout; | |
7f097988 | 215 | u8 padding[2]; |
ba2d3587 | 216 | } __packed; |
f5fc0f86 | 217 | |
f5fc0f86 LC |
218 | struct acx_rts_threshold { |
219 | struct acx_header header; | |
220 | ||
7f097988 EP |
221 | u8 role_id; |
222 | u8 reserved; | |
d0f63b20 | 223 | __le16 threshold; |
ba2d3587 | 224 | } __packed; |
f5fc0f86 LC |
225 | |
226 | struct acx_beacon_filter_option { | |
227 | struct acx_header header; | |
228 | ||
7f097988 | 229 | u8 role_id; |
f5fc0f86 | 230 | u8 enable; |
f5fc0f86 LC |
231 | /* |
232 | * The number of beacons without the unicast TIM | |
233 | * bit set that the firmware buffers before | |
234 | * signaling the host about ready frames. | |
235 | * When set to 0 and the filter is enabled, beacons | |
236 | * without the unicast TIM bit set are dropped. | |
237 | */ | |
238 | u8 max_num_beacons; | |
7f097988 | 239 | u8 pad[1]; |
ba2d3587 | 240 | } __packed; |
f5fc0f86 LC |
241 | |
242 | /* | |
243 | * ACXBeaconFilterEntry (not 221) | |
244 | * Byte Offset Size (Bytes) Definition | |
245 | * =========== ============ ========== | |
1937e742 | 246 | * 0 1 IE identifier |
f5fc0f86 LC |
247 | * 1 1 Treatment bit mask |
248 | * | |
249 | * ACXBeaconFilterEntry (221) | |
250 | * Byte Offset Size (Bytes) Definition | |
251 | * =========== ============ ========== | |
252 | * 0 1 IE identifier | |
253 | * 1 1 Treatment bit mask | |
254 | * 2 3 OUI | |
255 | * 5 1 Type | |
256 | * 6 2 Version | |
257 | * | |
258 | * | |
259 | * Treatment bit mask - The information element handling: | |
260 | * bit 0 - The information element is compared and transferred | |
261 | * in case of change. | |
262 | * bit 1 - The information element is transferred to the host | |
263 | * with each appearance or disappearance. | |
264 | * Note that both bits can be set at the same time. | |
265 | */ | |
266 | #define BEACON_FILTER_TABLE_MAX_IE_NUM (32) | |
267 | #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) | |
268 | #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) | |
269 | #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) | |
270 | #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ | |
271 | BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ | |
272 | (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ | |
273 | BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) | |
274 | ||
275 | struct acx_beacon_filter_ie_table { | |
276 | struct acx_header header; | |
277 | ||
7f097988 | 278 | u8 role_id; |
f5fc0f86 | 279 | u8 num_ie; |
7f097988 | 280 | u8 pad[2]; |
1937e742 | 281 | u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; |
ba2d3587 | 282 | } __packed; |
f5fc0f86 | 283 | |
34415236 JO |
284 | struct acx_conn_monit_params { |
285 | struct acx_header header; | |
286 | ||
7f097988 EP |
287 | u8 role_id; |
288 | u8 padding[3]; | |
d0f63b20 LC |
289 | __le32 synch_fail_thold; /* number of beacons missed */ |
290 | __le32 bss_lose_timeout; /* number of TU's from synch fail */ | |
ba2d3587 | 291 | } __packed; |
34415236 | 292 | |
f5fc0f86 LC |
293 | struct acx_bt_wlan_coex { |
294 | struct acx_header header; | |
295 | ||
f5fc0f86 LC |
296 | u8 enable; |
297 | u8 pad[3]; | |
ba2d3587 | 298 | } __packed; |
f5fc0f86 | 299 | |
3be4112c | 300 | struct acx_bt_wlan_coex_param { |
6e92b416 LC |
301 | struct acx_header header; |
302 | ||
3be4112c | 303 | __le32 params[CONF_SG_PARAMS_MAX]; |
885c9907 | 304 | u8 param_idx; |
6e92b416 | 305 | u8 padding[3]; |
ba2d3587 | 306 | } __packed; |
6e92b416 | 307 | |
885c9907 | 308 | struct acx_dco_itrim_params { |
f5fc0f86 LC |
309 | struct acx_header header; |
310 | ||
885c9907 | 311 | u8 enable; |
2b60100b | 312 | u8 padding[3]; |
885c9907 | 313 | __le32 timeout; |
ba2d3587 | 314 | } __packed; |
f5fc0f86 | 315 | |
f5fc0f86 LC |
316 | struct acx_energy_detection { |
317 | struct acx_header header; | |
318 | ||
319 | /* The RX Clear Channel Assessment threshold in the PHY */ | |
d0f63b20 | 320 | __le16 rx_cca_threshold; |
f5fc0f86 LC |
321 | u8 tx_energy_detection; |
322 | u8 pad; | |
ba2d3587 | 323 | } __packed; |
f5fc0f86 | 324 | |
f5fc0f86 LC |
325 | struct acx_beacon_broadcast { |
326 | struct acx_header header; | |
327 | ||
7f097988 | 328 | u8 role_id; |
f5fc0f86 LC |
329 | /* Enables receiving of broadcast packets in PS mode */ |
330 | u8 rx_broadcast_in_ps; | |
331 | ||
7f097988 EP |
332 | __le16 beacon_rx_timeout; |
333 | __le16 broadcast_timeout; | |
334 | ||
f5fc0f86 LC |
335 | /* Consecutive PS Poll failures before updating the host */ |
336 | u8 ps_poll_threshold; | |
7f097988 | 337 | u8 pad[1]; |
ba2d3587 | 338 | } __packed; |
f5fc0f86 LC |
339 | |
340 | struct acx_event_mask { | |
341 | struct acx_header header; | |
342 | ||
d0f63b20 LC |
343 | __le32 event_mask; |
344 | __le32 high_event_mask; /* Unused */ | |
ba2d3587 | 345 | } __packed; |
f5fc0f86 | 346 | |
f5fc0f86 LC |
347 | #define SCAN_PASSIVE BIT(0) |
348 | #define SCAN_5GHZ_BAND BIT(1) | |
349 | #define SCAN_TRIGGERED BIT(2) | |
350 | #define SCAN_PRIORITY_HIGH BIT(3) | |
351 | ||
2b60100b JO |
352 | /* When set, disable HW encryption */ |
353 | #define DF_ENCRYPTION_DISABLE 0x01 | |
354 | #define DF_SNIFF_MODE_ENABLE 0x80 | |
355 | ||
f5fc0f86 LC |
356 | struct acx_feature_config { |
357 | struct acx_header header; | |
358 | ||
7f097988 EP |
359 | u8 role_id; |
360 | u8 padding[3]; | |
d0f63b20 LC |
361 | __le32 options; |
362 | __le32 data_flow_options; | |
ba2d3587 | 363 | } __packed; |
f5fc0f86 LC |
364 | |
365 | struct acx_current_tx_power { | |
366 | struct acx_header header; | |
367 | ||
7f097988 | 368 | u8 role_id; |
f5fc0f86 | 369 | u8 current_tx_power; |
7f097988 | 370 | u8 padding[2]; |
ba2d3587 | 371 | } __packed; |
f5fc0f86 | 372 | |
f5fc0f86 LC |
373 | struct acx_wake_up_condition { |
374 | struct acx_header header; | |
375 | ||
7f097988 | 376 | u8 role_id; |
f5fc0f86 LC |
377 | u8 wake_up_event; /* Only one bit can be set */ |
378 | u8 listen_interval; | |
7f097988 | 379 | u8 pad[1]; |
ba2d3587 | 380 | } __packed; |
f5fc0f86 LC |
381 | |
382 | struct acx_aid { | |
383 | struct acx_header header; | |
384 | ||
385 | /* | |
386 | * To be set when associated with an AP. | |
387 | */ | |
7f097988 EP |
388 | u8 role_id; |
389 | u8 reserved; | |
d0f63b20 | 390 | __le16 aid; |
ba2d3587 | 391 | } __packed; |
f5fc0f86 LC |
392 | |
393 | enum acx_preamble_type { | |
394 | ACX_PREAMBLE_LONG = 0, | |
395 | ACX_PREAMBLE_SHORT = 1 | |
396 | }; | |
397 | ||
398 | struct acx_preamble { | |
399 | struct acx_header header; | |
400 | ||
401 | /* | |
402 | * When set, the WiLink transmits the frames with a short preamble and | |
403 | * when cleared, the WiLink transmits the frames with a long preamble. | |
404 | */ | |
7f097988 | 405 | u8 role_id; |
f5fc0f86 | 406 | u8 preamble; |
7f097988 | 407 | u8 padding[2]; |
ba2d3587 | 408 | } __packed; |
f5fc0f86 LC |
409 | |
410 | enum acx_ctsprotect_type { | |
411 | CTSPROTECT_DISABLE = 0, | |
412 | CTSPROTECT_ENABLE = 1 | |
413 | }; | |
414 | ||
415 | struct acx_ctsprotect { | |
416 | struct acx_header header; | |
7f097988 | 417 | u8 role_id; |
f5fc0f86 | 418 | u8 ctsprotect; |
7f097988 | 419 | u8 padding[2]; |
ba2d3587 | 420 | } __packed; |
f5fc0f86 | 421 | |
f5fc0f86 | 422 | struct acx_rate_class { |
d0f63b20 | 423 | __le32 enabled_rates; |
f5fc0f86 LC |
424 | u8 short_retry_limit; |
425 | u8 long_retry_limit; | |
426 | u8 aflags; | |
427 | u8 reserved; | |
428 | }; | |
429 | ||
7f097988 | 430 | struct acx_rate_policy { |
79b223f4 AN |
431 | struct acx_header header; |
432 | ||
433 | __le32 rate_policy_idx; | |
434 | struct acx_rate_class rate_policy; | |
435 | } __packed; | |
436 | ||
f5fc0f86 LC |
437 | struct acx_ac_cfg { |
438 | struct acx_header header; | |
7f097988 | 439 | u8 role_id; |
f5fc0f86 | 440 | u8 ac; |
7f097988 | 441 | u8 aifsn; |
f5fc0f86 | 442 | u8 cw_min; |
d0f63b20 | 443 | __le16 cw_max; |
d0f63b20 | 444 | __le16 tx_op_limit; |
ba2d3587 | 445 | } __packed; |
f5fc0f86 | 446 | |
f5fc0f86 LC |
447 | struct acx_tid_config { |
448 | struct acx_header header; | |
7f097988 | 449 | u8 role_id; |
f5fc0f86 LC |
450 | u8 queue_id; |
451 | u8 channel_type; | |
452 | u8 tsid; | |
453 | u8 ps_scheme; | |
454 | u8 ack_policy; | |
7f097988 | 455 | u8 padding[2]; |
d0f63b20 | 456 | __le32 apsd_conf[2]; |
ba2d3587 | 457 | } __packed; |
f5fc0f86 LC |
458 | |
459 | struct acx_frag_threshold { | |
460 | struct acx_header header; | |
d0f63b20 | 461 | __le16 frag_threshold; |
f5fc0f86 | 462 | u8 padding[2]; |
ba2d3587 | 463 | } __packed; |
f5fc0f86 | 464 | |
f5fc0f86 LC |
465 | struct acx_tx_config_options { |
466 | struct acx_header header; | |
d0f63b20 LC |
467 | __le16 tx_compl_timeout; /* msec */ |
468 | __le16 tx_compl_threshold; /* number of packets */ | |
ba2d3587 | 469 | } __packed; |
f5fc0f86 | 470 | |
7f097988 | 471 | struct wl12xx_acx_config_memory { |
c8bde243 EP |
472 | struct acx_header header; |
473 | ||
474 | u8 rx_mem_block_num; | |
475 | u8 tx_min_mem_block_num; | |
476 | u8 num_stations; | |
477 | u8 num_ssid_profiles; | |
478 | __le32 total_tx_descriptors; | |
479 | u8 dyn_mem_enable; | |
480 | u8 tx_free_req; | |
481 | u8 rx_free_req; | |
482 | u8 tx_min; | |
95dac04f IY |
483 | u8 fwlog_blocks; |
484 | u8 padding[3]; | |
c8bde243 EP |
485 | } __packed; |
486 | ||
f5fc0f86 LC |
487 | struct wl1271_acx_mem_map { |
488 | struct acx_header header; | |
489 | ||
d0f63b20 LC |
490 | __le32 code_start; |
491 | __le32 code_end; | |
f5fc0f86 | 492 | |
d0f63b20 LC |
493 | __le32 wep_defkey_start; |
494 | __le32 wep_defkey_end; | |
f5fc0f86 | 495 | |
d0f63b20 LC |
496 | __le32 sta_table_start; |
497 | __le32 sta_table_end; | |
f5fc0f86 | 498 | |
d0f63b20 LC |
499 | __le32 packet_template_start; |
500 | __le32 packet_template_end; | |
f5fc0f86 LC |
501 | |
502 | /* Address of the TX result interface (control block) */ | |
d0f63b20 LC |
503 | __le32 tx_result; |
504 | __le32 tx_result_queue_start; | |
f5fc0f86 | 505 | |
d0f63b20 LC |
506 | __le32 queue_memory_start; |
507 | __le32 queue_memory_end; | |
f5fc0f86 | 508 | |
d0f63b20 LC |
509 | __le32 packet_memory_pool_start; |
510 | __le32 packet_memory_pool_end; | |
f5fc0f86 | 511 | |
d0f63b20 LC |
512 | __le32 debug_buffer1_start; |
513 | __le32 debug_buffer1_end; | |
f5fc0f86 | 514 | |
d0f63b20 LC |
515 | __le32 debug_buffer2_start; |
516 | __le32 debug_buffer2_end; | |
f5fc0f86 LC |
517 | |
518 | /* Number of blocks FW allocated for TX packets */ | |
d0f63b20 | 519 | __le32 num_tx_mem_blocks; |
f5fc0f86 LC |
520 | |
521 | /* Number of blocks FW allocated for RX packets */ | |
d0f63b20 | 522 | __le32 num_rx_mem_blocks; |
f5fc0f86 LC |
523 | |
524 | /* the following 4 fields are valid in SLAVE mode only */ | |
525 | u8 *tx_cbuf; | |
526 | u8 *rx_cbuf; | |
d0f63b20 LC |
527 | __le32 rx_ctrl; |
528 | __le32 tx_ctrl; | |
ba2d3587 | 529 | } __packed; |
f5fc0f86 | 530 | |
f5fc0f86 LC |
531 | struct wl1271_acx_rx_config_opt { |
532 | struct acx_header header; | |
533 | ||
d0f63b20 LC |
534 | __le16 mblk_threshold; |
535 | __le16 threshold; | |
536 | __le16 timeout; | |
f5fc0f86 LC |
537 | u8 queue_type; |
538 | u8 reserved; | |
ba2d3587 | 539 | } __packed; |
f5fc0f86 | 540 | |
11f70f97 JO |
541 | |
542 | struct wl1271_acx_bet_enable { | |
543 | struct acx_header header; | |
544 | ||
7f097988 | 545 | u8 role_id; |
11f70f97 JO |
546 | u8 enable; |
547 | u8 max_consecutive; | |
7f097988 | 548 | u8 padding[1]; |
ba2d3587 | 549 | } __packed; |
11f70f97 | 550 | |
01c09162 JO |
551 | #define ACX_IPV4_VERSION 4 |
552 | #define ACX_IPV6_VERSION 6 | |
553 | #define ACX_IPV4_ADDR_SIZE 4 | |
c5312772 EP |
554 | |
555 | /* bitmap of enabled arp_filter features */ | |
556 | #define ACX_ARP_FILTER_ARP_FILTERING BIT(0) | |
557 | #define ACX_ARP_FILTER_AUTO_ARP BIT(1) | |
558 | ||
01c09162 JO |
559 | struct wl1271_acx_arp_filter { |
560 | struct acx_header header; | |
7f097988 | 561 | u8 role_id; |
01c09162 | 562 | u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */ |
c5312772 | 563 | u8 enable; /* bitmap of enabled ARP filtering features */ |
7f097988 | 564 | u8 padding[1]; |
01c09162 JO |
565 | u8 address[16]; /* The configured device IP address - all ARP |
566 | requests directed to this IP address will pass | |
567 | through. For IPv4, the first four bytes are | |
568 | used. */ | |
ba2d3587 | 569 | } __packed; |
01c09162 | 570 | |
38ad2d87 JO |
571 | struct wl1271_acx_pm_config { |
572 | struct acx_header header; | |
573 | ||
574 | __le32 host_clk_settling_time; | |
575 | u8 host_fast_wakeup_support; | |
576 | u8 padding[3]; | |
ba2d3587 | 577 | } __packed; |
01c09162 | 578 | |
c1899554 JO |
579 | struct wl1271_acx_keep_alive_mode { |
580 | struct acx_header header; | |
581 | ||
7f097988 | 582 | u8 role_id; |
c1899554 | 583 | u8 enabled; |
7f097988 | 584 | u8 padding[2]; |
ba2d3587 | 585 | } __packed; |
c1899554 JO |
586 | |
587 | enum { | |
588 | ACX_KEEP_ALIVE_NO_TX = 0, | |
589 | ACX_KEEP_ALIVE_PERIOD_ONLY | |
590 | }; | |
591 | ||
592 | enum { | |
593 | ACX_KEEP_ALIVE_TPL_INVALID = 0, | |
594 | ACX_KEEP_ALIVE_TPL_VALID | |
595 | }; | |
596 | ||
597 | struct wl1271_acx_keep_alive_config { | |
598 | struct acx_header header; | |
599 | ||
7f097988 | 600 | u8 role_id; |
c1899554 JO |
601 | u8 index; |
602 | u8 tpl_validation; | |
603 | u8 trigger; | |
7f097988 | 604 | __le32 period; |
ba2d3587 | 605 | } __packed; |
c1899554 | 606 | |
9d68d1ee | 607 | /* TODO: maybe this needs to be moved somewhere else? */ |
48a61477 SL |
608 | #define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0) |
609 | #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1) | |
610 | #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3) | |
b8422dcb LC |
611 | #define HOST_IF_CFG_RX_PAD_TO_SDIO_BLK BIT(4) |
612 | #define HOST_IF_CFG_ADD_RX_ALIGNMENT BIT(6) | |
48a61477 | 613 | |
00236aed JO |
614 | enum { |
615 | WL1271_ACX_TRIG_TYPE_LEVEL = 0, | |
616 | WL1271_ACX_TRIG_TYPE_EDGE, | |
617 | }; | |
618 | ||
619 | enum { | |
620 | WL1271_ACX_TRIG_DIR_LOW = 0, | |
621 | WL1271_ACX_TRIG_DIR_HIGH, | |
622 | WL1271_ACX_TRIG_DIR_BIDIR, | |
623 | }; | |
624 | ||
625 | enum { | |
626 | WL1271_ACX_TRIG_ENABLE = 1, | |
627 | WL1271_ACX_TRIG_DISABLE, | |
628 | }; | |
629 | ||
630 | enum { | |
631 | WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0, | |
632 | WL1271_ACX_TRIG_METRIC_RSSI_DATA, | |
633 | WL1271_ACX_TRIG_METRIC_SNR_BEACON, | |
634 | WL1271_ACX_TRIG_METRIC_SNR_DATA, | |
635 | }; | |
636 | ||
637 | enum { | |
638 | WL1271_ACX_TRIG_IDX_RSSI = 0, | |
639 | WL1271_ACX_TRIG_COUNT = 8, | |
640 | }; | |
641 | ||
642 | struct wl1271_acx_rssi_snr_trigger { | |
643 | struct acx_header header; | |
644 | ||
7f097988 | 645 | u8 role_id; |
00236aed JO |
646 | u8 metric; |
647 | u8 type; | |
648 | u8 dir; | |
7f097988 EP |
649 | __le16 threshold; |
650 | __le16 pacing; /* 0 - 60000 ms */ | |
00236aed JO |
651 | u8 hysteresis; |
652 | u8 index; | |
653 | u8 enable; | |
7f097988 | 654 | u8 padding[1]; |
00236aed JO |
655 | }; |
656 | ||
657 | struct wl1271_acx_rssi_snr_avg_weights { | |
658 | struct acx_header header; | |
659 | ||
7f097988 EP |
660 | u8 role_id; |
661 | u8 padding[3]; | |
00236aed JO |
662 | u8 rssi_beacon; |
663 | u8 rssi_data; | |
664 | u8 snr_beacon; | |
665 | u8 snr_data; | |
666 | }; | |
667 | ||
0f9c8250 AN |
668 | |
669 | /* special capability bit (not employed by the 802.11n spec) */ | |
670 | #define WL12XX_HT_CAP_HT_OPERATION BIT(16) | |
671 | ||
e8b03a2b SL |
672 | /* |
673 | * ACX_PEER_HT_CAP | |
674 | * Configure HT capabilities - declare the capabilities of the peer | |
675 | * we are connected to. | |
676 | */ | |
677 | struct wl1271_acx_ht_capabilities { | |
678 | struct acx_header header; | |
679 | ||
0f9c8250 | 680 | /* bitmask of capability bits supported by the peer */ |
e8b03a2b SL |
681 | __le32 ht_capabilites; |
682 | ||
7f097988 EP |
683 | /* Indicates to which link these capabilities apply. */ |
684 | u8 hlid; | |
e8b03a2b SL |
685 | |
686 | /* | |
687 | * This the maximum A-MPDU length supported by the AP. The FW may not | |
688 | * exceed this length when sending A-MPDUs | |
689 | */ | |
690 | u8 ampdu_max_length; | |
691 | ||
692 | /* This is the minimal spacing required when sending A-MPDUs to the AP*/ | |
693 | u8 ampdu_min_spacing; | |
7f097988 EP |
694 | |
695 | u8 padding; | |
e8b03a2b SL |
696 | } __packed; |
697 | ||
e8b03a2b SL |
698 | /* |
699 | * ACX_HT_BSS_OPERATION | |
700 | * Configure HT capabilities - AP rules for behavior in the BSS. | |
701 | */ | |
702 | struct wl1271_acx_ht_information { | |
703 | struct acx_header header; | |
704 | ||
7f097988 EP |
705 | u8 role_id; |
706 | ||
e8b03a2b SL |
707 | /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */ |
708 | u8 rifs_mode; | |
709 | ||
710 | /* Values: 0 - 3 like in spec */ | |
711 | u8 ht_protection; | |
712 | ||
713 | /* Values: 0 - GF protection not required, 1 - GF protection required */ | |
714 | u8 gf_protection; | |
715 | ||
716 | /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/ | |
717 | u8 ht_tx_burst_limit; | |
718 | ||
719 | /* | |
720 | * Values: 0 - Dual CTS protection not required, | |
721 | * 1 - Dual CTS Protection required | |
722 | * Note: When this value is set to 1 FW will protect all TXOP with RTS | |
723 | * frame and will not use CTS-to-self regardless of the value of the | |
724 | * ACX_CTS_PROTECTION information element | |
725 | */ | |
726 | u8 dual_cts_protection; | |
727 | ||
7f097988 | 728 | u8 padding[2]; |
e8b03a2b SL |
729 | } __packed; |
730 | ||
0a15d9b5 | 731 | #define RX_BA_MAX_SESSIONS 3 |
4b7fac77 | 732 | |
0f9c8250 | 733 | struct wl1271_acx_ba_initiator_policy { |
4b7fac77 | 734 | struct acx_header header; |
0f9c8250 AN |
735 | |
736 | /* Specifies role Id, Range 0-7, 0xFF means ANY role. */ | |
4b7fac77 | 737 | u8 role_id; |
0f9c8250 | 738 | |
4b7fac77 | 739 | /* |
0f9c8250 AN |
740 | * Per TID setting for allowing TX BA. Set a bit to 1 to allow |
741 | * TX BA sessions for the corresponding TID. | |
4b7fac77 | 742 | */ |
0f9c8250 | 743 | u8 tid_bitmap; |
4b7fac77 LS |
744 | |
745 | /* Windows size in number of packets */ | |
0f9c8250 | 746 | u8 win_size; |
4b7fac77 | 747 | |
0f9c8250 | 748 | u8 padding1[1]; |
4b7fac77 | 749 | |
0f9c8250 AN |
750 | /* As initiator inactivity timeout in time units(TU) of 1024us */ |
751 | u16 inactivity_timeout; | |
4b7fac77 | 752 | |
0f9c8250 | 753 | u8 padding[2]; |
4b7fac77 LS |
754 | } __packed; |
755 | ||
bbba3e68 LS |
756 | struct wl1271_acx_ba_receiver_setup { |
757 | struct acx_header header; | |
758 | ||
0f9c8250 AN |
759 | /* Specifies link id, range 0-31 */ |
760 | u8 hlid; | |
bbba3e68 LS |
761 | |
762 | u8 tid; | |
763 | ||
764 | u8 enable; | |
765 | ||
bbba3e68 | 766 | /* Windows size in number of packets */ |
0f9c8250 | 767 | u8 win_size; |
bbba3e68 LS |
768 | |
769 | /* BA session starting sequence number. RANGE 0-FFF */ | |
770 | u16 ssn; | |
0f9c8250 AN |
771 | |
772 | u8 padding[2]; | |
bbba3e68 LS |
773 | } __packed; |
774 | ||
9c531149 | 775 | struct wl12xx_acx_fw_tsf_information { |
bbbb538e JO |
776 | struct acx_header header; |
777 | ||
9c531149 EP |
778 | u8 role_id; |
779 | u8 padding1[3]; | |
bbbb538e JO |
780 | __le32 current_tsf_high; |
781 | __le32 current_tsf_low; | |
782 | __le32 last_bttt_high; | |
783 | __le32 last_tbtt_low; | |
784 | u8 last_dtim_count; | |
9c531149 | 785 | u8 padding2[3]; |
72e93e91 | 786 | } __packed; |
bbbb538e | 787 | |
f84673d5 EP |
788 | struct wl1271_acx_ps_rx_streaming { |
789 | struct acx_header header; | |
790 | ||
7f097988 | 791 | u8 role_id; |
f84673d5 EP |
792 | u8 tid; |
793 | u8 enable; | |
794 | ||
795 | /* interval between triggers (10-100 msec) */ | |
796 | u8 period; | |
797 | ||
798 | /* timeout before first trigger (0-200 msec) */ | |
799 | u8 timeout; | |
7f097988 | 800 | u8 padding[3]; |
f84673d5 EP |
801 | } __packed; |
802 | ||
3618f30f | 803 | struct wl1271_acx_ap_max_tx_retry { |
79b223f4 AN |
804 | struct acx_header header; |
805 | ||
7f097988 EP |
806 | u8 role_id; |
807 | u8 padding_1; | |
808 | ||
79b223f4 AN |
809 | /* |
810 | * the number of frames transmission failures before | |
811 | * issuing the aging event. | |
812 | */ | |
813 | __le16 max_tx_retry; | |
79b223f4 AN |
814 | } __packed; |
815 | ||
ee60833a EP |
816 | struct wl1271_acx_config_ps { |
817 | struct acx_header header; | |
818 | ||
819 | u8 exit_retries; | |
820 | u8 enter_retries; | |
821 | u8 padding[2]; | |
822 | __le32 null_data_rate; | |
823 | } __packed; | |
824 | ||
99a2775d AN |
825 | struct wl1271_acx_inconnection_sta { |
826 | struct acx_header header; | |
827 | ||
828 | u8 addr[ETH_ALEN]; | |
829 | u8 padding1[2]; | |
830 | } __packed; | |
831 | ||
ff86843d SL |
832 | /* |
833 | * ACX_FM_COEX_CFG | |
834 | * set the FM co-existence parameters. | |
835 | */ | |
836 | struct wl1271_acx_fm_coex { | |
837 | struct acx_header header; | |
838 | /* enable(1) / disable(0) the FM Coex feature */ | |
839 | u8 enable; | |
840 | /* | |
841 | * Swallow period used in COEX PLL swallowing mechanism. | |
842 | * 0xFF = use FW default | |
843 | */ | |
844 | u8 swallow_period; | |
845 | /* | |
846 | * The N divider used in COEX PLL swallowing mechanism for Fref of | |
847 | * 38.4/19.2 Mhz. 0xFF = use FW default | |
848 | */ | |
849 | u8 n_divider_fref_set_1; | |
850 | /* | |
851 | * The N divider used in COEX PLL swallowing mechanism for Fref of | |
852 | * 26/52 Mhz. 0xFF = use FW default | |
853 | */ | |
854 | u8 n_divider_fref_set_2; | |
855 | /* | |
856 | * The M divider used in COEX PLL swallowing mechanism for Fref of | |
857 | * 38.4/19.2 Mhz. 0xFFFF = use FW default | |
858 | */ | |
859 | __le16 m_divider_fref_set_1; | |
860 | /* | |
861 | * The M divider used in COEX PLL swallowing mechanism for Fref of | |
862 | * 26/52 Mhz. 0xFFFF = use FW default | |
863 | */ | |
864 | __le16 m_divider_fref_set_2; | |
865 | /* | |
866 | * The time duration in uSec required for COEX PLL to stabilize. | |
867 | * 0xFFFFFFFF = use FW default | |
868 | */ | |
869 | __le32 coex_pll_stabilization_time; | |
870 | /* | |
871 | * The time duration in uSec required for LDO to stabilize. | |
872 | * 0xFFFFFFFF = use FW default | |
873 | */ | |
874 | __le16 ldo_stabilization_time; | |
875 | /* | |
876 | * The disturbed frequency band margin around the disturbed frequency | |
877 | * center (single sided). | |
878 | * For example, if 2 is configured, the following channels will be | |
879 | * considered disturbed channel: | |
880 | * 80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH | |
881 | * 0xFF = use FW default | |
882 | */ | |
883 | u8 fm_disturbed_band_margin; | |
884 | /* | |
885 | * The swallow clock difference of the swallowing mechanism. | |
886 | * 0xFF = use FW default | |
887 | */ | |
888 | u8 swallow_clk_diff; | |
889 | } __packed; | |
890 | ||
fa6ad9f0 EP |
891 | #define ACX_RATE_MGMT_ALL_PARAMS 0xff |
892 | struct wl12xx_acx_set_rate_mgmt_params { | |
893 | struct acx_header header; | |
894 | ||
895 | u8 index; /* 0xff to configure all params */ | |
896 | u8 padding1; | |
897 | __le16 rate_retry_score; | |
898 | __le16 per_add; | |
899 | __le16 per_th1; | |
900 | __le16 per_th2; | |
901 | __le16 max_per; | |
902 | u8 inverse_curiosity_factor; | |
903 | u8 tx_fail_low_th; | |
904 | u8 tx_fail_high_th; | |
905 | u8 per_alpha_shift; | |
906 | u8 per_add_shift; | |
907 | u8 per_beta1_shift; | |
908 | u8 per_beta2_shift; | |
909 | u8 rate_check_up; | |
910 | u8 rate_check_down; | |
911 | u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES]; | |
912 | u8 padding2[2]; | |
913 | } __packed; | |
914 | ||
9487775c EP |
915 | struct wl12xx_acx_config_hangover { |
916 | struct acx_header header; | |
917 | ||
918 | __le32 recover_time; | |
919 | u8 hangover_period; | |
920 | u8 dynamic_mode; | |
921 | u8 early_termination_mode; | |
922 | u8 max_period; | |
923 | u8 min_period; | |
924 | u8 increase_delta; | |
925 | u8 decrease_delta; | |
926 | u8 quiet_time; | |
927 | u8 increase_time; | |
928 | u8 window_size; | |
929 | u8 padding[2]; | |
930 | } __packed; | |
931 | ||
c21eebb5 ES |
932 | |
933 | struct acx_default_rx_filter { | |
934 | struct acx_header header; | |
935 | u8 enable; | |
936 | ||
937 | /* action of type FILTER_XXX */ | |
938 | u8 default_action; | |
939 | ||
940 | u8 pad[2]; | |
941 | } __packed; | |
942 | ||
943 | ||
944 | struct acx_rx_filter_cfg { | |
945 | struct acx_header header; | |
946 | ||
947 | u8 enable; | |
948 | ||
949 | /* 0 - WL1271_MAX_RX_FILTERS-1 */ | |
950 | u8 index; | |
951 | ||
952 | u8 action; | |
953 | ||
954 | u8 num_fields; | |
955 | u8 fields[0]; | |
956 | } __packed; | |
957 | ||
f5fc0f86 | 958 | enum { |
8332f0f6 EP |
959 | ACX_WAKE_UP_CONDITIONS = 0x0000, |
960 | ACX_MEM_CFG = 0x0001, | |
961 | ACX_SLOT = 0x0002, | |
962 | ACX_AC_CFG = 0x0003, | |
963 | ACX_MEM_MAP = 0x0004, | |
964 | ACX_AID = 0x0005, | |
965 | ACX_MEDIUM_USAGE = 0x0006, | |
966 | ACX_STATISTICS = 0x0007, | |
967 | ACX_PWR_CONSUMPTION_STATISTICS = 0x0008, | |
968 | ACX_TID_CFG = 0x0009, | |
969 | ACX_PS_RX_STREAMING = 0x000A, | |
970 | ACX_BEACON_FILTER_OPT = 0x000B, | |
971 | ACX_NOISE_HIST = 0x000C, | |
972 | ACX_HDK_VERSION = 0x000D, | |
973 | ACX_PD_THRESHOLD = 0x000E, | |
974 | ACX_TX_CONFIG_OPT = 0x000F, | |
975 | ACX_CCA_THRESHOLD = 0x0010, | |
976 | ACX_EVENT_MBOX_MASK = 0x0011, | |
977 | ACX_CONN_MONIT_PARAMS = 0x0012, | |
978 | ACX_DISABLE_BROADCASTS = 0x0013, | |
979 | ACX_BCN_DTIM_OPTIONS = 0x0014, | |
980 | ACX_SG_ENABLE = 0x0015, | |
981 | ACX_SG_CFG = 0x0016, | |
982 | ACX_FM_COEX_CFG = 0x0017, | |
983 | ACX_BEACON_FILTER_TABLE = 0x0018, | |
984 | ACX_ARP_IP_FILTER = 0x0019, | |
985 | ACX_ROAMING_STATISTICS_TBL = 0x001A, | |
986 | ACX_RATE_POLICY = 0x001B, | |
987 | ACX_CTS_PROTECTION = 0x001C, | |
988 | ACX_SLEEP_AUTH = 0x001D, | |
989 | ACX_PREAMBLE_TYPE = 0x001E, | |
990 | ACX_ERROR_CNT = 0x001F, | |
991 | ACX_IBSS_FILTER = 0x0020, | |
992 | ACX_SERVICE_PERIOD_TIMEOUT = 0x0021, | |
993 | ACX_TSF_INFO = 0x0022, | |
994 | ACX_CONFIG_PS_WMM = 0x0023, | |
995 | ACX_ENABLE_RX_DATA_FILTER = 0x0024, | |
996 | ACX_SET_RX_DATA_FILTER = 0x0025, | |
997 | ACX_GET_DATA_FILTER_STATISTICS = 0x0026, | |
998 | ACX_RX_CONFIG_OPT = 0x0027, | |
999 | ACX_FRAG_CFG = 0x0028, | |
1000 | ACX_BET_ENABLE = 0x0029, | |
1001 | ACX_RSSI_SNR_TRIGGER = 0x002A, | |
1002 | ACX_RSSI_SNR_WEIGHTS = 0x002B, | |
1003 | ACX_KEEP_ALIVE_MODE = 0x002C, | |
1004 | ACX_SET_KEEP_ALIVE_CONFIG = 0x002D, | |
1005 | ACX_BA_SESSION_INIT_POLICY = 0x002E, | |
1006 | ACX_BA_SESSION_RX_SETUP = 0x002F, | |
1007 | ACX_PEER_HT_CAP = 0x0030, | |
1008 | ACX_HT_BSS_OPERATION = 0x0031, | |
1009 | ACX_COEX_ACTIVITY = 0x0032, | |
1010 | ACX_BURST_MODE = 0x0033, | |
1011 | ACX_SET_RATE_MGMT_PARAMS = 0x0034, | |
1012 | ACX_GET_RATE_MGMT_PARAMS = 0x0035, | |
1013 | ACX_SET_RATE_ADAPT_PARAMS = 0x0036, | |
1014 | ACX_SET_DCO_ITRIM_PARAMS = 0x0037, | |
1015 | ACX_GEN_FW_CMD = 0x0038, | |
1016 | ACX_HOST_IF_CFG_BITMAP = 0x0039, | |
1017 | ACX_MAX_TX_FAILURE = 0x003A, | |
1018 | ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B, | |
1019 | DOT11_RX_MSDU_LIFE_TIME = 0x003C, | |
1020 | DOT11_CUR_TX_PWR = 0x003D, | |
1021 | DOT11_RTS_THRESHOLD = 0x003E, | |
1022 | DOT11_GROUP_ADDRESS_TBL = 0x003F, | |
1023 | ACX_PM_CONFIG = 0x0040, | |
1024 | ACX_CONFIG_PS = 0x0041, | |
1025 | ACX_CONFIG_HANGOVER = 0x0042, | |
1026 | ACX_FEATURE_CFG = 0x0043, | |
1027 | ACX_PROTECTION_CFG = 0x0044, | |
2fc28de5 | 1028 | ACX_CHECKSUM_CONFIG = 0x0045, |
f5fc0f86 LC |
1029 | }; |
1030 | ||
1031 | ||
0603d891 | 1032 | int wl1271_acx_wake_up_conditions(struct wl1271 *wl, |
dae728fe ES |
1033 | struct wl12xx_vif *wlvif, |
1034 | u8 wake_up_event, u8 listen_interval); | |
f5fc0f86 | 1035 | int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth); |
0603d891 EP |
1036 | int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1037 | int power); | |
1038 | int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif); | |
f5fc0f86 LC |
1039 | int wl1271_acx_mem_map(struct wl1271 *wl, |
1040 | struct acx_header *mem_map, size_t len); | |
8793f9bb | 1041 | int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl); |
0603d891 EP |
1042 | int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1043 | enum acx_slot_type slot_time); | |
1044 | int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1045 | bool enable, void *mc_list, u32 mc_list_len); | |
1046 | int wl1271_acx_service_period_timeout(struct wl1271 *wl, | |
1047 | struct wl12xx_vif *wlvif); | |
1048 | int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1049 | u32 rts_threshold); | |
6e92b416 | 1050 | int wl1271_acx_dco_itrim_params(struct wl1271 *wl); |
0603d891 EP |
1051 | int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1052 | bool enable_filter); | |
1053 | int wl1271_acx_beacon_filter_table(struct wl1271 *wl, | |
1054 | struct wl12xx_vif *wlvif); | |
1055 | int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1056 | bool enable); | |
7fc3a864 | 1057 | int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable); |
3be4112c | 1058 | int wl12xx_acx_sg_cfg(struct wl1271 *wl); |
f5fc0f86 | 1059 | int wl1271_acx_cca_threshold(struct wl1271 *wl); |
0603d891 EP |
1060 | int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
1061 | int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid); | |
f5fc0f86 | 1062 | int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask); |
0603d891 EP |
1063 | int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1064 | enum acx_preamble_type preamble); | |
1065 | int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
11f70f97 | 1066 | enum acx_ctsprotect_type ctsprotect); |
4987257c | 1067 | int wl1271_acx_statistics(struct wl1271 *wl, void *stats); |
30d0c8fd | 1068 | int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
79b223f4 AN |
1069 | int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c, |
1070 | u8 idx); | |
0603d891 EP |
1071 | int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1072 | u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop); | |
1073 | int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1074 | u8 queue_id, u8 channel_type, | |
f2054df5 KV |
1075 | u8 tsid, u8 ps_scheme, u8 ack_policy, |
1076 | u32 apsd_conf0, u32 apsd_conf1); | |
5f704d18 | 1077 | int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold); |
f5fc0f86 | 1078 | int wl1271_acx_tx_config_options(struct wl1271 *wl); |
7f097988 | 1079 | int wl12xx_acx_mem_cfg(struct wl1271 *wl); |
f5fc0f86 LC |
1080 | int wl1271_acx_init_mem_config(struct wl1271 *wl); |
1081 | int wl1271_acx_init_rx_interrupt(struct wl1271 *wl); | |
3cfd6cf9 | 1082 | int wl1271_acx_smart_reflex(struct wl1271 *wl); |
0603d891 EP |
1083 | int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1084 | bool enable); | |
1085 | int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1086 | u8 enable, __be32 address); | |
38ad2d87 | 1087 | int wl1271_acx_pm_config(struct wl1271 *wl); |
0603d891 EP |
1088 | int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif, |
1089 | bool enable); | |
1090 | int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1091 | u8 index, u8 tpl_valid); | |
1092 | int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1093 | bool enable, s16 thold, u8 hyst); | |
1094 | int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl, | |
1095 | struct wl12xx_vif *wlvif); | |
c4db1c87 SL |
1096 | int wl1271_acx_set_ht_capabilities(struct wl1271 *wl, |
1097 | struct ieee80211_sta_ht_cap *ht_cap, | |
0b932ab9 | 1098 | bool allow_ht_operation, u8 hlid); |
c4db1c87 | 1099 | int wl1271_acx_set_ht_information(struct wl1271 *wl, |
0603d891 | 1100 | struct wl12xx_vif *wlvif, |
c4db1c87 | 1101 | u16 ht_operation_mode); |
0603d891 EP |
1102 | int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl, |
1103 | struct wl12xx_vif *wlvif); | |
0f9c8250 AN |
1104 | int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, |
1105 | u16 ssn, bool enable, u8 peer_hlid); | |
9c531149 EP |
1106 | int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1107 | u64 *mactime); | |
9eb599e9 EP |
1108 | int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1109 | bool enable); | |
0603d891 | 1110 | int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
d2d66c56 | 1111 | int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
99a2775d | 1112 | int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr); |
ff86843d | 1113 | int wl1271_acx_fm_coex(struct wl1271 *wl); |
fa6ad9f0 | 1114 | int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl); |
9487775c | 1115 | int wl12xx_acx_config_hangover(struct wl1271 *wl); |
4161923a ES |
1116 | |
1117 | #ifdef CONFIG_PM | |
c21eebb5 ES |
1118 | int wl1271_acx_default_rx_filter_enable(struct wl1271 *wl, bool enable, |
1119 | enum rx_filter_action action); | |
1120 | int wl1271_acx_set_rx_filter(struct wl1271 *wl, u8 index, bool enable, | |
1121 | struct wl12xx_rx_filter *filter); | |
4161923a | 1122 | #endif /* CONFIG_PM */ |
f5fc0f86 | 1123 | #endif /* __WL1271_ACX_H__ */ |