Commit | Line | Data |
---|---|---|
f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
1937e742 | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
f5fc0f86 LC |
6 | * |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
00d20100 SL |
25 | #ifndef __ACX_H__ |
26 | #define __ACX_H__ | |
f5fc0f86 | 27 | |
c31be25a | 28 | #include "wlcore.h" |
00d20100 | 29 | #include "cmd.h" |
f5fc0f86 LC |
30 | |
31 | /************************************************************************* | |
32 | ||
33 | Host Interrupt Register (WiLink -> Host) | |
34 | ||
35 | **************************************************************************/ | |
36 | /* HW Initiated interrupt Watchdog timer expiration */ | |
37 | #define WL1271_ACX_INTR_WATCHDOG BIT(0) | |
38 | /* Init sequence is done (masked interrupt, detection through polling only ) */ | |
39 | #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1) | |
40 | /* Event was entered to Event MBOX #A*/ | |
41 | #define WL1271_ACX_INTR_EVENT_A BIT(2) | |
42 | /* Event was entered to Event MBOX #B*/ | |
43 | #define WL1271_ACX_INTR_EVENT_B BIT(3) | |
44 | /* Command processing completion*/ | |
45 | #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4) | |
46 | /* Signaling the host on HW wakeup */ | |
47 | #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5) | |
48 | /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ | |
49 | #define WL1271_ACX_INTR_DATA BIT(6) | |
e8a8b252 | 50 | /* Trace message on MBOX #A */ |
f5fc0f86 | 51 | #define WL1271_ACX_INTR_TRACE_A BIT(7) |
e8a8b252 | 52 | /* Trace message on MBOX #B */ |
f5fc0f86 LC |
53 | #define WL1271_ACX_INTR_TRACE_B BIT(8) |
54 | ||
55 | #define WL1271_ACX_INTR_ALL 0xFFFFFFFF | |
56 | #define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ | |
57 | WL1271_ACX_INTR_INIT_COMPLETE | \ | |
58 | WL1271_ACX_INTR_EVENT_A | \ | |
59 | WL1271_ACX_INTR_EVENT_B | \ | |
60 | WL1271_ACX_INTR_CMD_COMPLETE | \ | |
61 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
62 | WL1271_ACX_INTR_DATA) | |
63 | ||
ccc83b04 EP |
64 | #define WL1271_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ |
65 | WL1271_ACX_INTR_EVENT_A | \ | |
37079a83 LC |
66 | WL1271_ACX_INTR_EVENT_B | \ |
67 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
f5fc0f86 LC |
68 | WL1271_ACX_INTR_DATA) |
69 | ||
70 | /* Target's information element */ | |
71 | struct acx_header { | |
72 | struct wl1271_cmd_header cmd; | |
73 | ||
74 | /* acx (or information element) header */ | |
d0f63b20 | 75 | __le16 id; |
f5fc0f86 LC |
76 | |
77 | /* payload length (not including headers */ | |
d0f63b20 | 78 | __le16 len; |
ba2d3587 | 79 | } __packed; |
f5fc0f86 LC |
80 | |
81 | struct acx_error_counter { | |
82 | struct acx_header header; | |
83 | ||
84 | /* The number of PLCP errors since the last time this */ | |
85 | /* information element was interrogated. This field is */ | |
86 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 87 | __le32 PLCP_error; |
f5fc0f86 LC |
88 | |
89 | /* The number of FCS errors since the last time this */ | |
90 | /* information element was interrogated. This field is */ | |
91 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 92 | __le32 FCS_error; |
f5fc0f86 LC |
93 | |
94 | /* The number of MPDUs without PLCP header errors received*/ | |
95 | /* since the last time this information element was interrogated. */ | |
96 | /* This field is automatically cleared when it is interrogated.*/ | |
d0f63b20 | 97 | __le32 valid_frame; |
f5fc0f86 LC |
98 | |
99 | /* the number of missed sequence numbers in the squentially */ | |
100 | /* values of frames seq numbers */ | |
d0f63b20 | 101 | __le32 seq_num_miss; |
ba2d3587 | 102 | } __packed; |
f5fc0f86 | 103 | |
7f097988 EP |
104 | enum wl12xx_role { |
105 | WL1271_ROLE_STA = 0, | |
106 | WL1271_ROLE_IBSS, | |
107 | WL1271_ROLE_AP, | |
108 | WL1271_ROLE_DEVICE, | |
109 | WL1271_ROLE_P2P_CL, | |
110 | WL1271_ROLE_P2P_GO, | |
111 | ||
112 | WL12XX_INVALID_ROLE_TYPE = 0xff | |
113 | }; | |
114 | ||
f5fc0f86 LC |
115 | enum wl1271_psm_mode { |
116 | /* Active mode */ | |
117 | WL1271_PSM_CAM = 0, | |
118 | ||
119 | /* Power save mode */ | |
120 | WL1271_PSM_PS = 1, | |
121 | ||
122 | /* Extreme low power */ | |
123 | WL1271_PSM_ELP = 2, | |
124 | }; | |
125 | ||
126 | struct acx_sleep_auth { | |
127 | struct acx_header header; | |
128 | ||
129 | /* The sleep level authorization of the device. */ | |
130 | /* 0 - Always active*/ | |
131 | /* 1 - Power down mode: light / fast sleep*/ | |
132 | /* 2 - ELP mode: Deep / Max sleep*/ | |
133 | u8 sleep_auth; | |
134 | u8 padding[3]; | |
ba2d3587 | 135 | } __packed; |
f5fc0f86 LC |
136 | |
137 | enum { | |
138 | HOSTIF_PCI_MASTER_HOST_INDIRECT, | |
139 | HOSTIF_PCI_MASTER_HOST_DIRECT, | |
140 | HOSTIF_SLAVE, | |
141 | HOSTIF_PKT_RING, | |
142 | HOSTIF_DONTCARE = 0xFF | |
143 | }; | |
144 | ||
145 | #define DEFAULT_UCAST_PRIORITY 0 | |
146 | #define DEFAULT_RX_Q_PRIORITY 0 | |
f5fc0f86 LC |
147 | #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ |
148 | #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ | |
149 | #define TRACE_BUFFER_MAX_SIZE 256 | |
150 | ||
151 | #define DP_RX_PACKET_RING_CHUNK_SIZE 1600 | |
152 | #define DP_TX_PACKET_RING_CHUNK_SIZE 1600 | |
153 | #define DP_RX_PACKET_RING_CHUNK_NUM 2 | |
154 | #define DP_TX_PACKET_RING_CHUNK_NUM 2 | |
155 | #define DP_TX_COMPLETE_TIME_OUT 20 | |
f5fc0f86 LC |
156 | |
157 | #define TX_MSDU_LIFETIME_MIN 0 | |
158 | #define TX_MSDU_LIFETIME_MAX 3000 | |
159 | #define TX_MSDU_LIFETIME_DEF 512 | |
160 | #define RX_MSDU_LIFETIME_MIN 0 | |
161 | #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF | |
162 | #define RX_MSDU_LIFETIME_DEF 512000 | |
163 | ||
164 | struct acx_rx_msdu_lifetime { | |
165 | struct acx_header header; | |
166 | ||
167 | /* | |
168 | * The maximum amount of time, in TU, before the | |
169 | * firmware discards the MSDU. | |
170 | */ | |
d0f63b20 | 171 | __le32 lifetime; |
ba2d3587 | 172 | } __packed; |
f5fc0f86 | 173 | |
f5fc0f86 LC |
174 | enum acx_slot_type { |
175 | SLOT_TIME_LONG = 0, | |
176 | SLOT_TIME_SHORT = 1, | |
177 | DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, | |
178 | MAX_SLOT_TIMES = 0xFF | |
179 | }; | |
180 | ||
181 | #define STATION_WONE_INDEX 0 | |
182 | ||
183 | struct acx_slot { | |
184 | struct acx_header header; | |
185 | ||
7f097988 | 186 | u8 role_id; |
f5fc0f86 LC |
187 | u8 wone_index; /* Reserved */ |
188 | u8 slot_time; | |
7f097988 | 189 | u8 reserved[5]; |
ba2d3587 | 190 | } __packed; |
f5fc0f86 LC |
191 | |
192 | ||
c87dec9f JO |
193 | #define ACX_MC_ADDRESS_GROUP_MAX (8) |
194 | #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX) | |
f5fc0f86 LC |
195 | |
196 | struct acx_dot11_grp_addr_tbl { | |
197 | struct acx_header header; | |
198 | ||
7f097988 | 199 | u8 role_id; |
f5fc0f86 LC |
200 | u8 enabled; |
201 | u8 num_groups; | |
7f097988 | 202 | u8 pad[1]; |
f5fc0f86 | 203 | u8 mac_table[ADDRESS_GROUP_MAX_LEN]; |
ba2d3587 | 204 | } __packed; |
f5fc0f86 | 205 | |
f5fc0f86 LC |
206 | struct acx_rx_timeout { |
207 | struct acx_header header; | |
208 | ||
7f097988 EP |
209 | u8 role_id; |
210 | u8 reserved; | |
d0f63b20 LC |
211 | __le16 ps_poll_timeout; |
212 | __le16 upsd_timeout; | |
7f097988 | 213 | u8 padding[2]; |
ba2d3587 | 214 | } __packed; |
f5fc0f86 | 215 | |
f5fc0f86 LC |
216 | struct acx_rts_threshold { |
217 | struct acx_header header; | |
218 | ||
7f097988 EP |
219 | u8 role_id; |
220 | u8 reserved; | |
d0f63b20 | 221 | __le16 threshold; |
ba2d3587 | 222 | } __packed; |
f5fc0f86 LC |
223 | |
224 | struct acx_beacon_filter_option { | |
225 | struct acx_header header; | |
226 | ||
7f097988 | 227 | u8 role_id; |
f5fc0f86 | 228 | u8 enable; |
f5fc0f86 LC |
229 | /* |
230 | * The number of beacons without the unicast TIM | |
231 | * bit set that the firmware buffers before | |
232 | * signaling the host about ready frames. | |
233 | * When set to 0 and the filter is enabled, beacons | |
234 | * without the unicast TIM bit set are dropped. | |
235 | */ | |
236 | u8 max_num_beacons; | |
7f097988 | 237 | u8 pad[1]; |
ba2d3587 | 238 | } __packed; |
f5fc0f86 LC |
239 | |
240 | /* | |
241 | * ACXBeaconFilterEntry (not 221) | |
242 | * Byte Offset Size (Bytes) Definition | |
243 | * =========== ============ ========== | |
1937e742 | 244 | * 0 1 IE identifier |
f5fc0f86 LC |
245 | * 1 1 Treatment bit mask |
246 | * | |
247 | * ACXBeaconFilterEntry (221) | |
248 | * Byte Offset Size (Bytes) Definition | |
249 | * =========== ============ ========== | |
250 | * 0 1 IE identifier | |
251 | * 1 1 Treatment bit mask | |
252 | * 2 3 OUI | |
253 | * 5 1 Type | |
254 | * 6 2 Version | |
255 | * | |
256 | * | |
257 | * Treatment bit mask - The information element handling: | |
258 | * bit 0 - The information element is compared and transferred | |
259 | * in case of change. | |
260 | * bit 1 - The information element is transferred to the host | |
261 | * with each appearance or disappearance. | |
262 | * Note that both bits can be set at the same time. | |
263 | */ | |
264 | #define BEACON_FILTER_TABLE_MAX_IE_NUM (32) | |
265 | #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) | |
266 | #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) | |
267 | #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) | |
268 | #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ | |
269 | BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ | |
270 | (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ | |
271 | BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) | |
272 | ||
273 | struct acx_beacon_filter_ie_table { | |
274 | struct acx_header header; | |
275 | ||
7f097988 | 276 | u8 role_id; |
f5fc0f86 | 277 | u8 num_ie; |
7f097988 | 278 | u8 pad[2]; |
1937e742 | 279 | u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; |
ba2d3587 | 280 | } __packed; |
f5fc0f86 | 281 | |
34415236 JO |
282 | struct acx_conn_monit_params { |
283 | struct acx_header header; | |
284 | ||
7f097988 EP |
285 | u8 role_id; |
286 | u8 padding[3]; | |
d0f63b20 LC |
287 | __le32 synch_fail_thold; /* number of beacons missed */ |
288 | __le32 bss_lose_timeout; /* number of TU's from synch fail */ | |
ba2d3587 | 289 | } __packed; |
34415236 | 290 | |
f5fc0f86 LC |
291 | struct acx_bt_wlan_coex { |
292 | struct acx_header header; | |
293 | ||
f5fc0f86 LC |
294 | u8 enable; |
295 | u8 pad[3]; | |
ba2d3587 | 296 | } __packed; |
f5fc0f86 | 297 | |
3be4112c | 298 | struct acx_bt_wlan_coex_param { |
6e92b416 LC |
299 | struct acx_header header; |
300 | ||
3be4112c | 301 | __le32 params[CONF_SG_PARAMS_MAX]; |
885c9907 | 302 | u8 param_idx; |
6e92b416 | 303 | u8 padding[3]; |
ba2d3587 | 304 | } __packed; |
6e92b416 | 305 | |
885c9907 | 306 | struct acx_dco_itrim_params { |
f5fc0f86 LC |
307 | struct acx_header header; |
308 | ||
885c9907 | 309 | u8 enable; |
2b60100b | 310 | u8 padding[3]; |
885c9907 | 311 | __le32 timeout; |
ba2d3587 | 312 | } __packed; |
f5fc0f86 | 313 | |
f5fc0f86 LC |
314 | struct acx_energy_detection { |
315 | struct acx_header header; | |
316 | ||
317 | /* The RX Clear Channel Assessment threshold in the PHY */ | |
d0f63b20 | 318 | __le16 rx_cca_threshold; |
f5fc0f86 LC |
319 | u8 tx_energy_detection; |
320 | u8 pad; | |
ba2d3587 | 321 | } __packed; |
f5fc0f86 | 322 | |
f5fc0f86 LC |
323 | struct acx_beacon_broadcast { |
324 | struct acx_header header; | |
325 | ||
7f097988 | 326 | u8 role_id; |
f5fc0f86 LC |
327 | /* Enables receiving of broadcast packets in PS mode */ |
328 | u8 rx_broadcast_in_ps; | |
329 | ||
7f097988 EP |
330 | __le16 beacon_rx_timeout; |
331 | __le16 broadcast_timeout; | |
332 | ||
f5fc0f86 LC |
333 | /* Consecutive PS Poll failures before updating the host */ |
334 | u8 ps_poll_threshold; | |
7f097988 | 335 | u8 pad[1]; |
ba2d3587 | 336 | } __packed; |
f5fc0f86 LC |
337 | |
338 | struct acx_event_mask { | |
339 | struct acx_header header; | |
340 | ||
d0f63b20 LC |
341 | __le32 event_mask; |
342 | __le32 high_event_mask; /* Unused */ | |
ba2d3587 | 343 | } __packed; |
f5fc0f86 | 344 | |
f5fc0f86 LC |
345 | #define SCAN_PASSIVE BIT(0) |
346 | #define SCAN_5GHZ_BAND BIT(1) | |
347 | #define SCAN_TRIGGERED BIT(2) | |
348 | #define SCAN_PRIORITY_HIGH BIT(3) | |
349 | ||
2b60100b JO |
350 | /* When set, disable HW encryption */ |
351 | #define DF_ENCRYPTION_DISABLE 0x01 | |
352 | #define DF_SNIFF_MODE_ENABLE 0x80 | |
353 | ||
f5fc0f86 LC |
354 | struct acx_feature_config { |
355 | struct acx_header header; | |
356 | ||
7f097988 EP |
357 | u8 role_id; |
358 | u8 padding[3]; | |
d0f63b20 LC |
359 | __le32 options; |
360 | __le32 data_flow_options; | |
ba2d3587 | 361 | } __packed; |
f5fc0f86 LC |
362 | |
363 | struct acx_current_tx_power { | |
364 | struct acx_header header; | |
365 | ||
7f097988 | 366 | u8 role_id; |
f5fc0f86 | 367 | u8 current_tx_power; |
7f097988 | 368 | u8 padding[2]; |
ba2d3587 | 369 | } __packed; |
f5fc0f86 | 370 | |
f5fc0f86 LC |
371 | struct acx_wake_up_condition { |
372 | struct acx_header header; | |
373 | ||
7f097988 | 374 | u8 role_id; |
f5fc0f86 LC |
375 | u8 wake_up_event; /* Only one bit can be set */ |
376 | u8 listen_interval; | |
7f097988 | 377 | u8 pad[1]; |
ba2d3587 | 378 | } __packed; |
f5fc0f86 LC |
379 | |
380 | struct acx_aid { | |
381 | struct acx_header header; | |
382 | ||
383 | /* | |
384 | * To be set when associated with an AP. | |
385 | */ | |
7f097988 EP |
386 | u8 role_id; |
387 | u8 reserved; | |
d0f63b20 | 388 | __le16 aid; |
ba2d3587 | 389 | } __packed; |
f5fc0f86 LC |
390 | |
391 | enum acx_preamble_type { | |
392 | ACX_PREAMBLE_LONG = 0, | |
393 | ACX_PREAMBLE_SHORT = 1 | |
394 | }; | |
395 | ||
396 | struct acx_preamble { | |
397 | struct acx_header header; | |
398 | ||
399 | /* | |
400 | * When set, the WiLink transmits the frames with a short preamble and | |
401 | * when cleared, the WiLink transmits the frames with a long preamble. | |
402 | */ | |
7f097988 | 403 | u8 role_id; |
f5fc0f86 | 404 | u8 preamble; |
7f097988 | 405 | u8 padding[2]; |
ba2d3587 | 406 | } __packed; |
f5fc0f86 LC |
407 | |
408 | enum acx_ctsprotect_type { | |
409 | CTSPROTECT_DISABLE = 0, | |
410 | CTSPROTECT_ENABLE = 1 | |
411 | }; | |
412 | ||
413 | struct acx_ctsprotect { | |
414 | struct acx_header header; | |
7f097988 | 415 | u8 role_id; |
f5fc0f86 | 416 | u8 ctsprotect; |
7f097988 | 417 | u8 padding[2]; |
ba2d3587 | 418 | } __packed; |
f5fc0f86 LC |
419 | |
420 | struct acx_tx_statistics { | |
d0f63b20 | 421 | __le32 internal_desc_overflow; |
ba2d3587 | 422 | } __packed; |
f5fc0f86 LC |
423 | |
424 | struct acx_rx_statistics { | |
d0f63b20 LC |
425 | __le32 out_of_mem; |
426 | __le32 hdr_overflow; | |
427 | __le32 hw_stuck; | |
428 | __le32 dropped; | |
429 | __le32 fcs_err; | |
430 | __le32 xfr_hint_trig; | |
431 | __le32 path_reset; | |
432 | __le32 reset_counter; | |
ba2d3587 | 433 | } __packed; |
f5fc0f86 LC |
434 | |
435 | struct acx_dma_statistics { | |
d0f63b20 LC |
436 | __le32 rx_requested; |
437 | __le32 rx_errors; | |
438 | __le32 tx_requested; | |
439 | __le32 tx_errors; | |
ba2d3587 | 440 | } __packed; |
f5fc0f86 LC |
441 | |
442 | struct acx_isr_statistics { | |
443 | /* host command complete */ | |
d0f63b20 | 444 | __le32 cmd_cmplt; |
f5fc0f86 LC |
445 | |
446 | /* fiqisr() */ | |
d0f63b20 | 447 | __le32 fiqs; |
f5fc0f86 LC |
448 | |
449 | /* (INT_STS_ND & INT_TRIG_RX_HEADER) */ | |
d0f63b20 | 450 | __le32 rx_headers; |
f5fc0f86 LC |
451 | |
452 | /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */ | |
d0f63b20 | 453 | __le32 rx_completes; |
f5fc0f86 LC |
454 | |
455 | /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */ | |
d0f63b20 | 456 | __le32 rx_mem_overflow; |
f5fc0f86 LC |
457 | |
458 | /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */ | |
d0f63b20 | 459 | __le32 rx_rdys; |
f5fc0f86 LC |
460 | |
461 | /* irqisr() */ | |
d0f63b20 | 462 | __le32 irqs; |
f5fc0f86 LC |
463 | |
464 | /* (INT_STS_ND & INT_TRIG_TX_PROC) */ | |
d0f63b20 | 465 | __le32 tx_procs; |
f5fc0f86 LC |
466 | |
467 | /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */ | |
d0f63b20 | 468 | __le32 decrypt_done; |
f5fc0f86 LC |
469 | |
470 | /* (INT_STS_ND & INT_TRIG_DMA0) */ | |
d0f63b20 | 471 | __le32 dma0_done; |
f5fc0f86 LC |
472 | |
473 | /* (INT_STS_ND & INT_TRIG_DMA1) */ | |
d0f63b20 | 474 | __le32 dma1_done; |
f5fc0f86 LC |
475 | |
476 | /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */ | |
d0f63b20 | 477 | __le32 tx_exch_complete; |
f5fc0f86 LC |
478 | |
479 | /* (INT_STS_ND & INT_TRIG_COMMAND) */ | |
d0f63b20 | 480 | __le32 commands; |
f5fc0f86 LC |
481 | |
482 | /* (INT_STS_ND & INT_TRIG_RX_PROC) */ | |
d0f63b20 | 483 | __le32 rx_procs; |
f5fc0f86 LC |
484 | |
485 | /* (INT_STS_ND & INT_TRIG_PM_802) */ | |
d0f63b20 | 486 | __le32 hw_pm_mode_changes; |
f5fc0f86 LC |
487 | |
488 | /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */ | |
d0f63b20 | 489 | __le32 host_acknowledges; |
f5fc0f86 LC |
490 | |
491 | /* (INT_STS_ND & INT_TRIG_PM_PCI) */ | |
d0f63b20 | 492 | __le32 pci_pm; |
f5fc0f86 LC |
493 | |
494 | /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */ | |
d0f63b20 | 495 | __le32 wakeups; |
f5fc0f86 LC |
496 | |
497 | /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */ | |
d0f63b20 | 498 | __le32 low_rssi; |
ba2d3587 | 499 | } __packed; |
f5fc0f86 LC |
500 | |
501 | struct acx_wep_statistics { | |
502 | /* WEP address keys configured */ | |
d0f63b20 | 503 | __le32 addr_key_count; |
f5fc0f86 LC |
504 | |
505 | /* default keys configured */ | |
d0f63b20 | 506 | __le32 default_key_count; |
f5fc0f86 | 507 | |
d0f63b20 | 508 | __le32 reserved; |
f5fc0f86 LC |
509 | |
510 | /* number of times that WEP key not found on lookup */ | |
d0f63b20 | 511 | __le32 key_not_found; |
f5fc0f86 LC |
512 | |
513 | /* number of times that WEP key decryption failed */ | |
d0f63b20 | 514 | __le32 decrypt_fail; |
f5fc0f86 LC |
515 | |
516 | /* WEP packets decrypted */ | |
d0f63b20 | 517 | __le32 packets; |
f5fc0f86 LC |
518 | |
519 | /* WEP decrypt interrupts */ | |
d0f63b20 | 520 | __le32 interrupt; |
ba2d3587 | 521 | } __packed; |
f5fc0f86 LC |
522 | |
523 | #define ACX_MISSED_BEACONS_SPREAD 10 | |
524 | ||
525 | struct acx_pwr_statistics { | |
526 | /* the amount of enters into power save mode (both PD & ELP) */ | |
d0f63b20 | 527 | __le32 ps_enter; |
f5fc0f86 LC |
528 | |
529 | /* the amount of enters into ELP mode */ | |
d0f63b20 | 530 | __le32 elp_enter; |
f5fc0f86 LC |
531 | |
532 | /* the amount of missing beacon interrupts to the host */ | |
d0f63b20 | 533 | __le32 missing_bcns; |
f5fc0f86 LC |
534 | |
535 | /* the amount of wake on host-access times */ | |
d0f63b20 | 536 | __le32 wake_on_host; |
f5fc0f86 LC |
537 | |
538 | /* the amount of wake on timer-expire */ | |
d0f63b20 | 539 | __le32 wake_on_timer_exp; |
f5fc0f86 LC |
540 | |
541 | /* the number of packets that were transmitted with PS bit set */ | |
d0f63b20 | 542 | __le32 tx_with_ps; |
f5fc0f86 LC |
543 | |
544 | /* the number of packets that were transmitted with PS bit clear */ | |
d0f63b20 | 545 | __le32 tx_without_ps; |
f5fc0f86 LC |
546 | |
547 | /* the number of received beacons */ | |
d0f63b20 | 548 | __le32 rcvd_beacons; |
f5fc0f86 LC |
549 | |
550 | /* the number of entering into PowerOn (power save off) */ | |
d0f63b20 | 551 | __le32 power_save_off; |
f5fc0f86 LC |
552 | |
553 | /* the number of entries into power save mode */ | |
d0f63b20 | 554 | __le16 enable_ps; |
f5fc0f86 LC |
555 | |
556 | /* | |
557 | * the number of exits from power save, not including failed PS | |
558 | * transitions | |
559 | */ | |
d0f63b20 | 560 | __le16 disable_ps; |
f5fc0f86 LC |
561 | |
562 | /* | |
563 | * the number of times the TSF counter was adjusted because | |
564 | * of drift | |
565 | */ | |
d0f63b20 | 566 | __le32 fix_tsf_ps; |
f5fc0f86 LC |
567 | |
568 | /* Gives statistics about the spread continuous missed beacons. | |
569 | * The 16 LSB are dedicated for the PS mode. | |
570 | * The 16 MSB are dedicated for the PS mode. | |
571 | * cont_miss_bcns_spread[0] - single missed beacon. | |
572 | * cont_miss_bcns_spread[1] - two continuous missed beacons. | |
573 | * cont_miss_bcns_spread[2] - three continuous missed beacons. | |
574 | * ... | |
575 | * cont_miss_bcns_spread[9] - ten and more continuous missed beacons. | |
576 | */ | |
d0f63b20 | 577 | __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD]; |
f5fc0f86 LC |
578 | |
579 | /* the number of beacons in awake mode */ | |
d0f63b20 | 580 | __le32 rcvd_awake_beacons; |
ba2d3587 | 581 | } __packed; |
f5fc0f86 LC |
582 | |
583 | struct acx_mic_statistics { | |
d0f63b20 LC |
584 | __le32 rx_pkts; |
585 | __le32 calc_failure; | |
ba2d3587 | 586 | } __packed; |
f5fc0f86 LC |
587 | |
588 | struct acx_aes_statistics { | |
d0f63b20 LC |
589 | __le32 encrypt_fail; |
590 | __le32 decrypt_fail; | |
591 | __le32 encrypt_packets; | |
592 | __le32 decrypt_packets; | |
593 | __le32 encrypt_interrupt; | |
594 | __le32 decrypt_interrupt; | |
ba2d3587 | 595 | } __packed; |
f5fc0f86 LC |
596 | |
597 | struct acx_event_statistics { | |
d0f63b20 LC |
598 | __le32 heart_beat; |
599 | __le32 calibration; | |
600 | __le32 rx_mismatch; | |
601 | __le32 rx_mem_empty; | |
602 | __le32 rx_pool; | |
603 | __le32 oom_late; | |
604 | __le32 phy_transmit_error; | |
605 | __le32 tx_stuck; | |
ba2d3587 | 606 | } __packed; |
f5fc0f86 LC |
607 | |
608 | struct acx_ps_statistics { | |
d0f63b20 LC |
609 | __le32 pspoll_timeouts; |
610 | __le32 upsd_timeouts; | |
611 | __le32 upsd_max_sptime; | |
612 | __le32 upsd_max_apturn; | |
613 | __le32 pspoll_max_apturn; | |
614 | __le32 pspoll_utilization; | |
615 | __le32 upsd_utilization; | |
ba2d3587 | 616 | } __packed; |
f5fc0f86 LC |
617 | |
618 | struct acx_rxpipe_statistics { | |
d0f63b20 LC |
619 | __le32 rx_prep_beacon_drop; |
620 | __le32 descr_host_int_trig_rx_data; | |
621 | __le32 beacon_buffer_thres_host_int_trig_rx_data; | |
622 | __le32 missed_beacon_host_int_trig_rx_data; | |
623 | __le32 tx_xfr_host_int_trig_rx_data; | |
ba2d3587 | 624 | } __packed; |
f5fc0f86 LC |
625 | |
626 | struct acx_statistics { | |
627 | struct acx_header header; | |
628 | ||
629 | struct acx_tx_statistics tx; | |
630 | struct acx_rx_statistics rx; | |
631 | struct acx_dma_statistics dma; | |
632 | struct acx_isr_statistics isr; | |
633 | struct acx_wep_statistics wep; | |
634 | struct acx_pwr_statistics pwr; | |
635 | struct acx_aes_statistics aes; | |
636 | struct acx_mic_statistics mic; | |
637 | struct acx_event_statistics event; | |
638 | struct acx_ps_statistics ps; | |
639 | struct acx_rxpipe_statistics rxpipe; | |
ba2d3587 | 640 | } __packed; |
f5fc0f86 | 641 | |
f5fc0f86 | 642 | struct acx_rate_class { |
d0f63b20 | 643 | __le32 enabled_rates; |
f5fc0f86 LC |
644 | u8 short_retry_limit; |
645 | u8 long_retry_limit; | |
646 | u8 aflags; | |
647 | u8 reserved; | |
648 | }; | |
649 | ||
7f097988 | 650 | struct acx_rate_policy { |
79b223f4 AN |
651 | struct acx_header header; |
652 | ||
653 | __le32 rate_policy_idx; | |
654 | struct acx_rate_class rate_policy; | |
655 | } __packed; | |
656 | ||
f5fc0f86 LC |
657 | struct acx_ac_cfg { |
658 | struct acx_header header; | |
7f097988 | 659 | u8 role_id; |
f5fc0f86 | 660 | u8 ac; |
7f097988 | 661 | u8 aifsn; |
f5fc0f86 | 662 | u8 cw_min; |
d0f63b20 | 663 | __le16 cw_max; |
d0f63b20 | 664 | __le16 tx_op_limit; |
ba2d3587 | 665 | } __packed; |
f5fc0f86 | 666 | |
f5fc0f86 LC |
667 | struct acx_tid_config { |
668 | struct acx_header header; | |
7f097988 | 669 | u8 role_id; |
f5fc0f86 LC |
670 | u8 queue_id; |
671 | u8 channel_type; | |
672 | u8 tsid; | |
673 | u8 ps_scheme; | |
674 | u8 ack_policy; | |
7f097988 | 675 | u8 padding[2]; |
d0f63b20 | 676 | __le32 apsd_conf[2]; |
ba2d3587 | 677 | } __packed; |
f5fc0f86 LC |
678 | |
679 | struct acx_frag_threshold { | |
680 | struct acx_header header; | |
d0f63b20 | 681 | __le16 frag_threshold; |
f5fc0f86 | 682 | u8 padding[2]; |
ba2d3587 | 683 | } __packed; |
f5fc0f86 | 684 | |
f5fc0f86 LC |
685 | struct acx_tx_config_options { |
686 | struct acx_header header; | |
d0f63b20 LC |
687 | __le16 tx_compl_timeout; /* msec */ |
688 | __le16 tx_compl_threshold; /* number of packets */ | |
ba2d3587 | 689 | } __packed; |
f5fc0f86 | 690 | |
7f097988 | 691 | struct wl12xx_acx_config_memory { |
c8bde243 EP |
692 | struct acx_header header; |
693 | ||
694 | u8 rx_mem_block_num; | |
695 | u8 tx_min_mem_block_num; | |
696 | u8 num_stations; | |
697 | u8 num_ssid_profiles; | |
698 | __le32 total_tx_descriptors; | |
699 | u8 dyn_mem_enable; | |
700 | u8 tx_free_req; | |
701 | u8 rx_free_req; | |
702 | u8 tx_min; | |
95dac04f IY |
703 | u8 fwlog_blocks; |
704 | u8 padding[3]; | |
c8bde243 EP |
705 | } __packed; |
706 | ||
f5fc0f86 LC |
707 | struct wl1271_acx_mem_map { |
708 | struct acx_header header; | |
709 | ||
d0f63b20 LC |
710 | __le32 code_start; |
711 | __le32 code_end; | |
f5fc0f86 | 712 | |
d0f63b20 LC |
713 | __le32 wep_defkey_start; |
714 | __le32 wep_defkey_end; | |
f5fc0f86 | 715 | |
d0f63b20 LC |
716 | __le32 sta_table_start; |
717 | __le32 sta_table_end; | |
f5fc0f86 | 718 | |
d0f63b20 LC |
719 | __le32 packet_template_start; |
720 | __le32 packet_template_end; | |
f5fc0f86 LC |
721 | |
722 | /* Address of the TX result interface (control block) */ | |
d0f63b20 LC |
723 | __le32 tx_result; |
724 | __le32 tx_result_queue_start; | |
f5fc0f86 | 725 | |
d0f63b20 LC |
726 | __le32 queue_memory_start; |
727 | __le32 queue_memory_end; | |
f5fc0f86 | 728 | |
d0f63b20 LC |
729 | __le32 packet_memory_pool_start; |
730 | __le32 packet_memory_pool_end; | |
f5fc0f86 | 731 | |
d0f63b20 LC |
732 | __le32 debug_buffer1_start; |
733 | __le32 debug_buffer1_end; | |
f5fc0f86 | 734 | |
d0f63b20 LC |
735 | __le32 debug_buffer2_start; |
736 | __le32 debug_buffer2_end; | |
f5fc0f86 LC |
737 | |
738 | /* Number of blocks FW allocated for TX packets */ | |
d0f63b20 | 739 | __le32 num_tx_mem_blocks; |
f5fc0f86 LC |
740 | |
741 | /* Number of blocks FW allocated for RX packets */ | |
d0f63b20 | 742 | __le32 num_rx_mem_blocks; |
f5fc0f86 LC |
743 | |
744 | /* the following 4 fields are valid in SLAVE mode only */ | |
745 | u8 *tx_cbuf; | |
746 | u8 *rx_cbuf; | |
d0f63b20 LC |
747 | __le32 rx_ctrl; |
748 | __le32 tx_ctrl; | |
ba2d3587 | 749 | } __packed; |
f5fc0f86 | 750 | |
f5fc0f86 LC |
751 | struct wl1271_acx_rx_config_opt { |
752 | struct acx_header header; | |
753 | ||
d0f63b20 LC |
754 | __le16 mblk_threshold; |
755 | __le16 threshold; | |
756 | __le16 timeout; | |
f5fc0f86 LC |
757 | u8 queue_type; |
758 | u8 reserved; | |
ba2d3587 | 759 | } __packed; |
f5fc0f86 | 760 | |
11f70f97 JO |
761 | |
762 | struct wl1271_acx_bet_enable { | |
763 | struct acx_header header; | |
764 | ||
7f097988 | 765 | u8 role_id; |
11f70f97 JO |
766 | u8 enable; |
767 | u8 max_consecutive; | |
7f097988 | 768 | u8 padding[1]; |
ba2d3587 | 769 | } __packed; |
11f70f97 | 770 | |
01c09162 JO |
771 | #define ACX_IPV4_VERSION 4 |
772 | #define ACX_IPV6_VERSION 6 | |
773 | #define ACX_IPV4_ADDR_SIZE 4 | |
c5312772 EP |
774 | |
775 | /* bitmap of enabled arp_filter features */ | |
776 | #define ACX_ARP_FILTER_ARP_FILTERING BIT(0) | |
777 | #define ACX_ARP_FILTER_AUTO_ARP BIT(1) | |
778 | ||
01c09162 JO |
779 | struct wl1271_acx_arp_filter { |
780 | struct acx_header header; | |
7f097988 | 781 | u8 role_id; |
01c09162 | 782 | u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */ |
c5312772 | 783 | u8 enable; /* bitmap of enabled ARP filtering features */ |
7f097988 | 784 | u8 padding[1]; |
01c09162 JO |
785 | u8 address[16]; /* The configured device IP address - all ARP |
786 | requests directed to this IP address will pass | |
787 | through. For IPv4, the first four bytes are | |
788 | used. */ | |
ba2d3587 | 789 | } __packed; |
01c09162 | 790 | |
38ad2d87 JO |
791 | struct wl1271_acx_pm_config { |
792 | struct acx_header header; | |
793 | ||
794 | __le32 host_clk_settling_time; | |
795 | u8 host_fast_wakeup_support; | |
796 | u8 padding[3]; | |
ba2d3587 | 797 | } __packed; |
01c09162 | 798 | |
c1899554 JO |
799 | struct wl1271_acx_keep_alive_mode { |
800 | struct acx_header header; | |
801 | ||
7f097988 | 802 | u8 role_id; |
c1899554 | 803 | u8 enabled; |
7f097988 | 804 | u8 padding[2]; |
ba2d3587 | 805 | } __packed; |
c1899554 JO |
806 | |
807 | enum { | |
808 | ACX_KEEP_ALIVE_NO_TX = 0, | |
809 | ACX_KEEP_ALIVE_PERIOD_ONLY | |
810 | }; | |
811 | ||
812 | enum { | |
813 | ACX_KEEP_ALIVE_TPL_INVALID = 0, | |
814 | ACX_KEEP_ALIVE_TPL_VALID | |
815 | }; | |
816 | ||
817 | struct wl1271_acx_keep_alive_config { | |
818 | struct acx_header header; | |
819 | ||
7f097988 | 820 | u8 role_id; |
c1899554 JO |
821 | u8 index; |
822 | u8 tpl_validation; | |
823 | u8 trigger; | |
7f097988 | 824 | __le32 period; |
ba2d3587 | 825 | } __packed; |
c1899554 | 826 | |
9d68d1ee | 827 | /* TODO: maybe this needs to be moved somewhere else? */ |
48a61477 SL |
828 | #define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0) |
829 | #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1) | |
830 | #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3) | |
831 | ||
00236aed JO |
832 | enum { |
833 | WL1271_ACX_TRIG_TYPE_LEVEL = 0, | |
834 | WL1271_ACX_TRIG_TYPE_EDGE, | |
835 | }; | |
836 | ||
837 | enum { | |
838 | WL1271_ACX_TRIG_DIR_LOW = 0, | |
839 | WL1271_ACX_TRIG_DIR_HIGH, | |
840 | WL1271_ACX_TRIG_DIR_BIDIR, | |
841 | }; | |
842 | ||
843 | enum { | |
844 | WL1271_ACX_TRIG_ENABLE = 1, | |
845 | WL1271_ACX_TRIG_DISABLE, | |
846 | }; | |
847 | ||
848 | enum { | |
849 | WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0, | |
850 | WL1271_ACX_TRIG_METRIC_RSSI_DATA, | |
851 | WL1271_ACX_TRIG_METRIC_SNR_BEACON, | |
852 | WL1271_ACX_TRIG_METRIC_SNR_DATA, | |
853 | }; | |
854 | ||
855 | enum { | |
856 | WL1271_ACX_TRIG_IDX_RSSI = 0, | |
857 | WL1271_ACX_TRIG_COUNT = 8, | |
858 | }; | |
859 | ||
860 | struct wl1271_acx_rssi_snr_trigger { | |
861 | struct acx_header header; | |
862 | ||
7f097988 | 863 | u8 role_id; |
00236aed JO |
864 | u8 metric; |
865 | u8 type; | |
866 | u8 dir; | |
7f097988 EP |
867 | __le16 threshold; |
868 | __le16 pacing; /* 0 - 60000 ms */ | |
00236aed JO |
869 | u8 hysteresis; |
870 | u8 index; | |
871 | u8 enable; | |
7f097988 | 872 | u8 padding[1]; |
00236aed JO |
873 | }; |
874 | ||
875 | struct wl1271_acx_rssi_snr_avg_weights { | |
876 | struct acx_header header; | |
877 | ||
7f097988 EP |
878 | u8 role_id; |
879 | u8 padding[3]; | |
00236aed JO |
880 | u8 rssi_beacon; |
881 | u8 rssi_data; | |
882 | u8 snr_beacon; | |
883 | u8 snr_data; | |
884 | }; | |
885 | ||
0f9c8250 AN |
886 | |
887 | /* special capability bit (not employed by the 802.11n spec) */ | |
888 | #define WL12XX_HT_CAP_HT_OPERATION BIT(16) | |
889 | ||
e8b03a2b SL |
890 | /* |
891 | * ACX_PEER_HT_CAP | |
892 | * Configure HT capabilities - declare the capabilities of the peer | |
893 | * we are connected to. | |
894 | */ | |
895 | struct wl1271_acx_ht_capabilities { | |
896 | struct acx_header header; | |
897 | ||
0f9c8250 | 898 | /* bitmask of capability bits supported by the peer */ |
e8b03a2b SL |
899 | __le32 ht_capabilites; |
900 | ||
7f097988 EP |
901 | /* Indicates to which link these capabilities apply. */ |
902 | u8 hlid; | |
e8b03a2b SL |
903 | |
904 | /* | |
905 | * This the maximum A-MPDU length supported by the AP. The FW may not | |
906 | * exceed this length when sending A-MPDUs | |
907 | */ | |
908 | u8 ampdu_max_length; | |
909 | ||
910 | /* This is the minimal spacing required when sending A-MPDUs to the AP*/ | |
911 | u8 ampdu_min_spacing; | |
7f097988 EP |
912 | |
913 | u8 padding; | |
e8b03a2b SL |
914 | } __packed; |
915 | ||
e8b03a2b SL |
916 | /* |
917 | * ACX_HT_BSS_OPERATION | |
918 | * Configure HT capabilities - AP rules for behavior in the BSS. | |
919 | */ | |
920 | struct wl1271_acx_ht_information { | |
921 | struct acx_header header; | |
922 | ||
7f097988 EP |
923 | u8 role_id; |
924 | ||
e8b03a2b SL |
925 | /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */ |
926 | u8 rifs_mode; | |
927 | ||
928 | /* Values: 0 - 3 like in spec */ | |
929 | u8 ht_protection; | |
930 | ||
931 | /* Values: 0 - GF protection not required, 1 - GF protection required */ | |
932 | u8 gf_protection; | |
933 | ||
934 | /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/ | |
935 | u8 ht_tx_burst_limit; | |
936 | ||
937 | /* | |
938 | * Values: 0 - Dual CTS protection not required, | |
939 | * 1 - Dual CTS Protection required | |
940 | * Note: When this value is set to 1 FW will protect all TXOP with RTS | |
941 | * frame and will not use CTS-to-self regardless of the value of the | |
942 | * ACX_CTS_PROTECTION information element | |
943 | */ | |
944 | u8 dual_cts_protection; | |
945 | ||
7f097988 | 946 | u8 padding[2]; |
e8b03a2b SL |
947 | } __packed; |
948 | ||
0f9c8250 | 949 | #define RX_BA_MAX_SESSIONS 2 |
4b7fac77 | 950 | |
0f9c8250 | 951 | struct wl1271_acx_ba_initiator_policy { |
4b7fac77 | 952 | struct acx_header header; |
0f9c8250 AN |
953 | |
954 | /* Specifies role Id, Range 0-7, 0xFF means ANY role. */ | |
4b7fac77 | 955 | u8 role_id; |
0f9c8250 | 956 | |
4b7fac77 | 957 | /* |
0f9c8250 AN |
958 | * Per TID setting for allowing TX BA. Set a bit to 1 to allow |
959 | * TX BA sessions for the corresponding TID. | |
4b7fac77 | 960 | */ |
0f9c8250 | 961 | u8 tid_bitmap; |
4b7fac77 LS |
962 | |
963 | /* Windows size in number of packets */ | |
0f9c8250 | 964 | u8 win_size; |
4b7fac77 | 965 | |
0f9c8250 | 966 | u8 padding1[1]; |
4b7fac77 | 967 | |
0f9c8250 AN |
968 | /* As initiator inactivity timeout in time units(TU) of 1024us */ |
969 | u16 inactivity_timeout; | |
4b7fac77 | 970 | |
0f9c8250 | 971 | u8 padding[2]; |
4b7fac77 LS |
972 | } __packed; |
973 | ||
bbba3e68 LS |
974 | struct wl1271_acx_ba_receiver_setup { |
975 | struct acx_header header; | |
976 | ||
0f9c8250 AN |
977 | /* Specifies link id, range 0-31 */ |
978 | u8 hlid; | |
bbba3e68 LS |
979 | |
980 | u8 tid; | |
981 | ||
982 | u8 enable; | |
983 | ||
bbba3e68 | 984 | /* Windows size in number of packets */ |
0f9c8250 | 985 | u8 win_size; |
bbba3e68 LS |
986 | |
987 | /* BA session starting sequence number. RANGE 0-FFF */ | |
988 | u16 ssn; | |
0f9c8250 AN |
989 | |
990 | u8 padding[2]; | |
bbba3e68 LS |
991 | } __packed; |
992 | ||
9c531149 | 993 | struct wl12xx_acx_fw_tsf_information { |
bbbb538e JO |
994 | struct acx_header header; |
995 | ||
9c531149 EP |
996 | u8 role_id; |
997 | u8 padding1[3]; | |
bbbb538e JO |
998 | __le32 current_tsf_high; |
999 | __le32 current_tsf_low; | |
1000 | __le32 last_bttt_high; | |
1001 | __le32 last_tbtt_low; | |
1002 | u8 last_dtim_count; | |
9c531149 | 1003 | u8 padding2[3]; |
72e93e91 | 1004 | } __packed; |
bbbb538e | 1005 | |
f84673d5 EP |
1006 | struct wl1271_acx_ps_rx_streaming { |
1007 | struct acx_header header; | |
1008 | ||
7f097988 | 1009 | u8 role_id; |
f84673d5 EP |
1010 | u8 tid; |
1011 | u8 enable; | |
1012 | ||
1013 | /* interval between triggers (10-100 msec) */ | |
1014 | u8 period; | |
1015 | ||
1016 | /* timeout before first trigger (0-200 msec) */ | |
1017 | u8 timeout; | |
7f097988 | 1018 | u8 padding[3]; |
f84673d5 EP |
1019 | } __packed; |
1020 | ||
3618f30f | 1021 | struct wl1271_acx_ap_max_tx_retry { |
79b223f4 AN |
1022 | struct acx_header header; |
1023 | ||
7f097988 EP |
1024 | u8 role_id; |
1025 | u8 padding_1; | |
1026 | ||
79b223f4 AN |
1027 | /* |
1028 | * the number of frames transmission failures before | |
1029 | * issuing the aging event. | |
1030 | */ | |
1031 | __le16 max_tx_retry; | |
79b223f4 AN |
1032 | } __packed; |
1033 | ||
ee60833a EP |
1034 | struct wl1271_acx_config_ps { |
1035 | struct acx_header header; | |
1036 | ||
1037 | u8 exit_retries; | |
1038 | u8 enter_retries; | |
1039 | u8 padding[2]; | |
1040 | __le32 null_data_rate; | |
1041 | } __packed; | |
1042 | ||
99a2775d AN |
1043 | struct wl1271_acx_inconnection_sta { |
1044 | struct acx_header header; | |
1045 | ||
1046 | u8 addr[ETH_ALEN]; | |
1047 | u8 padding1[2]; | |
1048 | } __packed; | |
1049 | ||
ff86843d SL |
1050 | /* |
1051 | * ACX_FM_COEX_CFG | |
1052 | * set the FM co-existence parameters. | |
1053 | */ | |
1054 | struct wl1271_acx_fm_coex { | |
1055 | struct acx_header header; | |
1056 | /* enable(1) / disable(0) the FM Coex feature */ | |
1057 | u8 enable; | |
1058 | /* | |
1059 | * Swallow period used in COEX PLL swallowing mechanism. | |
1060 | * 0xFF = use FW default | |
1061 | */ | |
1062 | u8 swallow_period; | |
1063 | /* | |
1064 | * The N divider used in COEX PLL swallowing mechanism for Fref of | |
1065 | * 38.4/19.2 Mhz. 0xFF = use FW default | |
1066 | */ | |
1067 | u8 n_divider_fref_set_1; | |
1068 | /* | |
1069 | * The N divider used in COEX PLL swallowing mechanism for Fref of | |
1070 | * 26/52 Mhz. 0xFF = use FW default | |
1071 | */ | |
1072 | u8 n_divider_fref_set_2; | |
1073 | /* | |
1074 | * The M divider used in COEX PLL swallowing mechanism for Fref of | |
1075 | * 38.4/19.2 Mhz. 0xFFFF = use FW default | |
1076 | */ | |
1077 | __le16 m_divider_fref_set_1; | |
1078 | /* | |
1079 | * The M divider used in COEX PLL swallowing mechanism for Fref of | |
1080 | * 26/52 Mhz. 0xFFFF = use FW default | |
1081 | */ | |
1082 | __le16 m_divider_fref_set_2; | |
1083 | /* | |
1084 | * The time duration in uSec required for COEX PLL to stabilize. | |
1085 | * 0xFFFFFFFF = use FW default | |
1086 | */ | |
1087 | __le32 coex_pll_stabilization_time; | |
1088 | /* | |
1089 | * The time duration in uSec required for LDO to stabilize. | |
1090 | * 0xFFFFFFFF = use FW default | |
1091 | */ | |
1092 | __le16 ldo_stabilization_time; | |
1093 | /* | |
1094 | * The disturbed frequency band margin around the disturbed frequency | |
1095 | * center (single sided). | |
1096 | * For example, if 2 is configured, the following channels will be | |
1097 | * considered disturbed channel: | |
1098 | * 80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH | |
1099 | * 0xFF = use FW default | |
1100 | */ | |
1101 | u8 fm_disturbed_band_margin; | |
1102 | /* | |
1103 | * The swallow clock difference of the swallowing mechanism. | |
1104 | * 0xFF = use FW default | |
1105 | */ | |
1106 | u8 swallow_clk_diff; | |
1107 | } __packed; | |
1108 | ||
fa6ad9f0 EP |
1109 | #define ACX_RATE_MGMT_ALL_PARAMS 0xff |
1110 | struct wl12xx_acx_set_rate_mgmt_params { | |
1111 | struct acx_header header; | |
1112 | ||
1113 | u8 index; /* 0xff to configure all params */ | |
1114 | u8 padding1; | |
1115 | __le16 rate_retry_score; | |
1116 | __le16 per_add; | |
1117 | __le16 per_th1; | |
1118 | __le16 per_th2; | |
1119 | __le16 max_per; | |
1120 | u8 inverse_curiosity_factor; | |
1121 | u8 tx_fail_low_th; | |
1122 | u8 tx_fail_high_th; | |
1123 | u8 per_alpha_shift; | |
1124 | u8 per_add_shift; | |
1125 | u8 per_beta1_shift; | |
1126 | u8 per_beta2_shift; | |
1127 | u8 rate_check_up; | |
1128 | u8 rate_check_down; | |
1129 | u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES]; | |
1130 | u8 padding2[2]; | |
1131 | } __packed; | |
1132 | ||
9487775c EP |
1133 | struct wl12xx_acx_config_hangover { |
1134 | struct acx_header header; | |
1135 | ||
1136 | __le32 recover_time; | |
1137 | u8 hangover_period; | |
1138 | u8 dynamic_mode; | |
1139 | u8 early_termination_mode; | |
1140 | u8 max_period; | |
1141 | u8 min_period; | |
1142 | u8 increase_delta; | |
1143 | u8 decrease_delta; | |
1144 | u8 quiet_time; | |
1145 | u8 increase_time; | |
1146 | u8 window_size; | |
1147 | u8 padding[2]; | |
1148 | } __packed; | |
1149 | ||
f5fc0f86 | 1150 | enum { |
8332f0f6 EP |
1151 | ACX_WAKE_UP_CONDITIONS = 0x0000, |
1152 | ACX_MEM_CFG = 0x0001, | |
1153 | ACX_SLOT = 0x0002, | |
1154 | ACX_AC_CFG = 0x0003, | |
1155 | ACX_MEM_MAP = 0x0004, | |
1156 | ACX_AID = 0x0005, | |
1157 | ACX_MEDIUM_USAGE = 0x0006, | |
1158 | ACX_STATISTICS = 0x0007, | |
1159 | ACX_PWR_CONSUMPTION_STATISTICS = 0x0008, | |
1160 | ACX_TID_CFG = 0x0009, | |
1161 | ACX_PS_RX_STREAMING = 0x000A, | |
1162 | ACX_BEACON_FILTER_OPT = 0x000B, | |
1163 | ACX_NOISE_HIST = 0x000C, | |
1164 | ACX_HDK_VERSION = 0x000D, | |
1165 | ACX_PD_THRESHOLD = 0x000E, | |
1166 | ACX_TX_CONFIG_OPT = 0x000F, | |
1167 | ACX_CCA_THRESHOLD = 0x0010, | |
1168 | ACX_EVENT_MBOX_MASK = 0x0011, | |
1169 | ACX_CONN_MONIT_PARAMS = 0x0012, | |
1170 | ACX_DISABLE_BROADCASTS = 0x0013, | |
1171 | ACX_BCN_DTIM_OPTIONS = 0x0014, | |
1172 | ACX_SG_ENABLE = 0x0015, | |
1173 | ACX_SG_CFG = 0x0016, | |
1174 | ACX_FM_COEX_CFG = 0x0017, | |
1175 | ACX_BEACON_FILTER_TABLE = 0x0018, | |
1176 | ACX_ARP_IP_FILTER = 0x0019, | |
1177 | ACX_ROAMING_STATISTICS_TBL = 0x001A, | |
1178 | ACX_RATE_POLICY = 0x001B, | |
1179 | ACX_CTS_PROTECTION = 0x001C, | |
1180 | ACX_SLEEP_AUTH = 0x001D, | |
1181 | ACX_PREAMBLE_TYPE = 0x001E, | |
1182 | ACX_ERROR_CNT = 0x001F, | |
1183 | ACX_IBSS_FILTER = 0x0020, | |
1184 | ACX_SERVICE_PERIOD_TIMEOUT = 0x0021, | |
1185 | ACX_TSF_INFO = 0x0022, | |
1186 | ACX_CONFIG_PS_WMM = 0x0023, | |
1187 | ACX_ENABLE_RX_DATA_FILTER = 0x0024, | |
1188 | ACX_SET_RX_DATA_FILTER = 0x0025, | |
1189 | ACX_GET_DATA_FILTER_STATISTICS = 0x0026, | |
1190 | ACX_RX_CONFIG_OPT = 0x0027, | |
1191 | ACX_FRAG_CFG = 0x0028, | |
1192 | ACX_BET_ENABLE = 0x0029, | |
1193 | ACX_RSSI_SNR_TRIGGER = 0x002A, | |
1194 | ACX_RSSI_SNR_WEIGHTS = 0x002B, | |
1195 | ACX_KEEP_ALIVE_MODE = 0x002C, | |
1196 | ACX_SET_KEEP_ALIVE_CONFIG = 0x002D, | |
1197 | ACX_BA_SESSION_INIT_POLICY = 0x002E, | |
1198 | ACX_BA_SESSION_RX_SETUP = 0x002F, | |
1199 | ACX_PEER_HT_CAP = 0x0030, | |
1200 | ACX_HT_BSS_OPERATION = 0x0031, | |
1201 | ACX_COEX_ACTIVITY = 0x0032, | |
1202 | ACX_BURST_MODE = 0x0033, | |
1203 | ACX_SET_RATE_MGMT_PARAMS = 0x0034, | |
1204 | ACX_GET_RATE_MGMT_PARAMS = 0x0035, | |
1205 | ACX_SET_RATE_ADAPT_PARAMS = 0x0036, | |
1206 | ACX_SET_DCO_ITRIM_PARAMS = 0x0037, | |
1207 | ACX_GEN_FW_CMD = 0x0038, | |
1208 | ACX_HOST_IF_CFG_BITMAP = 0x0039, | |
1209 | ACX_MAX_TX_FAILURE = 0x003A, | |
1210 | ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B, | |
1211 | DOT11_RX_MSDU_LIFE_TIME = 0x003C, | |
1212 | DOT11_CUR_TX_PWR = 0x003D, | |
1213 | DOT11_RTS_THRESHOLD = 0x003E, | |
1214 | DOT11_GROUP_ADDRESS_TBL = 0x003F, | |
1215 | ACX_PM_CONFIG = 0x0040, | |
1216 | ACX_CONFIG_PS = 0x0041, | |
1217 | ACX_CONFIG_HANGOVER = 0x0042, | |
1218 | ACX_FEATURE_CFG = 0x0043, | |
1219 | ACX_PROTECTION_CFG = 0x0044, | |
f5fc0f86 LC |
1220 | }; |
1221 | ||
1222 | ||
0603d891 | 1223 | int wl1271_acx_wake_up_conditions(struct wl1271 *wl, |
dae728fe ES |
1224 | struct wl12xx_vif *wlvif, |
1225 | u8 wake_up_event, u8 listen_interval); | |
f5fc0f86 | 1226 | int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth); |
0603d891 EP |
1227 | int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1228 | int power); | |
1229 | int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif); | |
f5fc0f86 LC |
1230 | int wl1271_acx_mem_map(struct wl1271 *wl, |
1231 | struct acx_header *mem_map, size_t len); | |
8793f9bb | 1232 | int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl); |
0603d891 EP |
1233 | int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1234 | enum acx_slot_type slot_time); | |
1235 | int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1236 | bool enable, void *mc_list, u32 mc_list_len); | |
1237 | int wl1271_acx_service_period_timeout(struct wl1271 *wl, | |
1238 | struct wl12xx_vif *wlvif); | |
1239 | int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1240 | u32 rts_threshold); | |
6e92b416 | 1241 | int wl1271_acx_dco_itrim_params(struct wl1271 *wl); |
0603d891 EP |
1242 | int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1243 | bool enable_filter); | |
1244 | int wl1271_acx_beacon_filter_table(struct wl1271 *wl, | |
1245 | struct wl12xx_vif *wlvif); | |
1246 | int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1247 | bool enable); | |
7fc3a864 | 1248 | int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable); |
3be4112c | 1249 | int wl12xx_acx_sg_cfg(struct wl1271 *wl); |
f5fc0f86 | 1250 | int wl1271_acx_cca_threshold(struct wl1271 *wl); |
0603d891 EP |
1251 | int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
1252 | int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid); | |
f5fc0f86 | 1253 | int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask); |
0603d891 EP |
1254 | int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1255 | enum acx_preamble_type preamble); | |
1256 | int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
11f70f97 | 1257 | enum acx_ctsprotect_type ctsprotect); |
f5fc0f86 | 1258 | int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats); |
30d0c8fd | 1259 | int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
79b223f4 AN |
1260 | int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c, |
1261 | u8 idx); | |
0603d891 EP |
1262 | int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1263 | u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop); | |
1264 | int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1265 | u8 queue_id, u8 channel_type, | |
f2054df5 KV |
1266 | u8 tsid, u8 ps_scheme, u8 ack_policy, |
1267 | u32 apsd_conf0, u32 apsd_conf1); | |
5f704d18 | 1268 | int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold); |
f5fc0f86 | 1269 | int wl1271_acx_tx_config_options(struct wl1271 *wl); |
7f097988 | 1270 | int wl12xx_acx_mem_cfg(struct wl1271 *wl); |
f5fc0f86 LC |
1271 | int wl1271_acx_init_mem_config(struct wl1271 *wl); |
1272 | int wl1271_acx_init_rx_interrupt(struct wl1271 *wl); | |
3cfd6cf9 | 1273 | int wl1271_acx_smart_reflex(struct wl1271 *wl); |
0603d891 EP |
1274 | int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1275 | bool enable); | |
1276 | int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1277 | u8 enable, __be32 address); | |
38ad2d87 | 1278 | int wl1271_acx_pm_config(struct wl1271 *wl); |
0603d891 EP |
1279 | int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif, |
1280 | bool enable); | |
1281 | int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1282 | u8 index, u8 tpl_valid); | |
1283 | int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1284 | bool enable, s16 thold, u8 hyst); | |
1285 | int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl, | |
1286 | struct wl12xx_vif *wlvif); | |
c4db1c87 SL |
1287 | int wl1271_acx_set_ht_capabilities(struct wl1271 *wl, |
1288 | struct ieee80211_sta_ht_cap *ht_cap, | |
0b932ab9 | 1289 | bool allow_ht_operation, u8 hlid); |
c4db1c87 | 1290 | int wl1271_acx_set_ht_information(struct wl1271 *wl, |
0603d891 | 1291 | struct wl12xx_vif *wlvif, |
c4db1c87 | 1292 | u16 ht_operation_mode); |
0603d891 EP |
1293 | int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl, |
1294 | struct wl12xx_vif *wlvif); | |
0f9c8250 AN |
1295 | int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, |
1296 | u16 ssn, bool enable, u8 peer_hlid); | |
9c531149 EP |
1297 | int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1298 | u64 *mactime); | |
9eb599e9 EP |
1299 | int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1300 | bool enable); | |
0603d891 | 1301 | int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
d2d66c56 | 1302 | int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
99a2775d | 1303 | int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr); |
ff86843d | 1304 | int wl1271_acx_fm_coex(struct wl1271 *wl); |
fa6ad9f0 | 1305 | int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl); |
9487775c | 1306 | int wl12xx_acx_config_hangover(struct wl1271 *wl); |
f5fc0f86 LC |
1307 | |
1308 | #endif /* __WL1271_ACX_H__ */ |