[deliverable/linux.git] / drivers / net / wireless / ti / wlcore / boot.c

/*
 * This file is part of wl1271
 *
 * Copyright (C) 2008-2010 Nokia Corporation
 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/slab.h>
#include <linux/wl12xx.h>
#include <linux/export.h>

#include "debug.h"
#include "acx.h"
#include "boot.h"
#include "io.h"
#include "event.h"
#include "rx.h"

static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
{
	u32 cpu_ctrl;

	/* 10.5.0 run the firmware (I) */
	cpu_ctrl = wlcore_read_reg(wl, REG_ECPU_CONTROL);

	/* 10.5.1 run the firmware (II) */
	cpu_ctrl |= flag;
	wlcore_write_reg(wl, REG_ECPU_CONTROL, cpu_ctrl);
}

static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl)
{
	unsigned int quirks = 0;
	unsigned int *fw_ver = wl->chip.fw_ver;

	/* Only new station firmwares support routing fw logs to the host */
	if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
	    (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
		quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;

	/* This feature is not yet supported for AP mode */
	if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
		quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;

	return quirks;
}

static void wl1271_parse_fw_ver(struct wl1271 *wl)
{
	int ret;

	ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
		     &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
		     &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
		     &wl->chip.fw_ver[4]);

	if (ret != 5) {
		wl1271_warning("fw version incorrect value");
		memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
		return;
	}

	/* Check if any quirks are needed with older fw versions */
	wl->quirks |= wl12xx_get_fw_ver_quirks(wl);
}

static void wl1271_boot_fw_version(struct wl1271 *wl)
{
	struct wl1271_static_data *static_data;

	static_data = kmalloc(sizeof(*static_data), GFP_DMA);
	if (!static_data) {
		__WARN();
		return;
	}

	wl1271_read(wl, wl->cmd_box_addr, static_data, sizeof(*static_data),
		    false);

	strncpy(wl->chip.fw_ver_str, static_data->fw_version,
		sizeof(wl->chip.fw_ver_str));

	kfree(static_data);

	/* make sure the string is NULL-terminated */
	wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';

	wl1271_parse_fw_ver(wl);
}

static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
					     size_t fw_data_len, u32 dest)
{
	struct wlcore_partition_set partition;
	int addr, chunk_num, partition_limit;
	u8 *p, *chunk;

	/* whal_FwCtrl_LoadFwImageSm() */

	wl1271_debug(DEBUG_BOOT, "starting firmware upload");

	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
		     fw_data_len, CHUNK_SIZE);

	if ((fw_data_len % 4) != 0) {
		wl1271_error("firmware length not multiple of four");
		return -EIO;
	}

	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	if (!chunk) {
		wl1271_error("allocation for firmware upload chunk failed");
		return -ENOMEM;
	}

	memcpy(&partition, &wl->ptable[PART_DOWN], sizeof(partition));
	partition.mem.start = dest;
	wlcore_set_partition(wl, &partition);

	/* 10.1 set partition limit and chunk num */
	chunk_num = 0;
	partition_limit = wl->ptable[PART_DOWN].mem.size;

	while (chunk_num < fw_data_len / CHUNK_SIZE) {
		/* 10.2 update partition, if needed */
		addr = dest + (chunk_num + 2) * CHUNK_SIZE;
		if (addr > partition_limit) {
			addr = dest + chunk_num * CHUNK_SIZE;
			partition_limit = chunk_num * CHUNK_SIZE +
				wl->ptable[PART_DOWN].mem.size;
			partition.mem.start = addr;
			wlcore_set_partition(wl, &partition);
		}

		/* 10.3 upload the chunk */
		addr = dest + chunk_num * CHUNK_SIZE;
		p = buf + chunk_num * CHUNK_SIZE;
		memcpy(chunk, p, CHUNK_SIZE);
		wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
			     p, addr);
		wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);

		chunk_num++;
	}

	/* 10.4 upload the last chunk */
	addr = dest + chunk_num * CHUNK_SIZE;
	p = buf + chunk_num * CHUNK_SIZE;
	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
		     fw_data_len % CHUNK_SIZE, p, addr);
	wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);

	kfree(chunk);
	return 0;
}

int wlcore_boot_upload_firmware(struct wl1271 *wl)
{
	u32 chunks, addr, len;
	int ret = 0;
	u8 *fw;

	fw = wl->fw;
	chunks = be32_to_cpup((__be32 *) fw);
	fw += sizeof(u32);

	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);

	while (chunks--) {
		addr = be32_to_cpup((__be32 *) fw);
		fw += sizeof(u32);
		len = be32_to_cpup((__be32 *) fw);
		fw += sizeof(u32);

		if (len > 300000) {
			wl1271_info("firmware chunk too long: %u", len);
			return -EINVAL;
		}
		wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
			     chunks, addr, len);
		ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
		if (ret != 0)
			break;
		fw += len;
	}

	return ret;
}
EXPORT_SYMBOL_GPL(wlcore_boot_upload_firmware);

int wlcore_boot_upload_nvs(struct wl1271 *wl)
{
	size_t nvs_len, burst_len;
	int i;
	u32 dest_addr, val;
	u8 *nvs_ptr, *nvs_aligned;

	if (wl->nvs == NULL)
		return -ENODEV;

	if (wl->quirks & WLCORE_QUIRK_LEGACY_NVS) {
		struct wl1271_nvs_file *nvs =
			(struct wl1271_nvs_file *)wl->nvs;
		/*
		 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
		 * band configurations) can be removed when those NVS files stop
		 * floating around.
		 */
		if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
		    wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
			if (nvs->general_params.dual_mode_select)
				wl->enable_11a = true;
		}

		if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
		    (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
		     wl->enable_11a)) {
			wl1271_error("nvs size is not as expected: %zu != %zu",
				wl->nvs_len, sizeof(struct wl1271_nvs_file));
			kfree(wl->nvs);
			wl->nvs = NULL;
			wl->nvs_len = 0;
			return -EILSEQ;
		}

		/* only the first part of the NVS needs to be uploaded */
		nvs_len = sizeof(nvs->nvs);
		nvs_ptr = (u8 *) nvs->nvs;
	} else {
		struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;

		if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
			if (nvs->general_params.dual_mode_select)
				wl->enable_11a = true;
		} else {
			wl1271_error("nvs size is not as expected: %zu != %zu",
				     wl->nvs_len,
				     sizeof(struct wl128x_nvs_file));
			kfree(wl->nvs);
			wl->nvs = NULL;
			wl->nvs_len = 0;
			return -EILSEQ;
		}

		/* only the first part of the NVS needs to be uploaded */
		nvs_len = sizeof(nvs->nvs);
		nvs_ptr = (u8 *)nvs->nvs;
	}

	/* update current MAC address to NVS */
	nvs_ptr[11] = wl->addresses[0].addr[0];
	nvs_ptr[10] = wl->addresses[0].addr[1];
	nvs_ptr[6] = wl->addresses[0].addr[2];
	nvs_ptr[5] = wl->addresses[0].addr[3];
	nvs_ptr[4] = wl->addresses[0].addr[4];
	nvs_ptr[3] = wl->addresses[0].addr[5];

	/*
	 * Layout before the actual NVS tables:
	 * 1 byte : burst length.
	 * 2 bytes: destination address.
	 * n bytes: data to burst copy.
	 *
	 * This is ended by a 0 length, then the NVS tables.
	 */

	/* FIXME: Do we need to check here whether the LSB is 1? */
	while (nvs_ptr[0]) {
		burst_len = nvs_ptr[0];
		dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));

		/*
		 * Due to our new wl1271_translate_reg_addr function,
		 * we need to add the register partition start address
		 * to the destination
		 */
		dest_addr += wl->curr_part.reg.start;

		/* We move our pointer to the data */
		nvs_ptr += 3;

		for (i = 0; i < burst_len; i++) {
			if (nvs_ptr + 3 >= (u8 *) wl->nvs + nvs_len)
				goto out_badnvs;

			val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
			       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

			wl1271_debug(DEBUG_BOOT,
				     "nvs burst write 0x%x: 0x%x",
				     dest_addr, val);
			wl1271_write32(wl, dest_addr, val);

			nvs_ptr += 4;
			dest_addr += 4;
		}

		if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
			goto out_badnvs;
	}

	/*
	 * We've reached the first zero length, the first NVS table
	 * is located at an aligned offset which is at least 7 bytes further.
	 * NOTE: The wl->nvs->nvs element must be first, in order to
	 * simplify the casting, we assume it is at the beginning of
	 * the wl->nvs structure.
	 */
	nvs_ptr = (u8 *)wl->nvs +
			ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);

	if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
		goto out_badnvs;

	nvs_len -= nvs_ptr - (u8 *)wl->nvs;

	/* Now we must set the partition correctly */
	wlcore_set_partition(wl, &wl->ptable[PART_WORK]);

	/* Copy the NVS tables to a new block to ensure alignment */
	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
	if (!nvs_aligned)
		return -ENOMEM;

	/* And finally we upload the NVS tables */
	wlcore_write_data(wl, REG_CMD_MBOX_ADDRESS,
			  nvs_aligned, nvs_len, false);

	kfree(nvs_aligned);
	return 0;

out_badnvs:
	wl1271_error("nvs data is malformed");
	return -EILSEQ;
}
EXPORT_SYMBOL_GPL(wlcore_boot_upload_nvs);

int wlcore_boot_run_firmware(struct wl1271 *wl)
{
	int loop, ret;
	u32 chip_id, intr;

	/* Make sure we have the boot partition */
	wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);

	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);

	chip_id = wlcore_read_reg(wl, REG_CHIP_ID_B);

	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);

	if (chip_id != wl->chip.id) {
		wl1271_error("chip id doesn't match after firmware boot");
		return -EIO;
	}

	/* wait for init to complete */
	loop = 0;
	while (loop++ < INIT_LOOP) {
		udelay(INIT_LOOP_DELAY);
		intr = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR);

		if (intr == 0xffffffff) {
			wl1271_error("error reading hardware complete "
				     "init indication");
			return -EIO;
		}
		/* check that ACX_INTR_INIT_COMPLETE is enabled */
		else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
			wlcore_write_reg(wl, REG_INTERRUPT_ACK,
					 WL1271_ACX_INTR_INIT_COMPLETE);
			break;
		}
	}

	if (loop > INIT_LOOP) {
		wl1271_error("timeout waiting for the hardware to "
			     "complete initialization");
		return -EIO;
	}

	/* get hardware config command mail box */
	wl->cmd_box_addr = wlcore_read_reg(wl, REG_COMMAND_MAILBOX_PTR);

	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x", wl->cmd_box_addr);

	/* get hardware config event mail box */
	wl->mbox_ptr[0] = wlcore_read_reg(wl, REG_EVENT_MAILBOX_PTR);
	wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox);

	wl1271_debug(DEBUG_MAILBOX, "MBOX ptrs: 0x%x 0x%x",
		     wl->mbox_ptr[0], wl->mbox_ptr[1]);

	wl1271_boot_fw_version(wl);

	/*
	 * in case of full asynchronous mode the firmware event must be
	 * ready to receive event from the command mailbox
	 */

	/* unmask required mbox events  */
	wl->event_mask = BSS_LOSE_EVENT_ID |
		SCAN_COMPLETE_EVENT_ID |
		ROLE_STOP_COMPLETE_EVENT_ID |
		RSSI_SNR_TRIGGER_0_EVENT_ID |
		PSPOLL_DELIVERY_FAILURE_EVENT_ID |
		SOFT_GEMINI_SENSE_EVENT_ID |
		PERIODIC_SCAN_REPORT_EVENT_ID |
		PERIODIC_SCAN_COMPLETE_EVENT_ID |
		DUMMY_PACKET_EVENT_ID |
		PEER_REMOVE_COMPLETE_EVENT_ID |
		BA_SESSION_RX_CONSTRAINT_EVENT_ID |
		REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
		INACTIVE_STA_EVENT_ID |
		MAX_TX_RETRY_EVENT_ID |
		CHANNEL_SWITCH_COMPLETE_EVENT_ID;

	ret = wl1271_event_unmask(wl);
	if (ret < 0) {
		wl1271_error("EVENT mask setting failed");
		return ret;
	}

	/* set the working partition to its "running" mode offset */
	wlcore_set_partition(wl, &wl->ptable[PART_WORK]);

	/* firmware startup completed */
	return 0;
}
EXPORT_SYMBOL_GPL(wlcore_boot_run_firmware);
Commit	Line	Data
f5fc0f86 LC	1	/*
	2	* This file is part of wl1271
	3	*
2f826f55	4	* Copyright (C) 2008-2010 Nokia Corporation
f5fc0f86 LC	5	*
	6	* Contact: Luciano Coelho <luciano.coelho@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
5a0e3ad6	24	#include <linux/slab.h>
5ea417ae	25	#include <linux/wl12xx.h>
ee40fa06	26	#include <linux/export.h>
f5fc0f86	27
0f4e3122	28	#include "debug.h"
00d20100	29	#include "acx.h"
00d20100 SL	30	#include "boot.h"
	31	#include "io.h"
	32	#include "event.h"
ae113b57	33	#include "rx.h"
f5fc0f86	34
f5fc0f86 LC	35	static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
	36	{
	37	u32 cpu_ctrl;
	38
	39	/* 10.5.0 run the firmware (I) */
00782136	40	cpu_ctrl = wlcore_read_reg(wl, REG_ECPU_CONTROL);
f5fc0f86 LC	41
	42	/* 10.5.1 run the firmware (II) */
	43	cpu_ctrl \|= flag;
00782136	44	wlcore_write_reg(wl, REG_ECPU_CONTROL, cpu_ctrl);
f5fc0f86 LC	45	}
f5fc0f86 LC	46
842f1a6c IY	47	static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl)
	48	{
	49	unsigned int quirks = 0;
	50	unsigned int *fw_ver = wl->chip.fw_ver;
	51
95dac04f IY	52	/* Only new station firmwares support routing fw logs to the host */
	53	if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
	54	(fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
6f7dd16c	55	quirks \|= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
95dac04f IY	56
	57	/* This feature is not yet supported for AP mode */
	58	if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
6f7dd16c	59	quirks \|= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
95dac04f	60
842f1a6c IY	61	return quirks;
	62	}
	63
4b7fac77 LS	64	static void wl1271_parse_fw_ver(struct wl1271 *wl)
	65	{
	66	int ret;
	67
	68	ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
	69	&wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
	70	&wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
	71	&wl->chip.fw_ver[4]);
	72
	73	if (ret != 5) {
	74	wl1271_warning("fw version incorrect value");
	75	memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
	76	return;
	77	}
842f1a6c IY	78
	79	/* Check if any quirks are needed with older fw versions */
	80	wl->quirks \|= wl12xx_get_fw_ver_quirks(wl);
4b7fac77 LS	81	}
4b7fac77 LS	82
f5fc0f86 LC	83	static void wl1271_boot_fw_version(struct wl1271 *wl)
f5fc0f86 LC	84	{
690142e9	85	struct wl1271_static_data *static_data;
f5fc0f86	86
690142e9 MG	87	static_data = kmalloc(sizeof(*static_data), GFP_DMA);
	88	if (!static_data) {
	89	__WARN();
	90	return;
	91	}
	92
	93	wl1271_read(wl, wl->cmd_box_addr, static_data, sizeof(*static_data),
7b048c52	94	false);
f5fc0f86	95
690142e9	96	strncpy(wl->chip.fw_ver_str, static_data->fw_version,
4b7fac77	97	sizeof(wl->chip.fw_ver_str));
f5fc0f86	98
690142e9 MG	99	kfree(static_data);
690142e9 MG	100
f5fc0f86	101	/* make sure the string is NULL-terminated */
4b7fac77 LS	102	wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
	103
	104	wl1271_parse_fw_ver(wl);
f5fc0f86 LC	105	}
	106
	107	static int wl1271_boot_upload_firmware_chunk(struct wl1271 wl, void buf,
	108	size_t fw_data_len, u32 dest)
	109	{
25a43d78	110	struct wlcore_partition_set partition;
f5fc0f86	111	int addr, chunk_num, partition_limit;
1fba4974	112	u8 p, chunk;
f5fc0f86 LC	113
	114	/* whal_FwCtrl_LoadFwImageSm() */
	115
	116	wl1271_debug(DEBUG_BOOT, "starting firmware upload");
	117
73d0a13c LC	118	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
73d0a13c LC	119	fw_data_len, CHUNK_SIZE);
f5fc0f86	120
f5fc0f86 LC	121	if ((fw_data_len % 4) != 0) {
	122	wl1271_error("firmware length not multiple of four");
	123	return -EIO;
	124	}
	125
1fba4974	126	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
ed317788	127	if (!chunk) {
1fba4974 JO	128	wl1271_error("allocation for firmware upload chunk failed");
	129	return -ENOMEM;
	130	}
	131
25a43d78	132	memcpy(&partition, &wl->ptable[PART_DOWN], sizeof(partition));
451de97a	133	partition.mem.start = dest;
25a43d78	134	wlcore_set_partition(wl, &partition);
f5fc0f86 LC	135
	136	/* 10.1 set partition limit and chunk num */
	137	chunk_num = 0;
25a43d78	138	partition_limit = wl->ptable[PART_DOWN].mem.size;
f5fc0f86 LC	139
	140	while (chunk_num < fw_data_len / CHUNK_SIZE) {
	141	/* 10.2 update partition, if needed */
	142	addr = dest + (chunk_num + 2) * CHUNK_SIZE;
	143	if (addr > partition_limit) {
	144	addr = dest + chunk_num * CHUNK_SIZE;
	145	partition_limit = chunk_num * CHUNK_SIZE +
25a43d78	146	wl->ptable[PART_DOWN].mem.size;
451de97a	147	partition.mem.start = addr;
25a43d78	148	wlcore_set_partition(wl, &partition);
f5fc0f86 LC	149	}
	150
	151	/* 10.3 upload the chunk */
	152	addr = dest + chunk_num * CHUNK_SIZE;
	153	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	154	memcpy(chunk, p, CHUNK_SIZE);
f5fc0f86 LC	155	wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
f5fc0f86 LC	156	p, addr);
7b048c52	157	wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
f5fc0f86 LC	158
	159	chunk_num++;
	160	}
	161
	162	/* 10.4 upload the last chunk */
	163	addr = dest + chunk_num * CHUNK_SIZE;
	164	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	165	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
73d0a13c	166	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
f5fc0f86	167	fw_data_len % CHUNK_SIZE, p, addr);
7b048c52	168	wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
f5fc0f86	169
1fba4974	170	kfree(chunk);
f5fc0f86 LC	171	return 0;
	172	}
	173
dd5512eb	174	int wlcore_boot_upload_firmware(struct wl1271 *wl)
f5fc0f86 LC	175	{
f5fc0f86 LC	176	u32 chunks, addr, len;
ed317788	177	int ret = 0;
f5fc0f86 LC	178	u8 *fw;
	179
	180	fw = wl->fw;
d0f63b20	181	chunks = be32_to_cpup((__be32 *) fw);
f5fc0f86 LC	182	fw += sizeof(u32);
	183
	184	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
	185
	186	while (chunks--) {
d0f63b20	187	addr = be32_to_cpup((__be32 *) fw);
f5fc0f86	188	fw += sizeof(u32);
d0f63b20	189	len = be32_to_cpup((__be32 *) fw);
f5fc0f86 LC	190	fw += sizeof(u32);
	191
	192	if (len > 300000) {
	193	wl1271_info("firmware chunk too long: %u", len);
	194	return -EINVAL;
	195	}
	196	wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
	197	chunks, addr, len);
ed317788 JO	198	ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
	199	if (ret != 0)
	200	break;
f5fc0f86 LC	201	fw += len;
	202	}
	203
ed317788	204	return ret;
f5fc0f86	205	}
dd5512eb	206	EXPORT_SYMBOL_GPL(wlcore_boot_upload_firmware);
f5fc0f86	207
dd5512eb	208	int wlcore_boot_upload_nvs(struct wl1271 *wl)
f5fc0f86 LC	209	{
	210	size_t nvs_len, burst_len;
	211	int i;
	212	u32 dest_addr, val;
152ee6e0	213	u8 nvs_ptr, nvs_aligned;
f5fc0f86	214
152ee6e0	215	if (wl->nvs == NULL)
f5fc0f86 LC	216	return -ENODEV;
f5fc0f86 LC	217
d203e59c	218	if (wl->quirks & WLCORE_QUIRK_LEGACY_NVS) {
bc765bf3 SL	219	struct wl1271_nvs_file *nvs =
	220	(struct wl1271_nvs_file *)wl->nvs;
	221	/*
	222	* FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
	223	* band configurations) can be removed when those NVS files stop
	224	* floating around.
	225	*/
	226	if (wl->nvs_len == sizeof(struct wl1271_nvs_file) \|\|
	227	wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
cabb81c9	228	if (nvs->general_params.dual_mode_select)
bc765bf3 SL	229	wl->enable_11a = true;
bc765bf3 SL	230	}
02fabb0e	231
bc765bf3 SL	232	if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
	233	(wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE \|\|
	234	wl->enable_11a)) {
	235	wl1271_error("nvs size is not as expected: %zu != %zu",
	236	wl->nvs_len, sizeof(struct wl1271_nvs_file));
	237	kfree(wl->nvs);
	238	wl->nvs = NULL;
	239	wl->nvs_len = 0;
	240	return -EILSEQ;
	241	}
	242
	243	/* only the first part of the NVS needs to be uploaded */
	244	nvs_len = sizeof(nvs->nvs);
	245	nvs_ptr = (u8 *) nvs->nvs;
d203e59c LC	246	} else {
	247	struct wl128x_nvs_file nvs = (struct wl128x_nvs_file )wl->nvs;
	248
	249	if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
	250	if (nvs->general_params.dual_mode_select)
	251	wl->enable_11a = true;
	252	} else {
	253	wl1271_error("nvs size is not as expected: %zu != %zu",
	254	wl->nvs_len,
	255	sizeof(struct wl128x_nvs_file));
	256	kfree(wl->nvs);
	257	wl->nvs = NULL;
	258	wl->nvs_len = 0;
	259	return -EILSEQ;
	260	}
	261
	262	/* only the first part of the NVS needs to be uploaded */
	263	nvs_len = sizeof(nvs->nvs);
	264	nvs_ptr = (u8 *)nvs->nvs;
bc765bf3	265	}
f5fc0f86	266
1b72aecd	267	/* update current MAC address to NVS */
5e037e74 LC	268	nvs_ptr[11] = wl->addresses[0].addr[0];
	269	nvs_ptr[10] = wl->addresses[0].addr[1];
	270	nvs_ptr[6] = wl->addresses[0].addr[2];
	271	nvs_ptr[5] = wl->addresses[0].addr[3];
	272	nvs_ptr[4] = wl->addresses[0].addr[4];
	273	nvs_ptr[3] = wl->addresses[0].addr[5];
1b72aecd	274
f5fc0f86 LC	275	/*
	276	* Layout before the actual NVS tables:
	277	* 1 byte : burst length.
	278	* 2 bytes: destination address.
	279	* n bytes: data to burst copy.
	280	*
	281	* This is ended by a 0 length, then the NVS tables.
	282	*/
	283
	284	/* FIXME: Do we need to check here whether the LSB is 1? */
	285	while (nvs_ptr[0]) {
	286	burst_len = nvs_ptr[0];
	287	dest_addr = (nvs_ptr[1] & 0xfe) \| ((u32)(nvs_ptr[2] << 8));
	288
2f63b011 JO	289	/*
2f63b011 JO	290	* Due to our new wl1271_translate_reg_addr function,
00782136 LC	291	* we need to add the register partition start address
00782136 LC	292	* to the destination
2f63b011	293	*/
00782136	294	dest_addr += wl->curr_part.reg.start;
f5fc0f86 LC	295
	296	/* We move our pointer to the data */
	297	nvs_ptr += 3;
	298
	299	for (i = 0; i < burst_len; i++) {
f6efe96e PF	300	if (nvs_ptr + 3 >= (u8 *) wl->nvs + nvs_len)
	301	goto out_badnvs;
	302
f5fc0f86 LC	303	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
	304	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
	305
	306	wl1271_debug(DEBUG_BOOT,
	307	"nvs burst write 0x%x: 0x%x",
	308	dest_addr, val);
7b048c52	309	wl1271_write32(wl, dest_addr, val);
f5fc0f86 LC	310
	311	nvs_ptr += 4;
	312	dest_addr += 4;
	313	}
f6efe96e PF	314
	315	if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
	316	goto out_badnvs;
f5fc0f86 LC	317	}
	318
	319	/*
	320	* We've reached the first zero length, the first NVS table
67e0208a	321	* is located at an aligned offset which is at least 7 bytes further.
bc765bf3 SL	322	* NOTE: The wl->nvs->nvs element must be first, in order to
	323	* simplify the casting, we assume it is at the beginning of
	324	* the wl->nvs structure.
f5fc0f86	325	*/
bc765bf3 SL	326	nvs_ptr = (u8 *)wl->nvs +
bc765bf3 SL	327	ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
f6efe96e PF	328
	329	if (nvs_ptr >= (u8 *) wl->nvs + nvs_len)
	330	goto out_badnvs;
	331
bc765bf3	332	nvs_len -= nvs_ptr - (u8 *)wl->nvs;
f5fc0f86	333
f5fc0f86	334	/* Now we must set the partition correctly */
25a43d78	335	wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
f5fc0f86 LC	336
f5fc0f86 LC	337	/* Copy the NVS tables to a new block to ensure alignment */
67e0208a IY	338	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
	339	if (!nvs_aligned)
	340	return -ENOMEM;
f5fc0f86 LC	341
f5fc0f86 LC	342	/* And finally we upload the NVS tables */
00782136 LC	343	wlcore_write_data(wl, REG_CMD_MBOX_ADDRESS,
00782136 LC	344	nvs_aligned, nvs_len, false);
f5fc0f86 LC	345
	346	kfree(nvs_aligned);
	347	return 0;
f6efe96e PF	348
	349	out_badnvs:
	350	wl1271_error("nvs data is malformed");
	351	return -EILSEQ;
f5fc0f86	352	}
dd5512eb	353	EXPORT_SYMBOL_GPL(wlcore_boot_upload_nvs);
f5fc0f86	354
dd5512eb	355	int wlcore_boot_run_firmware(struct wl1271 *wl)
f5fc0f86 LC	356	{
f5fc0f86 LC	357	int loop, ret;
23a7a51c	358	u32 chip_id, intr;
f5fc0f86	359
dd5512eb LC	360	/* Make sure we have the boot partition */
	361	wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
	362
f5fc0f86 LC	363	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
f5fc0f86 LC	364
00782136	365	chip_id = wlcore_read_reg(wl, REG_CHIP_ID_B);
f5fc0f86 LC	366
	367	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
	368
	369	if (chip_id != wl->chip.id) {
	370	wl1271_error("chip id doesn't match after firmware boot");
	371	return -EIO;
	372	}
	373
	374	/* wait for init to complete */
	375	loop = 0;
	376	while (loop++ < INIT_LOOP) {
	377	udelay(INIT_LOOP_DELAY);
00782136	378	intr = wlcore_read_reg(wl, REG_INTERRUPT_NO_CLEAR);
f5fc0f86	379
23a7a51c	380	if (intr == 0xffffffff) {
f5fc0f86 LC	381	wl1271_error("error reading hardware complete "
	382	"init indication");
	383	return -EIO;
	384	}
	385	/* check that ACX_INTR_INIT_COMPLETE is enabled */
23a7a51c	386	else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
00782136 LC	387	wlcore_write_reg(wl, REG_INTERRUPT_ACK,
00782136 LC	388	WL1271_ACX_INTR_INIT_COMPLETE);
f5fc0f86 LC	389	break;
	390	}
	391	}
	392
e7d17cf4	393	if (loop > INIT_LOOP) {
f5fc0f86 LC	394	wl1271_error("timeout waiting for the hardware to "
	395	"complete initialization");
	396	return -EIO;
	397	}
	398
	399	/* get hardware config command mail box */
00782136	400	wl->cmd_box_addr = wlcore_read_reg(wl, REG_COMMAND_MAILBOX_PTR);
f5fc0f86	401
4263c5f2 LC	402	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x", wl->cmd_box_addr);
4263c5f2 LC	403
f5fc0f86	404	/* get hardware config event mail box */
4263c5f2 LC	405	wl->mbox_ptr[0] = wlcore_read_reg(wl, REG_EVENT_MAILBOX_PTR);
4263c5f2 LC	406	wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox);
f5fc0f86	407
4263c5f2 LC	408	wl1271_debug(DEBUG_MAILBOX, "MBOX ptrs: 0x%x 0x%x",
4263c5f2 LC	409	wl->mbox_ptr[0], wl->mbox_ptr[1]);
f5fc0f86	410
f5fc0f86 LC	411	wl1271_boot_fw_version(wl);
	412
	413	/*
	414	* in case of full asynchronous mode the firmware event must be
	415	* ready to receive event from the command mailbox
	416	*/
	417
be823e5b JO	418	/* unmask required mbox events */
be823e5b JO	419	wl->event_mask = BSS_LOSE_EVENT_ID \|
19ad0715	420	SCAN_COMPLETE_EVENT_ID \|
8332f0f6	421	ROLE_STOP_COMPLETE_EVENT_ID \|
90494a90	422	RSSI_SNR_TRIGGER_0_EVENT_ID \|
8d2ef7bd	423	PSPOLL_DELIVERY_FAILURE_EVENT_ID \|
6394c01b LC	424	SOFT_GEMINI_SENSE_EVENT_ID \|
6394c01b LC	425	PERIODIC_SCAN_REPORT_EVENT_ID \|
c690ec81 EP	426	PERIODIC_SCAN_COMPLETE_EVENT_ID \|
	427	DUMMY_PACKET_EVENT_ID \|
	428	PEER_REMOVE_COMPLETE_EVENT_ID \|
	429	BA_SESSION_RX_CONSTRAINT_EVENT_ID \|
	430	REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID \|
	431	INACTIVE_STA_EVENT_ID \|
6d158ff3 SL	432	MAX_TX_RETRY_EVENT_ID \|
6d158ff3 SL	433	CHANNEL_SWITCH_COMPLETE_EVENT_ID;
203c903c	434
f5fc0f86 LC	435	ret = wl1271_event_unmask(wl);
	436	if (ret < 0) {
	437	wl1271_error("EVENT mask setting failed");
	438	return ret;
	439	}
	440
4263c5f2 LC	441	/* set the working partition to its "running" mode offset */
4263c5f2 LC	442	wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
f5fc0f86 LC	443
	444	/* firmware startup completed */
	445	return 0;
	446	}
dd5512eb	447	EXPORT_SYMBOL_GPL(wlcore_boot_run_firmware);