Commit | Line | Data |
---|---|---|
f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * | |
6 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
5a0e3ad6 | 24 | #include <linux/gfp.h> |
95dac04f | 25 | #include <linux/sched.h> |
5a0e3ad6 | 26 | |
c31be25a | 27 | #include "wlcore.h" |
0f4e3122 | 28 | #include "debug.h" |
00d20100 | 29 | #include "acx.h" |
00d20100 | 30 | #include "rx.h" |
9eb599e9 | 31 | #include "tx.h" |
00d20100 | 32 | #include "io.h" |
cd70f6a4 | 33 | #include "hw_ops.h" |
f5fc0f86 | 34 | |
00782136 LC |
35 | /* |
36 | * TODO: this is here just for now, it must be removed when the data | |
37 | * operations are in place. | |
38 | */ | |
39 | #include "../wl12xx/reg.h" | |
40 | ||
5766435e AN |
41 | static u32 wlcore_rx_get_buf_size(struct wl1271 *wl, |
42 | u32 rx_pkt_desc) | |
f5fc0f86 | 43 | { |
5766435e AN |
44 | if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) |
45 | return (rx_pkt_desc & ALIGNED_RX_BUF_SIZE_MASK) >> | |
46 | ALIGNED_RX_BUF_SIZE_SHIFT; | |
47 | ||
48 | return (rx_pkt_desc & RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV; | |
49 | } | |
50 | ||
51 | static u32 wlcore_rx_get_align_buf_size(struct wl1271 *wl, u32 pkt_len) | |
52 | { | |
53 | if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) | |
54 | return ALIGN(pkt_len, WL12XX_BUS_BLOCK_SIZE); | |
55 | ||
56 | return pkt_len; | |
f5fc0f86 LC |
57 | } |
58 | ||
f5fc0f86 LC |
59 | static void wl1271_rx_status(struct wl1271 *wl, |
60 | struct wl1271_rx_descriptor *desc, | |
61 | struct ieee80211_rx_status *status, | |
62 | u8 beacon) | |
63 | { | |
64 | memset(status, 0, sizeof(struct ieee80211_rx_status)); | |
65 | ||
6a2de93b | 66 | if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == WL1271_RX_DESC_BAND_BG) |
0af0467f | 67 | status->band = IEEE80211_BAND_2GHZ; |
6a2de93b | 68 | else |
0af0467f | 69 | status->band = IEEE80211_BAND_5GHZ; |
6a2de93b | 70 | |
43a8bc5a | 71 | status->rate_idx = wlcore_rate_to_idx(wl, desc->rate, status->band); |
a4102645 | 72 | |
18357850 | 73 | /* 11n support */ |
43a8bc5a | 74 | if (desc->rate <= wl->hw_min_ht_rate) |
18357850 | 75 | status->flag |= RX_FLAG_HT; |
18357850 | 76 | |
5d7e73ba GM |
77 | /* |
78 | * Read the signal level and antenna diversity indication. | |
79 | * The msb in the signal level is always set as it is a | |
80 | * negative number. | |
81 | * The antenna indication is the msb of the rssi. | |
82 | */ | |
5d6af28a GM |
83 | status->signal = ((desc->rssi & RSSI_LEVEL_BITMASK) | BIT(7)); |
84 | status->antenna = ((desc->rssi & ANT_DIVERSITY_BITMASK) >> 7); | |
f5fc0f86 | 85 | |
ece550d0 JL |
86 | /* |
87 | * FIXME: In wl1251, the SNR should be divided by two. In wl1271 we | |
88 | * need to divide by two for now, but TI has been discussing about | |
89 | * changing it. This needs to be rechecked. | |
90 | */ | |
91 | wl->noise = desc->rssi - (desc->snr >> 1); | |
92 | ||
0af0467f JO |
93 | status->freq = ieee80211_channel_to_frequency(desc->channel, |
94 | status->band); | |
f5fc0f86 LC |
95 | |
96 | if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) { | |
34c8e3d2 | 97 | u8 desc_err_code = desc->status & WL1271_RX_DESC_STATUS_MASK; |
f5fc0f86 | 98 | |
34c8e3d2 AN |
99 | status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED | |
100 | RX_FLAG_DECRYPTED; | |
101 | ||
387116b8 | 102 | if (unlikely(desc_err_code & WL1271_RX_DESC_MIC_FAIL)) { |
5d07b668 | 103 | status->flag |= RX_FLAG_MMIC_ERROR; |
387116b8 AN |
104 | wl1271_warning("Michael MIC error. Desc: 0x%x", |
105 | desc_err_code); | |
34c8e3d2 | 106 | } |
f5fc0f86 | 107 | } |
6b70e7eb VG |
108 | |
109 | if (beacon) | |
110 | wlcore_set_pending_regdomain_ch(wl, (u16)desc->channel, | |
111 | status->band); | |
f5fc0f86 LC |
112 | } |
113 | ||
0a1d3abc | 114 | static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length, |
cd70f6a4 | 115 | enum wl_rx_buf_align rx_align, u8 *hlid) |
f5fc0f86 | 116 | { |
f5fc0f86 LC |
117 | struct wl1271_rx_descriptor *desc; |
118 | struct sk_buff *skb; | |
92fe9b5f | 119 | struct ieee80211_hdr *hdr; |
f5fc0f86 LC |
120 | u8 *buf; |
121 | u8 beacon = 0; | |
77ddaa10 | 122 | u8 is_data = 0; |
387116b8 | 123 | u8 reserved = 0, offset_to_data = 0; |
5c472148 | 124 | u16 seq_num; |
4158149c | 125 | u32 pkt_data_len; |
f5fc0f86 | 126 | |
93c5bb68 KV |
127 | /* |
128 | * In PLT mode we seem to get frames and mac80211 warns about them, | |
129 | * workaround this by not retrieving them at all. | |
130 | */ | |
3fcdab70 | 131 | if (unlikely(wl->plt)) |
1f37cbc9 | 132 | return -EINVAL; |
93c5bb68 | 133 | |
4158149c AN |
134 | pkt_data_len = wlcore_hw_get_rx_packet_len(wl, data, length); |
135 | if (!pkt_data_len) { | |
136 | wl1271_error("Invalid packet arrived from HW. length %d", | |
137 | length); | |
138 | return -EINVAL; | |
139 | } | |
140 | ||
cd70f6a4 | 141 | if (rx_align == WLCORE_RX_BUF_UNALIGNED) |
04414e2a | 142 | reserved = RX_BUF_ALIGN; |
387116b8 AN |
143 | else if (rx_align == WLCORE_RX_BUF_PADDED) |
144 | offset_to_data = RX_BUF_ALIGN; | |
cd70f6a4 | 145 | |
34c8e3d2 AN |
146 | /* the data read starts with the descriptor */ |
147 | desc = (struct wl1271_rx_descriptor *) data; | |
148 | ||
95dac04f IY |
149 | if (desc->packet_class == WL12XX_RX_CLASS_LOGGER) { |
150 | size_t len = length - sizeof(*desc); | |
151 | wl12xx_copy_fwlog(wl, data + sizeof(*desc), len); | |
95dac04f IY |
152 | return 0; |
153 | } | |
154 | ||
34c8e3d2 | 155 | /* discard corrupted packets */ |
387116b8 AN |
156 | if (desc->status & WL1271_RX_DESC_DECRYPT_FAIL) { |
157 | hdr = (void *)(data + sizeof(*desc) + offset_to_data); | |
158 | wl1271_warning("corrupted packet in RX: status: 0x%x len: %d", | |
159 | desc->status & WL1271_RX_DESC_STATUS_MASK, | |
160 | pkt_data_len); | |
161 | wl1271_dump((DEBUG_RX|DEBUG_CMD), "PKT: ", data + sizeof(*desc), | |
162 | min(pkt_data_len, | |
163 | ieee80211_hdrlen(hdr->frame_control))); | |
34c8e3d2 AN |
164 | return -EINVAL; |
165 | } | |
166 | ||
4158149c AN |
167 | /* skb length not including rx descriptor */ |
168 | skb = __dev_alloc_skb(pkt_data_len + reserved, GFP_KERNEL); | |
f5fc0f86 LC |
169 | if (!skb) { |
170 | wl1271_error("Couldn't allocate RX frame"); | |
1f37cbc9 | 171 | return -ENOMEM; |
f5fc0f86 LC |
172 | } |
173 | ||
0a1d3abc SL |
174 | /* reserve the unaligned payload(if any) */ |
175 | skb_reserve(skb, reserved); | |
176 | ||
4158149c | 177 | buf = skb_put(skb, pkt_data_len); |
f5fc0f86 | 178 | |
0a1d3abc SL |
179 | /* |
180 | * Copy packets from aggregation buffer to the skbs without rx | |
181 | * descriptor and with packet payload aligned care. In case of unaligned | |
182 | * packets copy the packets in offset of 2 bytes guarantee IP header | |
183 | * payload aligned to 4 bytes. | |
184 | */ | |
4158149c | 185 | memcpy(buf, data + sizeof(*desc), pkt_data_len); |
cd70f6a4 | 186 | if (rx_align == WLCORE_RX_BUF_PADDED) |
04414e2a | 187 | skb_pull(skb, RX_BUF_ALIGN); |
cd70f6a4 | 188 | |
9eb599e9 | 189 | *hlid = desc->hlid; |
f5fc0f86 | 190 | |
92fe9b5f EP |
191 | hdr = (struct ieee80211_hdr *)skb->data; |
192 | if (ieee80211_is_beacon(hdr->frame_control)) | |
f5fc0f86 | 193 | beacon = 1; |
77ddaa10 EP |
194 | if (ieee80211_is_data_present(hdr->frame_control)) |
195 | is_data = 1; | |
f5fc0f86 | 196 | |
58be4607 | 197 | wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon); |
169da04f | 198 | wlcore_hw_set_rx_csum(wl, desc, skb); |
f5fc0f86 | 199 | |
5c472148 | 200 | seq_num = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; |
9eb599e9 | 201 | wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s seq %d hlid %d", skb, |
a20a5b7e | 202 | skb->len - desc->pad_len, |
5c472148 | 203 | beacon ? "beacon" : "", |
9eb599e9 | 204 | seq_num, *hlid); |
f5fc0f86 | 205 | |
a620865e | 206 | skb_queue_tail(&wl->deferred_rx_queue, skb); |
92ef8960 | 207 | queue_work(wl->freezable_wq, &wl->netstack_work); |
1f37cbc9 | 208 | |
77ddaa10 | 209 | return is_data; |
f5fc0f86 LC |
210 | } |
211 | ||
75fb4df7 | 212 | int wlcore_rx(struct wl1271 *wl, struct wl_fw_status *status) |
f5fc0f86 | 213 | { |
da08fdfa | 214 | unsigned long active_hlids[BITS_TO_LONGS(WLCORE_MAX_LINKS)] = {0}; |
f5fc0f86 | 215 | u32 buf_size; |
0afd04e5 AN |
216 | u32 fw_rx_counter = status->fw_rx_counter % wl->num_rx_desc; |
217 | u32 drv_rx_counter = wl->rx_counter % wl->num_rx_desc; | |
1f37cbc9 | 218 | u32 rx_counter; |
5766435e AN |
219 | u32 pkt_len, align_pkt_len; |
220 | u32 pkt_offset, des; | |
9eb599e9 | 221 | u8 hlid; |
cd70f6a4 | 222 | enum wl_rx_buf_align rx_align; |
045b9b5f | 223 | int ret = 0; |
f5fc0f86 LC |
224 | |
225 | while (drv_rx_counter != fw_rx_counter) { | |
1f37cbc9 IY |
226 | buf_size = 0; |
227 | rx_counter = drv_rx_counter; | |
228 | while (rx_counter != fw_rx_counter) { | |
5766435e AN |
229 | des = le32_to_cpu(status->rx_pkt_descs[rx_counter]); |
230 | pkt_len = wlcore_rx_get_buf_size(wl, des); | |
231 | align_pkt_len = wlcore_rx_get_align_buf_size(wl, | |
232 | pkt_len); | |
26a309c7 | 233 | if (buf_size + align_pkt_len > wl->aggr_buf_size) |
1f37cbc9 | 234 | break; |
5766435e | 235 | buf_size += align_pkt_len; |
1f37cbc9 | 236 | rx_counter++; |
0afd04e5 | 237 | rx_counter %= wl->num_rx_desc; |
1f37cbc9 | 238 | } |
f5fc0f86 LC |
239 | |
240 | if (buf_size == 0) { | |
241 | wl1271_warning("received empty data"); | |
242 | break; | |
243 | } | |
244 | ||
1f37cbc9 | 245 | /* Read all available packets at once */ |
b14684a0 | 246 | des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]); |
eb96f841 IY |
247 | ret = wlcore_hw_prepare_read(wl, des, buf_size); |
248 | if (ret < 0) | |
249 | goto out; | |
045b9b5f IY |
250 | |
251 | ret = wlcore_read_data(wl, REG_SLV_MEM_DATA, wl->aggr_buf, | |
252 | buf_size, true); | |
253 | if (ret < 0) | |
254 | goto out; | |
1f37cbc9 IY |
255 | |
256 | /* Split data into separate packets */ | |
257 | pkt_offset = 0; | |
258 | while (pkt_offset < buf_size) { | |
5766435e AN |
259 | des = le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]); |
260 | pkt_len = wlcore_rx_get_buf_size(wl, des); | |
cd70f6a4 | 261 | rx_align = wlcore_hw_get_rx_buf_align(wl, des); |
0a1d3abc | 262 | |
fb2382c7 JO |
263 | /* |
264 | * the handle data call can only fail in memory-outage | |
265 | * conditions, in that case the received frame will just | |
266 | * be dropped. | |
267 | */ | |
77ddaa10 EP |
268 | if (wl1271_rx_handle_data(wl, |
269 | wl->aggr_buf + pkt_offset, | |
cd70f6a4 | 270 | pkt_len, rx_align, |
9eb599e9 | 271 | &hlid) == 1) { |
da08fdfa | 272 | if (hlid < wl->num_links) |
f414218e LC |
273 | __set_bit(hlid, active_hlids); |
274 | else | |
275 | WARN(1, | |
da08fdfa EP |
276 | "hlid (%d) exceeded MAX_LINKS\n", |
277 | hlid); | |
9eb599e9 | 278 | } |
77ddaa10 | 279 | |
1f37cbc9 IY |
280 | wl->rx_counter++; |
281 | drv_rx_counter++; | |
0afd04e5 | 282 | drv_rx_counter %= wl->num_rx_desc; |
5766435e | 283 | pkt_offset += wlcore_rx_get_align_buf_size(wl, pkt_len); |
1f37cbc9 | 284 | } |
f5fc0f86 | 285 | } |
606ea9fa IY |
286 | |
287 | /* | |
288 | * Write the driver's packet counter to the FW. This is only required | |
289 | * for older hardware revisions | |
290 | */ | |
b0f0ad39 IY |
291 | if (wl->quirks & WLCORE_QUIRK_END_OF_TRANSACTION) { |
292 | ret = wlcore_write32(wl, WL12XX_REG_RX_DRIVER_COUNTER, | |
293 | wl->rx_counter); | |
294 | if (ret < 0) | |
295 | goto out; | |
296 | } | |
77ddaa10 | 297 | |
9eb599e9 | 298 | wl12xx_rearm_rx_streaming(wl, active_hlids); |
045b9b5f IY |
299 | |
300 | out: | |
301 | return ret; | |
f5fc0f86 | 302 | } |
dbe0a8cd | 303 | |
4161923a | 304 | #ifdef CONFIG_PM |
dbe0a8cd ES |
305 | int wl1271_rx_filter_enable(struct wl1271 *wl, |
306 | int index, bool enable, | |
307 | struct wl12xx_rx_filter *filter) | |
308 | { | |
309 | int ret; | |
310 | ||
02d0727c | 311 | if (!!test_bit(index, wl->rx_filter_enabled) == enable) { |
dbe0a8cd ES |
312 | wl1271_warning("Request to enable an already " |
313 | "enabled rx filter %d", index); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | ret = wl1271_acx_set_rx_filter(wl, index, enable, filter); | |
318 | ||
319 | if (ret) { | |
320 | wl1271_error("Failed to %s rx data filter %d (err=%d)", | |
321 | enable ? "enable" : "disable", index, ret); | |
322 | return ret; | |
323 | } | |
324 | ||
02d0727c NZ |
325 | if (enable) |
326 | __set_bit(index, wl->rx_filter_enabled); | |
327 | else | |
328 | __clear_bit(index, wl->rx_filter_enabled); | |
dbe0a8cd ES |
329 | |
330 | return 0; | |
331 | } | |
332 | ||
c439a1ca | 333 | int wl1271_rx_filter_clear_all(struct wl1271 *wl) |
dbe0a8cd | 334 | { |
c439a1ca | 335 | int i, ret = 0; |
dbe0a8cd ES |
336 | |
337 | for (i = 0; i < WL1271_MAX_RX_FILTERS; i++) { | |
02d0727c | 338 | if (!test_bit(i, wl->rx_filter_enabled)) |
dbe0a8cd | 339 | continue; |
c439a1ca AN |
340 | ret = wl1271_rx_filter_enable(wl, i, 0, NULL); |
341 | if (ret) | |
342 | goto out; | |
dbe0a8cd | 343 | } |
c439a1ca AN |
344 | |
345 | out: | |
346 | return ret; | |
dbe0a8cd | 347 | } |
4161923a | 348 | #endif /* CONFIG_PM */ |