Commit | Line | Data |
---|---|---|
b2ba99ff LC |
1 | /* |
2 | * This file is part of wlcore | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __WLCORE_H__ | |
23 | #define __WLCORE_H__ | |
24 | ||
c31be25a LC |
25 | #include <linux/platform_device.h> |
26 | ||
8388569a | 27 | #include "wlcore_i.h" |
c31be25a | 28 | #include "event.h" |
7140df6e | 29 | #include "boot.h" |
c31be25a | 30 | |
72b0624f AN |
31 | /* The maximum number of Tx descriptors in all chip families */ |
32 | #define WLCORE_MAX_TX_DESCRIPTORS 32 | |
33 | ||
f4afbed9 AN |
34 | /* |
35 | * We always allocate this number of mac addresses. If we don't | |
36 | * have enough allocated addresses, the LAA bit is used | |
37 | */ | |
38 | #define WLCORE_NUM_MAC_ADDRESSES 3 | |
39 | ||
583f8164 VG |
40 | /* wl12xx/wl18xx maximum transmission power (in dBm) */ |
41 | #define WLCORE_MAX_TXPWR 25 | |
42 | ||
cd70f6a4 AN |
43 | /* forward declaration */ |
44 | struct wl1271_tx_hw_descr; | |
45 | enum wl_rx_buf_align; | |
169da04f | 46 | struct wl1271_rx_descriptor; |
4158149c | 47 | |
c31be25a | 48 | struct wlcore_ops { |
3992eb2b | 49 | int (*setup)(struct wl1271 *wl); |
6f7dd16c | 50 | int (*identify_chip)(struct wl1271 *wl); |
80cd6610 | 51 | int (*identify_fw)(struct wl1271 *wl); |
dd5512eb | 52 | int (*boot)(struct wl1271 *wl); |
c331b344 | 53 | int (*plt_init)(struct wl1271 *wl); |
eb96f841 IY |
54 | int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr, |
55 | void *buf, size_t len); | |
b0f0ad39 | 56 | int (*ack_event)(struct wl1271 *wl); |
c50a2825 EP |
57 | int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event, |
58 | bool *timeout); | |
59 | int (*process_mailbox_events)(struct wl1271 *wl); | |
b3b4b4b8 | 60 | u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks); |
4a3b97ee AN |
61 | void (*set_tx_desc_blocks)(struct wl1271 *wl, |
62 | struct wl1271_tx_hw_descr *desc, | |
63 | u32 blks, u32 spare_blks); | |
6f266e91 AN |
64 | void (*set_tx_desc_data_len)(struct wl1271 *wl, |
65 | struct wl1271_tx_hw_descr *desc, | |
66 | struct sk_buff *skb); | |
cd70f6a4 AN |
67 | enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl, |
68 | u32 rx_desc); | |
eb96f841 | 69 | int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len); |
4158149c AN |
70 | u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data, |
71 | u32 data_len); | |
045b9b5f | 72 | int (*tx_delayed_compl)(struct wl1271 *wl); |
53d67a50 | 73 | void (*tx_immediate_compl)(struct wl1271 *wl); |
9d68d1ee | 74 | int (*hw_init)(struct wl1271 *wl); |
8a9affc0 | 75 | int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
75fb4df7 EP |
76 | void (*convert_fw_status)(struct wl1271 *wl, void *raw_fw_status, |
77 | struct wl_fw_status *fw_status); | |
fa7930af AN |
78 | u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl, |
79 | struct wl12xx_vif *wlvif); | |
6134323f IY |
80 | int (*get_pg_ver)(struct wl1271 *wl, s8 *ver); |
81 | int (*get_mac)(struct wl1271 *wl); | |
2fc28de5 AN |
82 | void (*set_tx_desc_csum)(struct wl1271 *wl, |
83 | struct wl1271_tx_hw_descr *desc, | |
84 | struct sk_buff *skb); | |
169da04f AN |
85 | void (*set_rx_csum)(struct wl1271 *wl, |
86 | struct wl1271_rx_descriptor *desc, | |
87 | struct sk_buff *skb); | |
ebc7e57d AN |
88 | u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl, |
89 | struct wl12xx_vif *wlvif); | |
4987257c | 90 | int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir); |
7140df6e LC |
91 | int (*handle_static_data)(struct wl1271 *wl, |
92 | struct wl1271_static_data *static_data); | |
78e28062 EP |
93 | int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
94 | struct cfg80211_scan_request *req); | |
95 | int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); | |
78e28062 EP |
96 | int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
97 | struct cfg80211_sched_scan_request *req, | |
98 | struct ieee80211_sched_scan_ies *ies); | |
99 | void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); | |
32bb2c03 | 100 | int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem); |
a1c597f2 AN |
101 | int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd, |
102 | struct ieee80211_vif *vif, | |
103 | struct ieee80211_sta *sta, | |
104 | struct ieee80211_key_conf *key_conf); | |
fcab1890 EP |
105 | int (*channel_switch)(struct wl1271 *wl, |
106 | struct wl12xx_vif *wlvif, | |
107 | struct ieee80211_channel_switch *ch_switch); | |
9fccc82e | 108 | u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len); |
5f9b6777 AN |
109 | void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
110 | struct ieee80211_sta *sta, u32 changed); | |
530abe19 EP |
111 | int (*set_peer_cap)(struct wl1271 *wl, |
112 | struct ieee80211_sta_ht_cap *ht_cap, | |
113 | bool allow_ht_operation, | |
114 | u32 rate_set, u8 hlid); | |
c83cb803 | 115 | u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr); |
f1626fd8 AN |
116 | bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid, |
117 | struct wl1271_link *lnk); | |
118 | bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid, | |
119 | struct wl1271_link *lnk); | |
c31be25a LC |
120 | }; |
121 | ||
25a43d78 LC |
122 | enum wlcore_partitions { |
123 | PART_DOWN, | |
124 | PART_WORK, | |
125 | PART_BOOT, | |
126 | PART_DRPW, | |
127 | PART_TOP_PRCM_ELP_SOC, | |
128 | PART_PHY_INIT, | |
129 | ||
130 | PART_TABLE_LEN, | |
131 | }; | |
132 | ||
133 | struct wlcore_partition { | |
134 | u32 size; | |
135 | u32 start; | |
136 | }; | |
137 | ||
138 | struct wlcore_partition_set { | |
139 | struct wlcore_partition mem; | |
140 | struct wlcore_partition reg; | |
141 | struct wlcore_partition mem2; | |
142 | struct wlcore_partition mem3; | |
143 | }; | |
144 | ||
00782136 LC |
145 | enum wlcore_registers { |
146 | /* register addresses, used with partition translation */ | |
147 | REG_ECPU_CONTROL, | |
148 | REG_INTERRUPT_NO_CLEAR, | |
149 | REG_INTERRUPT_ACK, | |
150 | REG_COMMAND_MAILBOX_PTR, | |
151 | REG_EVENT_MAILBOX_PTR, | |
152 | REG_INTERRUPT_TRIG, | |
153 | REG_INTERRUPT_MASK, | |
154 | REG_PC_ON_RECOVERY, | |
155 | REG_CHIP_ID_B, | |
156 | REG_CMD_MBOX_ADDRESS, | |
157 | ||
158 | /* data access memory addresses, used with partition translation */ | |
159 | REG_SLV_MEM_DATA, | |
160 | REG_SLV_REG_DATA, | |
161 | ||
162 | /* raw data access memory addresses */ | |
163 | REG_RAW_FW_STATUS_ADDR, | |
164 | ||
165 | REG_TABLE_LEN, | |
166 | }; | |
167 | ||
4987257c LC |
168 | struct wl1271_stats { |
169 | void *fw_stats; | |
170 | unsigned long fw_stats_update; | |
171 | size_t fw_stats_len; | |
172 | ||
173 | unsigned int retry_count; | |
174 | unsigned int excessive_retries; | |
175 | }; | |
176 | ||
c31be25a | 177 | struct wl1271 { |
6f8d6b20 | 178 | bool initialized; |
c31be25a LC |
179 | struct ieee80211_hw *hw; |
180 | bool mac80211_registered; | |
181 | ||
182 | struct device *dev; | |
3992eb2b | 183 | struct platform_device *pdev; |
c31be25a LC |
184 | |
185 | void *if_priv; | |
186 | ||
187 | struct wl1271_if_operations *if_ops; | |
188 | ||
c31be25a | 189 | int irq; |
c31be25a LC |
190 | |
191 | spinlock_t wl_lock; | |
192 | ||
4cc53383 | 193 | enum wlcore_state state; |
c31be25a LC |
194 | enum wl12xx_fw_type fw_type; |
195 | bool plt; | |
7019c80e | 196 | enum plt_mode plt_mode; |
ff324317 | 197 | u8 fem_manuf; |
c31be25a LC |
198 | u8 last_vif_count; |
199 | struct mutex mutex; | |
200 | ||
201 | unsigned long flags; | |
202 | ||
25a43d78 | 203 | struct wlcore_partition_set curr_part; |
c31be25a LC |
204 | |
205 | struct wl1271_chip chip; | |
206 | ||
207 | int cmd_box_addr; | |
c31be25a LC |
208 | |
209 | u8 *fw; | |
210 | size_t fw_len; | |
211 | void *nvs; | |
212 | size_t nvs_len; | |
213 | ||
214 | s8 hw_pg_ver; | |
215 | ||
216 | /* address read from the fuse ROM */ | |
217 | u32 fuse_oui_addr; | |
218 | u32 fuse_nic_addr; | |
219 | ||
220 | /* we have up to 2 MAC addresses */ | |
f4afbed9 | 221 | struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES]; |
c31be25a LC |
222 | int channel; |
223 | u8 system_hlid; | |
224 | ||
da08fdfa | 225 | unsigned long links_map[BITS_TO_LONGS(WLCORE_MAX_LINKS)]; |
c31be25a LC |
226 | unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; |
227 | unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; | |
228 | unsigned long rate_policies_map[ | |
229 | BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)]; | |
001e39a8 EP |
230 | unsigned long klv_templates_map[ |
231 | BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)]; | |
c31be25a | 232 | |
da08fdfa | 233 | u8 session_ids[WLCORE_MAX_LINKS]; |
978cd3a0 | 234 | |
c31be25a LC |
235 | struct list_head wlvif_list; |
236 | ||
237 | u8 sta_count; | |
238 | u8 ap_count; | |
239 | ||
240 | struct wl1271_acx_mem_map *target_mem_map; | |
241 | ||
242 | /* Accounting for allocated / available TX blocks on HW */ | |
243 | u32 tx_blocks_freed; | |
244 | u32 tx_blocks_available; | |
245 | u32 tx_allocated_blocks; | |
246 | u32 tx_results_count; | |
247 | ||
c31be25a LC |
248 | /* Accounting for allocated / available Tx packets in HW */ |
249 | u32 tx_pkts_freed[NUM_TX_QUEUES]; | |
250 | u32 tx_allocated_pkts[NUM_TX_QUEUES]; | |
251 | ||
252 | /* Transmitted TX packets counter for chipset interface */ | |
253 | u32 tx_packets_count; | |
254 | ||
255 | /* Time-offset between host and chipset clocks */ | |
256 | s64 time_offset; | |
257 | ||
258 | /* Frames scheduled for transmission, not handled yet */ | |
259 | int tx_queue_count[NUM_TX_QUEUES]; | |
1c33db78 AN |
260 | unsigned long queue_stop_reasons[ |
261 | NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES]; | |
c31be25a LC |
262 | |
263 | /* Frames received, not handled yet by mac80211 */ | |
264 | struct sk_buff_head deferred_rx_queue; | |
265 | ||
266 | /* Frames sent, not returned yet to mac80211 */ | |
267 | struct sk_buff_head deferred_tx_queue; | |
268 | ||
269 | struct work_struct tx_work; | |
270 | struct workqueue_struct *freezable_wq; | |
271 | ||
272 | /* Pending TX frames */ | |
72b0624f AN |
273 | unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)]; |
274 | struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS]; | |
c31be25a LC |
275 | int tx_frames_cnt; |
276 | ||
277 | /* FW Rx counter */ | |
278 | u32 rx_counter; | |
279 | ||
c31be25a LC |
280 | /* Intermediate buffer, used for packet aggregation */ |
281 | u8 *aggr_buf; | |
26a309c7 | 282 | u32 aggr_buf_size; |
c31be25a LC |
283 | |
284 | /* Reusable dummy packet template */ | |
285 | struct sk_buff *dummy_packet; | |
286 | ||
287 | /* Network stack work */ | |
288 | struct work_struct netstack_work; | |
289 | ||
290 | /* FW log buffer */ | |
291 | u8 *fwlog; | |
292 | ||
293 | /* Number of valid bytes in the FW log buffer */ | |
294 | ssize_t fwlog_size; | |
295 | ||
c83cb803 IC |
296 | /* FW log end marker */ |
297 | u32 fwlog_end; | |
298 | ||
299 | /* FW memory block size */ | |
300 | u32 fw_mem_block_size; | |
301 | ||
c31be25a LC |
302 | /* Sysfs FW log entry readers wait queue */ |
303 | wait_queue_head_t fwlog_waitq; | |
304 | ||
305 | /* Hardware recovery work */ | |
306 | struct work_struct recovery_work; | |
afbe3718 | 307 | bool watchdog_recovery; |
c31be25a | 308 | |
6b70e7eb VG |
309 | /* Reg domain last configuration */ |
310 | u32 reg_ch_conf_last[2]; | |
311 | /* Reg domain pending configuration */ | |
312 | u32 reg_ch_conf_pending[2]; | |
313 | ||
c31be25a | 314 | /* Pointer that holds DMA-friendly block for the mailbox */ |
c50a2825 | 315 | void *mbox; |
c31be25a LC |
316 | |
317 | /* The mbox event mask */ | |
318 | u32 event_mask; | |
71e996be EP |
319 | /* events to unmask only when ap interface is up */ |
320 | u32 ap_event_mask; | |
c31be25a LC |
321 | |
322 | /* Mailbox pointers */ | |
c50a2825 | 323 | u32 mbox_size; |
c31be25a LC |
324 | u32 mbox_ptr[2]; |
325 | ||
326 | /* Are we currently scanning */ | |
c50a2825 | 327 | struct wl12xx_vif *scan_wlvif; |
c31be25a LC |
328 | struct wl1271_scan scan; |
329 | struct delayed_work scan_complete_work; | |
330 | ||
dabf37db EP |
331 | struct ieee80211_vif *roc_vif; |
332 | struct delayed_work roc_complete_work; | |
5f561f68 | 333 | |
10199756 | 334 | struct wl12xx_vif *sched_vif; |
c31be25a LC |
335 | |
336 | /* The current band */ | |
337 | enum ieee80211_band band; | |
338 | ||
339 | struct completion *elp_compl; | |
340 | struct delayed_work elp_work; | |
341 | ||
342 | /* in dBm */ | |
343 | int power_level; | |
344 | ||
345 | struct wl1271_stats stats; | |
346 | ||
2e07d028 | 347 | __le32 *buffer_32; |
c31be25a LC |
348 | u32 buffer_cmd; |
349 | u32 buffer_busyword[WL1271_BUSY_WORD_CNT]; | |
350 | ||
75fb4df7 EP |
351 | void *raw_fw_status; |
352 | struct wl_fw_status *fw_status; | |
c31be25a LC |
353 | struct wl1271_tx_hw_res_if *tx_res_if; |
354 | ||
355 | /* Current chipset configuration */ | |
e87288f0 | 356 | struct wlcore_conf conf; |
c31be25a LC |
357 | |
358 | bool sg_enabled; | |
359 | ||
360 | bool enable_11a; | |
361 | ||
c108c905 LC |
362 | int recovery_count; |
363 | ||
c31be25a LC |
364 | /* Most recently reported noise in dBm */ |
365 | s8 noise; | |
366 | ||
367 | /* bands supported by this instance of wl12xx */ | |
091185d6 | 368 | struct ieee80211_supported_band bands[WLCORE_NUM_BANDS]; |
c31be25a | 369 | |
c31be25a LC |
370 | /* |
371 | * wowlan trigger was configured during suspend. | |
372 | * (currently, only "ANY" trigger is supported) | |
373 | */ | |
374 | bool wow_enabled; | |
375 | bool irq_wake_enabled; | |
376 | ||
377 | /* | |
378 | * AP-mode - links indexed by HLID. The global and broadcast links | |
379 | * are always active. | |
380 | */ | |
da08fdfa | 381 | struct wl1271_link links[WLCORE_MAX_LINKS]; |
c31be25a | 382 | |
9a100968 AN |
383 | /* number of currently active links */ |
384 | int active_link_count; | |
385 | ||
0e810479 AN |
386 | /* Fast/slow links bitmap according to FW */ |
387 | u32 fw_fast_lnk_map; | |
388 | ||
c31be25a LC |
389 | /* AP-mode - a bitmap of links currently in PS mode according to FW */ |
390 | u32 ap_fw_ps_map; | |
391 | ||
392 | /* AP-mode - a bitmap of links currently in PS mode in mac80211 */ | |
393 | unsigned long ap_ps_map; | |
394 | ||
395 | /* Quirks of specific hardware revisions */ | |
396 | unsigned int quirks; | |
397 | ||
398 | /* Platform limitations */ | |
399 | unsigned int platform_quirks; | |
400 | ||
401 | /* number of currently active RX BA sessions */ | |
402 | int ba_rx_session_count; | |
403 | ||
d21553f8 IC |
404 | /* Maximum number of supported RX BA sessions */ |
405 | int ba_rx_session_count_max; | |
406 | ||
c31be25a LC |
407 | /* AP-mode - number of currently connected stations */ |
408 | int active_sta_count; | |
409 | ||
bc566f92 AN |
410 | /* Flag determining whether AP should broadcast OFDM-only rates */ |
411 | bool ofdm_only_ap; | |
412 | ||
c31be25a LC |
413 | /* last wlvif we transmitted from */ |
414 | struct wl12xx_vif *last_wlvif; | |
415 | ||
416 | /* work to fire when Tx is stuck */ | |
417 | struct delayed_work tx_watchdog_work; | |
418 | ||
419 | struct wlcore_ops *ops; | |
25a43d78 LC |
420 | /* pointer to the lower driver partition table */ |
421 | const struct wlcore_partition_set *ptable; | |
00782136 LC |
422 | /* pointer to the lower driver register table */ |
423 | const int *rtable; | |
6f7dd16c LC |
424 | /* name of the firmwares to load - for PLT, single role, multi-role */ |
425 | const char *plt_fw_name; | |
426 | const char *sr_fw_name; | |
427 | const char *mr_fw_name; | |
96e0c683 | 428 | |
78e28062 EP |
429 | u8 scan_templ_id_2_4; |
430 | u8 scan_templ_id_5; | |
431 | u8 sched_scan_templ_id_2_4; | |
432 | u8 sched_scan_templ_id_5; | |
0a1c720c | 433 | u8 max_channels_5; |
78e28062 | 434 | |
96e0c683 AN |
435 | /* per-chip-family private structure */ |
436 | void *priv; | |
72b0624f AN |
437 | |
438 | /* number of TX descriptors the HW supports. */ | |
439 | u32 num_tx_desc; | |
0afd04e5 AN |
440 | /* number of RX descriptors the HW supports. */ |
441 | u32 num_rx_desc; | |
da08fdfa EP |
442 | /* number of links the HW supports */ |
443 | u8 num_links; | |
32f0fd5b EP |
444 | /* max stations a single AP can support */ |
445 | u8 max_ap_stations; | |
3edab305 | 446 | |
43a8bc5a AN |
447 | /* translate HW Tx rates to standard rate-indices */ |
448 | const u8 **band_rate_to_idx; | |
449 | ||
450 | /* size of table for HW rates that can be received from chip */ | |
451 | u8 hw_tx_rate_tbl_size; | |
452 | ||
453 | /* this HW rate and below are considered HT rates for this chip */ | |
454 | u8 hw_min_ht_rate; | |
4a589a6f AN |
455 | |
456 | /* HW HT (11n) capabilities */ | |
091185d6 | 457 | struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS]; |
6bac40a6 AN |
458 | |
459 | /* size of the private FW status data */ | |
75fb4df7 | 460 | size_t fw_status_len; |
6bac40a6 | 461 | size_t fw_status_priv_len; |
dbe0a8cd ES |
462 | |
463 | /* RX Data filter rule state - enabled/disabled */ | |
02d0727c | 464 | unsigned long rx_filter_enabled[BITS_TO_LONGS(WL1271_MAX_RX_FILTERS)]; |
83d08d3f | 465 | |
7140df6e LC |
466 | /* size of the private static data */ |
467 | size_t static_data_priv_len; | |
468 | ||
83d08d3f AN |
469 | /* the current channel type */ |
470 | enum nl80211_channel_type channel_type; | |
2c38849f AN |
471 | |
472 | /* mutex for protecting the tx_flush function */ | |
473 | struct mutex flush_mutex; | |
26b5858a LC |
474 | |
475 | /* sleep auth value currently configured to FW */ | |
476 | int sleep_auth; | |
4a1ccce8 | 477 | |
f4afbed9 AN |
478 | /* the number of allocated MAC addresses in this chip */ |
479 | int num_mac_addr; | |
480 | ||
8675f9ab LC |
481 | /* minimum FW version required for the driver to work in single-role */ |
482 | unsigned int min_sr_fw_ver[NUM_FW_VER]; | |
483 | ||
484 | /* minimum FW version required for the driver to work in multi-role */ | |
485 | unsigned int min_mr_fw_ver[NUM_FW_VER]; | |
6f8d6b20 IY |
486 | |
487 | struct completion nvs_loading_complete; | |
de40750f | 488 | |
abf0b249 EP |
489 | /* interface combinations supported by the hw */ |
490 | const struct ieee80211_iface_combination *iface_combinations; | |
491 | u8 n_iface_combinations; | |
c31be25a | 492 | }; |
ffeb501c | 493 | |
b74324d1 BP |
494 | int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev); |
495 | int wlcore_remove(struct platform_device *pdev); | |
c50a2825 EP |
496 | struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size, |
497 | u32 mbox_size); | |
ffeb501c | 498 | int wlcore_free_hw(struct wl1271 *wl); |
a1c597f2 AN |
499 | int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd, |
500 | struct ieee80211_vif *vif, | |
501 | struct ieee80211_sta *sta, | |
502 | struct ieee80211_key_conf *key_conf); | |
6b70e7eb | 503 | void wlcore_regdomain_config(struct wl1271 *wl); |
187e52cc AN |
504 | void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
505 | struct wl1271_station *wl_sta, bool in_conn); | |
ffeb501c | 506 | |
fa2adfcd AN |
507 | static inline void |
508 | wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band, | |
509 | struct ieee80211_sta_ht_cap *ht_cap) | |
510 | { | |
511 | memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap)); | |
512 | } | |
513 | ||
af4e94c5 LC |
514 | /* Tell wlcore not to care about this element when checking the version */ |
515 | #define WLCORE_FW_VER_IGNORE -1 | |
516 | ||
4a1ccce8 AN |
517 | static inline void |
518 | wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip, | |
8675f9ab LC |
519 | unsigned int iftype_sr, unsigned int major_sr, |
520 | unsigned int subtype_sr, unsigned int minor_sr, | |
521 | unsigned int iftype_mr, unsigned int major_mr, | |
522 | unsigned int subtype_mr, unsigned int minor_mr) | |
4a1ccce8 | 523 | { |
8675f9ab LC |
524 | wl->min_sr_fw_ver[FW_VER_CHIP] = chip; |
525 | wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr; | |
526 | wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr; | |
527 | wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr; | |
528 | wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr; | |
529 | ||
530 | wl->min_mr_fw_ver[FW_VER_CHIP] = chip; | |
531 | wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr; | |
532 | wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr; | |
533 | wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr; | |
534 | wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr; | |
4a1ccce8 AN |
535 | } |
536 | ||
00782136 LC |
537 | /* Firmware image load chunk size */ |
538 | #define CHUNK_SIZE 16384 | |
539 | ||
6f7dd16c LC |
540 | /* Quirks */ |
541 | ||
542 | /* Each RX/TX transaction requires an end-of-transaction transfer */ | |
543 | #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0) | |
544 | ||
18eab430 EP |
545 | /* the first start_role(sta) sometimes doesn't work on wl12xx */ |
546 | #define WLCORE_QUIRK_START_STA_FAILS BIT(1) | |
547 | ||
6f7dd16c | 548 | /* wl127x and SPI don't support SDIO block size alignment */ |
f83985bb | 549 | #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2) |
6f7dd16c | 550 | |
5766435e AN |
551 | /* means aggregated Rx packets are aligned to a SDIO block */ |
552 | #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3) | |
553 | ||
6f7dd16c LC |
554 | /* Older firmwares did not implement the FW logger over bus feature */ |
555 | #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4) | |
556 | ||
d203e59c LC |
557 | /* Older firmwares use an old NVS format */ |
558 | #define WLCORE_QUIRK_LEGACY_NVS BIT(5) | |
559 | ||
9fccc82e IR |
560 | /* pad only the last frame in the aggregate buffer */ |
561 | #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7) | |
562 | ||
2c0133a4 AN |
563 | /* extra header space is required for TKIP */ |
564 | #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8) | |
565 | ||
01b3c0e4 VG |
566 | /* Some firmwares not support sched scans while connected */ |
567 | #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9) | |
568 | ||
3df74f46 YD |
569 | /* separate probe response templates for one-shot and sched scans */ |
570 | #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10) | |
571 | ||
6b70e7eb VG |
572 | /* Firmware requires reg domain configuration for active calibration */ |
573 | #define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11) | |
574 | ||
3ea186d1 AN |
575 | /* The FW only support a zero session id for AP */ |
576 | #define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12) | |
00782136 LC |
577 | |
578 | /* TODO: move all these common registers and values elsewhere */ | |
579 | #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC | |
580 | ||
581 | /* ELP register commands */ | |
582 | #define ELPCTRL_WAKE_UP 0x1 | |
583 | #define ELPCTRL_WAKE_UP_WLAN_READY 0x5 | |
584 | #define ELPCTRL_SLEEP 0x0 | |
585 | /* ELP WLAN_READY bit */ | |
586 | #define ELPCTRL_WLAN_READY 0x2 | |
587 | ||
588 | /************************************************************************* | |
589 | ||
590 | Interrupt Trigger Register (Host -> WiLink) | |
591 | ||
592 | **************************************************************************/ | |
593 | ||
594 | /* Hardware to Embedded CPU Interrupts - first 32-bit register set */ | |
595 | ||
00782136 LC |
596 | /* |
597 | * The host sets this bit to inform the Wlan | |
598 | * FW that a TX packet is in the XFER | |
599 | * Buffer #0. | |
600 | */ | |
601 | #define INTR_TRIG_TX_PROC0 BIT(2) | |
602 | ||
603 | /* | |
604 | * The host sets this bit to inform the FW | |
605 | * that it read a packet from RX XFER | |
606 | * Buffer #0. | |
607 | */ | |
608 | #define INTR_TRIG_RX_PROC0 BIT(3) | |
609 | ||
610 | #define INTR_TRIG_DEBUG_ACK BIT(4) | |
611 | ||
612 | #define INTR_TRIG_STATE_CHANGED BIT(5) | |
613 | ||
614 | /* Hardware to Embedded CPU Interrupts - second 32-bit register set */ | |
615 | ||
616 | /* | |
617 | * The host sets this bit to inform the FW | |
618 | * that it read a packet from RX XFER | |
619 | * Buffer #1. | |
620 | */ | |
621 | #define INTR_TRIG_RX_PROC1 BIT(17) | |
622 | ||
623 | /* | |
624 | * The host sets this bit to inform the Wlan | |
625 | * hardware that a TX packet is in the XFER | |
626 | * Buffer #1. | |
627 | */ | |
628 | #define INTR_TRIG_TX_PROC1 BIT(18) | |
629 | ||
630 | #define ACX_SLV_SOFT_RESET_BIT BIT(1) | |
631 | #define SOFT_RESET_MAX_TIME 1000000 | |
632 | #define SOFT_RESET_STALL_TIME 1000 | |
633 | ||
634 | #define ECPU_CONTROL_HALT 0x00000101 | |
b2ba99ff | 635 | |
6f7dd16c LC |
636 | #define WELP_ARM_COMMAND_VAL 0x4 |
637 | ||
b2ba99ff | 638 | #endif /* __WLCORE_H__ */ |