[deliverable/linux.git] / drivers / net / wireless / ti / wlcore / wlcore.h

/*
 * This file is part of wlcore
 *
 * Copyright (C) 2011 Texas Instruments Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __WLCORE_H__
#define __WLCORE_H__

#include <linux/platform_device.h>

#include "wl12xx.h"
#include "event.h"

struct wlcore_ops {
	int (*identify_chip)(struct wl1271 *wl);
	int (*boot)(struct wl1271 *wl);
	void (*trigger_cmd)(struct wl1271 *wl);
	void (*ack_event)(struct wl1271 *wl);
	s8 (*get_pg_ver)(struct wl1271 *wl);
	void (*get_mac)(struct wl1271 *wl);
};

enum wlcore_partitions {
	PART_DOWN,
	PART_WORK,
	PART_BOOT,
	PART_DRPW,
	PART_TOP_PRCM_ELP_SOC,
	PART_PHY_INIT,

	PART_TABLE_LEN,
};

struct wlcore_partition {
	u32 size;
	u32 start;
};

struct wlcore_partition_set {
	struct wlcore_partition mem;
	struct wlcore_partition reg;
	struct wlcore_partition mem2;
	struct wlcore_partition mem3;
};

enum wlcore_registers {
	/* register addresses, used with partition translation */
	REG_ECPU_CONTROL,
	REG_INTERRUPT_NO_CLEAR,
	REG_INTERRUPT_ACK,
	REG_COMMAND_MAILBOX_PTR,
	REG_EVENT_MAILBOX_PTR,
	REG_INTERRUPT_TRIG,
	REG_INTERRUPT_MASK,
	REG_PC_ON_RECOVERY,
	REG_CHIP_ID_B,
	REG_CMD_MBOX_ADDRESS,

	/* data access memory addresses, used with partition translation */
	REG_SLV_MEM_DATA,
	REG_SLV_REG_DATA,

	/* raw data access memory addresses */
	REG_RAW_FW_STATUS_ADDR,

	REG_TABLE_LEN,
};

struct wl1271 {
	struct ieee80211_hw *hw;
	bool mac80211_registered;

	struct device *dev;

	void *if_priv;

	struct wl1271_if_operations *if_ops;

	void (*set_power)(bool enable);
	int irq;
	int ref_clock;

	spinlock_t wl_lock;

	enum wl1271_state state;
	enum wl12xx_fw_type fw_type;
	bool plt;
	u8 last_vif_count;
	struct mutex mutex;

	unsigned long flags;

	struct wlcore_partition_set curr_part;

	struct wl1271_chip chip;

	int cmd_box_addr;

	u8 *fw;
	size_t fw_len;
	void *nvs;
	size_t nvs_len;

	s8 hw_pg_ver;

	/* address read from the fuse ROM */
	u32 fuse_oui_addr;
	u32 fuse_nic_addr;

	/* we have up to 2 MAC addresses */
	struct mac_address addresses[2];
	int channel;
	u8 system_hlid;

	unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
	unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	unsigned long rate_policies_map[
			BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];

	struct list_head wlvif_list;

	u8 sta_count;
	u8 ap_count;

	struct wl1271_acx_mem_map *target_mem_map;

	/* Accounting for allocated / available TX blocks on HW */
	u32 tx_blocks_freed;
	u32 tx_blocks_available;
	u32 tx_allocated_blocks;
	u32 tx_results_count;

	/* amount of spare TX blocks to use */
	u32 tx_spare_blocks;

	/* Accounting for allocated / available Tx packets in HW */
	u32 tx_pkts_freed[NUM_TX_QUEUES];
	u32 tx_allocated_pkts[NUM_TX_QUEUES];

	/* Transmitted TX packets counter for chipset interface */
	u32 tx_packets_count;

	/* Time-offset between host and chipset clocks */
	s64 time_offset;

	/* Frames scheduled for transmission, not handled yet */
	int tx_queue_count[NUM_TX_QUEUES];
	long stopped_queues_map;

	/* Frames received, not handled yet by mac80211 */
	struct sk_buff_head deferred_rx_queue;

	/* Frames sent, not returned yet to mac80211 */
	struct sk_buff_head deferred_tx_queue;

	struct work_struct tx_work;
	struct workqueue_struct *freezable_wq;

	/* Pending TX frames */
	unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)];
	struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
	int tx_frames_cnt;

	/* FW Rx counter */
	u32 rx_counter;

	/* Rx memory pool address */
	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;

	/* Intermediate buffer, used for packet aggregation */
	u8 *aggr_buf;

	/* Reusable dummy packet template */
	struct sk_buff *dummy_packet;

	/* Network stack work  */
	struct work_struct netstack_work;

	/* FW log buffer */
	u8 *fwlog;

	/* Number of valid bytes in the FW log buffer */
	ssize_t fwlog_size;

	/* Sysfs FW log entry readers wait queue */
	wait_queue_head_t fwlog_waitq;

	/* Hardware recovery work */
	struct work_struct recovery_work;

	/* Pointer that holds DMA-friendly block for the mailbox */
	struct event_mailbox *mbox;

	/* The mbox event mask */
	u32 event_mask;

	/* Mailbox pointers */
	u32 mbox_ptr[2];

	/* Are we currently scanning */
	struct ieee80211_vif *scan_vif;
	struct wl1271_scan scan;
	struct delayed_work scan_complete_work;

	bool sched_scanning;

	/* The current band */
	enum ieee80211_band band;

	struct completion *elp_compl;
	struct delayed_work elp_work;

	/* in dBm */
	int power_level;

	struct wl1271_stats stats;

	__le32 buffer_32;
	u32 buffer_cmd;
	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];

	struct wl12xx_fw_status *fw_status;
	struct wl1271_tx_hw_res_if *tx_res_if;

	/* Current chipset configuration */
	struct conf_drv_settings conf;

	bool sg_enabled;

	bool enable_11a;

	/* Most recently reported noise in dBm */
	s8 noise;

	/* bands supported by this instance of wl12xx */
	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];

	int tcxo_clock;

	/*
	 * wowlan trigger was configured during suspend.
	 * (currently, only "ANY" trigger is supported)
	 */
	bool wow_enabled;
	bool irq_wake_enabled;

	/*
	 * AP-mode - links indexed by HLID. The global and broadcast links
	 * are always active.
	 */
	struct wl1271_link links[WL12XX_MAX_LINKS];

	/* AP-mode - a bitmap of links currently in PS mode according to FW */
	u32 ap_fw_ps_map;

	/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
	unsigned long ap_ps_map;

	/* Quirks of specific hardware revisions */
	unsigned int quirks;

	/* Platform limitations */
	unsigned int platform_quirks;

	/* number of currently active RX BA sessions */
	int ba_rx_session_count;

	/* AP-mode - number of currently connected stations */
	int active_sta_count;

	/* last wlvif we transmitted from */
	struct wl12xx_vif *last_wlvif;

	/* work to fire when Tx is stuck */
	struct delayed_work tx_watchdog_work;

	struct wlcore_ops *ops;
	/* pointer to the lower driver partition table */
	const struct wlcore_partition_set *ptable;
	/* pointer to the lower driver register table */
	const int *rtable;
	/* name of the firmwares to load - for PLT, single role, multi-role */
	const char *plt_fw_name;
	const char *sr_fw_name;
	const char *mr_fw_name;
};

int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
int __devexit wlcore_remove(struct platform_device *pdev);
struct ieee80211_hw *wlcore_alloc_hw(void);
int wlcore_free_hw(struct wl1271 *wl);

/* Firmware image load chunk size */
#define CHUNK_SIZE	16384

/* Quirks */

/* Each RX/TX transaction requires an end-of-transaction transfer */
#define WLCORE_QUIRK_END_OF_TRANSACTION		BIT(0)

/* wl127x and SPI don't support SDIO block size alignment */
#define WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT	BIT(2)

/* Older firmwares did not implement the FW logger over bus feature */
#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED	BIT(4)

/* Older firmwares use an old NVS format */
#define WLCORE_QUIRK_LEGACY_NVS			BIT(5)

/* Some firmwares may not support ELP */
#define WLCORE_QUIRK_NO_ELP			BIT(6)

/* TODO: move to the lower drivers when all usages are abstracted */
#define CHIP_ID_1271_PG10              (0x4030101)
#define CHIP_ID_1271_PG20              (0x4030111)
#define CHIP_ID_1283_PG10              (0x05030101)
#define CHIP_ID_1283_PG20              (0x05030111)

/* TODO: move all these common registers and values elsewhere */
#define HW_ACCESS_ELP_CTRL_REG		0x1FFFC

/* ELP register commands */
#define ELPCTRL_WAKE_UP             0x1
#define ELPCTRL_WAKE_UP_WLAN_READY  0x5
#define ELPCTRL_SLEEP               0x0
/* ELP WLAN_READY bit */
#define ELPCTRL_WLAN_READY          0x2

/*************************************************************************

    Interrupt Trigger Register (Host -> WiLink)

**************************************************************************/

/* Hardware to Embedded CPU Interrupts - first 32-bit register set */

/*
 * The host sets this bit to inform the Wlan
 * FW that a TX packet is in the XFER
 * Buffer #0.
 */
#define INTR_TRIG_TX_PROC0 BIT(2)

/*
 * The host sets this bit to inform the FW
 * that it read a packet from RX XFER
 * Buffer #0.
 */
#define INTR_TRIG_RX_PROC0 BIT(3)

#define INTR_TRIG_DEBUG_ACK BIT(4)

#define INTR_TRIG_STATE_CHANGED BIT(5)

/* Hardware to Embedded CPU Interrupts - second 32-bit register set */

/*
 * The host sets this bit to inform the FW
 * that it read a packet from RX XFER
 * Buffer #1.
 */
#define INTR_TRIG_RX_PROC1 BIT(17)

/*
 * The host sets this bit to inform the Wlan
 * hardware that a TX packet is in the XFER
 * Buffer #1.
 */
#define INTR_TRIG_TX_PROC1 BIT(18)

#define ACX_SLV_SOFT_RESET_BIT	BIT(1)
#define SOFT_RESET_MAX_TIME	1000000
#define SOFT_RESET_STALL_TIME	1000

#define ECPU_CONTROL_HALT	0x00000101

#define WELP_ARM_COMMAND_VAL	0x4

#endif /* __WLCORE_H__ */
Commit	Line	Data
b2ba99ff LC	1	/*
	2	* This file is part of wlcore
	3	*
	4	* Copyright (C) 2011 Texas Instruments Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* version 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	18	* 02110-1301 USA
	19	*
	20	*/
	21
	22	#ifndef __WLCORE_H__
	23	#define __WLCORE_H__
	24
c31be25a LC	25	#include <linux/platform_device.h>
c31be25a LC	26
ffeb501c	27	#include "wl12xx.h"
c31be25a LC	28	#include "event.h"
	29
	30	struct wlcore_ops {
6f7dd16c	31	int (identify_chip)(struct wl1271 wl);
dd5512eb	32	int (boot)(struct wl1271 wl);
f16ff758 LC	33	void (trigger_cmd)(struct wl1271 wl);
f16ff758 LC	34	void (ack_event)(struct wl1271 wl);
4ded91ce	35	s8 (get_pg_ver)(struct wl1271 wl);
30d9b4a5	36	void (get_mac)(struct wl1271 wl);
c31be25a LC	37	};
c31be25a LC	38
25a43d78 LC	39	enum wlcore_partitions {
	40	PART_DOWN,
	41	PART_WORK,
	42	PART_BOOT,
	43	PART_DRPW,
	44	PART_TOP_PRCM_ELP_SOC,
	45	PART_PHY_INIT,
	46
	47	PART_TABLE_LEN,
	48	};
	49
	50	struct wlcore_partition {
	51	u32 size;
	52	u32 start;
	53	};
	54
	55	struct wlcore_partition_set {
	56	struct wlcore_partition mem;
	57	struct wlcore_partition reg;
	58	struct wlcore_partition mem2;
	59	struct wlcore_partition mem3;
	60	};
	61
00782136 LC	62	enum wlcore_registers {
	63	/* register addresses, used with partition translation */
	64	REG_ECPU_CONTROL,
	65	REG_INTERRUPT_NO_CLEAR,
	66	REG_INTERRUPT_ACK,
	67	REG_COMMAND_MAILBOX_PTR,
	68	REG_EVENT_MAILBOX_PTR,
	69	REG_INTERRUPT_TRIG,
	70	REG_INTERRUPT_MASK,
	71	REG_PC_ON_RECOVERY,
	72	REG_CHIP_ID_B,
	73	REG_CMD_MBOX_ADDRESS,
	74
	75	/* data access memory addresses, used with partition translation */
	76	REG_SLV_MEM_DATA,
	77	REG_SLV_REG_DATA,
	78
	79	/* raw data access memory addresses */
	80	REG_RAW_FW_STATUS_ADDR,
	81
	82	REG_TABLE_LEN,
	83	};
	84
c31be25a LC	85	struct wl1271 {
	86	struct ieee80211_hw *hw;
	87	bool mac80211_registered;
	88
	89	struct device *dev;
	90
	91	void *if_priv;
	92
	93	struct wl1271_if_operations *if_ops;
	94
	95	void (*set_power)(bool enable);
	96	int irq;
	97	int ref_clock;
	98
	99	spinlock_t wl_lock;
	100
	101	enum wl1271_state state;
	102	enum wl12xx_fw_type fw_type;
	103	bool plt;
	104	u8 last_vif_count;
	105	struct mutex mutex;
	106
	107	unsigned long flags;
	108
25a43d78	109	struct wlcore_partition_set curr_part;
c31be25a LC	110
	111	struct wl1271_chip chip;
	112
	113	int cmd_box_addr;
c31be25a LC	114
	115	u8 *fw;
	116	size_t fw_len;
	117	void *nvs;
	118	size_t nvs_len;
	119
	120	s8 hw_pg_ver;
	121
	122	/* address read from the fuse ROM */
	123	u32 fuse_oui_addr;
	124	u32 fuse_nic_addr;
	125
	126	/* we have up to 2 MAC addresses */
	127	struct mac_address addresses[2];
	128	int channel;
	129	u8 system_hlid;
	130
	131	unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
	132	unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	133	unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	134	unsigned long rate_policies_map[
	135	BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
	136
	137	struct list_head wlvif_list;
	138
	139	u8 sta_count;
	140	u8 ap_count;
	141
	142	struct wl1271_acx_mem_map *target_mem_map;
	143
	144	/* Accounting for allocated / available TX blocks on HW */
	145	u32 tx_blocks_freed;
	146	u32 tx_blocks_available;
	147	u32 tx_allocated_blocks;
	148	u32 tx_results_count;
	149
	150	/* amount of spare TX blocks to use */
	151	u32 tx_spare_blocks;
	152
	153	/* Accounting for allocated / available Tx packets in HW */
	154	u32 tx_pkts_freed[NUM_TX_QUEUES];
	155	u32 tx_allocated_pkts[NUM_TX_QUEUES];
	156
	157	/* Transmitted TX packets counter for chipset interface */
	158	u32 tx_packets_count;
	159
	160	/* Time-offset between host and chipset clocks */
	161	s64 time_offset;
	162
	163	/* Frames scheduled for transmission, not handled yet */
	164	int tx_queue_count[NUM_TX_QUEUES];
	165	long stopped_queues_map;
	166
	167	/* Frames received, not handled yet by mac80211 */
	168	struct sk_buff_head deferred_rx_queue;
	169
	170	/* Frames sent, not returned yet to mac80211 */
	171	struct sk_buff_head deferred_tx_queue;
	172
	173	struct work_struct tx_work;
	174	struct workqueue_struct *freezable_wq;
	175
	176	/* Pending TX frames */
	177	unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)];
178	struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
179	int tx_frames_cnt;
180
181	/* FW Rx counter */
182	u32 rx_counter;
183
184	/* Rx memory pool address */
185	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
186
187	/* Intermediate buffer, used for packet aggregation */
188	u8 *aggr_buf;
189
190	/* Reusable dummy packet template */
191	struct sk_buff *dummy_packet;
192
193	/* Network stack work */
194	struct work_struct netstack_work;
195
196	/* FW log buffer */
197	u8 *fwlog;
198
199	/* Number of valid bytes in the FW log buffer */
200	ssize_t fwlog_size;
201
202	/* Sysfs FW log entry readers wait queue */
203	wait_queue_head_t fwlog_waitq;
204
205	/* Hardware recovery work */
206	struct work_struct recovery_work;
207
208	/* Pointer that holds DMA-friendly block for the mailbox */
209	struct event_mailbox *mbox;
210
211	/* The mbox event mask */
212	u32 event_mask;
213
214	/* Mailbox pointers */
215	u32 mbox_ptr[2];
216
217	/* Are we currently scanning */
218	struct ieee80211_vif *scan_vif;
219	struct wl1271_scan scan;
220	struct delayed_work scan_complete_work;
221
222	bool sched_scanning;
223
224	/* The current band */
225	enum ieee80211_band band;
226
227	struct completion *elp_compl;
228	struct delayed_work elp_work;
229
230	/* in dBm */
231	int power_level;
232
233	struct wl1271_stats stats;
234
235	__le32 buffer_32;
236	u32 buffer_cmd;
237	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
238
239	struct wl12xx_fw_status *fw_status;
240	struct wl1271_tx_hw_res_if *tx_res_if;
241
242	/* Current chipset configuration */
243	struct conf_drv_settings conf;
244
245	bool sg_enabled;
246
247	bool enable_11a;
248
249	/* Most recently reported noise in dBm */
250	s8 noise;
251
252	/* bands supported by this instance of wl12xx */
253	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
254
255	int tcxo_clock;
256
257	/*
258	* wowlan trigger was configured during suspend.
259	* (currently, only "ANY" trigger is supported)
260	*/
261	bool wow_enabled;
262	bool irq_wake_enabled;
263
264	/*
265	* AP-mode - links indexed by HLID. The global and broadcast links
266	* are always active.
267	*/
268	struct wl1271_link links[WL12XX_MAX_LINKS];
269
270	/* AP-mode - a bitmap of links currently in PS mode according to FW */
271	u32 ap_fw_ps_map;
272
273	/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
274	unsigned long ap_ps_map;
275
276	/* Quirks of specific hardware revisions */
277	unsigned int quirks;
278
279	/* Platform limitations */
280	unsigned int platform_quirks;
281
282	/* number of currently active RX BA sessions */
283	int ba_rx_session_count;
284
285	/* AP-mode - number of currently connected stations */
286	int active_sta_count;
287
288	/* last wlvif we transmitted from */
289	struct wl12xx_vif *last_wlvif;
290
291	/* work to fire when Tx is stuck */
292	struct delayed_work tx_watchdog_work;
293
294	struct wlcore_ops *ops;
25a43d78 LC	295	/* pointer to the lower driver partition table */
25a43d78 LC	296	const struct wlcore_partition_set *ptable;
00782136 LC	297	/* pointer to the lower driver register table */
00782136 LC	298	const int *rtable;
6f7dd16c LC	299	/* name of the firmwares to load - for PLT, single role, multi-role */
	300	const char *plt_fw_name;
	301	const char *sr_fw_name;
	302	const char *mr_fw_name;
c31be25a	303	};
ffeb501c LC	304
ffeb501c LC	305	int __devinit wlcore_probe(struct wl1271 wl, struct platform_device pdev);
b2ba99ff	306	int __devexit wlcore_remove(struct platform_device *pdev);
ffeb501c LC	307	struct ieee80211_hw *wlcore_alloc_hw(void);
	308	int wlcore_free_hw(struct wl1271 *wl);
	309
00782136 LC	310	/* Firmware image load chunk size */
	311	#define CHUNK_SIZE 16384
	312
6f7dd16c LC	313	/* Quirks */
	314
	315	/* Each RX/TX transaction requires an end-of-transaction transfer */
	316	#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
	317
	318	/* wl127x and SPI don't support SDIO block size alignment */
	319	#define WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT BIT(2)
	320
	321	/* Older firmwares did not implement the FW logger over bus feature */
	322	#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
	323
d203e59c LC	324	/* Older firmwares use an old NVS format */
	325	#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
	326
441101f6 LC	327	/* Some firmwares may not support ELP */
	328	#define WLCORE_QUIRK_NO_ELP BIT(6)
	329
00782136 LC	330	/* TODO: move to the lower drivers when all usages are abstracted */
	331	#define CHIP_ID_1271_PG10 (0x4030101)
	332	#define CHIP_ID_1271_PG20 (0x4030111)
	333	#define CHIP_ID_1283_PG10 (0x05030101)
	334	#define CHIP_ID_1283_PG20 (0x05030111)
	335
	336	/* TODO: move all these common registers and values elsewhere */
	337	#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
	338
	339	/* ELP register commands */
	340	#define ELPCTRL_WAKE_UP 0x1
	341	#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
	342	#define ELPCTRL_SLEEP 0x0
	343	/* ELP WLAN_READY bit */
	344	#define ELPCTRL_WLAN_READY 0x2
	345
	346	/*************************************************************************
	347
	348	Interrupt Trigger Register (Host -> WiLink)
	349
	350	**************************************************************************/
	351
	352	/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
	353
00782136 LC	354	/*
	355	* The host sets this bit to inform the Wlan
	356	* FW that a TX packet is in the XFER
	357	* Buffer #0.
	358	*/
	359	#define INTR_TRIG_TX_PROC0 BIT(2)
	360
	361	/*
	362	* The host sets this bit to inform the FW
	363	* that it read a packet from RX XFER
	364	* Buffer #0.
	365	*/
	366	#define INTR_TRIG_RX_PROC0 BIT(3)
	367
	368	#define INTR_TRIG_DEBUG_ACK BIT(4)
	369
	370	#define INTR_TRIG_STATE_CHANGED BIT(5)
	371
	372	/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
	373
	374	/*
	375	* The host sets this bit to inform the FW
	376	* that it read a packet from RX XFER
	377	* Buffer #1.
	378	*/
	379	#define INTR_TRIG_RX_PROC1 BIT(17)
	380
	381	/*
	382	* The host sets this bit to inform the Wlan
	383	* hardware that a TX packet is in the XFER
	384	* Buffer #1.
	385	*/
	386	#define INTR_TRIG_TX_PROC1 BIT(18)
	387
	388	#define ACX_SLV_SOFT_RESET_BIT BIT(1)
	389	#define SOFT_RESET_MAX_TIME 1000000
	390	#define SOFT_RESET_STALL_TIME 1000
	391
	392	#define ECPU_CONTROL_HALT 0x00000101
b2ba99ff	393
6f7dd16c LC	394	#define WELP_ARM_COMMAND_VAL 0x4
6f7dd16c LC	395
b2ba99ff	396	#endif /* __WLCORE_H__ */