[deliverable/linux.git] / drivers / net / wireless / wl1251 / boot.c

/*
 * This file is part of wl1251
 *
 * Copyright (C) 2008 Nokia Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/slab.h>

#include "reg.h"
#include "boot.h"
#include "io.h"
#include "spi.h"
#include "event.h"
#include "acx.h"

void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
{
	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
	wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
}

int wl1251_boot_soft_reset(struct wl1251 *wl)
{
	unsigned long timeout;
	u32 boot_data;

	/* perform soft reset */
	wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);

	/* SOFT_RESET is self clearing */
	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	while (1) {
		boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
		wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
		if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
			break;

		if (time_after(jiffies, timeout)) {
			/* 1.2 check pWhalBus->uSelfClearTime if the
			 * timeout was reached */
			wl1251_error("soft reset timeout");
			return -1;
		}

		udelay(SOFT_RESET_STALL_TIME);
	}

	/* disable Rx/Tx */
	wl1251_reg_write32(wl, ENABLE, 0x0);

	/* disable auto calibration on start*/
	wl1251_reg_write32(wl, SPARE_A2, 0xffff);

	return 0;
}

int wl1251_boot_init_seq(struct wl1251 *wl)
{
	u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;

	/*
	 * col #1: INTEGER_DIVIDER
	 * col #2: FRACTIONAL_DIVIDER
	 * col #3: ATTN_BB
	 * col #4: ALPHA_BB
	 * col #5: STOP_TIME_BB
	 * col #6: BB_PLL_LOOP_FILTER
	 */
	static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {

		{   83, 87381,  0xB, 5, 0xF00,  3}, /* REF_FREQ_19_2*/
		{   61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
		{   41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
		{   40, 0,      0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
		{   47, 162280, 0xC, 6, 0x2760, 1}  /* REF_FREQ_33_6        */
	};

	/* read NVS params */
	scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
	wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);

	/* read ELP_CMD */
	elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
	wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);

	/* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
	ref_freq = scr_pad6 & 0x000000FF;
	wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);

	wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);

	/*
	 * PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
	 */
	wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);

	/*
	 * set the clock detect feature to work in the restart wu procedure
	 * (ELP_CFG_MODE[14]) and Select the clock source type
	 * (ELP_CFG_MODE[13:12])
	 */
	tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
	wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);

	/* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
	elp_cmd |= 0x00000040;
	wl1251_reg_write32(wl, ELP_CMD, elp_cmd);

	/* PG 1.2: Set the BB PLL stable time to be 1000usec
	 * (PLL_STABLE_TIME) */
	wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);

	/* PG 1.2: read clock request time */
	init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);

	/*
	 * PG 1.2: set the clock request time to be ref_clk_settling_time -
	 * 1ms = 4ms
	 */
	if (init_data > 0x21)
		tmp = init_data - 0x21;
	else
		tmp = 0;
	wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);

	/* set BB PLL configurations in RF AFE */
	wl1251_reg_write32(wl, 0x003058cc, 0x4B5);

	/* set RF_AFE_REG_5 */
	wl1251_reg_write32(wl, 0x003058d4, 0x50);

	/* set RF_AFE_CTRL_REG_2 */
	wl1251_reg_write32(wl, 0x00305948, 0x11c001);

	/*
	 * change RF PLL and BB PLL divider for VCO clock and adjust VCO
	 * bais current(RF_AFE_REG_13)
	 */
	wl1251_reg_write32(wl, 0x003058f4, 0x1e);

	/* set BB PLL configurations */
	tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
	wl1251_reg_write32(wl, 0x00305840, tmp);

	/* set fractional divider according to Appendix C-BB PLL
	 * Calculations
	 */
	tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
	wl1251_reg_write32(wl, 0x00305844, tmp);

	/* set the initial data for the sigma delta */
	wl1251_reg_write32(wl, 0x00305848, 0x3039);

	/*
	 * set the accumulator attenuation value, calibration loop1
	 * (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
	 * the VCO gain
	 */
	tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
		(LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
	wl1251_reg_write32(wl, 0x00305854, tmp);

	/*
	 * set the calibration stop time after holdoff time expires and set
	 * settling time HOLD_OFF_TIME_BB
	 */
	tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
	wl1251_reg_write32(wl, 0x00305858, tmp);

	/*
	 * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
	 * constant leakage current to linearize PFD to 0uA -
	 * BB_ILOOPF[7:3]
	 */
	tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
	wl1251_reg_write32(wl, 0x003058f8, tmp);

	/*
	 * set regulator output voltage for n divider to
	 * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
	 * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
	 * PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
	 */
	wl1251_reg_write32(wl, 0x003058f0, 0x29);

	/* enable restart wakeup sequence (ELP_CMD[0]) */
	wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);

	/* restart sequence completed */
	udelay(2000);

	return 0;
}

static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
{
	u32 cpu_ctrl;

	/* 10.5.0 run the firmware (I) */
	cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);

	/* 10.5.1 run the firmware (II) */
	cpu_ctrl &= ~flag;
	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
}

int wl1251_boot_run_firmware(struct wl1251 *wl)
{
	int loop, ret;
	u32 chip_id, acx_intr;

	wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);

	chip_id = wl1251_reg_read32(wl, CHIP_ID_B);

	wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);

	if (chip_id != wl->chip_id) {
		wl1251_error("chip id doesn't match after firmware boot");
		return -EIO;
	}

	/* wait for init to complete */
	loop = 0;
	while (loop++ < INIT_LOOP) {
		udelay(INIT_LOOP_DELAY);
		acx_intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);

		if (acx_intr == 0xffffffff) {
			wl1251_error("error reading hardware complete "
				     "init indication");
			return -EIO;
		}
		/* check that ACX_INTR_INIT_COMPLETE is enabled */
		else if (acx_intr & WL1251_ACX_INTR_INIT_COMPLETE) {
			wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
					   WL1251_ACX_INTR_INIT_COMPLETE);
			break;
		}
	}

	if (loop > INIT_LOOP) {
		wl1251_error("timeout waiting for the hardware to "
			     "complete initialization");
		return -EIO;
	}

	/* get hardware config command mail box */
	wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);

	/* get hardware config event mail box */
	wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);

	/* set the working partition to its "running" mode offset */
	wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
			     WL1251_PART_WORK_MEM_SIZE,
			     WL1251_PART_WORK_REG_START,
			     WL1251_PART_WORK_REG_SIZE);

	wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
		     wl->cmd_box_addr, wl->event_box_addr);

	wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));

	/*
	 * in case of full asynchronous mode the firmware event must be
	 * ready to receive event from the command mailbox
	 */

	/* enable gpio interrupts */
	wl1251_enable_interrupts(wl);

	/* Enable target's interrupts */
	wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
		WL1251_ACX_INTR_RX1_DATA |
		WL1251_ACX_INTR_TX_RESULT |
		WL1251_ACX_INTR_EVENT_A |
		WL1251_ACX_INTR_EVENT_B |
		WL1251_ACX_INTR_INIT_COMPLETE;
	wl1251_boot_target_enable_interrupts(wl);

	wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID |
		SYNCHRONIZATION_TIMEOUT_EVENT_ID |
		ROAMING_TRIGGER_LOW_RSSI_EVENT_ID |
		ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID |
		REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID |
		BT_PTA_PREDICTION_EVENT_ID | JOIN_EVENT_COMPLETE_ID;

	ret = wl1251_event_unmask(wl);
	if (ret < 0) {
		wl1251_error("EVENT mask setting failed");
		return ret;
	}

	wl1251_event_mbox_config(wl);

	/* firmware startup completed */
	return 0;
}

static int wl1251_boot_upload_firmware(struct wl1251 *wl)
{
	int addr, chunk_num, partition_limit;
	size_t fw_data_len, len;
	u8 *p, *buf;

	/* whal_FwCtrl_LoadFwImageSm() */

	wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
		     wl1251_reg_read32(wl, CHIP_ID_B));

	/* 10.0 check firmware length and set partition */
	fw_data_len =  (wl->fw[4] << 24) | (wl->fw[5] << 16) |
		(wl->fw[6] << 8) | (wl->fw[7]);

	wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
		CHUNK_SIZE);

	if ((fw_data_len % 4) != 0) {
		wl1251_error("firmware length not multiple of four");
		return -EIO;
	}

	buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	if (!buf) {
		wl1251_error("allocation for firmware upload chunk failed");
		return -ENOMEM;
	}

	wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
			     WL1251_PART_DOWN_MEM_SIZE,
			     WL1251_PART_DOWN_REG_START,
			     WL1251_PART_DOWN_REG_SIZE);

	/* 10.1 set partition limit and chunk num */
	chunk_num = 0;
	partition_limit = WL1251_PART_DOWN_MEM_SIZE;

	while (chunk_num < fw_data_len / CHUNK_SIZE) {
		/* 10.2 update partition, if needed */
		addr = WL1251_PART_DOWN_MEM_START +
			(chunk_num + 2) * CHUNK_SIZE;
		if (addr > partition_limit) {
			addr = WL1251_PART_DOWN_MEM_START +
				chunk_num * CHUNK_SIZE;
			partition_limit = chunk_num * CHUNK_SIZE +
				WL1251_PART_DOWN_MEM_SIZE;
			wl1251_set_partition(wl,
					     addr,
					     WL1251_PART_DOWN_MEM_SIZE,
					     WL1251_PART_DOWN_REG_START,
					     WL1251_PART_DOWN_REG_SIZE);
		}

		/* 10.3 upload the chunk */
		addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
		p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
		wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
			     p, addr);

		/* need to copy the chunk for dma */
		len = CHUNK_SIZE;
		memcpy(buf, p, len);
		wl1251_mem_write(wl, addr, buf, len);

		chunk_num++;
	}

	/* 10.4 upload the last chunk */
	addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
	p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;

	/* need to copy the chunk for dma */
	len = fw_data_len % CHUNK_SIZE;
	memcpy(buf, p, len);

	wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
		     len, p, addr);
	wl1251_mem_write(wl, addr, buf, len);

	kfree(buf);

	return 0;
}

static int wl1251_boot_upload_nvs(struct wl1251 *wl)
{
	size_t nvs_len, nvs_bytes_written, burst_len;
	int nvs_start, i;
	u32 dest_addr, val;
	u8 *nvs_ptr, *nvs;

	nvs = wl->nvs;
	if (nvs == NULL)
		return -ENODEV;

	nvs_ptr = nvs;

	nvs_len = wl->nvs_len;
	nvs_start = wl->fw_len;

	/*
	 * Layout before the actual NVS tables:
	 * 1 byte : burst length.
	 * 2 bytes: destination address.
	 * n bytes: data to burst copy.
	 *
	 * This is ended by a 0 length, then the NVS tables.
	 */

	while (nvs_ptr[0]) {
		burst_len = nvs_ptr[0];
		dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));

		/* We move our pointer to the data */
		nvs_ptr += 3;

		for (i = 0; i < burst_len; i++) {
			val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
			       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

			wl1251_debug(DEBUG_BOOT,
				     "nvs burst write 0x%x: 0x%x",
				     dest_addr, val);
			wl1251_mem_write32(wl, dest_addr, val);

			nvs_ptr += 4;
			dest_addr += 4;
		}
	}

	/*
	 * We've reached the first zero length, the first NVS table
	 * is 7 bytes further.
	 */
	nvs_ptr += 7;
	nvs_len -= nvs_ptr - nvs;
	nvs_len = ALIGN(nvs_len, 4);

	/* Now we must set the partition correctly */
	wl1251_set_partition(wl, nvs_start,
			     WL1251_PART_DOWN_MEM_SIZE,
			     WL1251_PART_DOWN_REG_START,
			     WL1251_PART_DOWN_REG_SIZE);

	/* And finally we upload the NVS tables */
	nvs_bytes_written = 0;
	while (nvs_bytes_written < nvs_len) {
		val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
		       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

		wl1251_debug(DEBUG_BOOT,
			     "nvs write table 0x%x: 0x%x",
			     nvs_start, val);
		wl1251_mem_write32(wl, nvs_start, val);

		nvs_ptr += 4;
		nvs_bytes_written += 4;
		nvs_start += 4;
	}

	return 0;
}

int wl1251_boot(struct wl1251 *wl)
{
	int ret = 0, minor_minor_e2_ver;
	u32 tmp, boot_data;

	/* halt embedded ARM CPU while loading firmware */
	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);

	ret = wl1251_boot_soft_reset(wl);
	if (ret < 0)
		goto out;

	/* 2. start processing NVS file */
	if (wl->use_eeprom) {
		wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
		/* Wait for EEPROM NVS burst read to complete */
		msleep(40);
		wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
	} else {
		ret = wl1251_boot_upload_nvs(wl);
		if (ret < 0)
			goto out;

		/* write firmware's last address (ie. it's length) to
		 * ACX_EEPROMLESS_IND_REG */
		wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
	}

	/* 6. read the EEPROM parameters */
	tmp = wl1251_reg_read32(wl, SCR_PAD2);

	/* 7. read bootdata */
	wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
	wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
	tmp = wl1251_reg_read32(wl, SCR_PAD3);

	/* 8. check bootdata and call restart sequence */
	wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
	minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;

	wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
		     "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
		     wl->boot_attr.radio_type, wl->boot_attr.major,
		     wl->boot_attr.minor, minor_minor_e2_ver);

	ret = wl1251_boot_init_seq(wl);
	if (ret < 0)
		goto out;

	/* 9. NVS processing done */
	boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);

	wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);

	/* 10. check that ECPU_CONTROL_HALT bits are set in
	 * pWhalBus->uBootData and start uploading firmware
	 */
	if ((boot_data & ECPU_CONTROL_HALT) == 0) {
		wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
		ret = -EIO;
		goto out;
	}

	ret = wl1251_boot_upload_firmware(wl);
	if (ret < 0)
		goto out;

	/* 10.5 start firmware */
	ret = wl1251_boot_run_firmware(wl);
	if (ret < 0)
		goto out;

out:
	return ret;
}
Commit	Line	Data
2f01a1f5	1	/*
80301cdc	2	* This file is part of wl1251
2f01a1f5 KV	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	*
2f01a1f5 KV	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* version 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	18	* 02110-1301 USA
	19	*
	20	*/
	21
5a0e3ad6	22	#include <linux/slab.h>
2f01a1f5	23
9bc6772e KV	24	#include "reg.h"
	25	#include "boot.h"
	26	#include "io.h"
	27	#include "spi.h"
	28	#include "event.h"
	29	#include "acx.h"
2f01a1f5	30
80301cdc	31	void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
2f01a1f5	32	{
80301cdc KV	33	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
80301cdc KV	34	wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
2f01a1f5 KV	35	}
2f01a1f5 KV	36
80301cdc	37	int wl1251_boot_soft_reset(struct wl1251 *wl)
2f01a1f5 KV	38	{
	39	unsigned long timeout;
	40	u32 boot_data;
	41
	42	/* perform soft reset */
80301cdc	43	wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
2f01a1f5 KV	44
	45	/* SOFT_RESET is self clearing */
	46	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	47	while (1) {
80301cdc KV	48	boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
80301cdc KV	49	wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
2f01a1f5 KV	50	if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
	51	break;
	52
	53	if (time_after(jiffies, timeout)) {
	54	/* 1.2 check pWhalBus->uSelfClearTime if the
	55	* timeout was reached */
80301cdc	56	wl1251_error("soft reset timeout");
2f01a1f5 KV	57	return -1;
	58	}
	59
	60	udelay(SOFT_RESET_STALL_TIME);
	61	}
	62
	63	/* disable Rx/Tx */
80301cdc	64	wl1251_reg_write32(wl, ENABLE, 0x0);
2f01a1f5 KV	65
2f01a1f5 KV	66	/* disable auto calibration on start*/
80301cdc	67	wl1251_reg_write32(wl, SPARE_A2, 0xffff);
2f01a1f5 KV	68
	69	return 0;
	70	}
	71
80301cdc	72	int wl1251_boot_init_seq(struct wl1251 *wl)
2f01a1f5 KV	73	{
	74	u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
	75
	76	/*
	77	* col #1: INTEGER_DIVIDER
	78	* col #2: FRACTIONAL_DIVIDER
	79	* col #3: ATTN_BB
	80	* col #4: ALPHA_BB
	81	* col #5: STOP_TIME_BB
	82	* col #6: BB_PLL_LOOP_FILTER
	83	*/
	84	static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
	85
	86	{ 83, 87381, 0xB, 5, 0xF00, 3}, /* REF_FREQ_19_2*/
	87	{ 61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
	88	{ 41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
	89	{ 40, 0, 0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
	90	{ 47, 162280, 0xC, 6, 0x2760, 1} /* REF_FREQ_33_6 */
	91	};
	92
	93	/* read NVS params */
80301cdc KV	94	scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
80301cdc KV	95	wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
2f01a1f5 KV	96
2f01a1f5 KV	97	/* read ELP_CMD */
80301cdc KV	98	elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
80301cdc KV	99	wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
2f01a1f5 KV	100
	101	/* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
	102	ref_freq = scr_pad6 & 0x000000FF;
80301cdc	103	wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
2f01a1f5	104
80301cdc	105	wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
2f01a1f5 KV	106
	107	/*
	108	* PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
	109	*/
80301cdc	110	wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
2f01a1f5 KV	111
	112	/*
	113	* set the clock detect feature to work in the restart wu procedure
	114	* (ELP_CFG_MODE[14]) and Select the clock source type
	115	* (ELP_CFG_MODE[13:12])
	116	*/
	117	tmp = ((scr_pad6 & 0x0000FF00) << 4) \| 0x00004000;
80301cdc	118	wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
2f01a1f5 KV	119
	120	/* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
	121	elp_cmd \|= 0x00000040;
80301cdc	122	wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
2f01a1f5 KV	123
	124	/* PG 1.2: Set the BB PLL stable time to be 1000usec
	125	* (PLL_STABLE_TIME) */
80301cdc	126	wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
2f01a1f5 KV	127
2f01a1f5 KV	128	/* PG 1.2: read clock request time */
80301cdc	129	init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
2f01a1f5 KV	130
	131	/*
	132	* PG 1.2: set the clock request time to be ref_clk_settling_time -
	133	* 1ms = 4ms
	134	*/
	135	if (init_data > 0x21)
	136	tmp = init_data - 0x21;
	137	else
	138	tmp = 0;
80301cdc	139	wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
2f01a1f5 KV	140
2f01a1f5 KV	141	/* set BB PLL configurations in RF AFE */
80301cdc	142	wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
2f01a1f5 KV	143
2f01a1f5 KV	144	/* set RF_AFE_REG_5 */
80301cdc	145	wl1251_reg_write32(wl, 0x003058d4, 0x50);
2f01a1f5 KV	146
2f01a1f5 KV	147	/* set RF_AFE_CTRL_REG_2 */
80301cdc	148	wl1251_reg_write32(wl, 0x00305948, 0x11c001);
2f01a1f5 KV	149
	150	/*
	151	* change RF PLL and BB PLL divider for VCO clock and adjust VCO
	152	* bais current(RF_AFE_REG_13)
	153	*/
80301cdc	154	wl1251_reg_write32(wl, 0x003058f4, 0x1e);
2f01a1f5 KV	155
	156	/* set BB PLL configurations */
	157	tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] \| 0x00017000;
80301cdc	158	wl1251_reg_write32(wl, 0x00305840, tmp);
2f01a1f5 KV	159
	160	/* set fractional divider according to Appendix C-BB PLL
	161	* Calculations
	162	*/
	163	tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
80301cdc	164	wl1251_reg_write32(wl, 0x00305844, tmp);
2f01a1f5 KV	165
2f01a1f5 KV	166	/* set the initial data for the sigma delta */
80301cdc	167	wl1251_reg_write32(wl, 0x00305848, 0x3039);
2f01a1f5 KV	168
	169	/*
	170	* set the accumulator attenuation value, calibration loop1
	171	* (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
	172	* the VCO gain
	173	*/
	174	tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) \|
	175	(LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) \| 0x1;
80301cdc	176	wl1251_reg_write32(wl, 0x00305854, tmp);
2f01a1f5 KV	177
	178	/*
	179	* set the calibration stop time after holdoff time expires and set
	180	* settling time HOLD_OFF_TIME_BB
	181	*/
	182	tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] \| 0x000A0000;
80301cdc	183	wl1251_reg_write32(wl, 0x00305858, tmp);
2f01a1f5 KV	184
	185	/*
	186	* set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
	187	* constant leakage current to linearize PFD to 0uA -
	188	* BB_ILOOPF[7:3]
	189	*/
	190	tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] \| 0x00000030;
80301cdc	191	wl1251_reg_write32(wl, 0x003058f8, tmp);
2f01a1f5 KV	192
	193	/*
	194	* set regulator output voltage for n divider to
	195	* 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
	196	* set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
	197	* PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
	198	*/
80301cdc	199	wl1251_reg_write32(wl, 0x003058f0, 0x29);
2f01a1f5 KV	200
2f01a1f5 KV	201	/* enable restart wakeup sequence (ELP_CMD[0]) */
80301cdc	202	wl1251_reg_write32(wl, ELP_CMD, elp_cmd \| 0x1);
2f01a1f5 KV	203
	204	/* restart sequence completed */
	205	udelay(2000);
	206
	207	return 0;
	208	}
	209
0e71bb08 KV	210	static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
	211	{
	212	u32 cpu_ctrl;
	213
	214	/* 10.5.0 run the firmware (I) */
	215	cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
	216
	217	/* 10.5.1 run the firmware (II) */
	218	cpu_ctrl &= ~flag;
	219	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
	220	}
	221
80301cdc	222	int wl1251_boot_run_firmware(struct wl1251 *wl)
2f01a1f5 KV	223	{
2f01a1f5 KV	224	int loop, ret;
1ab36d68	225	u32 chip_id, acx_intr;
2f01a1f5	226
0e71bb08	227	wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
2f01a1f5	228
80301cdc	229	chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
2f01a1f5	230
80301cdc	231	wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
2f01a1f5	232
0e71bb08	233	if (chip_id != wl->chip_id) {
80301cdc	234	wl1251_error("chip id doesn't match after firmware boot");
2f01a1f5 KV	235	return -EIO;
	236	}
	237
	238	/* wait for init to complete */
	239	loop = 0;
	240	while (loop++ < INIT_LOOP) {
	241	udelay(INIT_LOOP_DELAY);
1ab36d68	242	acx_intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
2f01a1f5	243
1ab36d68	244	if (acx_intr == 0xffffffff) {
80301cdc	245	wl1251_error("error reading hardware complete "
2f01a1f5 KV	246	"init indication");
	247	return -EIO;
	248	}
	249	/* check that ACX_INTR_INIT_COMPLETE is enabled */
1ab36d68	250	else if (acx_intr & WL1251_ACX_INTR_INIT_COMPLETE) {
80301cdc	251	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
0e71bb08	252	WL1251_ACX_INTR_INIT_COMPLETE);
2f01a1f5 KV	253	break;
	254	}
	255	}
	256
e8a4a6df	257	if (loop > INIT_LOOP) {
80301cdc	258	wl1251_error("timeout waiting for the hardware to "
2f01a1f5 KV	259	"complete initialization");
	260	return -EIO;
	261	}
	262
	263	/* get hardware config command mail box */
80301cdc	264	wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
2f01a1f5 KV	265
2f01a1f5 KV	266	/* get hardware config event mail box */
80301cdc	267	wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
2f01a1f5 KV	268
2f01a1f5 KV	269	/* set the working partition to its "running" mode offset */
0e71bb08 KV	270	wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
	271	WL1251_PART_WORK_MEM_SIZE,
	272	WL1251_PART_WORK_REG_START,
	273	WL1251_PART_WORK_REG_SIZE);
2f01a1f5	274
80301cdc	275	wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
2f01a1f5 KV	276	wl->cmd_box_addr, wl->event_box_addr);
2f01a1f5 KV	277
0e71bb08	278	wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));
0d1c3839	279
2f01a1f5 KV	280	/*
	281	* in case of full asynchronous mode the firmware event must be
	282	* ready to receive event from the command mailbox
	283	*/
	284
	285	/* enable gpio interrupts */
b5ed9c1b	286	wl1251_enable_interrupts(wl);
2f01a1f5	287
0e71bb08 KV	288	/* Enable target's interrupts */
	289	wl->intr_mask = WL1251_ACX_INTR_RX0_DATA \|
	290	WL1251_ACX_INTR_RX1_DATA \|
	291	WL1251_ACX_INTR_TX_RESULT \|
	292	WL1251_ACX_INTR_EVENT_A \|
	293	WL1251_ACX_INTR_EVENT_B \|
	294	WL1251_ACX_INTR_INIT_COMPLETE;
	295	wl1251_boot_target_enable_interrupts(wl);
2f01a1f5	296
a1590f24 JY	297	wl->event_mask = SCAN_COMPLETE_EVENT_ID \| BSS_LOSE_EVENT_ID \|
	298	SYNCHRONIZATION_TIMEOUT_EVENT_ID \|
	299	ROAMING_TRIGGER_LOW_RSSI_EVENT_ID \|
	300	ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID \|
	301	REGAINED_BSS_EVENT_ID \| BT_PTA_SENSE_EVENT_ID \|
7273b970	302	BT_PTA_PREDICTION_EVENT_ID \| JOIN_EVENT_COMPLETE_ID;
2f01a1f5	303
80301cdc	304	ret = wl1251_event_unmask(wl);
2f01a1f5	305	if (ret < 0) {
80301cdc	306	wl1251_error("EVENT mask setting failed");
2f01a1f5 KV	307	return ret;
	308	}
	309
80301cdc	310	wl1251_event_mbox_config(wl);
2f01a1f5 KV	311
	312	/* firmware startup completed */
	313	return 0;
	314	}
0e71bb08 KV	315
	316	static int wl1251_boot_upload_firmware(struct wl1251 *wl)
	317	{
	318	int addr, chunk_num, partition_limit;
c74ddfd5 KV	319	size_t fw_data_len, len;
c74ddfd5 KV	320	u8 p, buf;
0e71bb08 KV	321
	322	/* whal_FwCtrl_LoadFwImageSm() */
	323
	324	wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
	325	wl1251_reg_read32(wl, CHIP_ID_B));
	326
	327	/* 10.0 check firmware length and set partition */
	328	fw_data_len = (wl->fw[4] << 24) \| (wl->fw[5] << 16) \|
	329	(wl->fw[6] << 8) \| (wl->fw[7]);
	330
	331	wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
	332	CHUNK_SIZE);
	333
	334	if ((fw_data_len % 4) != 0) {
	335	wl1251_error("firmware length not multiple of four");
	336	return -EIO;
	337	}
	338
c74ddfd5 KV	339	buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	340	if (!buf) {
	341	wl1251_error("allocation for firmware upload chunk failed");
	342	return -ENOMEM;
	343	}
	344
0e71bb08 KV	345	wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
	346	WL1251_PART_DOWN_MEM_SIZE,
	347	WL1251_PART_DOWN_REG_START,
	348	WL1251_PART_DOWN_REG_SIZE);
	349
	350	/* 10.1 set partition limit and chunk num */
	351	chunk_num = 0;
	352	partition_limit = WL1251_PART_DOWN_MEM_SIZE;
	353
	354	while (chunk_num < fw_data_len / CHUNK_SIZE) {
	355	/* 10.2 update partition, if needed */
	356	addr = WL1251_PART_DOWN_MEM_START +
	357	(chunk_num + 2) * CHUNK_SIZE;
	358	if (addr > partition_limit) {
	359	addr = WL1251_PART_DOWN_MEM_START +
	360	chunk_num * CHUNK_SIZE;
	361	partition_limit = chunk_num * CHUNK_SIZE +
	362	WL1251_PART_DOWN_MEM_SIZE;
	363	wl1251_set_partition(wl,
	364	addr,
	365	WL1251_PART_DOWN_MEM_SIZE,
	366	WL1251_PART_DOWN_REG_START,
	367	WL1251_PART_DOWN_REG_SIZE);
	368	}
	369
	370	/* 10.3 upload the chunk */
	371	addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
	372	p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
	373	wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
	374	p, addr);
c74ddfd5 KV	375
	376	/* need to copy the chunk for dma */
	377	len = CHUNK_SIZE;
	378	memcpy(buf, p, len);
	379	wl1251_mem_write(wl, addr, buf, len);
0e71bb08 KV	380
	381	chunk_num++;
	382	}
	383
	384	/* 10.4 upload the last chunk */
	385	addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
	386	p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
c74ddfd5 KV	387
	388	/* need to copy the chunk for dma */
	389	len = fw_data_len % CHUNK_SIZE;
	390	memcpy(buf, p, len);
	391
0e71bb08	392	wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
c74ddfd5 KV	393	len, p, addr);
	394	wl1251_mem_write(wl, addr, buf, len);
	395
	396	kfree(buf);
0e71bb08 KV	397
	398	return 0;
	399	}
	400
	401	static int wl1251_boot_upload_nvs(struct wl1251 *wl)
	402	{
	403	size_t nvs_len, nvs_bytes_written, burst_len;
	404	int nvs_start, i;
	405	u32 dest_addr, val;
	406	u8 nvs_ptr, nvs;
	407
	408	nvs = wl->nvs;
	409	if (nvs == NULL)
	410	return -ENODEV;
	411
	412	nvs_ptr = nvs;
	413
	414	nvs_len = wl->nvs_len;
	415	nvs_start = wl->fw_len;
	416
	417	/*
	418	* Layout before the actual NVS tables:
	419	* 1 byte : burst length.
	420	* 2 bytes: destination address.
	421	* n bytes: data to burst copy.
	422	*
	423	* This is ended by a 0 length, then the NVS tables.
	424	*/
	425
	426	while (nvs_ptr[0]) {
	427	burst_len = nvs_ptr[0];
	428	dest_addr = (nvs_ptr[1] & 0xfe) \| ((u32)(nvs_ptr[2] << 8));
	429
	430	/* We move our pointer to the data */
	431	nvs_ptr += 3;
	432
	433	for (i = 0; i < burst_len; i++) {
	434	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
	435	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
	436
	437	wl1251_debug(DEBUG_BOOT,
	438	"nvs burst write 0x%x: 0x%x",
	439	dest_addr, val);
	440	wl1251_mem_write32(wl, dest_addr, val);
	441
	442	nvs_ptr += 4;
	443	dest_addr += 4;
	444	}
	445	}
	446
	447	/*
	448	* We've reached the first zero length, the first NVS table
	449	* is 7 bytes further.
	450	*/
	451	nvs_ptr += 7;
	452	nvs_len -= nvs_ptr - nvs;
	453	nvs_len = ALIGN(nvs_len, 4);
	454
	455	/* Now we must set the partition correctly */
	456	wl1251_set_partition(wl, nvs_start,
	457	WL1251_PART_DOWN_MEM_SIZE,
	458	WL1251_PART_DOWN_REG_START,
	459	WL1251_PART_DOWN_REG_SIZE);
	460
461	/* And finally we upload the NVS tables */
462	nvs_bytes_written = 0;
463	while (nvs_bytes_written < nvs_len) {
464	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
465	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
466
0e71bb08 KV	467	wl1251_debug(DEBUG_BOOT,
	468	"nvs write table 0x%x: 0x%x",
	469	nvs_start, val);
	470	wl1251_mem_write32(wl, nvs_start, val);
	471
	472	nvs_ptr += 4;
	473	nvs_bytes_written += 4;
	474	nvs_start += 4;
	475	}
	476
	477	return 0;
	478	}
	479
	480	int wl1251_boot(struct wl1251 *wl)
	481	{
	482	int ret = 0, minor_minor_e2_ver;
	483	u32 tmp, boot_data;
	484
bcd64e0c BC	485	/* halt embedded ARM CPU while loading firmware */
	486	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);
	487
0e71bb08 KV	488	ret = wl1251_boot_soft_reset(wl);
	489	if (ret < 0)
	490	goto out;
	491
	492	/* 2. start processing NVS file */
c95cf3d0 DJW	493	if (wl->use_eeprom) {
c95cf3d0 DJW	494	wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
1e3f7ac8 GI	495	/* Wait for EEPROM NVS burst read to complete */
1e3f7ac8 GI	496	msleep(40);
c95cf3d0 DJW	497	wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
	498	} else {
	499	ret = wl1251_boot_upload_nvs(wl);
	500	if (ret < 0)
	501	goto out;
	502
	503	/* write firmware's last address (ie. it's length) to
	504	* ACX_EEPROMLESS_IND_REG */
	505	wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
	506	}
0e71bb08 KV	507
	508	/* 6. read the EEPROM parameters */
	509	tmp = wl1251_reg_read32(wl, SCR_PAD2);
	510
	511	/* 7. read bootdata */
	512	wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
	513	wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
	514	tmp = wl1251_reg_read32(wl, SCR_PAD3);
	515
	516	/* 8. check bootdata and call restart sequence */
	517	wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
	518	minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
	519
	520	wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
	521	"minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
	522	wl->boot_attr.radio_type, wl->boot_attr.major,
	523	wl->boot_attr.minor, minor_minor_e2_ver);
	524
	525	ret = wl1251_boot_init_seq(wl);
	526	if (ret < 0)
	527	goto out;
	528
	529	/* 9. NVS processing done */
	530	boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
	531
	532	wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
	533
	534	/* 10. check that ECPU_CONTROL_HALT bits are set in
	535	* pWhalBus->uBootData and start uploading firmware
	536	*/
	537	if ((boot_data & ECPU_CONTROL_HALT) == 0) {
	538	wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
	539	ret = -EIO;
	540	goto out;
	541	}
	542
	543	ret = wl1251_boot_upload_firmware(wl);
	544	if (ret < 0)
	545	goto out;
	546
	547	/* 10.5 start firmware */
	548	ret = wl1251_boot_run_firmware(wl);
	549	if (ret < 0)
	550	goto out;
	551
	552	out:
	553	return ret;
	554	}