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mac80211: Stop BA session event from device
[deliverable/linux.git] / drivers / net / wireless / wl12xx / boot.c
CommitLineData
f5fc0f86
LC		 1/*
2 * This file is part of wl1271
3 *
2f826f55 4 * Copyright (C) 2008-2010 Nokia Corporation
f5fc0f86
LC		 5 *
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
5a0e3ad6 24#include <linux/slab.h>
5ea417ae 25#include <linux/wl12xx.h>
f5fc0f86 26
00d20100
SL		 27#include "acx.h"
28#include "reg.h"
29#include "boot.h"
30#include "io.h"
31#include "event.h"
ae113b57 32#include "rx.h"
f5fc0f86
LC		 33
34static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
35 [PART_DOWN] = {
36 .mem = {
37 .start = 0x00000000,
38 .size = 0x000177c0
39 },
40 .reg = {
41 .start = REGISTERS_BASE,
42 .size = 0x00008800
43 },
451de97a
JO		 44 .mem2 = {
45 .start = 0x00000000,
46 .size = 0x00000000
47 },
48 .mem3 = {
49 .start = 0x00000000,
50 .size = 0x00000000
51 },
f5fc0f86
LC		 52 },
53
54 [PART_WORK] = {
55 .mem = {
56 .start = 0x00040000,
57 .size = 0x00014fc0
58 },
59 .reg = {
60 .start = REGISTERS_BASE,
451de97a
JO		 61 .size = 0x0000a000
62 },
63 .mem2 = {
64 .start = 0x003004f8,
65 .size = 0x00000004
66 },
67 .mem3 = {
68 .start = 0x00040404,
69 .size = 0x00000000
f5fc0f86
LC		 70 },
71 },
72
73 [PART_DRPW] = {
74 .mem = {
75 .start = 0x00040000,
76 .size = 0x00014fc0
77 },
78 .reg = {
79 .start = DRPW_BASE,
80 .size = 0x00006000
451de97a
JO		 81 },
82 .mem2 = {
83 .start = 0x00000000,
84 .size = 0x00000000
85 },
86 .mem3 = {
87 .start = 0x00000000,
88 .size = 0x00000000
f5fc0f86
LC		 89 }
90 }
91};
92
93static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
94{
95 u32 cpu_ctrl;
96
97 /* 10.5.0 run the firmware (I) */
7b048c52 98 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
f5fc0f86
LC		 99
100 /* 10.5.1 run the firmware (II) */
101 cpu_ctrl |= flag;
7b048c52 102 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
f5fc0f86
LC		 103}
104
4b7fac77
LS		 105static void wl1271_parse_fw_ver(struct wl1271 *wl)
106{
107 int ret;
108
109 ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
110 &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
111 &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
112 &wl->chip.fw_ver[4]);
113
114 if (ret != 5) {
115 wl1271_warning("fw version incorrect value");
116 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
117 return;
118 }
119}
120
f5fc0f86
LC		 121static void wl1271_boot_fw_version(struct wl1271 *wl)
122{
123 struct wl1271_static_data static_data;
124
7b048c52
TP		 125 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
126 false);
f5fc0f86 127
4b7fac77
LS		 128 strncpy(wl->chip.fw_ver_str, static_data.fw_version,
129 sizeof(wl->chip.fw_ver_str));
f5fc0f86
LC		 130
131 /* make sure the string is NULL-terminated */
4b7fac77
LS		 132 wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
133
134 wl1271_parse_fw_ver(wl);
f5fc0f86
LC		 135}
136
137static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
138 size_t fw_data_len, u32 dest)
139{
451de97a 140 struct wl1271_partition_set partition;
f5fc0f86 141 int addr, chunk_num, partition_limit;
1fba4974 142 u8 *p, *chunk;
f5fc0f86
LC		 143
144 /* whal_FwCtrl_LoadFwImageSm() */
145
146 wl1271_debug(DEBUG_BOOT, "starting firmware upload");
147
73d0a13c
LC		 148 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
149 fw_data_len, CHUNK_SIZE);
f5fc0f86 150
f5fc0f86
LC		 151 if ((fw_data_len % 4) != 0) {
152 wl1271_error("firmware length not multiple of four");
153 return -EIO;
154 }
155
1fba4974 156 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
ed317788 157 if (!chunk) {
1fba4974
JO		 158 wl1271_error("allocation for firmware upload chunk failed");
159 return -ENOMEM;
160 }
161
451de97a
JO		 162 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
163 partition.mem.start = dest;
164 wl1271_set_partition(wl, &partition);
f5fc0f86
LC		 165
166 /* 10.1 set partition limit and chunk num */
167 chunk_num = 0;
168 partition_limit = part_table[PART_DOWN].mem.size;
169
170 while (chunk_num < fw_data_len / CHUNK_SIZE) {
171 /* 10.2 update partition, if needed */
172 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
173 if (addr > partition_limit) {
174 addr = dest + chunk_num * CHUNK_SIZE;
175 partition_limit = chunk_num * CHUNK_SIZE +
176 part_table[PART_DOWN].mem.size;
451de97a
JO		 177 partition.mem.start = addr;
178 wl1271_set_partition(wl, &partition);
f5fc0f86
LC		 179 }
180
181 /* 10.3 upload the chunk */
182 addr = dest + chunk_num * CHUNK_SIZE;
183 p = buf + chunk_num * CHUNK_SIZE;
1fba4974 184 memcpy(chunk, p, CHUNK_SIZE);
f5fc0f86
LC		 185 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
186 p, addr);
7b048c52 187 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
f5fc0f86
LC		 188
189 chunk_num++;
190 }
191
192 /* 10.4 upload the last chunk */
193 addr = dest + chunk_num * CHUNK_SIZE;
194 p = buf + chunk_num * CHUNK_SIZE;
1fba4974 195 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
73d0a13c 196 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
f5fc0f86 197 fw_data_len % CHUNK_SIZE, p, addr);
7b048c52 198 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
f5fc0f86 199
1fba4974 200 kfree(chunk);
f5fc0f86
LC		 201 return 0;
202}
203
204static int wl1271_boot_upload_firmware(struct wl1271 *wl)
205{
206 u32 chunks, addr, len;
ed317788 207 int ret = 0;
f5fc0f86
LC		 208 u8 *fw;
209
210 fw = wl->fw;
d0f63b20 211 chunks = be32_to_cpup((__be32 *) fw);
f5fc0f86
LC		 212 fw += sizeof(u32);
213
214 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
215
216 while (chunks--) {
d0f63b20 217 addr = be32_to_cpup((__be32 *) fw);
f5fc0f86 218 fw += sizeof(u32);
d0f63b20 219 len = be32_to_cpup((__be32 *) fw);
f5fc0f86
LC		 220 fw += sizeof(u32);
221
222 if (len > 300000) {
223 wl1271_info("firmware chunk too long: %u", len);
224 return -EINVAL;
225 }
226 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
227 chunks, addr, len);
ed317788
JO		 228 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
229 if (ret != 0)
230 break;
f5fc0f86
LC		 231 fw += len;
232 }
233
ed317788 234 return ret;
f5fc0f86
LC		 235}
236
237static int wl1271_boot_upload_nvs(struct wl1271 *wl)
238{
239 size_t nvs_len, burst_len;
240 int i;
241 u32 dest_addr, val;
152ee6e0 242 u8 *nvs_ptr, *nvs_aligned;
f5fc0f86 243
152ee6e0 244 if (wl->nvs == NULL)
f5fc0f86
LC		 245 return -ENODEV;
246
bc765bf3
SL		 247 if (wl->chip.id == CHIP_ID_1283_PG20) {
248 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
249
250 if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
251 if (nvs->general_params.dual_mode_select)
252 wl->enable_11a = true;
253 } else {
254 wl1271_error("nvs size is not as expected: %zu != %zu",
255 wl->nvs_len,
256 sizeof(struct wl128x_nvs_file));
257 kfree(wl->nvs);
258 wl->nvs = NULL;
259 wl->nvs_len = 0;
260 return -EILSEQ;
261 }
02fabb0e 262
bc765bf3
SL		 263 /* only the first part of the NVS needs to be uploaded */
264 nvs_len = sizeof(nvs->nvs);
265 nvs_ptr = (u8 *)nvs->nvs;
266
267 } else {
268 struct wl1271_nvs_file *nvs =
269 (struct wl1271_nvs_file *)wl->nvs;
270 /*
271 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
272 * band configurations) can be removed when those NVS files stop
273 * floating around.
274 */
275 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
276 wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
277 /* for now 11a is unsupported in AP mode */
278 if (wl->bss_type != BSS_TYPE_AP_BSS &&
279 nvs->general_params.dual_mode_select)
280 wl->enable_11a = true;
281 }
02fabb0e 282
bc765bf3
SL		 283 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
284 (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
285 wl->enable_11a)) {
286 wl1271_error("nvs size is not as expected: %zu != %zu",
287 wl->nvs_len, sizeof(struct wl1271_nvs_file));
288 kfree(wl->nvs);
289 wl->nvs = NULL;
290 wl->nvs_len = 0;
291 return -EILSEQ;
292 }
293
294 /* only the first part of the NVS needs to be uploaded */
295 nvs_len = sizeof(nvs->nvs);
296 nvs_ptr = (u8 *) nvs->nvs;
297 }
f5fc0f86 298
1b72aecd
JO		 299 /* update current MAC address to NVS */
300 nvs_ptr[11] = wl->mac_addr[0];
301 nvs_ptr[10] = wl->mac_addr[1];
302 nvs_ptr[6] = wl->mac_addr[2];
303 nvs_ptr[5] = wl->mac_addr[3];
304 nvs_ptr[4] = wl->mac_addr[4];
305 nvs_ptr[3] = wl->mac_addr[5];
306
f5fc0f86
LC		 307 /*
308 * Layout before the actual NVS tables:
309 * 1 byte : burst length.
310 * 2 bytes: destination address.
311 * n bytes: data to burst copy.
312 *
313 * This is ended by a 0 length, then the NVS tables.
314 */
315
316 /* FIXME: Do we need to check here whether the LSB is 1? */
317 while (nvs_ptr[0]) {
318 burst_len = nvs_ptr[0];
319 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
320
2f63b011
JO		 321 /*
322 * Due to our new wl1271_translate_reg_addr function,
323 * we need to add the REGISTER_BASE to the destination
324 */
f5fc0f86
LC		 325 dest_addr += REGISTERS_BASE;
326
327 /* We move our pointer to the data */
328 nvs_ptr += 3;
329
330 for (i = 0; i < burst_len; i++) {
331 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
332 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
333
334 wl1271_debug(DEBUG_BOOT,
335 "nvs burst write 0x%x: 0x%x",
336 dest_addr, val);
7b048c52 337 wl1271_write32(wl, dest_addr, val);
f5fc0f86
LC		 338
339 nvs_ptr += 4;
340 dest_addr += 4;
341 }
342 }
343
344 /*
345 * We've reached the first zero length, the first NVS table
67e0208a 346 * is located at an aligned offset which is at least 7 bytes further.
bc765bf3
SL		 347 * NOTE: The wl->nvs->nvs element must be first, in order to
348 * simplify the casting, we assume it is at the beginning of
349 * the wl->nvs structure.
f5fc0f86 350 */
bc765bf3
SL		 351 nvs_ptr = (u8 *)wl->nvs +
352 ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
353 nvs_len -= nvs_ptr - (u8 *)wl->nvs;
f5fc0f86 354
f5fc0f86 355 /* Now we must set the partition correctly */
451de97a 356 wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86
LC		 357
358 /* Copy the NVS tables to a new block to ensure alignment */
67e0208a
IY		 359 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
360 if (!nvs_aligned)
361 return -ENOMEM;
f5fc0f86
LC		 362
363 /* And finally we upload the NVS tables */
7b048c52 364 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
f5fc0f86
LC		 365
366 kfree(nvs_aligned);
367 return 0;
368}
369
370static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
371{
54f7e503 372 wl1271_enable_interrupts(wl);
7b048c52
TP		 373 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
374 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
375 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
f5fc0f86
LC		 376}
377
378static int wl1271_boot_soft_reset(struct wl1271 *wl)
379{
380 unsigned long timeout;
381 u32 boot_data;
382
383 /* perform soft reset */
7b048c52 384 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
f5fc0f86
LC		 385
386 /* SOFT_RESET is self clearing */
387 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
388 while (1) {
7b048c52 389 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
f5fc0f86
LC		 390 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
391 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
392 break;
393
394 if (time_after(jiffies, timeout)) {
395 /* 1.2 check pWhalBus->uSelfClearTime if the
396 * timeout was reached */
397 wl1271_error("soft reset timeout");
398 return -1;
399 }
400
401 udelay(SOFT_RESET_STALL_TIME);
402 }
403
404 /* disable Rx/Tx */
7b048c52 405 wl1271_write32(wl, ENABLE, 0x0);
f5fc0f86
LC		 406
407 /* disable auto calibration on start*/
7b048c52 408 wl1271_write32(wl, SPARE_A2, 0xffff);
f5fc0f86
LC		 409
410 return 0;
411}
412
413static int wl1271_boot_run_firmware(struct wl1271 *wl)
414{
415 int loop, ret;
23a7a51c 416 u32 chip_id, intr;
f5fc0f86
LC		 417
418 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
419
7b048c52 420 chip_id = wl1271_read32(wl, CHIP_ID_B);
f5fc0f86
LC		 421
422 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
423
424 if (chip_id != wl->chip.id) {
425 wl1271_error("chip id doesn't match after firmware boot");
426 return -EIO;
427 }
428
429 /* wait for init to complete */
430 loop = 0;
431 while (loop++ < INIT_LOOP) {
432 udelay(INIT_LOOP_DELAY);
23a7a51c 433 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
f5fc0f86 434
23a7a51c 435 if (intr == 0xffffffff) {
f5fc0f86
LC		 436 wl1271_error("error reading hardware complete "
437 "init indication");
438 return -EIO;
439 }
440 /* check that ACX_INTR_INIT_COMPLETE is enabled */
23a7a51c 441 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
7b048c52
TP		 442 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
443 WL1271_ACX_INTR_INIT_COMPLETE);
f5fc0f86
LC		 444 break;
445 }
446 }
447
e7d17cf4 448 if (loop > INIT_LOOP) {
f5fc0f86
LC		 449 wl1271_error("timeout waiting for the hardware to "
450 "complete initialization");
451 return -EIO;
452 }
453
454 /* get hardware config command mail box */
7b048c52 455 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
f5fc0f86
LC		 456
457 /* get hardware config event mail box */
7b048c52 458 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
f5fc0f86
LC		 459
460 /* set the working partition to its "running" mode offset */
451de97a 461 wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86
LC		 462
463 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
464 wl->cmd_box_addr, wl->event_box_addr);
465
466 wl1271_boot_fw_version(wl);
467
468 /*
469 * in case of full asynchronous mode the firmware event must be
470 * ready to receive event from the command mailbox
471 */
472
be823e5b
JO		 473 /* unmask required mbox events */
474 wl->event_mask = BSS_LOSE_EVENT_ID |
19ad0715 475 SCAN_COMPLETE_EVENT_ID |
99d84c1d 476 PS_REPORT_EVENT_ID |
2f826f55 477 JOIN_EVENT_COMPLETE_ID |
00236aed 478 DISCONNECT_EVENT_COMPLETE_ID |
90494a90 479 RSSI_SNR_TRIGGER_0_EVENT_ID |
8d2ef7bd 480 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
6394c01b
LC		 481 SOFT_GEMINI_SENSE_EVENT_ID |
482 PERIODIC_SCAN_REPORT_EVENT_ID |
483 PERIODIC_SCAN_COMPLETE_EVENT_ID;
f5fc0f86 484
203c903c 485 if (wl->bss_type == BSS_TYPE_AP_BSS)
25eaea30 486 wl->event_mask |= STA_REMOVE_COMPLETE_EVENT_ID;
ae47c45f
SL		 487 else
488 wl->event_mask |= DUMMY_PACKET_EVENT_ID;
203c903c 489
f5fc0f86
LC		 490 ret = wl1271_event_unmask(wl);
491 if (ret < 0) {
492 wl1271_error("EVENT mask setting failed");
493 return ret;
494 }
495
496 wl1271_event_mbox_config(wl);
497
498 /* firmware startup completed */
499 return 0;
500}
501
502static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
503{
e8768eeb 504 u32 polarity;
f5fc0f86 505
e8768eeb 506 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
f5fc0f86
LC		 507
508 /* We use HIGH polarity, so unset the LOW bit */
509 polarity &= ~POLARITY_LOW;
e8768eeb 510 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
f5fc0f86
LC		 511
512 return 0;
513}
514
d717fd61
JO		 515static void wl1271_boot_hw_version(struct wl1271 *wl)
516{
517 u32 fuse;
518
519 fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
520 fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
521
522 wl->hw_pg_ver = (s8)fuse;
606ea9fa
IY		 523
524 if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3)
525 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION;
d717fd61
JO		 526}
527
d29633b4 528static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
f5fc0f86 529{
d29633b4 530 u16 spare_reg;
5ea417ae 531
d29633b4
IY		 532 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
533 spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
534 if (spare_reg == 0xFFFF)
535 return -EFAULT;
536 spare_reg |= (BIT(3) | BIT(5) | BIT(6));
537 wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
5ea417ae 538
d29633b4
IY		 539 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
540 wl1271_top_reg_write(wl, SYS_CLK_CFG_REG,
541 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
5ea417ae 542
d29633b4
IY		 543 /* Delay execution for 15msec, to let the HW settle */
544 mdelay(15);
5ea417ae 545
d29633b4
IY		 546 return 0;
547}
5ea417ae 548
d29633b4
IY		 549static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
550{
551 u16 tcxo_detection;
552
553 tcxo_detection = wl1271_top_reg_read(wl, TCXO_CLK_DETECT_REG);
554 if (tcxo_detection & TCXO_DET_FAILED)
555 return false;
5ea417ae 556
d29633b4 557 return true;
5ea417ae
SL		 558}
559
d29633b4 560static bool wl128x_is_fref_valid(struct wl1271 *wl)
5ea417ae 561{
d29633b4 562 u16 fref_detection;
5ea417ae 563
d29633b4
IY		 564 fref_detection = wl1271_top_reg_read(wl, FREF_CLK_DETECT_REG);
565 if (fref_detection & FREF_CLK_DETECT_FAIL)
566 return false;
5ea417ae 567
d29633b4
IY		 568 return true;
569}
5ea417ae 570
d29633b4
IY		 571static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
572{
573 wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
574 wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
575 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL);
5ea417ae 576
d29633b4
IY		 577 return 0;
578}
5ea417ae 579
d29633b4
IY		 580static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
581{
582 u16 spare_reg;
583 u16 pll_config;
584 u8 input_freq;
585
586 /* Mask bits [3:1] in the sys_clk_cfg register */
587 spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
588 if (spare_reg == 0xFFFF)
589 return -EFAULT;
590 spare_reg |= BIT(2);
591 wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
592
593 /* Handle special cases of the TCXO clock */
594 if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
595 wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
596 return wl128x_manually_configure_mcs_pll(wl);
597
598 /* Set the input frequency according to the selected clock source */
599 input_freq = (clk & 1) + 1;
600
601 pll_config = wl1271_top_reg_read(wl, MCS_PLL_CONFIG_REG);
602 if (pll_config == 0xFFFF)
603 return -EFAULT;
604 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
605 pll_config |= MCS_PLL_ENABLE_HP;
606 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
5ea417ae 607
d29633b4
IY		 608 return 0;
609}
610
611/*
612 * WL128x has two clocks input - TCXO and FREF.
613 * TCXO is the main clock of the device, while FREF is used to sync
614 * between the GPS and the cellular modem.
615 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
616 * as the WLAN/BT main clock.
617 */
618static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
619{
620 u16 sys_clk_cfg;
621
622 /* For XTAL-only modes, FREF will be used after switching from TCXO */
623 if (wl->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
624 wl->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
625 if (!wl128x_switch_tcxo_to_fref(wl))
626 return -EINVAL;
627 goto fref_clk;
5ea417ae
SL		 628 }
629
d29633b4
IY		 630 /* Query the HW, to determine which clock source we should use */
631 sys_clk_cfg = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG);
632 if (sys_clk_cfg == 0xFFFF)
633 return -EINVAL;
634 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
635 goto fref_clk;
636
637 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
638 if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
639 wl->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
640 if (!wl128x_switch_tcxo_to_fref(wl))
641 return -EINVAL;
642 goto fref_clk;
643 }
644
645 /* TCXO clock is selected */
646 if (!wl128x_is_tcxo_valid(wl))
647 return -EINVAL;
648 *selected_clock = wl->tcxo_clock;
649 goto config_mcs_pll;
650
651fref_clk:
652 /* FREF clock is selected */
653 if (!wl128x_is_fref_valid(wl))
654 return -EINVAL;
655 *selected_clock = wl->ref_clock;
656
657config_mcs_pll:
658 return wl128x_configure_mcs_pll(wl, *selected_clock);
5ea417ae
SL		 659}
660
661static int wl127x_boot_clk(struct wl1271 *wl)
662{
663 u32 pause;
664 u32 clk;
f5fc0f86 665
d717fd61
JO		 666 wl1271_boot_hw_version(wl);
667
5ea417ae
SL		 668 if (wl->ref_clock == CONF_REF_CLK_19_2_E ||
669 wl->ref_clock == CONF_REF_CLK_38_4_E ||
670 wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
284134eb 671 /* ref clk: 19.2/38.4/38.4-XTAL */
f5fc0f86 672 clk = 0x3;
5ea417ae
SL		 673 else if (wl->ref_clock == CONF_REF_CLK_26_E ||
674 wl->ref_clock == CONF_REF_CLK_52_E)
f5fc0f86
LC		 675 /* ref clk: 26/52 */
676 clk = 0x5;
15cea993
OBC		 677 else
678 return -EINVAL;
f5fc0f86 679
5ea417ae 680 if (wl->ref_clock != CONF_REF_CLK_19_2_E) {
284134eb 681 u16 val;
9d4e5bb3 682 /* Set clock type (open drain) */
284134eb
JO		 683 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
684 val &= FREF_CLK_TYPE_BITS;
284134eb 685 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
9d4e5bb3
JO		 686
687 /* Set clock pull mode (no pull) */
688 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
689 val |= NO_PULL;
690 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
284134eb
JO		 691 } else {
692 u16 val;
693 /* Set clock polarity */
694 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
695 val &= FREF_CLK_POLARITY_BITS;
696 val |= CLK_REQ_OUTN_SEL;
697 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
698 }
699
7b048c52 700 wl1271_write32(wl, PLL_PARAMETERS, clk);
f5fc0f86 701
7b048c52 702 pause = wl1271_read32(wl, PLL_PARAMETERS);
f5fc0f86
LC		 703
704 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
705
2f63b011 706 pause &= ~(WU_COUNTER_PAUSE_VAL);
f5fc0f86 707 pause |= WU_COUNTER_PAUSE_VAL;
7b048c52 708 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
f5fc0f86 709
5ea417ae
SL		 710 return 0;
711}
712
713/* uploads NVS and firmware */
714int wl1271_load_firmware(struct wl1271 *wl)
715{
716 int ret = 0;
717 u32 tmp, clk;
d29633b4 718 int selected_clock = -1;
5ea417ae
SL		 719
720 if (wl->chip.id == CHIP_ID_1283_PG20) {
d29633b4 721 ret = wl128x_boot_clk(wl, &selected_clock);
5ea417ae
SL		 722 if (ret < 0)
723 goto out;
724 } else {
725 ret = wl127x_boot_clk(wl);
726 if (ret < 0)
727 goto out;
728 }
729
f5fc0f86 730 /* Continue the ELP wake up sequence */
7b048c52 731 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
f5fc0f86
LC		 732 udelay(500);
733
451de97a 734 wl1271_set_partition(wl, &part_table[PART_DRPW]);
f5fc0f86
LC		 735
736 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
737 to be used by DRPw FW. The RTRIM value will be added by the FW
738 before taking DRPw out of reset */
739
740 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
7b048c52 741 clk = wl1271_read32(wl, DRPW_SCRATCH_START);
f5fc0f86
LC		 742
743 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
744
5ea417ae 745 if (wl->chip.id == CHIP_ID_1283_PG20) {
d29633b4 746 clk |= ((selected_clock & 0x3) << 1) << 4;
5ea417ae
SL		 747 } else {
748 clk |= (wl->ref_clock << 1) << 4;
749 }
750
7b048c52 751 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
f5fc0f86 752
451de97a 753 wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86
LC		 754
755 /* Disable interrupts */
7b048c52 756 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
f5fc0f86
LC		 757
758 ret = wl1271_boot_soft_reset(wl);
759 if (ret < 0)
760 goto out;
761
762 /* 2. start processing NVS file */
763 ret = wl1271_boot_upload_nvs(wl);
764 if (ret < 0)
765 goto out;
766
767 /* write firmware's last address (ie. it's length) to
768 * ACX_EEPROMLESS_IND_REG */
769 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
770
7b048c52 771 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
f5fc0f86 772
7b048c52 773 tmp = wl1271_read32(wl, CHIP_ID_B);
f5fc0f86
LC		 774
775 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
776
777 /* 6. read the EEPROM parameters */
7b048c52 778 tmp = wl1271_read32(wl, SCR_PAD2);
f5fc0f86 779
f5fc0f86
LC		 780 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
781 * to upload_fw) */
782
5ea417ae 783 if (wl->chip.id == CHIP_ID_1283_PG20)
afb7d3cd 784 wl1271_top_reg_write(wl, SDIO_IO_DS, wl->conf.hci_io_ds);
5ea417ae 785
f5fc0f86
LC		 786 ret = wl1271_boot_upload_firmware(wl);
787 if (ret < 0)
788 goto out;
789
870c367c
RQ		 790out:
791 return ret;
792}
793EXPORT_SYMBOL_GPL(wl1271_load_firmware);
794
795int wl1271_boot(struct wl1271 *wl)
796{
797 int ret;
798
799 /* upload NVS and firmware */
800 ret = wl1271_load_firmware(wl);
801 if (ret)
802 return ret;
803
f5fc0f86
LC		 804 /* 10.5 start firmware */
805 ret = wl1271_boot_run_firmware(wl);
806 if (ret < 0)
807 goto out;
808
b9b0fdea
SL		 809 ret = wl1271_boot_write_irq_polarity(wl);
810 if (ret < 0)
811 goto out;
812
813 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
814 WL1271_ACX_ALL_EVENTS_VECTOR);
815
eb5b28d0
JO		 816 /* Enable firmware interrupts now */
817 wl1271_boot_enable_interrupts(wl);
818
f5fc0f86 819 /* set the wl1271 default filters */
ae113b57 820 wl1271_set_default_filters(wl);
f5fc0f86
LC		 821
822 wl1271_event_mbox_config(wl);
823
824out:
825 return ret;
826}
Linux kernel - Deliverables
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