Commit | Line | Data |
---|---|---|
2f01a1f5 | 1 | /* |
80301cdc | 2 | * This file is part of wl1251 |
2f01a1f5 KV |
3 | * |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * | |
6 | * Contact: Kalle Valo <kalle.valo@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/gpio.h> | |
25 | ||
29d904c4 | 26 | #include "wl1251_reg.h" |
ef2f8d45 | 27 | #include "wl1251_boot.h" |
0764de64 | 28 | #include "wl1251_io.h" |
08d9f572 | 29 | #include "wl1251_spi.h" |
ef2f8d45 | 30 | #include "wl1251_event.h" |
0e71bb08 | 31 | #include "wl1251_acx.h" |
2f01a1f5 | 32 | |
80301cdc | 33 | void wl1251_boot_target_enable_interrupts(struct wl1251 *wl) |
2f01a1f5 | 34 | { |
80301cdc KV |
35 | wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask)); |
36 | wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL); | |
2f01a1f5 KV |
37 | } |
38 | ||
80301cdc | 39 | int wl1251_boot_soft_reset(struct wl1251 *wl) |
2f01a1f5 KV |
40 | { |
41 | unsigned long timeout; | |
42 | u32 boot_data; | |
43 | ||
44 | /* perform soft reset */ | |
80301cdc | 45 | wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); |
2f01a1f5 KV |
46 | |
47 | /* SOFT_RESET is self clearing */ | |
48 | timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); | |
49 | while (1) { | |
80301cdc KV |
50 | boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET); |
51 | wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); | |
2f01a1f5 KV |
52 | if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) |
53 | break; | |
54 | ||
55 | if (time_after(jiffies, timeout)) { | |
56 | /* 1.2 check pWhalBus->uSelfClearTime if the | |
57 | * timeout was reached */ | |
80301cdc | 58 | wl1251_error("soft reset timeout"); |
2f01a1f5 KV |
59 | return -1; |
60 | } | |
61 | ||
62 | udelay(SOFT_RESET_STALL_TIME); | |
63 | } | |
64 | ||
65 | /* disable Rx/Tx */ | |
80301cdc | 66 | wl1251_reg_write32(wl, ENABLE, 0x0); |
2f01a1f5 KV |
67 | |
68 | /* disable auto calibration on start*/ | |
80301cdc | 69 | wl1251_reg_write32(wl, SPARE_A2, 0xffff); |
2f01a1f5 KV |
70 | |
71 | return 0; | |
72 | } | |
73 | ||
80301cdc | 74 | int wl1251_boot_init_seq(struct wl1251 *wl) |
2f01a1f5 KV |
75 | { |
76 | u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq; | |
77 | ||
78 | /* | |
79 | * col #1: INTEGER_DIVIDER | |
80 | * col #2: FRACTIONAL_DIVIDER | |
81 | * col #3: ATTN_BB | |
82 | * col #4: ALPHA_BB | |
83 | * col #5: STOP_TIME_BB | |
84 | * col #6: BB_PLL_LOOP_FILTER | |
85 | */ | |
86 | static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = { | |
87 | ||
88 | { 83, 87381, 0xB, 5, 0xF00, 3}, /* REF_FREQ_19_2*/ | |
89 | { 61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/ | |
90 | { 41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/ | |
91 | { 40, 0, 0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/ | |
92 | { 47, 162280, 0xC, 6, 0x2760, 1} /* REF_FREQ_33_6 */ | |
93 | }; | |
94 | ||
95 | /* read NVS params */ | |
80301cdc KV |
96 | scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6); |
97 | wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6); | |
2f01a1f5 KV |
98 | |
99 | /* read ELP_CMD */ | |
80301cdc KV |
100 | elp_cmd = wl1251_reg_read32(wl, ELP_CMD); |
101 | wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd); | |
2f01a1f5 KV |
102 | |
103 | /* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */ | |
104 | ref_freq = scr_pad6 & 0x000000FF; | |
80301cdc | 105 | wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq); |
2f01a1f5 | 106 | |
80301cdc | 107 | wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9); |
2f01a1f5 KV |
108 | |
109 | /* | |
110 | * PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME) | |
111 | */ | |
80301cdc | 112 | wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6); |
2f01a1f5 KV |
113 | |
114 | /* | |
115 | * set the clock detect feature to work in the restart wu procedure | |
116 | * (ELP_CFG_MODE[14]) and Select the clock source type | |
117 | * (ELP_CFG_MODE[13:12]) | |
118 | */ | |
119 | tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000; | |
80301cdc | 120 | wl1251_reg_write32(wl, ELP_CFG_MODE, tmp); |
2f01a1f5 KV |
121 | |
122 | /* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */ | |
123 | elp_cmd |= 0x00000040; | |
80301cdc | 124 | wl1251_reg_write32(wl, ELP_CMD, elp_cmd); |
2f01a1f5 KV |
125 | |
126 | /* PG 1.2: Set the BB PLL stable time to be 1000usec | |
127 | * (PLL_STABLE_TIME) */ | |
80301cdc | 128 | wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20); |
2f01a1f5 KV |
129 | |
130 | /* PG 1.2: read clock request time */ | |
80301cdc | 131 | init_data = wl1251_reg_read32(wl, CLK_REQ_TIME); |
2f01a1f5 KV |
132 | |
133 | /* | |
134 | * PG 1.2: set the clock request time to be ref_clk_settling_time - | |
135 | * 1ms = 4ms | |
136 | */ | |
137 | if (init_data > 0x21) | |
138 | tmp = init_data - 0x21; | |
139 | else | |
140 | tmp = 0; | |
80301cdc | 141 | wl1251_reg_write32(wl, CLK_REQ_TIME, tmp); |
2f01a1f5 KV |
142 | |
143 | /* set BB PLL configurations in RF AFE */ | |
80301cdc | 144 | wl1251_reg_write32(wl, 0x003058cc, 0x4B5); |
2f01a1f5 KV |
145 | |
146 | /* set RF_AFE_REG_5 */ | |
80301cdc | 147 | wl1251_reg_write32(wl, 0x003058d4, 0x50); |
2f01a1f5 KV |
148 | |
149 | /* set RF_AFE_CTRL_REG_2 */ | |
80301cdc | 150 | wl1251_reg_write32(wl, 0x00305948, 0x11c001); |
2f01a1f5 KV |
151 | |
152 | /* | |
153 | * change RF PLL and BB PLL divider for VCO clock and adjust VCO | |
154 | * bais current(RF_AFE_REG_13) | |
155 | */ | |
80301cdc | 156 | wl1251_reg_write32(wl, 0x003058f4, 0x1e); |
2f01a1f5 KV |
157 | |
158 | /* set BB PLL configurations */ | |
159 | tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; | |
80301cdc | 160 | wl1251_reg_write32(wl, 0x00305840, tmp); |
2f01a1f5 KV |
161 | |
162 | /* set fractional divider according to Appendix C-BB PLL | |
163 | * Calculations | |
164 | */ | |
165 | tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; | |
80301cdc | 166 | wl1251_reg_write32(wl, 0x00305844, tmp); |
2f01a1f5 KV |
167 | |
168 | /* set the initial data for the sigma delta */ | |
80301cdc | 169 | wl1251_reg_write32(wl, 0x00305848, 0x3039); |
2f01a1f5 KV |
170 | |
171 | /* | |
172 | * set the accumulator attenuation value, calibration loop1 | |
173 | * (alpha), calibration loop2 (beta), calibration loop3 (gamma) and | |
174 | * the VCO gain | |
175 | */ | |
176 | tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) | | |
177 | (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1; | |
80301cdc | 178 | wl1251_reg_write32(wl, 0x00305854, tmp); |
2f01a1f5 KV |
179 | |
180 | /* | |
181 | * set the calibration stop time after holdoff time expires and set | |
182 | * settling time HOLD_OFF_TIME_BB | |
183 | */ | |
184 | tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000; | |
80301cdc | 185 | wl1251_reg_write32(wl, 0x00305858, tmp); |
2f01a1f5 KV |
186 | |
187 | /* | |
188 | * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL | |
189 | * constant leakage current to linearize PFD to 0uA - | |
190 | * BB_ILOOPF[7:3] | |
191 | */ | |
192 | tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030; | |
80301cdc | 193 | wl1251_reg_write32(wl, 0x003058f8, tmp); |
2f01a1f5 KV |
194 | |
195 | /* | |
196 | * set regulator output voltage for n divider to | |
197 | * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2], | |
198 | * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB | |
199 | * PLL auto-call to normal mode- BB_CALGAIN_3DB[8] | |
200 | */ | |
80301cdc | 201 | wl1251_reg_write32(wl, 0x003058f0, 0x29); |
2f01a1f5 KV |
202 | |
203 | /* enable restart wakeup sequence (ELP_CMD[0]) */ | |
80301cdc | 204 | wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1); |
2f01a1f5 KV |
205 | |
206 | /* restart sequence completed */ | |
207 | udelay(2000); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
0e71bb08 KV |
212 | static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag) |
213 | { | |
214 | u32 cpu_ctrl; | |
215 | ||
216 | /* 10.5.0 run the firmware (I) */ | |
217 | cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL); | |
218 | ||
219 | /* 10.5.1 run the firmware (II) */ | |
220 | cpu_ctrl &= ~flag; | |
221 | wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); | |
222 | } | |
223 | ||
80301cdc | 224 | int wl1251_boot_run_firmware(struct wl1251 *wl) |
2f01a1f5 KV |
225 | { |
226 | int loop, ret; | |
227 | u32 chip_id, interrupt; | |
228 | ||
0e71bb08 | 229 | wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); |
2f01a1f5 | 230 | |
80301cdc | 231 | chip_id = wl1251_reg_read32(wl, CHIP_ID_B); |
2f01a1f5 | 232 | |
80301cdc | 233 | wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); |
2f01a1f5 | 234 | |
0e71bb08 | 235 | if (chip_id != wl->chip_id) { |
80301cdc | 236 | wl1251_error("chip id doesn't match after firmware boot"); |
2f01a1f5 KV |
237 | return -EIO; |
238 | } | |
239 | ||
240 | /* wait for init to complete */ | |
241 | loop = 0; | |
242 | while (loop++ < INIT_LOOP) { | |
243 | udelay(INIT_LOOP_DELAY); | |
80301cdc | 244 | interrupt = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); |
2f01a1f5 KV |
245 | |
246 | if (interrupt == 0xffffffff) { | |
80301cdc | 247 | wl1251_error("error reading hardware complete " |
2f01a1f5 KV |
248 | "init indication"); |
249 | return -EIO; | |
250 | } | |
251 | /* check that ACX_INTR_INIT_COMPLETE is enabled */ | |
0e71bb08 | 252 | else if (interrupt & WL1251_ACX_INTR_INIT_COMPLETE) { |
80301cdc | 253 | wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK, |
0e71bb08 | 254 | WL1251_ACX_INTR_INIT_COMPLETE); |
2f01a1f5 KV |
255 | break; |
256 | } | |
257 | } | |
258 | ||
e8a4a6df | 259 | if (loop > INIT_LOOP) { |
80301cdc | 260 | wl1251_error("timeout waiting for the hardware to " |
2f01a1f5 KV |
261 | "complete initialization"); |
262 | return -EIO; | |
263 | } | |
264 | ||
265 | /* get hardware config command mail box */ | |
80301cdc | 266 | wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR); |
2f01a1f5 KV |
267 | |
268 | /* get hardware config event mail box */ | |
80301cdc | 269 | wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR); |
2f01a1f5 KV |
270 | |
271 | /* set the working partition to its "running" mode offset */ | |
0e71bb08 KV |
272 | wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START, |
273 | WL1251_PART_WORK_MEM_SIZE, | |
274 | WL1251_PART_WORK_REG_START, | |
275 | WL1251_PART_WORK_REG_SIZE); | |
2f01a1f5 | 276 | |
80301cdc | 277 | wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x", |
2f01a1f5 KV |
278 | wl->cmd_box_addr, wl->event_box_addr); |
279 | ||
0e71bb08 | 280 | wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver)); |
0d1c3839 | 281 | |
2f01a1f5 KV |
282 | /* |
283 | * in case of full asynchronous mode the firmware event must be | |
284 | * ready to receive event from the command mailbox | |
285 | */ | |
286 | ||
287 | /* enable gpio interrupts */ | |
b5ed9c1b | 288 | wl1251_enable_interrupts(wl); |
2f01a1f5 | 289 | |
0e71bb08 KV |
290 | /* Enable target's interrupts */ |
291 | wl->intr_mask = WL1251_ACX_INTR_RX0_DATA | | |
292 | WL1251_ACX_INTR_RX1_DATA | | |
293 | WL1251_ACX_INTR_TX_RESULT | | |
294 | WL1251_ACX_INTR_EVENT_A | | |
295 | WL1251_ACX_INTR_EVENT_B | | |
296 | WL1251_ACX_INTR_INIT_COMPLETE; | |
297 | wl1251_boot_target_enable_interrupts(wl); | |
2f01a1f5 | 298 | |
a1590f24 JY |
299 | wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID | |
300 | SYNCHRONIZATION_TIMEOUT_EVENT_ID | | |
301 | ROAMING_TRIGGER_LOW_RSSI_EVENT_ID | | |
302 | ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID | | |
303 | REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID | | |
304 | BT_PTA_PREDICTION_EVENT_ID; | |
2f01a1f5 | 305 | |
80301cdc | 306 | ret = wl1251_event_unmask(wl); |
2f01a1f5 | 307 | if (ret < 0) { |
80301cdc | 308 | wl1251_error("EVENT mask setting failed"); |
2f01a1f5 KV |
309 | return ret; |
310 | } | |
311 | ||
80301cdc | 312 | wl1251_event_mbox_config(wl); |
2f01a1f5 KV |
313 | |
314 | /* firmware startup completed */ | |
315 | return 0; | |
316 | } | |
0e71bb08 KV |
317 | |
318 | static int wl1251_boot_upload_firmware(struct wl1251 *wl) | |
319 | { | |
320 | int addr, chunk_num, partition_limit; | |
c74ddfd5 KV |
321 | size_t fw_data_len, len; |
322 | u8 *p, *buf; | |
0e71bb08 KV |
323 | |
324 | /* whal_FwCtrl_LoadFwImageSm() */ | |
325 | ||
326 | wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x", | |
327 | wl1251_reg_read32(wl, CHIP_ID_B)); | |
328 | ||
329 | /* 10.0 check firmware length and set partition */ | |
330 | fw_data_len = (wl->fw[4] << 24) | (wl->fw[5] << 16) | | |
331 | (wl->fw[6] << 8) | (wl->fw[7]); | |
332 | ||
333 | wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len, | |
334 | CHUNK_SIZE); | |
335 | ||
336 | if ((fw_data_len % 4) != 0) { | |
337 | wl1251_error("firmware length not multiple of four"); | |
338 | return -EIO; | |
339 | } | |
340 | ||
c74ddfd5 KV |
341 | buf = kmalloc(CHUNK_SIZE, GFP_KERNEL); |
342 | if (!buf) { | |
343 | wl1251_error("allocation for firmware upload chunk failed"); | |
344 | return -ENOMEM; | |
345 | } | |
346 | ||
0e71bb08 KV |
347 | wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START, |
348 | WL1251_PART_DOWN_MEM_SIZE, | |
349 | WL1251_PART_DOWN_REG_START, | |
350 | WL1251_PART_DOWN_REG_SIZE); | |
351 | ||
352 | /* 10.1 set partition limit and chunk num */ | |
353 | chunk_num = 0; | |
354 | partition_limit = WL1251_PART_DOWN_MEM_SIZE; | |
355 | ||
356 | while (chunk_num < fw_data_len / CHUNK_SIZE) { | |
357 | /* 10.2 update partition, if needed */ | |
358 | addr = WL1251_PART_DOWN_MEM_START + | |
359 | (chunk_num + 2) * CHUNK_SIZE; | |
360 | if (addr > partition_limit) { | |
361 | addr = WL1251_PART_DOWN_MEM_START + | |
362 | chunk_num * CHUNK_SIZE; | |
363 | partition_limit = chunk_num * CHUNK_SIZE + | |
364 | WL1251_PART_DOWN_MEM_SIZE; | |
365 | wl1251_set_partition(wl, | |
366 | addr, | |
367 | WL1251_PART_DOWN_MEM_SIZE, | |
368 | WL1251_PART_DOWN_REG_START, | |
369 | WL1251_PART_DOWN_REG_SIZE); | |
370 | } | |
371 | ||
372 | /* 10.3 upload the chunk */ | |
373 | addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE; | |
374 | p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; | |
375 | wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", | |
376 | p, addr); | |
c74ddfd5 KV |
377 | |
378 | /* need to copy the chunk for dma */ | |
379 | len = CHUNK_SIZE; | |
380 | memcpy(buf, p, len); | |
381 | wl1251_mem_write(wl, addr, buf, len); | |
0e71bb08 KV |
382 | |
383 | chunk_num++; | |
384 | } | |
385 | ||
386 | /* 10.4 upload the last chunk */ | |
387 | addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE; | |
388 | p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; | |
c74ddfd5 KV |
389 | |
390 | /* need to copy the chunk for dma */ | |
391 | len = fw_data_len % CHUNK_SIZE; | |
392 | memcpy(buf, p, len); | |
393 | ||
0e71bb08 | 394 | wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x", |
c74ddfd5 KV |
395 | len, p, addr); |
396 | wl1251_mem_write(wl, addr, buf, len); | |
397 | ||
398 | kfree(buf); | |
0e71bb08 KV |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
403 | static int wl1251_boot_upload_nvs(struct wl1251 *wl) | |
404 | { | |
405 | size_t nvs_len, nvs_bytes_written, burst_len; | |
406 | int nvs_start, i; | |
407 | u32 dest_addr, val; | |
408 | u8 *nvs_ptr, *nvs; | |
409 | ||
410 | nvs = wl->nvs; | |
411 | if (nvs == NULL) | |
412 | return -ENODEV; | |
413 | ||
414 | nvs_ptr = nvs; | |
415 | ||
416 | nvs_len = wl->nvs_len; | |
417 | nvs_start = wl->fw_len; | |
418 | ||
419 | /* | |
420 | * Layout before the actual NVS tables: | |
421 | * 1 byte : burst length. | |
422 | * 2 bytes: destination address. | |
423 | * n bytes: data to burst copy. | |
424 | * | |
425 | * This is ended by a 0 length, then the NVS tables. | |
426 | */ | |
427 | ||
428 | while (nvs_ptr[0]) { | |
429 | burst_len = nvs_ptr[0]; | |
430 | dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8)); | |
431 | ||
432 | /* We move our pointer to the data */ | |
433 | nvs_ptr += 3; | |
434 | ||
435 | for (i = 0; i < burst_len; i++) { | |
436 | val = (nvs_ptr[0] | (nvs_ptr[1] << 8) | |
437 | | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); | |
438 | ||
439 | wl1251_debug(DEBUG_BOOT, | |
440 | "nvs burst write 0x%x: 0x%x", | |
441 | dest_addr, val); | |
442 | wl1251_mem_write32(wl, dest_addr, val); | |
443 | ||
444 | nvs_ptr += 4; | |
445 | dest_addr += 4; | |
446 | } | |
447 | } | |
448 | ||
449 | /* | |
450 | * We've reached the first zero length, the first NVS table | |
451 | * is 7 bytes further. | |
452 | */ | |
453 | nvs_ptr += 7; | |
454 | nvs_len -= nvs_ptr - nvs; | |
455 | nvs_len = ALIGN(nvs_len, 4); | |
456 | ||
457 | /* Now we must set the partition correctly */ | |
458 | wl1251_set_partition(wl, nvs_start, | |
459 | WL1251_PART_DOWN_MEM_SIZE, | |
460 | WL1251_PART_DOWN_REG_START, | |
461 | WL1251_PART_DOWN_REG_SIZE); | |
462 | ||
463 | /* And finally we upload the NVS tables */ | |
464 | nvs_bytes_written = 0; | |
465 | while (nvs_bytes_written < nvs_len) { | |
466 | val = (nvs_ptr[0] | (nvs_ptr[1] << 8) | |
467 | | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); | |
468 | ||
469 | val = cpu_to_le32(val); | |
470 | ||
471 | wl1251_debug(DEBUG_BOOT, | |
472 | "nvs write table 0x%x: 0x%x", | |
473 | nvs_start, val); | |
474 | wl1251_mem_write32(wl, nvs_start, val); | |
475 | ||
476 | nvs_ptr += 4; | |
477 | nvs_bytes_written += 4; | |
478 | nvs_start += 4; | |
479 | } | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | int wl1251_boot(struct wl1251 *wl) | |
485 | { | |
486 | int ret = 0, minor_minor_e2_ver; | |
487 | u32 tmp, boot_data; | |
488 | ||
bcd64e0c BC |
489 | /* halt embedded ARM CPU while loading firmware */ |
490 | wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT); | |
491 | ||
0e71bb08 KV |
492 | ret = wl1251_boot_soft_reset(wl); |
493 | if (ret < 0) | |
494 | goto out; | |
495 | ||
496 | /* 2. start processing NVS file */ | |
c95cf3d0 DJW |
497 | if (wl->use_eeprom) { |
498 | wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR); | |
499 | msleep(4000); | |
500 | wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM); | |
501 | } else { | |
502 | ret = wl1251_boot_upload_nvs(wl); | |
503 | if (ret < 0) | |
504 | goto out; | |
505 | ||
506 | /* write firmware's last address (ie. it's length) to | |
507 | * ACX_EEPROMLESS_IND_REG */ | |
508 | wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len); | |
509 | } | |
0e71bb08 KV |
510 | |
511 | /* 6. read the EEPROM parameters */ | |
512 | tmp = wl1251_reg_read32(wl, SCR_PAD2); | |
513 | ||
514 | /* 7. read bootdata */ | |
515 | wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8; | |
516 | wl->boot_attr.major = (tmp & 0x00FF0000) >> 16; | |
517 | tmp = wl1251_reg_read32(wl, SCR_PAD3); | |
518 | ||
519 | /* 8. check bootdata and call restart sequence */ | |
520 | wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16; | |
521 | minor_minor_e2_ver = (tmp & 0xFF000000) >> 24; | |
522 | ||
523 | wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x " | |
524 | "minorE2Ver 0x%x minor_minor_e2_ver 0x%x", | |
525 | wl->boot_attr.radio_type, wl->boot_attr.major, | |
526 | wl->boot_attr.minor, minor_minor_e2_ver); | |
527 | ||
528 | ret = wl1251_boot_init_seq(wl); | |
529 | if (ret < 0) | |
530 | goto out; | |
531 | ||
532 | /* 9. NVS processing done */ | |
533 | boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL); | |
534 | ||
535 | wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data); | |
536 | ||
537 | /* 10. check that ECPU_CONTROL_HALT bits are set in | |
538 | * pWhalBus->uBootData and start uploading firmware | |
539 | */ | |
540 | if ((boot_data & ECPU_CONTROL_HALT) == 0) { | |
541 | wl1251_error("boot failed, ECPU_CONTROL_HALT not set"); | |
542 | ret = -EIO; | |
543 | goto out; | |
544 | } | |
545 | ||
546 | ret = wl1251_boot_upload_firmware(wl); | |
547 | if (ret < 0) | |
548 | goto out; | |
549 | ||
550 | /* 10.5 start firmware */ | |
551 | ret = wl1251_boot_run_firmware(wl); | |
552 | if (ret < 0) | |
553 | goto out; | |
554 | ||
555 | out: | |
556 | return ret; | |
557 | } |