[deliverable/linux.git] / drivers / net / wireless / wl12xx / wl1271_boot.c

/*
 * This file is part of wl1271
 *
 * Copyright (C) 2008-2010 Nokia Corporation
 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/gpio.h>
#include <linux/slab.h>

#include "wl1271_acx.h"
#include "wl1271_reg.h"
#include "wl1271_boot.h"
#include "wl1271_io.h"
#include "wl1271_event.h"

static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
	[PART_DOWN] = {
		.mem = {
			.start = 0x00000000,
			.size  = 0x000177c0
		},
		.reg = {
			.start = REGISTERS_BASE,
			.size  = 0x00008800
		},
		.mem2 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
		.mem3 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
	},

	[PART_WORK] = {
		.mem = {
			.start = 0x00040000,
			.size  = 0x00014fc0
		},
		.reg = {
			.start = REGISTERS_BASE,
			.size  = 0x0000a000
		},
		.mem2 = {
			.start = 0x003004f8,
			.size  = 0x00000004
		},
		.mem3 = {
			.start = 0x00040404,
			.size  = 0x00000000
		},
	},

	[PART_DRPW] = {
		.mem = {
			.start = 0x00040000,
			.size  = 0x00014fc0
		},
		.reg = {
			.start = DRPW_BASE,
			.size  = 0x00006000
		},
		.mem2 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
		.mem3 = {
			.start = 0x00000000,
			.size  = 0x00000000
		}
	}
};

static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
{
	u32 cpu_ctrl;

	/* 10.5.0 run the firmware (I) */
	cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);

	/* 10.5.1 run the firmware (II) */
	cpu_ctrl |= flag;
	wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
}

static void wl1271_boot_fw_version(struct wl1271 *wl)
{
	struct wl1271_static_data static_data;

	wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
		    false);

	strncpy(wl->chip.fw_ver, static_data.fw_version,
		sizeof(wl->chip.fw_ver));

	/* make sure the string is NULL-terminated */
	wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
}

static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
					     size_t fw_data_len, u32 dest)
{
	struct wl1271_partition_set partition;
	int addr, chunk_num, partition_limit;
	u8 *p, *chunk;

	/* whal_FwCtrl_LoadFwImageSm() */

	wl1271_debug(DEBUG_BOOT, "starting firmware upload");

	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
		     fw_data_len, CHUNK_SIZE);

	if ((fw_data_len % 4) != 0) {
		wl1271_error("firmware length not multiple of four");
		return -EIO;
	}

	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	if (!chunk) {
		wl1271_error("allocation for firmware upload chunk failed");
		return -ENOMEM;
	}

	memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
	partition.mem.start = dest;
	wl1271_set_partition(wl, &partition);

	/* 10.1 set partition limit and chunk num */
	chunk_num = 0;
	partition_limit = part_table[PART_DOWN].mem.size;

	while (chunk_num < fw_data_len / CHUNK_SIZE) {
		/* 10.2 update partition, if needed */
		addr = dest + (chunk_num + 2) * CHUNK_SIZE;
		if (addr > partition_limit) {
			addr = dest + chunk_num * CHUNK_SIZE;
			partition_limit = chunk_num * CHUNK_SIZE +
				part_table[PART_DOWN].mem.size;
			partition.mem.start = addr;
			wl1271_set_partition(wl, &partition);
		}

		/* 10.3 upload the chunk */
		addr = dest + chunk_num * CHUNK_SIZE;
		p = buf + chunk_num * CHUNK_SIZE;
		memcpy(chunk, p, CHUNK_SIZE);
		wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
			     p, addr);
		wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);

		chunk_num++;
	}

	/* 10.4 upload the last chunk */
	addr = dest + chunk_num * CHUNK_SIZE;
	p = buf + chunk_num * CHUNK_SIZE;
	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
		     fw_data_len % CHUNK_SIZE, p, addr);
	wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);

	kfree(chunk);
	return 0;
}

static int wl1271_boot_upload_firmware(struct wl1271 *wl)
{
	u32 chunks, addr, len;
	int ret = 0;
	u8 *fw;

	fw = wl->fw;
	chunks = be32_to_cpup((__be32 *) fw);
	fw += sizeof(u32);

	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);

	while (chunks--) {
		addr = be32_to_cpup((__be32 *) fw);
		fw += sizeof(u32);
		len = be32_to_cpup((__be32 *) fw);
		fw += sizeof(u32);

		if (len > 300000) {
			wl1271_info("firmware chunk too long: %u", len);
			return -EINVAL;
		}
		wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
			     chunks, addr, len);
		ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
		if (ret != 0)
			break;
		fw += len;
	}

	return ret;
}

static int wl1271_boot_upload_nvs(struct wl1271 *wl)
{
	size_t nvs_len, burst_len;
	int i;
	u32 dest_addr, val;
	u8 *nvs_ptr, *nvs_aligned;

	if (wl->nvs == NULL)
		return -ENODEV;

	/*
	 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz band
	 * configurations) can be removed when those NVS files stop floating
	 * around.
	 */
	if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
	    wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
		if (wl->nvs->general_params.dual_mode_select)
			wl->enable_11a = true;
	}

	if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
	    (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
	     wl->enable_11a)) {
		wl1271_error("nvs size is not as expected: %zu != %zu",
			     wl->nvs_len, sizeof(struct wl1271_nvs_file));
		kfree(wl->nvs);
		wl->nvs = NULL;
		wl->nvs_len = 0;
		return -EILSEQ;
	}

	/* only the first part of the NVS needs to be uploaded */
	nvs_len = sizeof(wl->nvs->nvs);
	nvs_ptr = (u8 *)wl->nvs->nvs;

	/* update current MAC address to NVS */
	nvs_ptr[11] = wl->mac_addr[0];
	nvs_ptr[10] = wl->mac_addr[1];
	nvs_ptr[6] = wl->mac_addr[2];
	nvs_ptr[5] = wl->mac_addr[3];
	nvs_ptr[4] = wl->mac_addr[4];
	nvs_ptr[3] = wl->mac_addr[5];

	/*
	 * Layout before the actual NVS tables:
	 * 1 byte : burst length.
	 * 2 bytes: destination address.
	 * n bytes: data to burst copy.
	 *
	 * This is ended by a 0 length, then the NVS tables.
	 */

	/* FIXME: Do we need to check here whether the LSB is 1? */
	while (nvs_ptr[0]) {
		burst_len = nvs_ptr[0];
		dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));

		/*
		 * Due to our new wl1271_translate_reg_addr function,
		 * we need to add the REGISTER_BASE to the destination
		 */
		dest_addr += REGISTERS_BASE;

		/* We move our pointer to the data */
		nvs_ptr += 3;

		for (i = 0; i < burst_len; i++) {
			val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
			       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

			wl1271_debug(DEBUG_BOOT,
				     "nvs burst write 0x%x: 0x%x",
				     dest_addr, val);
			wl1271_write32(wl, dest_addr, val);

			nvs_ptr += 4;
			dest_addr += 4;
		}
	}

	/*
	 * We've reached the first zero length, the first NVS table
	 * is located at an aligned offset which is at least 7 bytes further.
	 */
	nvs_ptr = (u8 *)wl->nvs->nvs +
			ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
	nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;

	/* Now we must set the partition correctly */
	wl1271_set_partition(wl, &part_table[PART_WORK]);

	/* Copy the NVS tables to a new block to ensure alignment */
	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
	if (!nvs_aligned)
		return -ENOMEM;

	/* And finally we upload the NVS tables */
	wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);

	kfree(nvs_aligned);
	return 0;
}

static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
{
	wl1271_enable_interrupts(wl);
	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
		       WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
	wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
}

static int wl1271_boot_soft_reset(struct wl1271 *wl)
{
	unsigned long timeout;
	u32 boot_data;

	/* perform soft reset */
	wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);

	/* SOFT_RESET is self clearing */
	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	while (1) {
		boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
		wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
		if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
			break;

		if (time_after(jiffies, timeout)) {
			/* 1.2 check pWhalBus->uSelfClearTime if the
			 * timeout was reached */
			wl1271_error("soft reset timeout");
			return -1;
		}

		udelay(SOFT_RESET_STALL_TIME);
	}

	/* disable Rx/Tx */
	wl1271_write32(wl, ENABLE, 0x0);

	/* disable auto calibration on start*/
	wl1271_write32(wl, SPARE_A2, 0xffff);

	return 0;
}

static int wl1271_boot_run_firmware(struct wl1271 *wl)
{
	int loop, ret;
	u32 chip_id, intr;

	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);

	chip_id = wl1271_read32(wl, CHIP_ID_B);

	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);

	if (chip_id != wl->chip.id) {
		wl1271_error("chip id doesn't match after firmware boot");
		return -EIO;
	}

	/* wait for init to complete */
	loop = 0;
	while (loop++ < INIT_LOOP) {
		udelay(INIT_LOOP_DELAY);
		intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);

		if (intr == 0xffffffff) {
			wl1271_error("error reading hardware complete "
				     "init indication");
			return -EIO;
		}
		/* check that ACX_INTR_INIT_COMPLETE is enabled */
		else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
			wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
				       WL1271_ACX_INTR_INIT_COMPLETE);
			break;
		}
	}

	if (loop > INIT_LOOP) {
		wl1271_error("timeout waiting for the hardware to "
			     "complete initialization");
		return -EIO;
	}

	/* get hardware config command mail box */
	wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);

	/* get hardware config event mail box */
	wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);

	/* set the working partition to its "running" mode offset */
	wl1271_set_partition(wl, &part_table[PART_WORK]);

	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
		     wl->cmd_box_addr, wl->event_box_addr);

	wl1271_boot_fw_version(wl);

	/*
	 * in case of full asynchronous mode the firmware event must be
	 * ready to receive event from the command mailbox
	 */

	/* unmask required mbox events  */
	wl->event_mask = BSS_LOSE_EVENT_ID |
		SCAN_COMPLETE_EVENT_ID |
		PS_REPORT_EVENT_ID |
		JOIN_EVENT_COMPLETE_ID |
		DISCONNECT_EVENT_COMPLETE_ID |
		RSSI_SNR_TRIGGER_0_EVENT_ID |
		PSPOLL_DELIVERY_FAILURE_EVENT_ID |
		SOFT_GEMINI_SENSE_EVENT_ID;

	ret = wl1271_event_unmask(wl);
	if (ret < 0) {
		wl1271_error("EVENT mask setting failed");
		return ret;
	}

	wl1271_event_mbox_config(wl);

	/* firmware startup completed */
	return 0;
}

static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
{
	u32 polarity;

	polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);

	/* We use HIGH polarity, so unset the LOW bit */
	polarity &= ~POLARITY_LOW;
	wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);

	return 0;
}

static void wl1271_boot_hw_version(struct wl1271 *wl)
{
	u32 fuse;

	fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
	fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;

	wl->hw_pg_ver = (s8)fuse;
}

int wl1271_boot(struct wl1271 *wl)
{
	int ret = 0;
	u32 tmp, clk, pause;

	wl1271_boot_hw_version(wl);

	if (wl->ref_clock == 0 || wl->ref_clock == 2 || wl->ref_clock == 4)
		/* ref clk: 19.2/38.4/38.4-XTAL */
		clk = 0x3;
	else if (wl->ref_clock == 1 || wl->ref_clock == 3)
		/* ref clk: 26/52 */
		clk = 0x5;
	else
		return -EINVAL;

	if (wl->ref_clock != 0) {
		u16 val;
		/* Set clock type (open drain) */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
		val &= FREF_CLK_TYPE_BITS;
		wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);

		/* Set clock pull mode (no pull) */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
		val |= NO_PULL;
		wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
	} else {
		u16 val;
		/* Set clock polarity */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
		val &= FREF_CLK_POLARITY_BITS;
		val |= CLK_REQ_OUTN_SEL;
		wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
	}

	wl1271_write32(wl, PLL_PARAMETERS, clk);

	pause = wl1271_read32(wl, PLL_PARAMETERS);

	wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);

	pause &= ~(WU_COUNTER_PAUSE_VAL);
	pause |= WU_COUNTER_PAUSE_VAL;
	wl1271_write32(wl, WU_COUNTER_PAUSE, pause);

	/* Continue the ELP wake up sequence */
	wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
	udelay(500);

	wl1271_set_partition(wl, &part_table[PART_DRPW]);

	/* Read-modify-write DRPW_SCRATCH_START register (see next state)
	   to be used by DRPw FW. The RTRIM value will be added by the FW
	   before taking DRPw out of reset */

	wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
	clk = wl1271_read32(wl, DRPW_SCRATCH_START);

	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);

	clk |= (wl->ref_clock << 1) << 4;
	wl1271_write32(wl, DRPW_SCRATCH_START, clk);

	wl1271_set_partition(wl, &part_table[PART_WORK]);

	/* Disable interrupts */
	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);

	ret = wl1271_boot_soft_reset(wl);
	if (ret < 0)
		goto out;

	/* 2. start processing NVS file */
	ret = wl1271_boot_upload_nvs(wl);
	if (ret < 0)
		goto out;

	/* write firmware's last address (ie. it's length) to
	 * ACX_EEPROMLESS_IND_REG */
	wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");

	wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);

	tmp = wl1271_read32(wl, CHIP_ID_B);

	wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);

	/* 6. read the EEPROM parameters */
	tmp = wl1271_read32(wl, SCR_PAD2);

	ret = wl1271_boot_write_irq_polarity(wl);
	if (ret < 0)
		goto out;

	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
		       WL1271_ACX_ALL_EVENTS_VECTOR);

	/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
	 * to upload_fw) */

	ret = wl1271_boot_upload_firmware(wl);
	if (ret < 0)
		goto out;

	/* 10.5 start firmware */
	ret = wl1271_boot_run_firmware(wl);
	if (ret < 0)
		goto out;

	/* Enable firmware interrupts now */
	wl1271_boot_enable_interrupts(wl);

	/* set the wl1271 default filters */
	wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
	wl->rx_filter = WL1271_DEFAULT_RX_FILTER;

	wl1271_event_mbox_config(wl);

out:
	return ret;
}
Commit	Line	Data
f5fc0f86 LC	1	/*
	2	* This file is part of wl1271
	3	*
2f826f55	4	* Copyright (C) 2008-2010 Nokia Corporation
f5fc0f86 LC	5	*
	6	* Contact: Luciano Coelho <luciano.coelho@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
	24	#include <linux/gpio.h>
5a0e3ad6	25	#include <linux/slab.h>
f5fc0f86 LC	26
	27	#include "wl1271_acx.h"
	28	#include "wl1271_reg.h"
	29	#include "wl1271_boot.h"
7b048c52	30	#include "wl1271_io.h"
f5fc0f86 LC	31	#include "wl1271_event.h"
	32
	33	static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
	34	[PART_DOWN] = {
	35	.mem = {
	36	.start = 0x00000000,
	37	.size = 0x000177c0
	38	},
	39	.reg = {
	40	.start = REGISTERS_BASE,
	41	.size = 0x00008800
	42	},
451de97a JO	43	.mem2 = {
	44	.start = 0x00000000,
	45	.size = 0x00000000
	46	},
	47	.mem3 = {
	48	.start = 0x00000000,
	49	.size = 0x00000000
	50	},
f5fc0f86 LC	51	},
	52
	53	[PART_WORK] = {
	54	.mem = {
	55	.start = 0x00040000,
	56	.size = 0x00014fc0
	57	},
	58	.reg = {
	59	.start = REGISTERS_BASE,
451de97a JO	60	.size = 0x0000a000
	61	},
	62	.mem2 = {
	63	.start = 0x003004f8,
	64	.size = 0x00000004
	65	},
	66	.mem3 = {
	67	.start = 0x00040404,
	68	.size = 0x00000000
f5fc0f86 LC	69	},
	70	},
	71
	72	[PART_DRPW] = {
	73	.mem = {
	74	.start = 0x00040000,
	75	.size = 0x00014fc0
	76	},
	77	.reg = {
	78	.start = DRPW_BASE,
	79	.size = 0x00006000
451de97a JO	80	},
	81	.mem2 = {
	82	.start = 0x00000000,
	83	.size = 0x00000000
	84	},
	85	.mem3 = {
	86	.start = 0x00000000,
	87	.size = 0x00000000
f5fc0f86 LC	88	}
	89	}
	90	};
	91
	92	static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
	93	{
	94	u32 cpu_ctrl;
	95
	96	/* 10.5.0 run the firmware (I) */
7b048c52	97	cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
f5fc0f86 LC	98
	99	/* 10.5.1 run the firmware (II) */
	100	cpu_ctrl \|= flag;
7b048c52	101	wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
f5fc0f86 LC	102	}
	103
	104	static void wl1271_boot_fw_version(struct wl1271 *wl)
	105	{
	106	struct wl1271_static_data static_data;
	107
7b048c52 TP	108	wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
7b048c52 TP	109	false);
f5fc0f86 LC	110
	111	strncpy(wl->chip.fw_ver, static_data.fw_version,
	112	sizeof(wl->chip.fw_ver));
	113
	114	/* make sure the string is NULL-terminated */
	115	wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
	116	}
	117
	118	static int wl1271_boot_upload_firmware_chunk(struct wl1271 wl, void buf,
	119	size_t fw_data_len, u32 dest)
	120	{
451de97a	121	struct wl1271_partition_set partition;
f5fc0f86	122	int addr, chunk_num, partition_limit;
1fba4974	123	u8 p, chunk;
f5fc0f86 LC	124
	125	/* whal_FwCtrl_LoadFwImageSm() */
	126
	127	wl1271_debug(DEBUG_BOOT, "starting firmware upload");
	128
73d0a13c LC	129	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
73d0a13c LC	130	fw_data_len, CHUNK_SIZE);
f5fc0f86	131
f5fc0f86 LC	132	if ((fw_data_len % 4) != 0) {
	133	wl1271_error("firmware length not multiple of four");
	134	return -EIO;
	135	}
	136
1fba4974	137	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
ed317788	138	if (!chunk) {
1fba4974 JO	139	wl1271_error("allocation for firmware upload chunk failed");
	140	return -ENOMEM;
	141	}
	142
451de97a JO	143	memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
	144	partition.mem.start = dest;
	145	wl1271_set_partition(wl, &partition);
f5fc0f86 LC	146
	147	/* 10.1 set partition limit and chunk num */
	148	chunk_num = 0;
	149	partition_limit = part_table[PART_DOWN].mem.size;
	150
	151	while (chunk_num < fw_data_len / CHUNK_SIZE) {
	152	/* 10.2 update partition, if needed */
	153	addr = dest + (chunk_num + 2) * CHUNK_SIZE;
	154	if (addr > partition_limit) {
	155	addr = dest + chunk_num * CHUNK_SIZE;
	156	partition_limit = chunk_num * CHUNK_SIZE +
	157	part_table[PART_DOWN].mem.size;
451de97a JO	158	partition.mem.start = addr;
451de97a JO	159	wl1271_set_partition(wl, &partition);
f5fc0f86 LC	160	}
	161
	162	/* 10.3 upload the chunk */
	163	addr = dest + chunk_num * CHUNK_SIZE;
	164	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	165	memcpy(chunk, p, CHUNK_SIZE);
f5fc0f86 LC	166	wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
f5fc0f86 LC	167	p, addr);
7b048c52	168	wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
f5fc0f86 LC	169
	170	chunk_num++;
	171	}
	172
	173	/* 10.4 upload the last chunk */
	174	addr = dest + chunk_num * CHUNK_SIZE;
	175	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	176	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
73d0a13c	177	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
f5fc0f86	178	fw_data_len % CHUNK_SIZE, p, addr);
7b048c52	179	wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
f5fc0f86	180
1fba4974	181	kfree(chunk);
f5fc0f86 LC	182	return 0;
	183	}
	184
	185	static int wl1271_boot_upload_firmware(struct wl1271 *wl)
	186	{
	187	u32 chunks, addr, len;
ed317788	188	int ret = 0;
f5fc0f86 LC	189	u8 *fw;
	190
	191	fw = wl->fw;
d0f63b20	192	chunks = be32_to_cpup((__be32 *) fw);
f5fc0f86 LC	193	fw += sizeof(u32);
	194
	195	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
	196
	197	while (chunks--) {
d0f63b20	198	addr = be32_to_cpup((__be32 *) fw);
f5fc0f86	199	fw += sizeof(u32);
d0f63b20	200	len = be32_to_cpup((__be32 *) fw);
f5fc0f86 LC	201	fw += sizeof(u32);
	202
	203	if (len > 300000) {
	204	wl1271_info("firmware chunk too long: %u", len);
	205	return -EINVAL;
	206	}
	207	wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
	208	chunks, addr, len);
ed317788 JO	209	ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
	210	if (ret != 0)
	211	break;
f5fc0f86 LC	212	fw += len;
	213	}
	214
ed317788	215	return ret;
f5fc0f86 LC	216	}
	217
	218	static int wl1271_boot_upload_nvs(struct wl1271 *wl)
	219	{
	220	size_t nvs_len, burst_len;
	221	int i;
	222	u32 dest_addr, val;
152ee6e0	223	u8 nvs_ptr, nvs_aligned;
f5fc0f86	224
152ee6e0	225	if (wl->nvs == NULL)
f5fc0f86 LC	226	return -ENODEV;
f5fc0f86 LC	227
02fabb0e JO	228	/*
	229	* FIXME: the LEGACY NVS image support (NVS's missing the 5GHz band
	230	* configurations) can be removed when those NVS files stop floating
	231	* around.
	232	*/
	233	if (wl->nvs_len == sizeof(struct wl1271_nvs_file) \|\|
	234	wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
	235	if (wl->nvs->general_params.dual_mode_select)
	236	wl->enable_11a = true;
	237	}
	238
	239	if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
	240	(wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE \|\|
	241	wl->enable_11a)) {
	242	wl1271_error("nvs size is not as expected: %zu != %zu",
	243	wl->nvs_len, sizeof(struct wl1271_nvs_file));
	244	kfree(wl->nvs);
	245	wl->nvs = NULL;
	246	wl->nvs_len = 0;
	247	return -EILSEQ;
	248	}
	249
8cf5e8e5	250	/* only the first part of the NVS needs to be uploaded */
152ee6e0 JO	251	nvs_len = sizeof(wl->nvs->nvs);
152ee6e0 JO	252	nvs_ptr = (u8 *)wl->nvs->nvs;
f5fc0f86	253
1b72aecd JO	254	/* update current MAC address to NVS */
	255	nvs_ptr[11] = wl->mac_addr[0];
	256	nvs_ptr[10] = wl->mac_addr[1];
	257	nvs_ptr[6] = wl->mac_addr[2];
	258	nvs_ptr[5] = wl->mac_addr[3];
	259	nvs_ptr[4] = wl->mac_addr[4];
	260	nvs_ptr[3] = wl->mac_addr[5];
	261
f5fc0f86 LC	262	/*
	263	* Layout before the actual NVS tables:
	264	* 1 byte : burst length.
	265	* 2 bytes: destination address.
	266	* n bytes: data to burst copy.
	267	*
	268	* This is ended by a 0 length, then the NVS tables.
	269	*/
	270
	271	/* FIXME: Do we need to check here whether the LSB is 1? */
	272	while (nvs_ptr[0]) {
	273	burst_len = nvs_ptr[0];
	274	dest_addr = (nvs_ptr[1] & 0xfe) \| ((u32)(nvs_ptr[2] << 8));
	275
2f63b011 JO	276	/*
	277	* Due to our new wl1271_translate_reg_addr function,
	278	* we need to add the REGISTER_BASE to the destination
	279	*/
f5fc0f86 LC	280	dest_addr += REGISTERS_BASE;
	281
	282	/* We move our pointer to the data */
	283	nvs_ptr += 3;
	284
	285	for (i = 0; i < burst_len; i++) {
	286	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
	287	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
	288
	289	wl1271_debug(DEBUG_BOOT,
	290	"nvs burst write 0x%x: 0x%x",
	291	dest_addr, val);
7b048c52	292	wl1271_write32(wl, dest_addr, val);
f5fc0f86 LC	293
	294	nvs_ptr += 4;
	295	dest_addr += 4;
	296	}
	297	}
	298
	299	/*
	300	* We've reached the first zero length, the first NVS table
67e0208a	301	* is located at an aligned offset which is at least 7 bytes further.
f5fc0f86	302	*/
67e0208a IY	303	nvs_ptr = (u8 *)wl->nvs->nvs +
67e0208a IY	304	ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
152ee6e0	305	nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
f5fc0f86	306
f5fc0f86	307	/* Now we must set the partition correctly */
451de97a	308	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	309
f5fc0f86 LC	310	/* Copy the NVS tables to a new block to ensure alignment */
67e0208a IY	311	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
	312	if (!nvs_aligned)
	313	return -ENOMEM;
f5fc0f86 LC	314
f5fc0f86 LC	315	/* And finally we upload the NVS tables */
7b048c52	316	wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
f5fc0f86 LC	317
	318	kfree(nvs_aligned);
	319	return 0;
	320	}
	321
	322	static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
	323	{
54f7e503	324	wl1271_enable_interrupts(wl);
7b048c52 TP	325	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
	326	WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
	327	wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
f5fc0f86 LC	328	}
	329
	330	static int wl1271_boot_soft_reset(struct wl1271 *wl)
	331	{
	332	unsigned long timeout;
	333	u32 boot_data;
	334
	335	/* perform soft reset */
7b048c52	336	wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
f5fc0f86 LC	337
	338	/* SOFT_RESET is self clearing */
	339	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	340	while (1) {
7b048c52	341	boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
f5fc0f86 LC	342	wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
	343	if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
	344	break;
	345
	346	if (time_after(jiffies, timeout)) {
	347	/* 1.2 check pWhalBus->uSelfClearTime if the
	348	* timeout was reached */
	349	wl1271_error("soft reset timeout");
	350	return -1;
	351	}
	352
	353	udelay(SOFT_RESET_STALL_TIME);
	354	}
	355
	356	/* disable Rx/Tx */
7b048c52	357	wl1271_write32(wl, ENABLE, 0x0);
f5fc0f86 LC	358
f5fc0f86 LC	359	/* disable auto calibration on start*/
7b048c52	360	wl1271_write32(wl, SPARE_A2, 0xffff);
f5fc0f86 LC	361
	362	return 0;
	363	}
	364
	365	static int wl1271_boot_run_firmware(struct wl1271 *wl)
	366	{
	367	int loop, ret;
23a7a51c	368	u32 chip_id, intr;
f5fc0f86 LC	369
	370	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
	371
7b048c52	372	chip_id = wl1271_read32(wl, CHIP_ID_B);
f5fc0f86 LC	373
	374	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
	375
	376	if (chip_id != wl->chip.id) {
	377	wl1271_error("chip id doesn't match after firmware boot");
	378	return -EIO;
	379	}
	380
	381	/* wait for init to complete */
	382	loop = 0;
	383	while (loop++ < INIT_LOOP) {
	384	udelay(INIT_LOOP_DELAY);
23a7a51c	385	intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
f5fc0f86	386
23a7a51c	387	if (intr == 0xffffffff) {
f5fc0f86 LC	388	wl1271_error("error reading hardware complete "
	389	"init indication");
	390	return -EIO;
	391	}
	392	/* check that ACX_INTR_INIT_COMPLETE is enabled */
23a7a51c	393	else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
7b048c52 TP	394	wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
7b048c52 TP	395	WL1271_ACX_INTR_INIT_COMPLETE);
f5fc0f86 LC	396	break;
	397	}
	398	}
	399
e7d17cf4	400	if (loop > INIT_LOOP) {
f5fc0f86 LC	401	wl1271_error("timeout waiting for the hardware to "
	402	"complete initialization");
	403	return -EIO;
	404	}
	405
	406	/* get hardware config command mail box */
7b048c52	407	wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
f5fc0f86 LC	408
f5fc0f86 LC	409	/* get hardware config event mail box */
7b048c52	410	wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
f5fc0f86 LC	411
f5fc0f86 LC	412	/* set the working partition to its "running" mode offset */
451de97a	413	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	414
	415	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
	416	wl->cmd_box_addr, wl->event_box_addr);
	417
	418	wl1271_boot_fw_version(wl);
	419
	420	/*
	421	* in case of full asynchronous mode the firmware event must be
	422	* ready to receive event from the command mailbox
	423	*/
	424
be823e5b JO	425	/* unmask required mbox events */
be823e5b JO	426	wl->event_mask = BSS_LOSE_EVENT_ID \|
19ad0715	427	SCAN_COMPLETE_EVENT_ID \|
99d84c1d	428	PS_REPORT_EVENT_ID \|
2f826f55	429	JOIN_EVENT_COMPLETE_ID \|
00236aed	430	DISCONNECT_EVENT_COMPLETE_ID \|
90494a90	431	RSSI_SNR_TRIGGER_0_EVENT_ID \|
8d2ef7bd JO	432	PSPOLL_DELIVERY_FAILURE_EVENT_ID \|
8d2ef7bd JO	433	SOFT_GEMINI_SENSE_EVENT_ID;
f5fc0f86 LC	434
	435	ret = wl1271_event_unmask(wl);
	436	if (ret < 0) {
	437	wl1271_error("EVENT mask setting failed");
	438	return ret;
	439	}
	440
	441	wl1271_event_mbox_config(wl);
	442
	443	/* firmware startup completed */
	444	return 0;
	445	}
	446
	447	static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
	448	{
e8768eeb	449	u32 polarity;
f5fc0f86	450
e8768eeb	451	polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
f5fc0f86 LC	452
	453	/* We use HIGH polarity, so unset the LOW bit */
	454	polarity &= ~POLARITY_LOW;
e8768eeb	455	wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
f5fc0f86 LC	456
	457	return 0;
	458	}
	459
d717fd61 JO	460	static void wl1271_boot_hw_version(struct wl1271 *wl)
	461	{
	462	u32 fuse;
	463
	464	fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
	465	fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
	466
	467	wl->hw_pg_ver = (s8)fuse;
	468	}
	469
f5fc0f86 LC	470	int wl1271_boot(struct wl1271 *wl)
	471	{
	472	int ret = 0;
	473	u32 tmp, clk, pause;
	474
d717fd61 JO	475	wl1271_boot_hw_version(wl);
d717fd61 JO	476
c8aea565	477	if (wl->ref_clock == 0 \|\| wl->ref_clock == 2 \|\| wl->ref_clock == 4)
284134eb	478	/* ref clk: 19.2/38.4/38.4-XTAL */
f5fc0f86	479	clk = 0x3;
c8aea565	480	else if (wl->ref_clock == 1 \|\| wl->ref_clock == 3)
f5fc0f86 LC	481	/* ref clk: 26/52 */
f5fc0f86 LC	482	clk = 0x5;
15cea993 OBC	483	else
15cea993 OBC	484	return -EINVAL;
f5fc0f86	485
c8aea565	486	if (wl->ref_clock != 0) {
284134eb	487	u16 val;
9d4e5bb3	488	/* Set clock type (open drain) */
284134eb JO	489	val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
284134eb JO	490	val &= FREF_CLK_TYPE_BITS;
284134eb	491	wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
9d4e5bb3 JO	492
	493	/* Set clock pull mode (no pull) */
	494	val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
	495	val \|= NO_PULL;
	496	wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
284134eb JO	497	} else {
	498	u16 val;
	499	/* Set clock polarity */
	500	val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
	501	val &= FREF_CLK_POLARITY_BITS;
	502	val \|= CLK_REQ_OUTN_SEL;
	503	wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
	504	}
	505
7b048c52	506	wl1271_write32(wl, PLL_PARAMETERS, clk);
f5fc0f86	507
7b048c52	508	pause = wl1271_read32(wl, PLL_PARAMETERS);
f5fc0f86 LC	509
	510	wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
	511
2f63b011	512	pause &= ~(WU_COUNTER_PAUSE_VAL);
f5fc0f86	513	pause \|= WU_COUNTER_PAUSE_VAL;
7b048c52	514	wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
f5fc0f86 LC	515
f5fc0f86 LC	516	/* Continue the ELP wake up sequence */
7b048c52	517	wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
f5fc0f86 LC	518	udelay(500);
f5fc0f86 LC	519
451de97a	520	wl1271_set_partition(wl, &part_table[PART_DRPW]);
f5fc0f86 LC	521
	522	/* Read-modify-write DRPW_SCRATCH_START register (see next state)
	523	to be used by DRPw FW. The RTRIM value will be added by the FW
	524	before taking DRPw out of reset */
	525
	526	wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
7b048c52	527	clk = wl1271_read32(wl, DRPW_SCRATCH_START);
f5fc0f86 LC	528
	529	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
	530
c8aea565	531	clk \|= (wl->ref_clock << 1) << 4;
7b048c52	532	wl1271_write32(wl, DRPW_SCRATCH_START, clk);
f5fc0f86	533
451de97a	534	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	535
f5fc0f86 LC	536	/* Disable interrupts */
7b048c52	537	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
f5fc0f86 LC	538
	539	ret = wl1271_boot_soft_reset(wl);
	540	if (ret < 0)
	541	goto out;
	542
	543	/* 2. start processing NVS file */
	544	ret = wl1271_boot_upload_nvs(wl);
	545	if (ret < 0)
	546	goto out;
	547
	548	/* write firmware's last address (ie. it's length) to
	549	* ACX_EEPROMLESS_IND_REG */
	550	wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
	551
7b048c52	552	wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
f5fc0f86	553
7b048c52	554	tmp = wl1271_read32(wl, CHIP_ID_B);
f5fc0f86 LC	555
	556	wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
	557
	558	/* 6. read the EEPROM parameters */
7b048c52	559	tmp = wl1271_read32(wl, SCR_PAD2);
f5fc0f86 LC	560
	561	ret = wl1271_boot_write_irq_polarity(wl);
	562	if (ret < 0)
	563	goto out;
	564
7b048c52 TP	565	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
7b048c52 TP	566	WL1271_ACX_ALL_EVENTS_VECTOR);
f5fc0f86 LC	567
	568	/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
	569	* to upload_fw) */
	570
	571	ret = wl1271_boot_upload_firmware(wl);
	572	if (ret < 0)
	573	goto out;
	574
	575	/* 10.5 start firmware */
	576	ret = wl1271_boot_run_firmware(wl);
	577	if (ret < 0)
	578	goto out;
	579
eb5b28d0 JO	580	/* Enable firmware interrupts now */
	581	wl1271_boot_enable_interrupts(wl);
	582
f5fc0f86 LC	583	/* set the wl1271 default filters */
	584	wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
	585	wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
	586
	587	wl1271_event_mbox_config(wl);
	588
	589	out:
	590	return ret;
	591	}