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[PATCH] zd1211rw: Generic HMAC initialization
[deliverable/linux.git] / drivers / net / wireless / zd1211rw / zd_chip.c
CommitLineData
e85d0918
DD		 1/* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18/* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25
26#include "zd_def.h"
27#include "zd_chip.h"
28#include "zd_ieee80211.h"
29#include "zd_mac.h"
30#include "zd_rf.h"
31#include "zd_util.h"
32
33void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36{
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41}
42
43void zd_chip_clear(struct zd_chip *chip)
44{
c48cf125 45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
e85d0918
DD		 46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
e85d0918 48 mutex_destroy(&chip->mutex);
c48cf125 49 ZD_MEMCLEAR(chip, sizeof(*chip));
e85d0918
DD		 50}
51
52static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
53{
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
56}
57
58/* Prints an identifier line, which will support debugging. */
59static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
60{
61 int i = 0;
62
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
20fe2176 70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type,
e85d0918
DD		 71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
20fe2176
DD		 73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-');
e85d0918
DD		 75 return i;
76}
77
78static void print_id(struct zd_chip *chip)
79{
80 char buffer[80];
81
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
85}
86
87/* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
89 */
90int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
91 unsigned int count)
92{
93 int r;
94 int i;
95 zd_addr_t *a16 = (zd_addr_t *)NULL;
96 u16 *v16;
97 unsigned int count16;
98
99 if (count > USB_MAX_IOREAD32_COUNT)
100 return -EINVAL;
101
102 /* Allocate a single memory block for values and addresses. */
103 count16 = 2*count;
5cbded58 104 a16 = kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
e85d0918
DD		 105 GFP_NOFS);
106 if (!a16) {
107 dev_dbg_f(zd_chip_dev(chip),
108 "error ENOMEM in allocation of a16\n");
109 r = -ENOMEM;
110 goto out;
111 }
112 v16 = (u16 *)(a16 + count16);
113
114 for (i = 0; i < count; i++) {
115 int j = 2*i;
116 /* We read the high word always first. */
117 a16[j] = zd_inc_word(addr[i]);
118 a16[j+1] = addr[i];
119 }
120
121 r = zd_ioread16v_locked(chip, v16, a16, count16);
122 if (r) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error: zd_ioread16v_locked. Error number %d\n", r);
125 goto out;
126 }
127
128 for (i = 0; i < count; i++) {
129 int j = 2*i;
130 values[i] = (v16[j] << 16) | v16[j+1];
131 }
132
133out:
134 kfree((void *)a16);
135 return r;
136}
137
138int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
139 unsigned int count)
140{
141 int i, j, r;
142 struct zd_ioreq16 *ioreqs16;
143 unsigned int count16;
144
145 ZD_ASSERT(mutex_is_locked(&chip->mutex));
146
147 if (count == 0)
148 return 0;
149 if (count > USB_MAX_IOWRITE32_COUNT)
150 return -EINVAL;
151
152 /* Allocate a single memory block for values and addresses. */
153 count16 = 2*count;
154 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
155 if (!ioreqs16) {
156 r = -ENOMEM;
157 dev_dbg_f(zd_chip_dev(chip),
158 "error %d in ioreqs16 allocation\n", r);
159 goto out;
160 }
161
162 for (i = 0; i < count; i++) {
163 j = 2*i;
164 /* We write the high word always first. */
165 ioreqs16[j].value = ioreqs[i].value >> 16;
166 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
167 ioreqs16[j+1].value = ioreqs[i].value;
168 ioreqs16[j+1].addr = ioreqs[i].addr;
169 }
170
171 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
172#ifdef DEBUG
173 if (r) {
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in zd_usb_write16v\n", r);
176 }
177#endif /* DEBUG */
178out:
179 kfree(ioreqs16);
180 return r;
181}
182
183int zd_iowrite16a_locked(struct zd_chip *chip,
184 const struct zd_ioreq16 *ioreqs, unsigned int count)
185{
186 int r;
187 unsigned int i, j, t, max;
188
189 ZD_ASSERT(mutex_is_locked(&chip->mutex));
190 for (i = 0; i < count; i += j + t) {
191 t = 0;
192 max = count-i;
193 if (max > USB_MAX_IOWRITE16_COUNT)
194 max = USB_MAX_IOWRITE16_COUNT;
195 for (j = 0; j < max; j++) {
196 if (!ioreqs[i+j].addr) {
197 t = 1;
198 break;
199 }
200 }
201
202 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
203 if (r) {
204 dev_dbg_f(zd_chip_dev(chip),
205 "error zd_usb_iowrite16v. Error number %d\n",
206 r);
207 return r;
208 }
209 }
210
211 return 0;
212}
213
214/* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
217 */
218int zd_iowrite32a_locked(struct zd_chip *chip,
219 const struct zd_ioreq32 *ioreqs, unsigned int count)
220{
221 int r;
222 unsigned int i, j, t, max;
223
224 for (i = 0; i < count; i += j + t) {
225 t = 0;
226 max = count-i;
227 if (max > USB_MAX_IOWRITE32_COUNT)
228 max = USB_MAX_IOWRITE32_COUNT;
229 for (j = 0; j < max; j++) {
230 if (!ioreqs[i+j].addr) {
231 t = 1;
232 break;
233 }
234 }
235
236 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
237 if (r) {
238 dev_dbg_f(zd_chip_dev(chip),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r);
241 return r;
242 }
243 }
244
245 return 0;
246}
247
248int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
249{
250 int r;
251
e85d0918
DD		 252 mutex_lock(&chip->mutex);
253 r = zd_ioread16_locked(chip, value, addr);
254 mutex_unlock(&chip->mutex);
255 return r;
256}
257
258int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
259{
260 int r;
261
e85d0918
DD		 262 mutex_lock(&chip->mutex);
263 r = zd_ioread32_locked(chip, value, addr);
264 mutex_unlock(&chip->mutex);
265 return r;
266}
267
268int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
269{
270 int r;
271
e85d0918
DD		 272 mutex_lock(&chip->mutex);
273 r = zd_iowrite16_locked(chip, value, addr);
274 mutex_unlock(&chip->mutex);
275 return r;
276}
277
278int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
279{
280 int r;
281
e85d0918
DD		 282 mutex_lock(&chip->mutex);
283 r = zd_iowrite32_locked(chip, value, addr);
284 mutex_unlock(&chip->mutex);
285 return r;
286}
287
288int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
289 u32 *values, unsigned int count)
290{
291 int r;
292
e85d0918
DD		 293 mutex_lock(&chip->mutex);
294 r = zd_ioread32v_locked(chip, values, addresses, count);
295 mutex_unlock(&chip->mutex);
296 return r;
297}
298
299int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
300 unsigned int count)
301{
302 int r;
303
e85d0918
DD		 304 mutex_lock(&chip->mutex);
305 r = zd_iowrite32a_locked(chip, ioreqs, count);
306 mutex_unlock(&chip->mutex);
307 return r;
308}
309
310static int read_pod(struct zd_chip *chip, u8 *rf_type)
311{
312 int r;
313 u32 value;
314
315 ZD_ASSERT(mutex_is_locked(&chip->mutex));
316 r = zd_ioread32_locked(chip, &value, E2P_POD);
317 if (r)
318 goto error;
319 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
320
321 /* FIXME: AL2230 handling (Bit 7 in POD) */
322 *rf_type = value & 0x0f;
323 chip->pa_type = (value >> 16) & 0x0f;
324 chip->patch_cck_gain = (value >> 8) & 0x1;
325 chip->patch_cr157 = (value >> 13) & 0x1;
326 chip->patch_6m_band_edge = (value >> 21) & 0x1;
20fe2176 327 chip->new_phy_layout = (value >> 31) & 0x1;
583afd1e
UK		 328 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
329 chip->supports_tx_led = 1;
330 if (value & (1 << 24)) { /* LED scenario */
331 if (value & (1 << 29))
332 chip->supports_tx_led = 0;
333 }
e85d0918
DD		 334
335 dev_dbg_f(zd_chip_dev(chip),
336 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
583afd1e 337 "patch 6M %d new PHY %d link LED%d tx led %d\n",
e85d0918
DD		 338 zd_rf_name(*rf_type), *rf_type,
339 chip->pa_type, chip->patch_cck_gain,
583afd1e
UK		 340 chip->patch_cr157, chip->patch_6m_band_edge,
341 chip->new_phy_layout,
342 chip->link_led == LED1 ? 1 : 2,
343 chip->supports_tx_led);
e85d0918
DD		 344 return 0;
345error:
346 *rf_type = 0;
347 chip->pa_type = 0;
348 chip->patch_cck_gain = 0;
349 chip->patch_cr157 = 0;
350 chip->patch_6m_band_edge = 0;
20fe2176 351 chip->new_phy_layout = 0;
e85d0918
DD		 352 return r;
353}
354
355static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
356 const zd_addr_t *addr)
357{
358 int r;
359 u32 parts[2];
360
361 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
362 if (r) {
363 dev_dbg_f(zd_chip_dev(chip),
364 "error: couldn't read e2p macs. Error number %d\n", r);
365 return r;
366 }
367
368 mac_addr[0] = parts[0];
369 mac_addr[1] = parts[0] >> 8;
370 mac_addr[2] = parts[0] >> 16;
371 mac_addr[3] = parts[0] >> 24;
372 mac_addr[4] = parts[1];
373 mac_addr[5] = parts[1] >> 8;
374
375 return 0;
376}
377
378static int read_e2p_mac_addr(struct zd_chip *chip)
379{
380 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
381
382 ZD_ASSERT(mutex_is_locked(&chip->mutex));
383 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
384}
385
386/* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
387 * CR_MAC_ADDR_P2 must be overwritten
388 */
389void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
390{
391 mutex_lock(&chip->mutex);
392 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
393 mutex_unlock(&chip->mutex);
394}
395
396static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
397{
398 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
399 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
400}
401
402int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
403{
404 int r;
405
406 dev_dbg_f(zd_chip_dev(chip), "\n");
407 mutex_lock(&chip->mutex);
408 r = read_mac_addr(chip, mac_addr);
409 mutex_unlock(&chip->mutex);
410 return r;
411}
412
413int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
414{
415 int r;
416 struct zd_ioreq32 reqs[2] = {
417 [0] = { .addr = CR_MAC_ADDR_P1 },
418 [1] = { .addr = CR_MAC_ADDR_P2 },
419 };
420
421 reqs[0].value = (mac_addr[3] << 24)
422 | (mac_addr[2] << 16)
423 | (mac_addr[1] << 8)
424 | mac_addr[0];
425 reqs[1].value = (mac_addr[5] << 8)
426 | mac_addr[4];
427
428 dev_dbg_f(zd_chip_dev(chip),
429 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
430
431 mutex_lock(&chip->mutex);
432 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
433#ifdef DEBUG
434 {
435 u8 tmp[ETH_ALEN];
436 read_mac_addr(chip, tmp);
437 }
438#endif /* DEBUG */
439 mutex_unlock(&chip->mutex);
440 return r;
441}
442
443int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
444{
445 int r;
446 u32 value;
447
448 mutex_lock(&chip->mutex);
449 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
450 mutex_unlock(&chip->mutex);
451 if (r)
452 return r;
453
454 *regdomain = value >> 16;
455 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
456
457 return 0;
458}
459
460static int read_values(struct zd_chip *chip, u8 *values, size_t count,
461 zd_addr_t e2p_addr, u32 guard)
462{
463 int r;
464 int i;
465 u32 v;
466
467 ZD_ASSERT(mutex_is_locked(&chip->mutex));
468 for (i = 0;;) {
469 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
470 if (r)
471 return r;
472 v -= guard;
473 if (i+4 < count) {
474 values[i++] = v;
475 values[i++] = v >> 8;
476 values[i++] = v >> 16;
477 values[i++] = v >> 24;
478 continue;
479 }
480 for (;i < count; i++)
481 values[i] = v >> (8*(i%3));
482 return 0;
483 }
484}
485
486static int read_pwr_cal_values(struct zd_chip *chip)
487{
488 return read_values(chip, chip->pwr_cal_values,
489 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
490 0);
491}
492
493static int read_pwr_int_values(struct zd_chip *chip)
494{
495 return read_values(chip, chip->pwr_int_values,
496 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
497 E2P_PWR_INT_GUARD);
498}
499
500static int read_ofdm_cal_values(struct zd_chip *chip)
501{
502 int r;
503 int i;
504 static const zd_addr_t addresses[] = {
505 E2P_36M_CAL_VALUE1,
506 E2P_48M_CAL_VALUE1,
507 E2P_54M_CAL_VALUE1,
508 };
509
510 for (i = 0; i < 3; i++) {
511 r = read_values(chip, chip->ofdm_cal_values[i],
512 E2P_CHANNEL_COUNT, addresses[i], 0);
513 if (r)
514 return r;
515 }
516 return 0;
517}
518
519static int read_cal_int_tables(struct zd_chip *chip)
520{
521 int r;
522
523 r = read_pwr_cal_values(chip);
524 if (r)
525 return r;
526 r = read_pwr_int_values(chip);
527 if (r)
528 return r;
529 r = read_ofdm_cal_values(chip);
530 if (r)
531 return r;
532 return 0;
533}
534
535/* phy means physical registers */
536int zd_chip_lock_phy_regs(struct zd_chip *chip)
537{
538 int r;
539 u32 tmp;
540
541 ZD_ASSERT(mutex_is_locked(&chip->mutex));
542 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
543 if (r) {
544 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
545 return r;
546 }
547
548 dev_dbg_f(zd_chip_dev(chip),
549 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
550 tmp &= ~UNLOCK_PHY_REGS;
551
552 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
553 if (r)
554 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
555 return r;
556}
557
558int zd_chip_unlock_phy_regs(struct zd_chip *chip)
559{
560 int r;
561 u32 tmp;
562
563 ZD_ASSERT(mutex_is_locked(&chip->mutex));
564 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
565 if (r) {
566 dev_err(zd_chip_dev(chip),
567 "error ioread32(CR_REG1): %d\n", r);
568 return r;
569 }
570
571 dev_dbg_f(zd_chip_dev(chip),
572 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
573 tmp |= UNLOCK_PHY_REGS;
574
575 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
576 if (r)
577 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
578 return r;
579}
580
581/* CR157 can be optionally patched by the EEPROM */
582static int patch_cr157(struct zd_chip *chip)
583{
584 int r;
585 u32 value;
586
587 if (!chip->patch_cr157)
588 return 0;
589
590 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
591 if (r)
592 return r;
593
594 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
595 return zd_iowrite32_locked(chip, value >> 8, CR157);
596}
597
598/*
599 * 6M band edge can be optionally overwritten for certain RF's
600 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
601 * bit (for AL2230, AL2230S)
602 */
603static int patch_6m_band_edge(struct zd_chip *chip, int channel)
604{
605 struct zd_ioreq16 ioreqs[] = {
606 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
607 { CR47, 0x1e },
608 };
609
610 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
611 return 0;
612
613 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
614 if (channel == 1 || channel == 11)
615 ioreqs[0].value = 0x12;
616
617 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
618 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
619}
620
621static int zd1211_hw_reset_phy(struct zd_chip *chip)
622{
623 static const struct zd_ioreq16 ioreqs[] = {
624 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
625 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
626 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
627 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
628 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
629 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
630 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
631 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
632 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
633 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
634 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
635 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
636 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
637 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
638 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
639 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
640 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
641 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
642 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
643 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
644 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
645 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
646 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
647 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
648 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
649 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
650 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
651 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
652 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
653 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
654 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
655 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
656 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
657 { },
658 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
659 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
660 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
661 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
662 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
663 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
664 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
665 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
666 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
667 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
668 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
669 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
670 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
671 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
672 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
673 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
674 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
675 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
676 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
677 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
678 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
679 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
680 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
681 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
682 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
683 /* Note: CR204 must lead the CR203 */
684 { CR204, 0x7d },
685 { },
686 { CR203, 0x30 },
687 };
688
689 int r, t;
690
691 dev_dbg_f(zd_chip_dev(chip), "\n");
692
693 r = zd_chip_lock_phy_regs(chip);
694 if (r)
695 goto out;
696
697 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
698 if (r)
699 goto unlock;
700
701 r = patch_cr157(chip);
702unlock:
703 t = zd_chip_unlock_phy_regs(chip);
704 if (t && !r)
705 r = t;
706out:
707 return r;
708}
709
710static int zd1211b_hw_reset_phy(struct zd_chip *chip)
711{
712 static const struct zd_ioreq16 ioreqs[] = {
713 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
714 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
715 { CR10, 0x81 },
716 /* power control { { CR11, 1 << 6 }, */
717 { CR11, 0x00 },
718 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
719 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
720 { CR18, 0x0a }, { CR19, 0x48 },
721 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
722 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
723 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
724 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
fe7215ca 725 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
e85d0918
DD		 726 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
727 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
728 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
729 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
730 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
731 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
732 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
733 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
734 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
735 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
736 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
737 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
738 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
739 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
740 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
741 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
742 { CR94, 0x01 },
743 { CR95, 0x20 }, /* ZD1211B */
744 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
745 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
746 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
747 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
748 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
749 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
750 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
751 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
752 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
753 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
754 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
755 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
756 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
757 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
758 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
759 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
760 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
761 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
762 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
763 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
764 { CR170, 0xba }, { CR171, 0xba },
765 /* Note: CR204 must lead the CR203 */
766 { CR204, 0x7d },
767 {},
768 { CR203, 0x30 },
769 };
770
771 int r, t;
772
773 dev_dbg_f(zd_chip_dev(chip), "\n");
774
775 r = zd_chip_lock_phy_regs(chip);
776 if (r)
777 goto out;
778
779 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
780 if (r)
781 goto unlock;
782
783 r = patch_cr157(chip);
784unlock:
785 t = zd_chip_unlock_phy_regs(chip);
786 if (t && !r)
787 r = t;
788out:
789 return r;
790}
791
792static int hw_reset_phy(struct zd_chip *chip)
793{
794 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
795 zd1211_hw_reset_phy(chip);
796}
797
798static int zd1211_hw_init_hmac(struct zd_chip *chip)
799{
800 static const struct zd_ioreq32 ioreqs[] = {
e85d0918 801 { CR_ZD1211_RETRY_MAX, 0x2 },
e85d0918 802 { CR_RX_THRESHOLD, 0x000c0640 },
e85d0918
DD		 803 };
804
e85d0918
DD		 805 dev_dbg_f(zd_chip_dev(chip), "\n");
806 ZD_ASSERT(mutex_is_locked(&chip->mutex));
34c44912 807 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 808}
809
810static int zd1211b_hw_init_hmac(struct zd_chip *chip)
811{
812 static const struct zd_ioreq32 ioreqs[] = {
e85d0918
DD		 813 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
814 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
815 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
816 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
817 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
818 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
819 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
820 { CR_ZD1211B_TXOP, 0x01800824 },
34c44912
DD		 821 { CR_RX_THRESHOLD, 0x000c0eff, },
822 };
823
824 dev_dbg_f(zd_chip_dev(chip), "\n");
825 ZD_ASSERT(mutex_is_locked(&chip->mutex));
826 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
827}
828
829static int hw_init_hmac(struct zd_chip *chip)
830{
831 int r;
832 static const struct zd_ioreq32 ioreqs[] = {
833 { CR_ACK_TIMEOUT_EXT, 0x20 },
834 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
e85d0918 835 { CR_SNIFFER_ON, 0 },
fde627b5 836 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 837 { CR_GROUP_HASH_P1, 0x00 },
838 { CR_GROUP_HASH_P2, 0x80000000 },
839 { CR_REG1, 0xa4 },
840 { CR_ADDA_PWR_DWN, 0x7f },
841 { CR_BCN_PLCP_CFG, 0x00f00401 },
842 { CR_PHY_DELAY, 0x00 },
843 { CR_ACK_TIMEOUT_EXT, 0x80 },
844 { CR_ADDA_PWR_DWN, 0x00 },
845 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 846 { CR_RX_PE_DELAY, 0x70 },
847 { CR_PS_CTRL, 0x10000000 },
848 { CR_RTS_CTS_RATE, 0x02030203 },
e85d0918
DD		 849 { CR_AFTER_PNP, 0x1 },
850 { CR_WEP_PROTECT, 0x114 },
34c44912 851 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
e85d0918
DD		 852 };
853
e85d0918
DD		 854 ZD_ASSERT(mutex_is_locked(&chip->mutex));
855 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
34c44912
DD		 856 if (r)
857 return r;
e85d0918 858
e85d0918
DD		 859 return chip->is_zd1211b ?
860 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
861}
862
863struct aw_pt_bi {
864 u32 atim_wnd_period;
865 u32 pre_tbtt;
866 u32 beacon_interval;
867};
868
869static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
870{
871 int r;
872 static const zd_addr_t aw_pt_bi_addr[] =
873 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
874 u32 values[3];
875
876 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
877 ARRAY_SIZE(aw_pt_bi_addr));
878 if (r) {
879 memset(s, 0, sizeof(*s));
880 return r;
881 }
882
883 s->atim_wnd_period = values[0];
884 s->pre_tbtt = values[1];
885 s->beacon_interval = values[2];
886 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
887 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
888 return 0;
889}
890
891static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
892{
893 struct zd_ioreq32 reqs[3];
894
895 if (s->beacon_interval <= 5)
896 s->beacon_interval = 5;
897 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
898 s->pre_tbtt = s->beacon_interval - 1;
899 if (s->atim_wnd_period >= s->pre_tbtt)
900 s->atim_wnd_period = s->pre_tbtt - 1;
901
902 reqs[0].addr = CR_ATIM_WND_PERIOD;
903 reqs[0].value = s->atim_wnd_period;
904 reqs[1].addr = CR_PRE_TBTT;
905 reqs[1].value = s->pre_tbtt;
906 reqs[2].addr = CR_BCN_INTERVAL;
907 reqs[2].value = s->beacon_interval;
908
909 dev_dbg_f(zd_chip_dev(chip),
910 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
911 s->beacon_interval);
912 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
913}
914
915
916static int set_beacon_interval(struct zd_chip *chip, u32 interval)
917{
918 int r;
919 struct aw_pt_bi s;
920
921 ZD_ASSERT(mutex_is_locked(&chip->mutex));
922 r = get_aw_pt_bi(chip, &s);
923 if (r)
924 return r;
925 s.beacon_interval = interval;
926 return set_aw_pt_bi(chip, &s);
927}
928
929int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
930{
931 int r;
932
933 mutex_lock(&chip->mutex);
934 r = set_beacon_interval(chip, interval);
935 mutex_unlock(&chip->mutex);
936 return r;
937}
938
939static int hw_init(struct zd_chip *chip)
940{
941 int r;
942
943 dev_dbg_f(zd_chip_dev(chip), "\n");
944 ZD_ASSERT(mutex_is_locked(&chip->mutex));
945 r = hw_reset_phy(chip);
946 if (r)
947 return r;
948
949 r = hw_init_hmac(chip);
950 if (r)
951 return r;
98227a90 952
98227a90 953 return set_beacon_interval(chip, 100);
e85d0918
DD		 954}
955
956#ifdef DEBUG
957static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
958 const char *addr_string)
959{
960 int r;
961 u32 value;
962
963 r = zd_ioread32_locked(chip, &value, addr);
964 if (r) {
965 dev_dbg_f(zd_chip_dev(chip),
966 "error reading %s. Error number %d\n", addr_string, r);
967 return r;
968 }
969
970 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
971 addr_string, (unsigned int)value);
972 return 0;
973}
974
975static int test_init(struct zd_chip *chip)
976{
977 int r;
978
979 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
980 if (r)
981 return r;
982 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
983 if (r)
984 return r;
985 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
986}
987
988static void dump_fw_registers(struct zd_chip *chip)
989{
990 static const zd_addr_t addr[4] = {
991 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
992 FW_LINK_STATUS
993 };
994
995 int r;
996 u16 values[4];
997
998 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
999 ARRAY_SIZE(addr));
1000 if (r) {
1001 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1002 r);
1003 return;
1004 }
1005
1006 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1007 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1008 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1009 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1010}
1011#endif /* DEBUG */
1012
1013static int print_fw_version(struct zd_chip *chip)
1014{
1015 int r;
1016 u16 version;
1017
1018 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1019 if (r)
1020 return r;
1021
1022 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1023 return 0;
1024}
1025
1026static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1027{
1028 u32 rates;
1029 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1030 /* This sets the mandatory rates, which only depend from the standard
1031 * that the device is supporting. Until further notice we should try
1032 * to support 802.11g also for full speed USB.
1033 */
1034 switch (std) {
1035 case IEEE80211B:
1036 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1037 break;
1038 case IEEE80211G:
1039 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1040 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1041 break;
1042 default:
1043 return -EINVAL;
1044 }
1045 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1046}
1047
b1382ede
DD		 1048int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1049 u8 rts_rate, int preamble)
1050{
1051 int rts_mod = ZD_RX_CCK;
1052 u32 value = 0;
1053
1054 /* Modulation bit */
1055 if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM)
1056 rts_mod = ZD_RX_OFDM;
1057
1058 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1059 rts_rate, preamble);
1060
1061 value |= rts_rate << RTSCTS_SH_RTS_RATE;
1062 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1063 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1064 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1065
1066 /* We always send 11M self-CTS messages, like the vendor driver. */
1067 value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE;
1068 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1069
1070 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1071}
1072
e85d0918
DD		 1073int zd_chip_enable_hwint(struct zd_chip *chip)
1074{
1075 int r;
1076
1077 mutex_lock(&chip->mutex);
1078 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1079 mutex_unlock(&chip->mutex);
1080 return r;
1081}
1082
1083static int disable_hwint(struct zd_chip *chip)
1084{
1085 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1086}
1087
1088int zd_chip_disable_hwint(struct zd_chip *chip)
1089{
1090 int r;
1091
1092 mutex_lock(&chip->mutex);
1093 r = disable_hwint(chip);
1094 mutex_unlock(&chip->mutex);
1095 return r;
1096}
1097
1098int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1099{
1100 int r;
1101 u8 rf_type;
1102
1103 dev_dbg_f(zd_chip_dev(chip), "\n");
1104
1105 mutex_lock(&chip->mutex);
1106 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1107
1108#ifdef DEBUG
1109 r = test_init(chip);
1110 if (r)
1111 goto out;
1112#endif
1113 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1114 if (r)
1115 goto out;
1116
1117 r = zd_usb_init_hw(&chip->usb);
1118 if (r)
1119 goto out;
1120
1121 /* GPI is always disabled, also in the other driver.
1122 */
1123 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1124 if (r)
1125 goto out;
1126 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1127 if (r)
1128 goto out;
1129 /* Currently we support IEEE 802.11g for full and high speed USB.
1130 * It might be discussed, whether we should suppport pure b mode for
1131 * full speed USB.
1132 */
1133 r = set_mandatory_rates(chip, IEEE80211G);
1134 if (r)
1135 goto out;
1136 /* Disabling interrupts is certainly a smart thing here.
1137 */
1138 r = disable_hwint(chip);
1139 if (r)
1140 goto out;
1141 r = read_pod(chip, &rf_type);
1142 if (r)
1143 goto out;
1144 r = hw_init(chip);
1145 if (r)
1146 goto out;
1147 r = zd_rf_init_hw(&chip->rf, rf_type);
1148 if (r)
1149 goto out;
1150
1151 r = print_fw_version(chip);
1152 if (r)
1153 goto out;
1154
1155#ifdef DEBUG
1156 dump_fw_registers(chip);
1157 r = test_init(chip);
1158 if (r)
1159 goto out;
1160#endif /* DEBUG */
1161
1162 r = read_e2p_mac_addr(chip);
1163 if (r)
1164 goto out;
1165
1166 r = read_cal_int_tables(chip);
1167 if (r)
1168 goto out;
1169
1170 print_id(chip);
1171out:
1172 mutex_unlock(&chip->mutex);
1173 return r;
1174}
1175
1176static int update_pwr_int(struct zd_chip *chip, u8 channel)
1177{
1178 u8 value = chip->pwr_int_values[channel - 1];
1179 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1180 channel, value);
cbb5e6bb 1181 return zd_iowrite16_locked(chip, value, CR31);
e85d0918
DD		 1182}
1183
1184static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1185{
1186 u8 value = chip->pwr_cal_values[channel-1];
1187 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1188 channel, value);
cbb5e6bb 1189 return zd_iowrite16_locked(chip, value, CR68);
e85d0918
DD		 1190}
1191
1192static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1193{
cbb5e6bb 1194 struct zd_ioreq16 ioreqs[3];
e85d0918
DD		 1195
1196 ioreqs[0].addr = CR67;
1197 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1198 ioreqs[1].addr = CR66;
1199 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1200 ioreqs[2].addr = CR65;
1201 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1202
1203 dev_dbg_f(zd_chip_dev(chip),
1204 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1205 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
cbb5e6bb 1206 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1207}
1208
1209static int update_channel_integration_and_calibration(struct zd_chip *chip,
1210 u8 channel)
1211{
1212 int r;
1213
1214 r = update_pwr_int(chip, channel);
1215 if (r)
1216 return r;
1217 if (chip->is_zd1211b) {
cbb5e6bb 1218 static const struct zd_ioreq16 ioreqs[] = {
e85d0918
DD		 1219 { CR69, 0x28 },
1220 {},
1221 { CR69, 0x2a },
1222 };
1223
1224 r = update_ofdm_cal(chip, channel);
1225 if (r)
1226 return r;
1227 r = update_pwr_cal(chip, channel);
1228 if (r)
1229 return r;
cbb5e6bb 1230 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1231 if (r)
1232 return r;
1233 }
1234
1235 return 0;
1236}
1237
1238/* The CCK baseband gain can be optionally patched by the EEPROM */
1239static int patch_cck_gain(struct zd_chip *chip)
1240{
1241 int r;
1242 u32 value;
1243
1244 if (!chip->patch_cck_gain)
1245 return 0;
1246
1247 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1248 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1249 if (r)
1250 return r;
1251 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
cbb5e6bb 1252 return zd_iowrite16_locked(chip, value & 0xff, CR47);
e85d0918
DD		 1253}
1254
1255int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1256{
1257 int r, t;
1258
1259 mutex_lock(&chip->mutex);
1260 r = zd_chip_lock_phy_regs(chip);
1261 if (r)
1262 goto out;
1263 r = zd_rf_set_channel(&chip->rf, channel);
1264 if (r)
1265 goto unlock;
1266 r = update_channel_integration_and_calibration(chip, channel);
1267 if (r)
1268 goto unlock;
1269 r = patch_cck_gain(chip);
1270 if (r)
1271 goto unlock;
1272 r = patch_6m_band_edge(chip, channel);
1273 if (r)
1274 goto unlock;
1275 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1276unlock:
1277 t = zd_chip_unlock_phy_regs(chip);
1278 if (t && !r)
1279 r = t;
1280out:
1281 mutex_unlock(&chip->mutex);
1282 return r;
1283}
1284
1285u8 zd_chip_get_channel(struct zd_chip *chip)
1286{
1287 u8 channel;
1288
1289 mutex_lock(&chip->mutex);
1290 channel = chip->rf.channel;
1291 mutex_unlock(&chip->mutex);
1292 return channel;
1293}
1294
583afd1e 1295int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
e85d0918 1296{
583afd1e
UK		 1297 static const zd_addr_t a[] = {
1298 FW_LINK_STATUS,
1299 CR_LED,
1300 };
e85d0918 1301
583afd1e
UK		 1302 int r;
1303 u16 v[ARRAY_SIZE(a)];
1304 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1305 [0] = { FW_LINK_STATUS },
1306 [1] = { CR_LED },
1307 };
1308 u16 other_led;
e85d0918 1309
e85d0918 1310 mutex_lock(&chip->mutex);
583afd1e 1311 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
e85d0918 1312 if (r)
583afd1e
UK		 1313 goto out;
1314
1315 other_led = chip->link_led == LED1 ? LED2 : LED1;
1316
e85d0918 1317 switch (status) {
e85d0918 1318 case LED_OFF:
583afd1e
UK		 1319 ioreqs[0].value = FW_LINK_OFF;
1320 ioreqs[1].value = v[1] & ~(LED1|LED2);
e85d0918 1321 break;
583afd1e
UK		 1322 case LED_SCANNING:
1323 ioreqs[0].value = FW_LINK_OFF;
1324 ioreqs[1].value = v[1] & ~other_led;
1325 if (get_seconds() % 3 == 0) {
1326 ioreqs[1].value &= ~chip->link_led;
1327 } else {
1328 ioreqs[1].value |= chip->link_led;
1329 }
e85d0918 1330 break;
583afd1e
UK		 1331 case LED_ASSOCIATED:
1332 ioreqs[0].value = FW_LINK_TX;
1333 ioreqs[1].value = v[1] & ~other_led;
1334 ioreqs[1].value |= chip->link_led;
e85d0918
DD		 1335 break;
1336 default:
583afd1e 1337 r = -EINVAL;
e85d0918
DD		 1338 goto out;
1339 }
e85d0918 1340
583afd1e
UK		 1341 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1342 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1343 if (r)
e85d0918 1344 goto out;
e85d0918 1345 }
583afd1e 1346 r = 0;
e85d0918 1347out:
583afd1e 1348 mutex_unlock(&chip->mutex);
e85d0918
DD		 1349 return r;
1350}
1351
b1382ede 1352int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
e85d0918 1353{
b1382ede
DD		 1354 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1355 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
e85d0918 1356
b1382ede 1357 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
e85d0918
DD		 1358}
1359
1360static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1361{
1362 static const u16 constants[] = {
1363 715, 655, 585, 540, 470, 410, 360, 315,
1364 270, 235, 205, 175, 150, 125, 105, 85,
1365 65, 50, 40, 25, 15
1366 };
1367
1368 int i;
1369 u32 x;
1370
1371 /* It seems that their quality parameter is somehow per signal
1372 * and is now transferred per bit.
1373 */
1374 switch (rate) {
1375 case ZD_OFDM_RATE_6M:
1376 case ZD_OFDM_RATE_12M:
1377 case ZD_OFDM_RATE_24M:
1378 size *= 2;
1379 break;
1380 case ZD_OFDM_RATE_9M:
1381 case ZD_OFDM_RATE_18M:
1382 case ZD_OFDM_RATE_36M:
1383 case ZD_OFDM_RATE_54M:
1384 size *= 4;
1385 size /= 3;
1386 break;
1387 case ZD_OFDM_RATE_48M:
1388 size *= 3;
1389 size /= 2;
1390 break;
1391 default:
1392 return -EINVAL;
1393 }
1394
1395 x = (10000 * status_quality)/size;
1396 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1397 if (x > constants[i])
1398 break;
1399 }
1400
db888aed
UK		 1401 switch (rate) {
1402 case ZD_OFDM_RATE_6M:
1403 case ZD_OFDM_RATE_9M:
1404 i += 3;
1405 break;
1406 case ZD_OFDM_RATE_12M:
1407 case ZD_OFDM_RATE_18M:
1408 i += 5;
1409 break;
1410 case ZD_OFDM_RATE_24M:
1411 case ZD_OFDM_RATE_36M:
1412 i += 9;
1413 break;
1414 case ZD_OFDM_RATE_48M:
1415 case ZD_OFDM_RATE_54M:
1416 i += 15;
1417 break;
1418 default:
1419 return -EINVAL;
1420 }
1421
e85d0918
DD		 1422 return i;
1423}
1424
db888aed
UK		 1425static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1426{
1427 int r;
1428
1429 r = ofdm_qual_db(status_quality, rate, size);
1430 ZD_ASSERT(r >= 0);
1431 if (r < 0)
1432 r = 0;
1433
1434 r = (r * 100)/29;
1435 return r <= 100 ? r : 100;
1436}
1437
e85d0918
DD		 1438static unsigned int log10times100(unsigned int x)
1439{
1440 static const u8 log10[] = {
1441 0,
1442 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1443 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1444 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1445 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1446 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1447 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1448 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1449 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1450 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1451 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1452 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1453 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1454 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1455 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1456 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1457 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1458 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1459 223, 223, 223, 224, 224, 224, 224,
1460 };
1461
1462 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1463}
1464
1465enum {
1466 MAX_CCK_EVM_DB = 45,
1467};
1468
1469static int cck_evm_db(u8 status_quality)
1470{
1471 return (20 * log10times100(status_quality)) / 100;
1472}
1473
1474static int cck_snr_db(u8 status_quality)
1475{
1476 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1477 ZD_ASSERT(r >= 0);
1478 return r;
1479}
1480
db888aed 1481static int cck_qual_percent(u8 status_quality)
e85d0918 1482{
db888aed
UK		 1483 int r;
1484
1485 r = cck_snr_db(status_quality);
1486 r = (100*r)/17;
1487 return r <= 100 ? r : 100;
e85d0918
DD		 1488}
1489
1490u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1491 const struct rx_status *status)
1492{
db888aed
UK		 1493 return (status->frame_status&ZD_RX_OFDM) ?
1494 ofdm_qual_percent(status->signal_quality_ofdm,
1495 zd_ofdm_plcp_header_rate(rx_frame),
1496 size) :
1497 cck_qual_percent(status->signal_quality_cck);
e85d0918
DD		 1498}
1499
1500u8 zd_rx_strength_percent(u8 rssi)
1501{
db888aed 1502 int r = (rssi*100) / 41;
e85d0918
DD		 1503 if (r > 100)
1504 r = 100;
1505 return (u8) r;
1506}
1507
1508u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1509{
1510 static const u16 ofdm_rates[] = {
1511 [ZD_OFDM_RATE_6M] = 60,
1512 [ZD_OFDM_RATE_9M] = 90,
1513 [ZD_OFDM_RATE_12M] = 120,
1514 [ZD_OFDM_RATE_18M] = 180,
1515 [ZD_OFDM_RATE_24M] = 240,
1516 [ZD_OFDM_RATE_36M] = 360,
1517 [ZD_OFDM_RATE_48M] = 480,
1518 [ZD_OFDM_RATE_54M] = 540,
1519 };
1520 u16 rate;
1521 if (status->frame_status & ZD_RX_OFDM) {
1522 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1523 rate = ofdm_rates[ofdm_rate & 0xf];
1524 } else {
1525 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1526 switch (cck_rate) {
1527 case ZD_CCK_SIGNAL_1M:
1528 rate = 10;
1529 break;
1530 case ZD_CCK_SIGNAL_2M:
1531 rate = 20;
1532 break;
1533 case ZD_CCK_SIGNAL_5M5:
1534 rate = 55;
1535 break;
1536 case ZD_CCK_SIGNAL_11M:
1537 rate = 110;
1538 break;
1539 default:
1540 rate = 0;
1541 }
1542 }
1543
1544 return rate;
1545}
1546
1547int zd_chip_switch_radio_on(struct zd_chip *chip)
1548{
1549 int r;
1550
1551 mutex_lock(&chip->mutex);
1552 r = zd_switch_radio_on(&chip->rf);
1553 mutex_unlock(&chip->mutex);
1554 return r;
1555}
1556
1557int zd_chip_switch_radio_off(struct zd_chip *chip)
1558{
1559 int r;
1560
1561 mutex_lock(&chip->mutex);
1562 r = zd_switch_radio_off(&chip->rf);
1563 mutex_unlock(&chip->mutex);
1564 return r;
1565}
1566
1567int zd_chip_enable_int(struct zd_chip *chip)
1568{
1569 int r;
1570
1571 mutex_lock(&chip->mutex);
1572 r = zd_usb_enable_int(&chip->usb);
1573 mutex_unlock(&chip->mutex);
1574 return r;
1575}
1576
1577void zd_chip_disable_int(struct zd_chip *chip)
1578{
1579 mutex_lock(&chip->mutex);
1580 zd_usb_disable_int(&chip->usb);
1581 mutex_unlock(&chip->mutex);
1582}
1583
1584int zd_chip_enable_rx(struct zd_chip *chip)
1585{
1586 int r;
1587
1588 mutex_lock(&chip->mutex);
1589 r = zd_usb_enable_rx(&chip->usb);
1590 mutex_unlock(&chip->mutex);
1591 return r;
1592}
1593
1594void zd_chip_disable_rx(struct zd_chip *chip)
1595{
1596 mutex_lock(&chip->mutex);
1597 zd_usb_disable_rx(&chip->usb);
1598 mutex_unlock(&chip->mutex);
1599}
1600
1601int zd_rfwritev_locked(struct zd_chip *chip,
1602 const u32* values, unsigned int count, u8 bits)
1603{
1604 int r;
1605 unsigned int i;
1606
1607 for (i = 0; i < count; i++) {
1608 r = zd_rfwrite_locked(chip, values[i], bits);
1609 if (r)
1610 return r;
1611 }
1612
1613 return 0;
1614}
20fe2176
DD		 1615
1616/*
1617 * We can optionally program the RF directly through CR regs, if supported by
1618 * the hardware. This is much faster than the older method.
1619 */
ec62bd91 1620int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
20fe2176
DD		 1621{
1622 struct zd_ioreq16 ioreqs[] = {
1623 { CR244, (value >> 16) & 0xff },
1624 { CR243, (value >> 8) & 0xff },
1625 { CR242, value & 0xff },
1626 };
1627 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1628 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1629}
1630
1631int zd_rfwritev_cr_locked(struct zd_chip *chip,
1632 const u32 *values, unsigned int count)
1633{
1634 int r;
1635 unsigned int i;
1636
1637 for (i = 0; i < count; i++) {
1638 r = zd_rfwrite_cr_locked(chip, values[i]);
1639 if (r)
1640 return r;
1641 }
1642
1643 return 0;
1644}
9cdac965
UK		 1645
1646int zd_chip_set_multicast_hash(struct zd_chip *chip,
1647 struct zd_mc_hash *hash)
1648{
1649 struct zd_ioreq32 ioreqs[] = {
1650 { CR_GROUP_HASH_P1, hash->low },
1651 { CR_GROUP_HASH_P2, hash->high },
1652 };
1653
1654 dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n",
1655 ioreqs[0].value, ioreqs[1].value);
1656 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1657}
Linux kernel - Deliverables
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