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e85d0918 DD |
1 | /* zd_chip.c |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License as published by | |
5 | * the Free Software Foundation; either version 2 of the License, or | |
6 | * (at your option) any later version. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
16 | */ | |
17 | ||
18 | /* This file implements all the hardware specific functions for the ZD1211 | |
19 | * and ZD1211B chips. Support for the ZD1211B was possible after Timothy | |
20 | * Legge sent me a ZD1211B device. Thank you Tim. -- Uli | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/errno.h> | |
25 | ||
26 | #include "zd_def.h" | |
27 | #include "zd_chip.h" | |
28 | #include "zd_ieee80211.h" | |
29 | #include "zd_mac.h" | |
30 | #include "zd_rf.h" | |
31 | #include "zd_util.h" | |
32 | ||
33 | void zd_chip_init(struct zd_chip *chip, | |
34 | struct net_device *netdev, | |
35 | struct usb_interface *intf) | |
36 | { | |
37 | memset(chip, 0, sizeof(*chip)); | |
38 | mutex_init(&chip->mutex); | |
39 | zd_usb_init(&chip->usb, netdev, intf); | |
40 | zd_rf_init(&chip->rf); | |
41 | } | |
42 | ||
43 | void zd_chip_clear(struct zd_chip *chip) | |
44 | { | |
45 | mutex_lock(&chip->mutex); | |
46 | zd_usb_clear(&chip->usb); | |
47 | zd_rf_clear(&chip->rf); | |
48 | mutex_unlock(&chip->mutex); | |
49 | mutex_destroy(&chip->mutex); | |
50 | memset(chip, 0, sizeof(*chip)); | |
51 | } | |
52 | ||
53 | static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size) | |
54 | { | |
55 | return scnprintf(buffer, size, "%02x-%02x-%02x", | |
56 | addr[0], addr[1], addr[2]); | |
57 | } | |
58 | ||
59 | /* Prints an identifier line, which will support debugging. */ | |
60 | static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) | |
61 | { | |
62 | int i = 0; | |
63 | ||
64 | i = scnprintf(buffer, size, "zd1211%s chip ", | |
65 | chip->is_zd1211b ? "b" : ""); | |
66 | i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); | |
67 | i += scnprintf(buffer+i, size-i, " "); | |
68 | i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i); | |
69 | i += scnprintf(buffer+i, size-i, " "); | |
70 | i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); | |
71 | i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c", chip->pa_type, | |
72 | chip->patch_cck_gain ? 'g' : '-', | |
73 | chip->patch_cr157 ? '7' : '-', | |
74 | chip->patch_6m_band_edge ? '6' : '-'); | |
75 | return i; | |
76 | } | |
77 | ||
78 | static void print_id(struct zd_chip *chip) | |
79 | { | |
80 | char buffer[80]; | |
81 | ||
82 | scnprint_id(chip, buffer, sizeof(buffer)); | |
83 | buffer[sizeof(buffer)-1] = 0; | |
84 | dev_info(zd_chip_dev(chip), "%s\n", buffer); | |
85 | } | |
86 | ||
87 | /* Read a variable number of 32-bit values. Parameter count is not allowed to | |
88 | * exceed USB_MAX_IOREAD32_COUNT. | |
89 | */ | |
90 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, | |
91 | unsigned int count) | |
92 | { | |
93 | int r; | |
94 | int i; | |
95 | zd_addr_t *a16 = (zd_addr_t *)NULL; | |
96 | u16 *v16; | |
97 | unsigned int count16; | |
98 | ||
99 | if (count > USB_MAX_IOREAD32_COUNT) | |
100 | return -EINVAL; | |
101 | ||
102 | /* Allocate a single memory block for values and addresses. */ | |
103 | count16 = 2*count; | |
104 | a16 = (zd_addr_t *)kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)), | |
105 | GFP_NOFS); | |
106 | if (!a16) { | |
107 | dev_dbg_f(zd_chip_dev(chip), | |
108 | "error ENOMEM in allocation of a16\n"); | |
109 | r = -ENOMEM; | |
110 | goto out; | |
111 | } | |
112 | v16 = (u16 *)(a16 + count16); | |
113 | ||
114 | for (i = 0; i < count; i++) { | |
115 | int j = 2*i; | |
116 | /* We read the high word always first. */ | |
117 | a16[j] = zd_inc_word(addr[i]); | |
118 | a16[j+1] = addr[i]; | |
119 | } | |
120 | ||
121 | r = zd_ioread16v_locked(chip, v16, a16, count16); | |
122 | if (r) { | |
123 | dev_dbg_f(zd_chip_dev(chip), | |
124 | "error: zd_ioread16v_locked. Error number %d\n", r); | |
125 | goto out; | |
126 | } | |
127 | ||
128 | for (i = 0; i < count; i++) { | |
129 | int j = 2*i; | |
130 | values[i] = (v16[j] << 16) | v16[j+1]; | |
131 | } | |
132 | ||
133 | out: | |
134 | kfree((void *)a16); | |
135 | return r; | |
136 | } | |
137 | ||
138 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
139 | unsigned int count) | |
140 | { | |
141 | int i, j, r; | |
142 | struct zd_ioreq16 *ioreqs16; | |
143 | unsigned int count16; | |
144 | ||
145 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
146 | ||
147 | if (count == 0) | |
148 | return 0; | |
149 | if (count > USB_MAX_IOWRITE32_COUNT) | |
150 | return -EINVAL; | |
151 | ||
152 | /* Allocate a single memory block for values and addresses. */ | |
153 | count16 = 2*count; | |
154 | ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS); | |
155 | if (!ioreqs16) { | |
156 | r = -ENOMEM; | |
157 | dev_dbg_f(zd_chip_dev(chip), | |
158 | "error %d in ioreqs16 allocation\n", r); | |
159 | goto out; | |
160 | } | |
161 | ||
162 | for (i = 0; i < count; i++) { | |
163 | j = 2*i; | |
164 | /* We write the high word always first. */ | |
165 | ioreqs16[j].value = ioreqs[i].value >> 16; | |
166 | ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr); | |
167 | ioreqs16[j+1].value = ioreqs[i].value; | |
168 | ioreqs16[j+1].addr = ioreqs[i].addr; | |
169 | } | |
170 | ||
171 | r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16); | |
172 | #ifdef DEBUG | |
173 | if (r) { | |
174 | dev_dbg_f(zd_chip_dev(chip), | |
175 | "error %d in zd_usb_write16v\n", r); | |
176 | } | |
177 | #endif /* DEBUG */ | |
178 | out: | |
179 | kfree(ioreqs16); | |
180 | return r; | |
181 | } | |
182 | ||
183 | int zd_iowrite16a_locked(struct zd_chip *chip, | |
184 | const struct zd_ioreq16 *ioreqs, unsigned int count) | |
185 | { | |
186 | int r; | |
187 | unsigned int i, j, t, max; | |
188 | ||
189 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
190 | for (i = 0; i < count; i += j + t) { | |
191 | t = 0; | |
192 | max = count-i; | |
193 | if (max > USB_MAX_IOWRITE16_COUNT) | |
194 | max = USB_MAX_IOWRITE16_COUNT; | |
195 | for (j = 0; j < max; j++) { | |
196 | if (!ioreqs[i+j].addr) { | |
197 | t = 1; | |
198 | break; | |
199 | } | |
200 | } | |
201 | ||
202 | r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j); | |
203 | if (r) { | |
204 | dev_dbg_f(zd_chip_dev(chip), | |
205 | "error zd_usb_iowrite16v. Error number %d\n", | |
206 | r); | |
207 | return r; | |
208 | } | |
209 | } | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | /* Writes a variable number of 32 bit registers. The functions will split | |
215 | * that in several USB requests. A split can be forced by inserting an IO | |
216 | * request with an zero address field. | |
217 | */ | |
218 | int zd_iowrite32a_locked(struct zd_chip *chip, | |
219 | const struct zd_ioreq32 *ioreqs, unsigned int count) | |
220 | { | |
221 | int r; | |
222 | unsigned int i, j, t, max; | |
223 | ||
224 | for (i = 0; i < count; i += j + t) { | |
225 | t = 0; | |
226 | max = count-i; | |
227 | if (max > USB_MAX_IOWRITE32_COUNT) | |
228 | max = USB_MAX_IOWRITE32_COUNT; | |
229 | for (j = 0; j < max; j++) { | |
230 | if (!ioreqs[i+j].addr) { | |
231 | t = 1; | |
232 | break; | |
233 | } | |
234 | } | |
235 | ||
236 | r = _zd_iowrite32v_locked(chip, &ioreqs[i], j); | |
237 | if (r) { | |
238 | dev_dbg_f(zd_chip_dev(chip), | |
239 | "error _zd_iowrite32v_locked." | |
240 | " Error number %d\n", r); | |
241 | return r; | |
242 | } | |
243 | } | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) | |
249 | { | |
250 | int r; | |
251 | ||
252 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); | |
253 | mutex_lock(&chip->mutex); | |
254 | r = zd_ioread16_locked(chip, value, addr); | |
255 | mutex_unlock(&chip->mutex); | |
256 | return r; | |
257 | } | |
258 | ||
259 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) | |
260 | { | |
261 | int r; | |
262 | ||
263 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); | |
264 | mutex_lock(&chip->mutex); | |
265 | r = zd_ioread32_locked(chip, value, addr); | |
266 | mutex_unlock(&chip->mutex); | |
267 | return r; | |
268 | } | |
269 | ||
270 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) | |
271 | { | |
272 | int r; | |
273 | ||
274 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); | |
275 | mutex_lock(&chip->mutex); | |
276 | r = zd_iowrite16_locked(chip, value, addr); | |
277 | mutex_unlock(&chip->mutex); | |
278 | return r; | |
279 | } | |
280 | ||
281 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) | |
282 | { | |
283 | int r; | |
284 | ||
285 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); | |
286 | mutex_lock(&chip->mutex); | |
287 | r = zd_iowrite32_locked(chip, value, addr); | |
288 | mutex_unlock(&chip->mutex); | |
289 | return r; | |
290 | } | |
291 | ||
292 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | |
293 | u32 *values, unsigned int count) | |
294 | { | |
295 | int r; | |
296 | ||
297 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); | |
298 | mutex_lock(&chip->mutex); | |
299 | r = zd_ioread32v_locked(chip, values, addresses, count); | |
300 | mutex_unlock(&chip->mutex); | |
301 | return r; | |
302 | } | |
303 | ||
304 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
305 | unsigned int count) | |
306 | { | |
307 | int r; | |
308 | ||
309 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); | |
310 | mutex_lock(&chip->mutex); | |
311 | r = zd_iowrite32a_locked(chip, ioreqs, count); | |
312 | mutex_unlock(&chip->mutex); | |
313 | return r; | |
314 | } | |
315 | ||
316 | static int read_pod(struct zd_chip *chip, u8 *rf_type) | |
317 | { | |
318 | int r; | |
319 | u32 value; | |
320 | ||
321 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
322 | r = zd_ioread32_locked(chip, &value, E2P_POD); | |
323 | if (r) | |
324 | goto error; | |
325 | dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); | |
326 | ||
327 | /* FIXME: AL2230 handling (Bit 7 in POD) */ | |
328 | *rf_type = value & 0x0f; | |
329 | chip->pa_type = (value >> 16) & 0x0f; | |
330 | chip->patch_cck_gain = (value >> 8) & 0x1; | |
331 | chip->patch_cr157 = (value >> 13) & 0x1; | |
332 | chip->patch_6m_band_edge = (value >> 21) & 0x1; | |
333 | ||
334 | dev_dbg_f(zd_chip_dev(chip), | |
335 | "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " | |
336 | "patch 6M %d\n", | |
337 | zd_rf_name(*rf_type), *rf_type, | |
338 | chip->pa_type, chip->patch_cck_gain, | |
339 | chip->patch_cr157, chip->patch_6m_band_edge); | |
340 | return 0; | |
341 | error: | |
342 | *rf_type = 0; | |
343 | chip->pa_type = 0; | |
344 | chip->patch_cck_gain = 0; | |
345 | chip->patch_cr157 = 0; | |
346 | chip->patch_6m_band_edge = 0; | |
347 | return r; | |
348 | } | |
349 | ||
350 | static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr, | |
351 | const zd_addr_t *addr) | |
352 | { | |
353 | int r; | |
354 | u32 parts[2]; | |
355 | ||
356 | r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2); | |
357 | if (r) { | |
358 | dev_dbg_f(zd_chip_dev(chip), | |
359 | "error: couldn't read e2p macs. Error number %d\n", r); | |
360 | return r; | |
361 | } | |
362 | ||
363 | mac_addr[0] = parts[0]; | |
364 | mac_addr[1] = parts[0] >> 8; | |
365 | mac_addr[2] = parts[0] >> 16; | |
366 | mac_addr[3] = parts[0] >> 24; | |
367 | mac_addr[4] = parts[1]; | |
368 | mac_addr[5] = parts[1] >> 8; | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static int read_e2p_mac_addr(struct zd_chip *chip) | |
374 | { | |
375 | static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 }; | |
376 | ||
377 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
378 | return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr); | |
379 | } | |
380 | ||
381 | /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and | |
382 | * CR_MAC_ADDR_P2 must be overwritten | |
383 | */ | |
384 | void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
385 | { | |
386 | mutex_lock(&chip->mutex); | |
387 | memcpy(mac_addr, chip->e2p_mac, ETH_ALEN); | |
388 | mutex_unlock(&chip->mutex); | |
389 | } | |
390 | ||
391 | static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
392 | { | |
393 | static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 }; | |
394 | return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr); | |
395 | } | |
396 | ||
397 | int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr) | |
398 | { | |
399 | int r; | |
400 | ||
401 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
402 | mutex_lock(&chip->mutex); | |
403 | r = read_mac_addr(chip, mac_addr); | |
404 | mutex_unlock(&chip->mutex); | |
405 | return r; | |
406 | } | |
407 | ||
408 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) | |
409 | { | |
410 | int r; | |
411 | struct zd_ioreq32 reqs[2] = { | |
412 | [0] = { .addr = CR_MAC_ADDR_P1 }, | |
413 | [1] = { .addr = CR_MAC_ADDR_P2 }, | |
414 | }; | |
415 | ||
416 | reqs[0].value = (mac_addr[3] << 24) | |
417 | | (mac_addr[2] << 16) | |
418 | | (mac_addr[1] << 8) | |
419 | | mac_addr[0]; | |
420 | reqs[1].value = (mac_addr[5] << 8) | |
421 | | mac_addr[4]; | |
422 | ||
423 | dev_dbg_f(zd_chip_dev(chip), | |
424 | "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr)); | |
425 | ||
426 | mutex_lock(&chip->mutex); | |
427 | r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
428 | #ifdef DEBUG | |
429 | { | |
430 | u8 tmp[ETH_ALEN]; | |
431 | read_mac_addr(chip, tmp); | |
432 | } | |
433 | #endif /* DEBUG */ | |
434 | mutex_unlock(&chip->mutex); | |
435 | return r; | |
436 | } | |
437 | ||
438 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) | |
439 | { | |
440 | int r; | |
441 | u32 value; | |
442 | ||
443 | mutex_lock(&chip->mutex); | |
444 | r = zd_ioread32_locked(chip, &value, E2P_SUBID); | |
445 | mutex_unlock(&chip->mutex); | |
446 | if (r) | |
447 | return r; | |
448 | ||
449 | *regdomain = value >> 16; | |
450 | dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static int read_values(struct zd_chip *chip, u8 *values, size_t count, | |
456 | zd_addr_t e2p_addr, u32 guard) | |
457 | { | |
458 | int r; | |
459 | int i; | |
460 | u32 v; | |
461 | ||
462 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
463 | for (i = 0;;) { | |
464 | r = zd_ioread32_locked(chip, &v, e2p_addr+i/2); | |
465 | if (r) | |
466 | return r; | |
467 | v -= guard; | |
468 | if (i+4 < count) { | |
469 | values[i++] = v; | |
470 | values[i++] = v >> 8; | |
471 | values[i++] = v >> 16; | |
472 | values[i++] = v >> 24; | |
473 | continue; | |
474 | } | |
475 | for (;i < count; i++) | |
476 | values[i] = v >> (8*(i%3)); | |
477 | return 0; | |
478 | } | |
479 | } | |
480 | ||
481 | static int read_pwr_cal_values(struct zd_chip *chip) | |
482 | { | |
483 | return read_values(chip, chip->pwr_cal_values, | |
484 | E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, | |
485 | 0); | |
486 | } | |
487 | ||
488 | static int read_pwr_int_values(struct zd_chip *chip) | |
489 | { | |
490 | return read_values(chip, chip->pwr_int_values, | |
491 | E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, | |
492 | E2P_PWR_INT_GUARD); | |
493 | } | |
494 | ||
495 | static int read_ofdm_cal_values(struct zd_chip *chip) | |
496 | { | |
497 | int r; | |
498 | int i; | |
499 | static const zd_addr_t addresses[] = { | |
500 | E2P_36M_CAL_VALUE1, | |
501 | E2P_48M_CAL_VALUE1, | |
502 | E2P_54M_CAL_VALUE1, | |
503 | }; | |
504 | ||
505 | for (i = 0; i < 3; i++) { | |
506 | r = read_values(chip, chip->ofdm_cal_values[i], | |
507 | E2P_CHANNEL_COUNT, addresses[i], 0); | |
508 | if (r) | |
509 | return r; | |
510 | } | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static int read_cal_int_tables(struct zd_chip *chip) | |
515 | { | |
516 | int r; | |
517 | ||
518 | r = read_pwr_cal_values(chip); | |
519 | if (r) | |
520 | return r; | |
521 | r = read_pwr_int_values(chip); | |
522 | if (r) | |
523 | return r; | |
524 | r = read_ofdm_cal_values(chip); | |
525 | if (r) | |
526 | return r; | |
527 | return 0; | |
528 | } | |
529 | ||
530 | /* phy means physical registers */ | |
531 | int zd_chip_lock_phy_regs(struct zd_chip *chip) | |
532 | { | |
533 | int r; | |
534 | u32 tmp; | |
535 | ||
536 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
537 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
538 | if (r) { | |
539 | dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); | |
540 | return r; | |
541 | } | |
542 | ||
543 | dev_dbg_f(zd_chip_dev(chip), | |
544 | "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS); | |
545 | tmp &= ~UNLOCK_PHY_REGS; | |
546 | ||
547 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
548 | if (r) | |
549 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
550 | return r; | |
551 | } | |
552 | ||
553 | int zd_chip_unlock_phy_regs(struct zd_chip *chip) | |
554 | { | |
555 | int r; | |
556 | u32 tmp; | |
557 | ||
558 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
559 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); | |
560 | if (r) { | |
561 | dev_err(zd_chip_dev(chip), | |
562 | "error ioread32(CR_REG1): %d\n", r); | |
563 | return r; | |
564 | } | |
565 | ||
566 | dev_dbg_f(zd_chip_dev(chip), | |
567 | "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS); | |
568 | tmp |= UNLOCK_PHY_REGS; | |
569 | ||
570 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); | |
571 | if (r) | |
572 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); | |
573 | return r; | |
574 | } | |
575 | ||
576 | /* CR157 can be optionally patched by the EEPROM */ | |
577 | static int patch_cr157(struct zd_chip *chip) | |
578 | { | |
579 | int r; | |
580 | u32 value; | |
581 | ||
582 | if (!chip->patch_cr157) | |
583 | return 0; | |
584 | ||
585 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); | |
586 | if (r) | |
587 | return r; | |
588 | ||
589 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); | |
590 | return zd_iowrite32_locked(chip, value >> 8, CR157); | |
591 | } | |
592 | ||
593 | /* | |
594 | * 6M band edge can be optionally overwritten for certain RF's | |
595 | * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge | |
596 | * bit (for AL2230, AL2230S) | |
597 | */ | |
598 | static int patch_6m_band_edge(struct zd_chip *chip, int channel) | |
599 | { | |
600 | struct zd_ioreq16 ioreqs[] = { | |
601 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
602 | { CR47, 0x1e }, | |
603 | }; | |
604 | ||
605 | if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge) | |
606 | return 0; | |
607 | ||
608 | /* FIXME: Channel 11 is not the edge for all regulatory domains. */ | |
609 | if (channel == 1 || channel == 11) | |
610 | ioreqs[0].value = 0x12; | |
611 | ||
612 | dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); | |
613 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
614 | } | |
615 | ||
616 | static int zd1211_hw_reset_phy(struct zd_chip *chip) | |
617 | { | |
618 | static const struct zd_ioreq16 ioreqs[] = { | |
619 | { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 }, | |
620 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 }, | |
621 | { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f }, | |
622 | { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d }, | |
623 | { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a }, | |
624 | { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c }, | |
625 | { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 }, | |
626 | { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 }, | |
627 | { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b }, | |
628 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, | |
629 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
630 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
631 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
632 | { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff }, | |
633 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
634 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
635 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
636 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
637 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
638 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
639 | { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
640 | { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 }, | |
641 | { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 }, | |
642 | { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 }, | |
643 | { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 }, | |
644 | { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff }, | |
645 | { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 }, | |
646 | { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 }, | |
647 | { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 }, | |
648 | { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a }, | |
649 | { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 }, | |
650 | { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e }, | |
651 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
652 | { }, | |
653 | { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 }, | |
654 | { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 }, | |
655 | { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 }, | |
656 | { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 }, | |
657 | { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C }, | |
658 | { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 }, | |
659 | { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 }, | |
660 | { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 }, | |
661 | { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 }, | |
662 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
663 | { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 }, | |
664 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
665 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
666 | { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f }, | |
667 | { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 }, | |
668 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
669 | { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 }, | |
670 | { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 }, | |
671 | { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c }, | |
672 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c }, | |
673 | { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 }, | |
674 | { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa }, | |
675 | { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea }, | |
676 | { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a }, | |
677 | { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba }, | |
678 | /* Note: CR204 must lead the CR203 */ | |
679 | { CR204, 0x7d }, | |
680 | { }, | |
681 | { CR203, 0x30 }, | |
682 | }; | |
683 | ||
684 | int r, t; | |
685 | ||
686 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
687 | ||
688 | r = zd_chip_lock_phy_regs(chip); | |
689 | if (r) | |
690 | goto out; | |
691 | ||
692 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
693 | if (r) | |
694 | goto unlock; | |
695 | ||
696 | r = patch_cr157(chip); | |
697 | unlock: | |
698 | t = zd_chip_unlock_phy_regs(chip); | |
699 | if (t && !r) | |
700 | r = t; | |
701 | out: | |
702 | return r; | |
703 | } | |
704 | ||
705 | static int zd1211b_hw_reset_phy(struct zd_chip *chip) | |
706 | { | |
707 | static const struct zd_ioreq16 ioreqs[] = { | |
708 | { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 }, | |
709 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 }, | |
710 | { CR10, 0x81 }, | |
711 | /* power control { { CR11, 1 << 6 }, */ | |
712 | { CR11, 0x00 }, | |
713 | { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 }, | |
714 | { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e }, | |
715 | { CR18, 0x0a }, { CR19, 0x48 }, | |
716 | { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ | |
717 | { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 }, | |
718 | { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 }, | |
719 | { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 }, | |
720 | { CR30, 0x49 }, /* jointly decoder, no ASIC */ | |
721 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, | |
722 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, | |
723 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, | |
724 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, | |
725 | { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff }, | |
726 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, | |
727 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, | |
728 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, | |
729 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, | |
730 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, | |
731 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, | |
732 | { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 }, | |
733 | { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 }, | |
734 | { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 }, | |
735 | { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 }, | |
736 | { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 }, | |
737 | { CR94, 0x01 }, | |
738 | { CR95, 0x20 }, /* ZD1211B */ | |
739 | { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 }, | |
740 | { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 }, | |
741 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, | |
742 | { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 }, | |
743 | { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 }, | |
744 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, | |
745 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, | |
746 | { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e }, | |
747 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, | |
748 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, | |
749 | { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 }, | |
750 | { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 }, | |
751 | { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c }, | |
752 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 }, | |
753 | { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ | |
754 | { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ | |
755 | { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe }, | |
756 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, | |
757 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, | |
758 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, | |
759 | { CR170, 0xba }, { CR171, 0xba }, | |
760 | /* Note: CR204 must lead the CR203 */ | |
761 | { CR204, 0x7d }, | |
762 | {}, | |
763 | { CR203, 0x30 }, | |
764 | }; | |
765 | ||
766 | int r, t; | |
767 | ||
768 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
769 | ||
770 | r = zd_chip_lock_phy_regs(chip); | |
771 | if (r) | |
772 | goto out; | |
773 | ||
774 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
775 | if (r) | |
776 | goto unlock; | |
777 | ||
778 | r = patch_cr157(chip); | |
779 | unlock: | |
780 | t = zd_chip_unlock_phy_regs(chip); | |
781 | if (t && !r) | |
782 | r = t; | |
783 | out: | |
784 | return r; | |
785 | } | |
786 | ||
787 | static int hw_reset_phy(struct zd_chip *chip) | |
788 | { | |
789 | return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) : | |
790 | zd1211_hw_reset_phy(chip); | |
791 | } | |
792 | ||
793 | static int zd1211_hw_init_hmac(struct zd_chip *chip) | |
794 | { | |
795 | static const struct zd_ioreq32 ioreqs[] = { | |
796 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | |
797 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | |
798 | { CR_ZD1211_RETRY_MAX, 0x2 }, | |
799 | { CR_SNIFFER_ON, 0 }, | |
fde627b5 | 800 | { CR_RX_FILTER, STA_RX_FILTER }, |
e85d0918 DD |
801 | { CR_GROUP_HASH_P1, 0x00 }, |
802 | { CR_GROUP_HASH_P2, 0x80000000 }, | |
803 | { CR_REG1, 0xa4 }, | |
804 | { CR_ADDA_PWR_DWN, 0x7f }, | |
805 | { CR_BCN_PLCP_CFG, 0x00f00401 }, | |
806 | { CR_PHY_DELAY, 0x00 }, | |
807 | { CR_ACK_TIMEOUT_EXT, 0x80 }, | |
808 | { CR_ADDA_PWR_DWN, 0x00 }, | |
809 | { CR_ACK_TIME_80211, 0x100 }, | |
810 | { CR_IFS_VALUE, 0x547c032 }, | |
811 | { CR_RX_PE_DELAY, 0x70 }, | |
812 | { CR_PS_CTRL, 0x10000000 }, | |
813 | { CR_RTS_CTS_RATE, 0x02030203 }, | |
814 | { CR_RX_THRESHOLD, 0x000c0640 }, | |
815 | { CR_AFTER_PNP, 0x1 }, | |
816 | { CR_WEP_PROTECT, 0x114 }, | |
817 | }; | |
818 | ||
819 | int r; | |
820 | ||
821 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
822 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
823 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
824 | #ifdef DEBUG | |
825 | if (r) { | |
826 | dev_err(zd_chip_dev(chip), | |
827 | "error in zd_iowrite32a_locked. Error number %d\n", r); | |
828 | } | |
829 | #endif /* DEBUG */ | |
830 | return r; | |
831 | } | |
832 | ||
833 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) | |
834 | { | |
835 | static const struct zd_ioreq32 ioreqs[] = { | |
836 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | |
837 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | |
838 | { CR_ZD1211B_RETRY_MAX, 0x02020202 }, | |
839 | { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f }, | |
840 | { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f }, | |
841 | { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f }, | |
842 | { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f }, | |
843 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, | |
844 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, | |
845 | { CR_ZD1211B_TXOP, 0x01800824 }, | |
846 | { CR_SNIFFER_ON, 0 }, | |
fde627b5 | 847 | { CR_RX_FILTER, STA_RX_FILTER }, |
e85d0918 DD |
848 | { CR_GROUP_HASH_P1, 0x00 }, |
849 | { CR_GROUP_HASH_P2, 0x80000000 }, | |
850 | { CR_REG1, 0xa4 }, | |
851 | { CR_ADDA_PWR_DWN, 0x7f }, | |
852 | { CR_BCN_PLCP_CFG, 0x00f00401 }, | |
853 | { CR_PHY_DELAY, 0x00 }, | |
854 | { CR_ACK_TIMEOUT_EXT, 0x80 }, | |
855 | { CR_ADDA_PWR_DWN, 0x00 }, | |
856 | { CR_ACK_TIME_80211, 0x100 }, | |
857 | { CR_IFS_VALUE, 0x547c032 }, | |
858 | { CR_RX_PE_DELAY, 0x70 }, | |
859 | { CR_PS_CTRL, 0x10000000 }, | |
860 | { CR_RTS_CTS_RATE, 0x02030203 }, | |
861 | { CR_RX_THRESHOLD, 0x000c0640 }, | |
862 | { CR_AFTER_PNP, 0x1 }, | |
863 | { CR_WEP_PROTECT, 0x114 }, | |
864 | }; | |
865 | ||
866 | int r; | |
867 | ||
868 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
869 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
870 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
871 | if (r) { | |
872 | dev_dbg_f(zd_chip_dev(chip), | |
873 | "error in zd_iowrite32a_locked. Error number %d\n", r); | |
874 | } | |
875 | return r; | |
876 | } | |
877 | ||
878 | static int hw_init_hmac(struct zd_chip *chip) | |
879 | { | |
880 | return chip->is_zd1211b ? | |
881 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); | |
882 | } | |
883 | ||
884 | struct aw_pt_bi { | |
885 | u32 atim_wnd_period; | |
886 | u32 pre_tbtt; | |
887 | u32 beacon_interval; | |
888 | }; | |
889 | ||
890 | static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
891 | { | |
892 | int r; | |
893 | static const zd_addr_t aw_pt_bi_addr[] = | |
894 | { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; | |
895 | u32 values[3]; | |
896 | ||
897 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, | |
898 | ARRAY_SIZE(aw_pt_bi_addr)); | |
899 | if (r) { | |
900 | memset(s, 0, sizeof(*s)); | |
901 | return r; | |
902 | } | |
903 | ||
904 | s->atim_wnd_period = values[0]; | |
905 | s->pre_tbtt = values[1]; | |
906 | s->beacon_interval = values[2]; | |
907 | dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n", | |
908 | s->atim_wnd_period, s->pre_tbtt, s->beacon_interval); | |
909 | return 0; | |
910 | } | |
911 | ||
912 | static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) | |
913 | { | |
914 | struct zd_ioreq32 reqs[3]; | |
915 | ||
916 | if (s->beacon_interval <= 5) | |
917 | s->beacon_interval = 5; | |
918 | if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval) | |
919 | s->pre_tbtt = s->beacon_interval - 1; | |
920 | if (s->atim_wnd_period >= s->pre_tbtt) | |
921 | s->atim_wnd_period = s->pre_tbtt - 1; | |
922 | ||
923 | reqs[0].addr = CR_ATIM_WND_PERIOD; | |
924 | reqs[0].value = s->atim_wnd_period; | |
925 | reqs[1].addr = CR_PRE_TBTT; | |
926 | reqs[1].value = s->pre_tbtt; | |
927 | reqs[2].addr = CR_BCN_INTERVAL; | |
928 | reqs[2].value = s->beacon_interval; | |
929 | ||
930 | dev_dbg_f(zd_chip_dev(chip), | |
931 | "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt, | |
932 | s->beacon_interval); | |
933 | return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); | |
934 | } | |
935 | ||
936 | ||
937 | static int set_beacon_interval(struct zd_chip *chip, u32 interval) | |
938 | { | |
939 | int r; | |
940 | struct aw_pt_bi s; | |
941 | ||
942 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
943 | r = get_aw_pt_bi(chip, &s); | |
944 | if (r) | |
945 | return r; | |
946 | s.beacon_interval = interval; | |
947 | return set_aw_pt_bi(chip, &s); | |
948 | } | |
949 | ||
950 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval) | |
951 | { | |
952 | int r; | |
953 | ||
954 | mutex_lock(&chip->mutex); | |
955 | r = set_beacon_interval(chip, interval); | |
956 | mutex_unlock(&chip->mutex); | |
957 | return r; | |
958 | } | |
959 | ||
960 | static int hw_init(struct zd_chip *chip) | |
961 | { | |
962 | int r; | |
963 | ||
964 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
965 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
966 | r = hw_reset_phy(chip); | |
967 | if (r) | |
968 | return r; | |
969 | ||
970 | r = hw_init_hmac(chip); | |
971 | if (r) | |
972 | return r; | |
973 | r = set_beacon_interval(chip, 100); | |
974 | if (r) | |
975 | return r; | |
976 | return 0; | |
977 | } | |
978 | ||
979 | #ifdef DEBUG | |
980 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, | |
981 | const char *addr_string) | |
982 | { | |
983 | int r; | |
984 | u32 value; | |
985 | ||
986 | r = zd_ioread32_locked(chip, &value, addr); | |
987 | if (r) { | |
988 | dev_dbg_f(zd_chip_dev(chip), | |
989 | "error reading %s. Error number %d\n", addr_string, r); | |
990 | return r; | |
991 | } | |
992 | ||
993 | dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", | |
994 | addr_string, (unsigned int)value); | |
995 | return 0; | |
996 | } | |
997 | ||
998 | static int test_init(struct zd_chip *chip) | |
999 | { | |
1000 | int r; | |
1001 | ||
1002 | r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); | |
1003 | if (r) | |
1004 | return r; | |
1005 | r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); | |
1006 | if (r) | |
1007 | return r; | |
1008 | return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); | |
1009 | } | |
1010 | ||
1011 | static void dump_fw_registers(struct zd_chip *chip) | |
1012 | { | |
1013 | static const zd_addr_t addr[4] = { | |
1014 | FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE, | |
1015 | FW_LINK_STATUS | |
1016 | }; | |
1017 | ||
1018 | int r; | |
1019 | u16 values[4]; | |
1020 | ||
1021 | r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, | |
1022 | ARRAY_SIZE(addr)); | |
1023 | if (r) { | |
1024 | dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", | |
1025 | r); | |
1026 | return; | |
1027 | } | |
1028 | ||
1029 | dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); | |
1030 | dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); | |
1031 | dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); | |
1032 | dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); | |
1033 | } | |
1034 | #endif /* DEBUG */ | |
1035 | ||
1036 | static int print_fw_version(struct zd_chip *chip) | |
1037 | { | |
1038 | int r; | |
1039 | u16 version; | |
1040 | ||
1041 | r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER); | |
1042 | if (r) | |
1043 | return r; | |
1044 | ||
1045 | dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); | |
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std) | |
1050 | { | |
1051 | u32 rates; | |
1052 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1053 | /* This sets the mandatory rates, which only depend from the standard | |
1054 | * that the device is supporting. Until further notice we should try | |
1055 | * to support 802.11g also for full speed USB. | |
1056 | */ | |
1057 | switch (std) { | |
1058 | case IEEE80211B: | |
1059 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; | |
1060 | break; | |
1061 | case IEEE80211G: | |
1062 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| | |
1063 | CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; | |
1064 | break; | |
1065 | default: | |
1066 | return -EINVAL; | |
1067 | } | |
1068 | return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); | |
1069 | } | |
1070 | ||
1071 | int zd_chip_enable_hwint(struct zd_chip *chip) | |
1072 | { | |
1073 | int r; | |
1074 | ||
1075 | mutex_lock(&chip->mutex); | |
1076 | r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); | |
1077 | mutex_unlock(&chip->mutex); | |
1078 | return r; | |
1079 | } | |
1080 | ||
1081 | static int disable_hwint(struct zd_chip *chip) | |
1082 | { | |
1083 | return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); | |
1084 | } | |
1085 | ||
1086 | int zd_chip_disable_hwint(struct zd_chip *chip) | |
1087 | { | |
1088 | int r; | |
1089 | ||
1090 | mutex_lock(&chip->mutex); | |
1091 | r = disable_hwint(chip); | |
1092 | mutex_unlock(&chip->mutex); | |
1093 | return r; | |
1094 | } | |
1095 | ||
1096 | int zd_chip_init_hw(struct zd_chip *chip, u8 device_type) | |
1097 | { | |
1098 | int r; | |
1099 | u8 rf_type; | |
1100 | ||
1101 | dev_dbg_f(zd_chip_dev(chip), "\n"); | |
1102 | ||
1103 | mutex_lock(&chip->mutex); | |
1104 | chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0; | |
1105 | ||
1106 | #ifdef DEBUG | |
1107 | r = test_init(chip); | |
1108 | if (r) | |
1109 | goto out; | |
1110 | #endif | |
1111 | r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); | |
1112 | if (r) | |
1113 | goto out; | |
1114 | ||
1115 | r = zd_usb_init_hw(&chip->usb); | |
1116 | if (r) | |
1117 | goto out; | |
1118 | ||
1119 | /* GPI is always disabled, also in the other driver. | |
1120 | */ | |
1121 | r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); | |
1122 | if (r) | |
1123 | goto out; | |
1124 | r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); | |
1125 | if (r) | |
1126 | goto out; | |
1127 | /* Currently we support IEEE 802.11g for full and high speed USB. | |
1128 | * It might be discussed, whether we should suppport pure b mode for | |
1129 | * full speed USB. | |
1130 | */ | |
1131 | r = set_mandatory_rates(chip, IEEE80211G); | |
1132 | if (r) | |
1133 | goto out; | |
1134 | /* Disabling interrupts is certainly a smart thing here. | |
1135 | */ | |
1136 | r = disable_hwint(chip); | |
1137 | if (r) | |
1138 | goto out; | |
1139 | r = read_pod(chip, &rf_type); | |
1140 | if (r) | |
1141 | goto out; | |
1142 | r = hw_init(chip); | |
1143 | if (r) | |
1144 | goto out; | |
1145 | r = zd_rf_init_hw(&chip->rf, rf_type); | |
1146 | if (r) | |
1147 | goto out; | |
1148 | ||
1149 | r = print_fw_version(chip); | |
1150 | if (r) | |
1151 | goto out; | |
1152 | ||
1153 | #ifdef DEBUG | |
1154 | dump_fw_registers(chip); | |
1155 | r = test_init(chip); | |
1156 | if (r) | |
1157 | goto out; | |
1158 | #endif /* DEBUG */ | |
1159 | ||
1160 | r = read_e2p_mac_addr(chip); | |
1161 | if (r) | |
1162 | goto out; | |
1163 | ||
1164 | r = read_cal_int_tables(chip); | |
1165 | if (r) | |
1166 | goto out; | |
1167 | ||
1168 | print_id(chip); | |
1169 | out: | |
1170 | mutex_unlock(&chip->mutex); | |
1171 | return r; | |
1172 | } | |
1173 | ||
1174 | static int update_pwr_int(struct zd_chip *chip, u8 channel) | |
1175 | { | |
1176 | u8 value = chip->pwr_int_values[channel - 1]; | |
1177 | dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n", | |
1178 | channel, value); | |
1179 | return zd_iowrite32_locked(chip, value, CR31); | |
1180 | } | |
1181 | ||
1182 | static int update_pwr_cal(struct zd_chip *chip, u8 channel) | |
1183 | { | |
1184 | u8 value = chip->pwr_cal_values[channel-1]; | |
1185 | dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n", | |
1186 | channel, value); | |
1187 | return zd_iowrite32_locked(chip, value, CR68); | |
1188 | } | |
1189 | ||
1190 | static int update_ofdm_cal(struct zd_chip *chip, u8 channel) | |
1191 | { | |
1192 | struct zd_ioreq32 ioreqs[3]; | |
1193 | ||
1194 | ioreqs[0].addr = CR67; | |
1195 | ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; | |
1196 | ioreqs[1].addr = CR66; | |
1197 | ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; | |
1198 | ioreqs[2].addr = CR65; | |
1199 | ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; | |
1200 | ||
1201 | dev_dbg_f(zd_chip_dev(chip), | |
1202 | "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n", | |
1203 | channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value); | |
1204 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1205 | } | |
1206 | ||
1207 | static int update_channel_integration_and_calibration(struct zd_chip *chip, | |
1208 | u8 channel) | |
1209 | { | |
1210 | int r; | |
1211 | ||
1212 | r = update_pwr_int(chip, channel); | |
1213 | if (r) | |
1214 | return r; | |
1215 | if (chip->is_zd1211b) { | |
1216 | static const struct zd_ioreq32 ioreqs[] = { | |
1217 | { CR69, 0x28 }, | |
1218 | {}, | |
1219 | { CR69, 0x2a }, | |
1220 | }; | |
1221 | ||
1222 | r = update_ofdm_cal(chip, channel); | |
1223 | if (r) | |
1224 | return r; | |
1225 | r = update_pwr_cal(chip, channel); | |
1226 | if (r) | |
1227 | return r; | |
1228 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
1229 | if (r) | |
1230 | return r; | |
1231 | } | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | /* The CCK baseband gain can be optionally patched by the EEPROM */ | |
1237 | static int patch_cck_gain(struct zd_chip *chip) | |
1238 | { | |
1239 | int r; | |
1240 | u32 value; | |
1241 | ||
1242 | if (!chip->patch_cck_gain) | |
1243 | return 0; | |
1244 | ||
1245 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1246 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); | |
1247 | if (r) | |
1248 | return r; | |
1249 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); | |
1250 | return zd_iowrite32_locked(chip, value & 0xff, CR47); | |
1251 | } | |
1252 | ||
1253 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel) | |
1254 | { | |
1255 | int r, t; | |
1256 | ||
1257 | mutex_lock(&chip->mutex); | |
1258 | r = zd_chip_lock_phy_regs(chip); | |
1259 | if (r) | |
1260 | goto out; | |
1261 | r = zd_rf_set_channel(&chip->rf, channel); | |
1262 | if (r) | |
1263 | goto unlock; | |
1264 | r = update_channel_integration_and_calibration(chip, channel); | |
1265 | if (r) | |
1266 | goto unlock; | |
1267 | r = patch_cck_gain(chip); | |
1268 | if (r) | |
1269 | goto unlock; | |
1270 | r = patch_6m_band_edge(chip, channel); | |
1271 | if (r) | |
1272 | goto unlock; | |
1273 | r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); | |
1274 | unlock: | |
1275 | t = zd_chip_unlock_phy_regs(chip); | |
1276 | if (t && !r) | |
1277 | r = t; | |
1278 | out: | |
1279 | mutex_unlock(&chip->mutex); | |
1280 | return r; | |
1281 | } | |
1282 | ||
1283 | u8 zd_chip_get_channel(struct zd_chip *chip) | |
1284 | { | |
1285 | u8 channel; | |
1286 | ||
1287 | mutex_lock(&chip->mutex); | |
1288 | channel = chip->rf.channel; | |
1289 | mutex_unlock(&chip->mutex); | |
1290 | return channel; | |
1291 | } | |
1292 | ||
1293 | static u16 led_mask(int led) | |
1294 | { | |
1295 | switch (led) { | |
1296 | case 1: | |
1297 | return LED1; | |
1298 | case 2: | |
1299 | return LED2; | |
1300 | default: | |
1301 | return 0; | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | static int read_led_reg(struct zd_chip *chip, u16 *status) | |
1306 | { | |
1307 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1308 | return zd_ioread16_locked(chip, status, CR_LED); | |
1309 | } | |
1310 | ||
1311 | static int write_led_reg(struct zd_chip *chip, u16 status) | |
1312 | { | |
1313 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
1314 | return zd_iowrite16_locked(chip, status, CR_LED); | |
1315 | } | |
1316 | ||
1317 | int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status) | |
1318 | { | |
1319 | int r, ret; | |
1320 | u16 mask = led_mask(led); | |
1321 | u16 reg; | |
1322 | ||
1323 | if (!mask) | |
1324 | return -EINVAL; | |
1325 | mutex_lock(&chip->mutex); | |
1326 | r = read_led_reg(chip, ®); | |
1327 | if (r) | |
1328 | return r; | |
1329 | switch (status) { | |
1330 | case LED_STATUS: | |
1331 | return (reg & mask) ? LED_ON : LED_OFF; | |
1332 | case LED_OFF: | |
1333 | reg &= ~mask; | |
1334 | ret = LED_OFF; | |
1335 | break; | |
1336 | case LED_FLIP: | |
1337 | reg ^= mask; | |
1338 | ret = (reg&mask) ? LED_ON : LED_OFF; | |
1339 | break; | |
1340 | case LED_ON: | |
1341 | reg |= mask; | |
1342 | ret = LED_ON; | |
1343 | break; | |
1344 | default: | |
1345 | return -EINVAL; | |
1346 | } | |
1347 | r = write_led_reg(chip, reg); | |
1348 | if (r) { | |
1349 | ret = r; | |
1350 | goto out; | |
1351 | } | |
1352 | out: | |
1353 | mutex_unlock(&chip->mutex); | |
1354 | return r; | |
1355 | } | |
1356 | ||
1357 | int zd_chip_led_flip(struct zd_chip *chip, int led, | |
1358 | const unsigned int *phases_msecs, unsigned int count) | |
1359 | { | |
1360 | int i, r; | |
1361 | enum led_status status; | |
1362 | ||
1363 | r = zd_chip_led_status(chip, led, LED_STATUS); | |
1364 | if (r) | |
1365 | return r; | |
1366 | status = r; | |
1367 | for (i = 0; i < count; i++) { | |
1368 | r = zd_chip_led_status(chip, led, LED_FLIP); | |
1369 | if (r < 0) | |
1370 | goto out; | |
1371 | msleep(phases_msecs[i]); | |
1372 | } | |
1373 | ||
1374 | out: | |
1375 | zd_chip_led_status(chip, led, status); | |
1376 | return r; | |
1377 | } | |
1378 | ||
1379 | int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) | |
1380 | { | |
1381 | int r; | |
1382 | ||
1383 | if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G)) | |
1384 | return -EINVAL; | |
1385 | ||
1386 | mutex_lock(&chip->mutex); | |
1387 | r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); | |
1388 | mutex_unlock(&chip->mutex); | |
1389 | return r; | |
1390 | } | |
1391 | ||
1392 | static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size) | |
1393 | { | |
1394 | static const u16 constants[] = { | |
1395 | 715, 655, 585, 540, 470, 410, 360, 315, | |
1396 | 270, 235, 205, 175, 150, 125, 105, 85, | |
1397 | 65, 50, 40, 25, 15 | |
1398 | }; | |
1399 | ||
1400 | int i; | |
1401 | u32 x; | |
1402 | ||
1403 | /* It seems that their quality parameter is somehow per signal | |
1404 | * and is now transferred per bit. | |
1405 | */ | |
1406 | switch (rate) { | |
1407 | case ZD_OFDM_RATE_6M: | |
1408 | case ZD_OFDM_RATE_12M: | |
1409 | case ZD_OFDM_RATE_24M: | |
1410 | size *= 2; | |
1411 | break; | |
1412 | case ZD_OFDM_RATE_9M: | |
1413 | case ZD_OFDM_RATE_18M: | |
1414 | case ZD_OFDM_RATE_36M: | |
1415 | case ZD_OFDM_RATE_54M: | |
1416 | size *= 4; | |
1417 | size /= 3; | |
1418 | break; | |
1419 | case ZD_OFDM_RATE_48M: | |
1420 | size *= 3; | |
1421 | size /= 2; | |
1422 | break; | |
1423 | default: | |
1424 | return -EINVAL; | |
1425 | } | |
1426 | ||
1427 | x = (10000 * status_quality)/size; | |
1428 | for (i = 0; i < ARRAY_SIZE(constants); i++) { | |
1429 | if (x > constants[i]) | |
1430 | break; | |
1431 | } | |
1432 | ||
1433 | return i; | |
1434 | } | |
1435 | ||
1436 | static unsigned int log10times100(unsigned int x) | |
1437 | { | |
1438 | static const u8 log10[] = { | |
1439 | 0, | |
1440 | 0, 30, 47, 60, 69, 77, 84, 90, 95, 100, | |
1441 | 104, 107, 111, 114, 117, 120, 123, 125, 127, 130, | |
1442 | 132, 134, 136, 138, 139, 141, 143, 144, 146, 147, | |
1443 | 149, 150, 151, 153, 154, 155, 156, 157, 159, 160, | |
1444 | 161, 162, 163, 164, 165, 166, 167, 168, 169, 169, | |
1445 | 170, 171, 172, 173, 174, 174, 175, 176, 177, 177, | |
1446 | 178, 179, 179, 180, 181, 181, 182, 183, 183, 184, | |
1447 | 185, 185, 186, 186, 187, 188, 188, 189, 189, 190, | |
1448 | 190, 191, 191, 192, 192, 193, 193, 194, 194, 195, | |
1449 | 195, 196, 196, 197, 197, 198, 198, 199, 199, 200, | |
1450 | 200, 200, 201, 201, 202, 202, 202, 203, 203, 204, | |
1451 | 204, 204, 205, 205, 206, 206, 206, 207, 207, 207, | |
1452 | 208, 208, 208, 209, 209, 210, 210, 210, 211, 211, | |
1453 | 211, 212, 212, 212, 213, 213, 213, 213, 214, 214, | |
1454 | 214, 215, 215, 215, 216, 216, 216, 217, 217, 217, | |
1455 | 217, 218, 218, 218, 219, 219, 219, 219, 220, 220, | |
1456 | 220, 220, 221, 221, 221, 222, 222, 222, 222, 223, | |
1457 | 223, 223, 223, 224, 224, 224, 224, | |
1458 | }; | |
1459 | ||
1460 | return x < ARRAY_SIZE(log10) ? log10[x] : 225; | |
1461 | } | |
1462 | ||
1463 | enum { | |
1464 | MAX_CCK_EVM_DB = 45, | |
1465 | }; | |
1466 | ||
1467 | static int cck_evm_db(u8 status_quality) | |
1468 | { | |
1469 | return (20 * log10times100(status_quality)) / 100; | |
1470 | } | |
1471 | ||
1472 | static int cck_snr_db(u8 status_quality) | |
1473 | { | |
1474 | int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality); | |
1475 | ZD_ASSERT(r >= 0); | |
1476 | return r; | |
1477 | } | |
1478 | ||
1479 | static int rx_qual_db(const void *rx_frame, unsigned int size, | |
1480 | const struct rx_status *status) | |
1481 | { | |
1482 | return (status->frame_status&ZD_RX_OFDM) ? | |
1483 | ofdm_qual_db(status->signal_quality_ofdm, | |
1484 | zd_ofdm_plcp_header_rate(rx_frame), | |
1485 | size) : | |
1486 | cck_snr_db(status->signal_quality_cck); | |
1487 | } | |
1488 | ||
1489 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, | |
1490 | const struct rx_status *status) | |
1491 | { | |
1492 | int r = rx_qual_db(rx_frame, size, status); | |
1493 | if (r < 0) | |
1494 | r = 0; | |
1495 | r = (r * 100) / 14; | |
1496 | if (r > 100) | |
1497 | r = 100; | |
1498 | return r; | |
1499 | } | |
1500 | ||
1501 | u8 zd_rx_strength_percent(u8 rssi) | |
1502 | { | |
1503 | int r = (rssi*100) / 30; | |
1504 | if (r > 100) | |
1505 | r = 100; | |
1506 | return (u8) r; | |
1507 | } | |
1508 | ||
1509 | u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status) | |
1510 | { | |
1511 | static const u16 ofdm_rates[] = { | |
1512 | [ZD_OFDM_RATE_6M] = 60, | |
1513 | [ZD_OFDM_RATE_9M] = 90, | |
1514 | [ZD_OFDM_RATE_12M] = 120, | |
1515 | [ZD_OFDM_RATE_18M] = 180, | |
1516 | [ZD_OFDM_RATE_24M] = 240, | |
1517 | [ZD_OFDM_RATE_36M] = 360, | |
1518 | [ZD_OFDM_RATE_48M] = 480, | |
1519 | [ZD_OFDM_RATE_54M] = 540, | |
1520 | }; | |
1521 | u16 rate; | |
1522 | if (status->frame_status & ZD_RX_OFDM) { | |
1523 | u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame); | |
1524 | rate = ofdm_rates[ofdm_rate & 0xf]; | |
1525 | } else { | |
1526 | u8 cck_rate = zd_cck_plcp_header_rate(rx_frame); | |
1527 | switch (cck_rate) { | |
1528 | case ZD_CCK_SIGNAL_1M: | |
1529 | rate = 10; | |
1530 | break; | |
1531 | case ZD_CCK_SIGNAL_2M: | |
1532 | rate = 20; | |
1533 | break; | |
1534 | case ZD_CCK_SIGNAL_5M5: | |
1535 | rate = 55; | |
1536 | break; | |
1537 | case ZD_CCK_SIGNAL_11M: | |
1538 | rate = 110; | |
1539 | break; | |
1540 | default: | |
1541 | rate = 0; | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | return rate; | |
1546 | } | |
1547 | ||
1548 | int zd_chip_switch_radio_on(struct zd_chip *chip) | |
1549 | { | |
1550 | int r; | |
1551 | ||
1552 | mutex_lock(&chip->mutex); | |
1553 | r = zd_switch_radio_on(&chip->rf); | |
1554 | mutex_unlock(&chip->mutex); | |
1555 | return r; | |
1556 | } | |
1557 | ||
1558 | int zd_chip_switch_radio_off(struct zd_chip *chip) | |
1559 | { | |
1560 | int r; | |
1561 | ||
1562 | mutex_lock(&chip->mutex); | |
1563 | r = zd_switch_radio_off(&chip->rf); | |
1564 | mutex_unlock(&chip->mutex); | |
1565 | return r; | |
1566 | } | |
1567 | ||
1568 | int zd_chip_enable_int(struct zd_chip *chip) | |
1569 | { | |
1570 | int r; | |
1571 | ||
1572 | mutex_lock(&chip->mutex); | |
1573 | r = zd_usb_enable_int(&chip->usb); | |
1574 | mutex_unlock(&chip->mutex); | |
1575 | return r; | |
1576 | } | |
1577 | ||
1578 | void zd_chip_disable_int(struct zd_chip *chip) | |
1579 | { | |
1580 | mutex_lock(&chip->mutex); | |
1581 | zd_usb_disable_int(&chip->usb); | |
1582 | mutex_unlock(&chip->mutex); | |
1583 | } | |
1584 | ||
1585 | int zd_chip_enable_rx(struct zd_chip *chip) | |
1586 | { | |
1587 | int r; | |
1588 | ||
1589 | mutex_lock(&chip->mutex); | |
1590 | r = zd_usb_enable_rx(&chip->usb); | |
1591 | mutex_unlock(&chip->mutex); | |
1592 | return r; | |
1593 | } | |
1594 | ||
1595 | void zd_chip_disable_rx(struct zd_chip *chip) | |
1596 | { | |
1597 | mutex_lock(&chip->mutex); | |
1598 | zd_usb_disable_rx(&chip->usb); | |
1599 | mutex_unlock(&chip->mutex); | |
1600 | } | |
1601 | ||
1602 | int zd_rfwritev_locked(struct zd_chip *chip, | |
1603 | const u32* values, unsigned int count, u8 bits) | |
1604 | { | |
1605 | int r; | |
1606 | unsigned int i; | |
1607 | ||
1608 | for (i = 0; i < count; i++) { | |
1609 | r = zd_rfwrite_locked(chip, values[i], bits); | |
1610 | if (r) | |
1611 | return r; | |
1612 | } | |
1613 | ||
1614 | return 0; | |
1615 | } |