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[PATCH] zd1211rw: USB id 1582:6003 for Longshine 8131G3 added
[deliverable/linux.git] / drivers / net / wireless / zd1211rw / zd_chip.c
CommitLineData
e85d0918
DD		 1/* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18/* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25
26#include "zd_def.h"
27#include "zd_chip.h"
28#include "zd_ieee80211.h"
29#include "zd_mac.h"
30#include "zd_rf.h"
31#include "zd_util.h"
32
33void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36{
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41}
42
43void zd_chip_clear(struct zd_chip *chip)
44{
45 mutex_lock(&chip->mutex);
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_unlock(&chip->mutex);
49 mutex_destroy(&chip->mutex);
50 memset(chip, 0, sizeof(*chip));
51}
52
53static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
54{
55 return scnprintf(buffer, size, "%02x-%02x-%02x",
56 addr[0], addr[1], addr[2]);
57}
58
59/* Prints an identifier line, which will support debugging. */
60static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
61{
62 int i = 0;
63
64 i = scnprintf(buffer, size, "zd1211%s chip ",
65 chip->is_zd1211b ? "b" : "");
66 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
67 i += scnprintf(buffer+i, size-i, " ");
68 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
20fe2176 71 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type,
e85d0918
DD		 72 chip->patch_cck_gain ? 'g' : '-',
73 chip->patch_cr157 ? '7' : '-',
20fe2176
DD		 74 chip->patch_6m_band_edge ? '6' : '-',
75 chip->new_phy_layout ? 'N' : '-');
e85d0918
DD		 76 return i;
77}
78
79static void print_id(struct zd_chip *chip)
80{
81 char buffer[80];
82
83 scnprint_id(chip, buffer, sizeof(buffer));
84 buffer[sizeof(buffer)-1] = 0;
85 dev_info(zd_chip_dev(chip), "%s\n", buffer);
86}
87
88/* Read a variable number of 32-bit values. Parameter count is not allowed to
89 * exceed USB_MAX_IOREAD32_COUNT.
90 */
91int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
92 unsigned int count)
93{
94 int r;
95 int i;
96 zd_addr_t *a16 = (zd_addr_t *)NULL;
97 u16 *v16;
98 unsigned int count16;
99
100 if (count > USB_MAX_IOREAD32_COUNT)
101 return -EINVAL;
102
103 /* Allocate a single memory block for values and addresses. */
104 count16 = 2*count;
105 a16 = (zd_addr_t *)kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
106 GFP_NOFS);
107 if (!a16) {
108 dev_dbg_f(zd_chip_dev(chip),
109 "error ENOMEM in allocation of a16\n");
110 r = -ENOMEM;
111 goto out;
112 }
113 v16 = (u16 *)(a16 + count16);
114
115 for (i = 0; i < count; i++) {
116 int j = 2*i;
117 /* We read the high word always first. */
118 a16[j] = zd_inc_word(addr[i]);
119 a16[j+1] = addr[i];
120 }
121
122 r = zd_ioread16v_locked(chip, v16, a16, count16);
123 if (r) {
124 dev_dbg_f(zd_chip_dev(chip),
125 "error: zd_ioread16v_locked. Error number %d\n", r);
126 goto out;
127 }
128
129 for (i = 0; i < count; i++) {
130 int j = 2*i;
131 values[i] = (v16[j] << 16) | v16[j+1];
132 }
133
134out:
135 kfree((void *)a16);
136 return r;
137}
138
139int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
140 unsigned int count)
141{
142 int i, j, r;
143 struct zd_ioreq16 *ioreqs16;
144 unsigned int count16;
145
146 ZD_ASSERT(mutex_is_locked(&chip->mutex));
147
148 if (count == 0)
149 return 0;
150 if (count > USB_MAX_IOWRITE32_COUNT)
151 return -EINVAL;
152
153 /* Allocate a single memory block for values and addresses. */
154 count16 = 2*count;
155 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
156 if (!ioreqs16) {
157 r = -ENOMEM;
158 dev_dbg_f(zd_chip_dev(chip),
159 "error %d in ioreqs16 allocation\n", r);
160 goto out;
161 }
162
163 for (i = 0; i < count; i++) {
164 j = 2*i;
165 /* We write the high word always first. */
166 ioreqs16[j].value = ioreqs[i].value >> 16;
167 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
168 ioreqs16[j+1].value = ioreqs[i].value;
169 ioreqs16[j+1].addr = ioreqs[i].addr;
170 }
171
172 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
173#ifdef DEBUG
174 if (r) {
175 dev_dbg_f(zd_chip_dev(chip),
176 "error %d in zd_usb_write16v\n", r);
177 }
178#endif /* DEBUG */
179out:
180 kfree(ioreqs16);
181 return r;
182}
183
184int zd_iowrite16a_locked(struct zd_chip *chip,
185 const struct zd_ioreq16 *ioreqs, unsigned int count)
186{
187 int r;
188 unsigned int i, j, t, max;
189
190 ZD_ASSERT(mutex_is_locked(&chip->mutex));
191 for (i = 0; i < count; i += j + t) {
192 t = 0;
193 max = count-i;
194 if (max > USB_MAX_IOWRITE16_COUNT)
195 max = USB_MAX_IOWRITE16_COUNT;
196 for (j = 0; j < max; j++) {
197 if (!ioreqs[i+j].addr) {
198 t = 1;
199 break;
200 }
201 }
202
203 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
204 if (r) {
205 dev_dbg_f(zd_chip_dev(chip),
206 "error zd_usb_iowrite16v. Error number %d\n",
207 r);
208 return r;
209 }
210 }
211
212 return 0;
213}
214
215/* Writes a variable number of 32 bit registers. The functions will split
216 * that in several USB requests. A split can be forced by inserting an IO
217 * request with an zero address field.
218 */
219int zd_iowrite32a_locked(struct zd_chip *chip,
220 const struct zd_ioreq32 *ioreqs, unsigned int count)
221{
222 int r;
223 unsigned int i, j, t, max;
224
225 for (i = 0; i < count; i += j + t) {
226 t = 0;
227 max = count-i;
228 if (max > USB_MAX_IOWRITE32_COUNT)
229 max = USB_MAX_IOWRITE32_COUNT;
230 for (j = 0; j < max; j++) {
231 if (!ioreqs[i+j].addr) {
232 t = 1;
233 break;
234 }
235 }
236
237 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
238 if (r) {
239 dev_dbg_f(zd_chip_dev(chip),
240 "error _zd_iowrite32v_locked."
241 " Error number %d\n", r);
242 return r;
243 }
244 }
245
246 return 0;
247}
248
249int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
250{
251 int r;
252
253 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
254 mutex_lock(&chip->mutex);
255 r = zd_ioread16_locked(chip, value, addr);
256 mutex_unlock(&chip->mutex);
257 return r;
258}
259
260int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
261{
262 int r;
263
264 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
265 mutex_lock(&chip->mutex);
266 r = zd_ioread32_locked(chip, value, addr);
267 mutex_unlock(&chip->mutex);
268 return r;
269}
270
271int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
272{
273 int r;
274
275 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
276 mutex_lock(&chip->mutex);
277 r = zd_iowrite16_locked(chip, value, addr);
278 mutex_unlock(&chip->mutex);
279 return r;
280}
281
282int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
283{
284 int r;
285
286 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
287 mutex_lock(&chip->mutex);
288 r = zd_iowrite32_locked(chip, value, addr);
289 mutex_unlock(&chip->mutex);
290 return r;
291}
292
293int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
294 u32 *values, unsigned int count)
295{
296 int r;
297
298 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
299 mutex_lock(&chip->mutex);
300 r = zd_ioread32v_locked(chip, values, addresses, count);
301 mutex_unlock(&chip->mutex);
302 return r;
303}
304
305int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
306 unsigned int count)
307{
308 int r;
309
310 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
311 mutex_lock(&chip->mutex);
312 r = zd_iowrite32a_locked(chip, ioreqs, count);
313 mutex_unlock(&chip->mutex);
314 return r;
315}
316
317static int read_pod(struct zd_chip *chip, u8 *rf_type)
318{
319 int r;
320 u32 value;
321
322 ZD_ASSERT(mutex_is_locked(&chip->mutex));
323 r = zd_ioread32_locked(chip, &value, E2P_POD);
324 if (r)
325 goto error;
326 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
327
328 /* FIXME: AL2230 handling (Bit 7 in POD) */
329 *rf_type = value & 0x0f;
330 chip->pa_type = (value >> 16) & 0x0f;
331 chip->patch_cck_gain = (value >> 8) & 0x1;
332 chip->patch_cr157 = (value >> 13) & 0x1;
333 chip->patch_6m_band_edge = (value >> 21) & 0x1;
20fe2176 334 chip->new_phy_layout = (value >> 31) & 0x1;
e85d0918
DD		 335
336 dev_dbg_f(zd_chip_dev(chip),
337 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
20fe2176 338 "patch 6M %d new PHY %d\n",
e85d0918
DD		 339 zd_rf_name(*rf_type), *rf_type,
340 chip->pa_type, chip->patch_cck_gain,
20fe2176 341 chip->patch_cr157, chip->patch_6m_band_edge, chip->new_phy_layout);
e85d0918
DD		 342 return 0;
343error:
344 *rf_type = 0;
345 chip->pa_type = 0;
346 chip->patch_cck_gain = 0;
347 chip->patch_cr157 = 0;
348 chip->patch_6m_band_edge = 0;
20fe2176 349 chip->new_phy_layout = 0;
e85d0918
DD		 350 return r;
351}
352
353static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
354 const zd_addr_t *addr)
355{
356 int r;
357 u32 parts[2];
358
359 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
360 if (r) {
361 dev_dbg_f(zd_chip_dev(chip),
362 "error: couldn't read e2p macs. Error number %d\n", r);
363 return r;
364 }
365
366 mac_addr[0] = parts[0];
367 mac_addr[1] = parts[0] >> 8;
368 mac_addr[2] = parts[0] >> 16;
369 mac_addr[3] = parts[0] >> 24;
370 mac_addr[4] = parts[1];
371 mac_addr[5] = parts[1] >> 8;
372
373 return 0;
374}
375
376static int read_e2p_mac_addr(struct zd_chip *chip)
377{
378 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
379
380 ZD_ASSERT(mutex_is_locked(&chip->mutex));
381 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
382}
383
384/* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
385 * CR_MAC_ADDR_P2 must be overwritten
386 */
387void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
388{
389 mutex_lock(&chip->mutex);
390 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
391 mutex_unlock(&chip->mutex);
392}
393
394static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
395{
396 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
397 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
398}
399
400int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
401{
402 int r;
403
404 dev_dbg_f(zd_chip_dev(chip), "\n");
405 mutex_lock(&chip->mutex);
406 r = read_mac_addr(chip, mac_addr);
407 mutex_unlock(&chip->mutex);
408 return r;
409}
410
411int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
412{
413 int r;
414 struct zd_ioreq32 reqs[2] = {
415 [0] = { .addr = CR_MAC_ADDR_P1 },
416 [1] = { .addr = CR_MAC_ADDR_P2 },
417 };
418
419 reqs[0].value = (mac_addr[3] << 24)
420 | (mac_addr[2] << 16)
421 | (mac_addr[1] << 8)
422 | mac_addr[0];
423 reqs[1].value = (mac_addr[5] << 8)
424 | mac_addr[4];
425
426 dev_dbg_f(zd_chip_dev(chip),
427 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
428
429 mutex_lock(&chip->mutex);
430 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
431#ifdef DEBUG
432 {
433 u8 tmp[ETH_ALEN];
434 read_mac_addr(chip, tmp);
435 }
436#endif /* DEBUG */
437 mutex_unlock(&chip->mutex);
438 return r;
439}
440
441int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
442{
443 int r;
444 u32 value;
445
446 mutex_lock(&chip->mutex);
447 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
448 mutex_unlock(&chip->mutex);
449 if (r)
450 return r;
451
452 *regdomain = value >> 16;
453 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
454
455 return 0;
456}
457
458static int read_values(struct zd_chip *chip, u8 *values, size_t count,
459 zd_addr_t e2p_addr, u32 guard)
460{
461 int r;
462 int i;
463 u32 v;
464
465 ZD_ASSERT(mutex_is_locked(&chip->mutex));
466 for (i = 0;;) {
467 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
468 if (r)
469 return r;
470 v -= guard;
471 if (i+4 < count) {
472 values[i++] = v;
473 values[i++] = v >> 8;
474 values[i++] = v >> 16;
475 values[i++] = v >> 24;
476 continue;
477 }
478 for (;i < count; i++)
479 values[i] = v >> (8*(i%3));
480 return 0;
481 }
482}
483
484static int read_pwr_cal_values(struct zd_chip *chip)
485{
486 return read_values(chip, chip->pwr_cal_values,
487 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
488 0);
489}
490
491static int read_pwr_int_values(struct zd_chip *chip)
492{
493 return read_values(chip, chip->pwr_int_values,
494 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
495 E2P_PWR_INT_GUARD);
496}
497
498static int read_ofdm_cal_values(struct zd_chip *chip)
499{
500 int r;
501 int i;
502 static const zd_addr_t addresses[] = {
503 E2P_36M_CAL_VALUE1,
504 E2P_48M_CAL_VALUE1,
505 E2P_54M_CAL_VALUE1,
506 };
507
508 for (i = 0; i < 3; i++) {
509 r = read_values(chip, chip->ofdm_cal_values[i],
510 E2P_CHANNEL_COUNT, addresses[i], 0);
511 if (r)
512 return r;
513 }
514 return 0;
515}
516
517static int read_cal_int_tables(struct zd_chip *chip)
518{
519 int r;
520
521 r = read_pwr_cal_values(chip);
522 if (r)
523 return r;
524 r = read_pwr_int_values(chip);
525 if (r)
526 return r;
527 r = read_ofdm_cal_values(chip);
528 if (r)
529 return r;
530 return 0;
531}
532
533/* phy means physical registers */
534int zd_chip_lock_phy_regs(struct zd_chip *chip)
535{
536 int r;
537 u32 tmp;
538
539 ZD_ASSERT(mutex_is_locked(&chip->mutex));
540 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
541 if (r) {
542 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
543 return r;
544 }
545
546 dev_dbg_f(zd_chip_dev(chip),
547 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
548 tmp &= ~UNLOCK_PHY_REGS;
549
550 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
551 if (r)
552 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
553 return r;
554}
555
556int zd_chip_unlock_phy_regs(struct zd_chip *chip)
557{
558 int r;
559 u32 tmp;
560
561 ZD_ASSERT(mutex_is_locked(&chip->mutex));
562 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
563 if (r) {
564 dev_err(zd_chip_dev(chip),
565 "error ioread32(CR_REG1): %d\n", r);
566 return r;
567 }
568
569 dev_dbg_f(zd_chip_dev(chip),
570 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
571 tmp |= UNLOCK_PHY_REGS;
572
573 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
574 if (r)
575 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
576 return r;
577}
578
579/* CR157 can be optionally patched by the EEPROM */
580static int patch_cr157(struct zd_chip *chip)
581{
582 int r;
583 u32 value;
584
585 if (!chip->patch_cr157)
586 return 0;
587
588 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
589 if (r)
590 return r;
591
592 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
593 return zd_iowrite32_locked(chip, value >> 8, CR157);
594}
595
596/*
597 * 6M band edge can be optionally overwritten for certain RF's
598 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
599 * bit (for AL2230, AL2230S)
600 */
601static int patch_6m_band_edge(struct zd_chip *chip, int channel)
602{
603 struct zd_ioreq16 ioreqs[] = {
604 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
605 { CR47, 0x1e },
606 };
607
608 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
609 return 0;
610
611 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
612 if (channel == 1 || channel == 11)
613 ioreqs[0].value = 0x12;
614
615 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
616 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
617}
618
619static int zd1211_hw_reset_phy(struct zd_chip *chip)
620{
621 static const struct zd_ioreq16 ioreqs[] = {
622 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
623 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
624 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
625 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
626 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
627 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
628 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
629 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
630 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
631 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
632 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
633 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
634 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
635 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
636 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
637 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
638 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
639 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
640 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
641 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
642 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
643 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
644 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
645 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
646 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
647 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
648 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
649 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
650 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
651 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
652 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
653 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
654 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
655 { },
656 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
657 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
658 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
659 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
660 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
661 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
662 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
663 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
664 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
665 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
666 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
667 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
668 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
669 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
670 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
671 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
672 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
673 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
674 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
675 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
676 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
677 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
678 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
679 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
680 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
681 /* Note: CR204 must lead the CR203 */
682 { CR204, 0x7d },
683 { },
684 { CR203, 0x30 },
685 };
686
687 int r, t;
688
689 dev_dbg_f(zd_chip_dev(chip), "\n");
690
691 r = zd_chip_lock_phy_regs(chip);
692 if (r)
693 goto out;
694
695 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
696 if (r)
697 goto unlock;
698
699 r = patch_cr157(chip);
700unlock:
701 t = zd_chip_unlock_phy_regs(chip);
702 if (t && !r)
703 r = t;
704out:
705 return r;
706}
707
708static int zd1211b_hw_reset_phy(struct zd_chip *chip)
709{
710 static const struct zd_ioreq16 ioreqs[] = {
711 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
712 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
713 { CR10, 0x81 },
714 /* power control { { CR11, 1 << 6 }, */
715 { CR11, 0x00 },
716 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
717 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
718 { CR18, 0x0a }, { CR19, 0x48 },
719 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
720 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
721 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
722 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
fe7215ca 723 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
e85d0918
DD		 724 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
725 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
726 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
727 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
728 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
729 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
730 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
731 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
732 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
733 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
734 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
735 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
736 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
737 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
738 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
739 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
740 { CR94, 0x01 },
741 { CR95, 0x20 }, /* ZD1211B */
742 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
743 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
744 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
745 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
746 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
747 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
748 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
749 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
750 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
751 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
752 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
753 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
754 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
755 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
756 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
757 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
758 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
759 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
760 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
761 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
762 { CR170, 0xba }, { CR171, 0xba },
763 /* Note: CR204 must lead the CR203 */
764 { CR204, 0x7d },
765 {},
766 { CR203, 0x30 },
767 };
768
769 int r, t;
770
771 dev_dbg_f(zd_chip_dev(chip), "\n");
772
773 r = zd_chip_lock_phy_regs(chip);
774 if (r)
775 goto out;
776
777 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
778 if (r)
779 goto unlock;
780
781 r = patch_cr157(chip);
782unlock:
783 t = zd_chip_unlock_phy_regs(chip);
784 if (t && !r)
785 r = t;
786out:
787 return r;
788}
789
790static int hw_reset_phy(struct zd_chip *chip)
791{
792 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
793 zd1211_hw_reset_phy(chip);
794}
795
796static int zd1211_hw_init_hmac(struct zd_chip *chip)
797{
798 static const struct zd_ioreq32 ioreqs[] = {
799 { CR_ACK_TIMEOUT_EXT, 0x20 },
800 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
801 { CR_ZD1211_RETRY_MAX, 0x2 },
802 { CR_SNIFFER_ON, 0 },
fde627b5 803 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 804 { CR_GROUP_HASH_P1, 0x00 },
805 { CR_GROUP_HASH_P2, 0x80000000 },
806 { CR_REG1, 0xa4 },
807 { CR_ADDA_PWR_DWN, 0x7f },
808 { CR_BCN_PLCP_CFG, 0x00f00401 },
809 { CR_PHY_DELAY, 0x00 },
810 { CR_ACK_TIMEOUT_EXT, 0x80 },
811 { CR_ADDA_PWR_DWN, 0x00 },
812 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 813 { CR_RX_PE_DELAY, 0x70 },
814 { CR_PS_CTRL, 0x10000000 },
815 { CR_RTS_CTS_RATE, 0x02030203 },
816 { CR_RX_THRESHOLD, 0x000c0640 },
817 { CR_AFTER_PNP, 0x1 },
818 { CR_WEP_PROTECT, 0x114 },
819 };
820
821 int r;
822
823 dev_dbg_f(zd_chip_dev(chip), "\n");
824 ZD_ASSERT(mutex_is_locked(&chip->mutex));
825 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
826#ifdef DEBUG
827 if (r) {
828 dev_err(zd_chip_dev(chip),
829 "error in zd_iowrite32a_locked. Error number %d\n", r);
830 }
831#endif /* DEBUG */
832 return r;
833}
834
835static int zd1211b_hw_init_hmac(struct zd_chip *chip)
836{
837 static const struct zd_ioreq32 ioreqs[] = {
838 { CR_ACK_TIMEOUT_EXT, 0x20 },
839 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
840 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
841 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
842 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
843 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
844 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
845 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
846 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
847 { CR_ZD1211B_TXOP, 0x01800824 },
848 { CR_SNIFFER_ON, 0 },
fde627b5 849 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 850 { CR_GROUP_HASH_P1, 0x00 },
851 { CR_GROUP_HASH_P2, 0x80000000 },
852 { CR_REG1, 0xa4 },
853 { CR_ADDA_PWR_DWN, 0x7f },
854 { CR_BCN_PLCP_CFG, 0x00f00401 },
855 { CR_PHY_DELAY, 0x00 },
856 { CR_ACK_TIMEOUT_EXT, 0x80 },
857 { CR_ADDA_PWR_DWN, 0x00 },
858 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 859 { CR_RX_PE_DELAY, 0x70 },
860 { CR_PS_CTRL, 0x10000000 },
861 { CR_RTS_CTS_RATE, 0x02030203 },
20fe2176 862 { CR_RX_THRESHOLD, 0x000c0eff, },
e85d0918
DD		 863 { CR_AFTER_PNP, 0x1 },
864 { CR_WEP_PROTECT, 0x114 },
865 };
866
867 int r;
868
869 dev_dbg_f(zd_chip_dev(chip), "\n");
870 ZD_ASSERT(mutex_is_locked(&chip->mutex));
871 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
872 if (r) {
873 dev_dbg_f(zd_chip_dev(chip),
874 "error in zd_iowrite32a_locked. Error number %d\n", r);
875 }
876 return r;
877}
878
879static int hw_init_hmac(struct zd_chip *chip)
880{
881 return chip->is_zd1211b ?
882 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
883}
884
885struct aw_pt_bi {
886 u32 atim_wnd_period;
887 u32 pre_tbtt;
888 u32 beacon_interval;
889};
890
891static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
892{
893 int r;
894 static const zd_addr_t aw_pt_bi_addr[] =
895 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
896 u32 values[3];
897
898 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
899 ARRAY_SIZE(aw_pt_bi_addr));
900 if (r) {
901 memset(s, 0, sizeof(*s));
902 return r;
903 }
904
905 s->atim_wnd_period = values[0];
906 s->pre_tbtt = values[1];
907 s->beacon_interval = values[2];
908 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
909 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
910 return 0;
911}
912
913static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
914{
915 struct zd_ioreq32 reqs[3];
916
917 if (s->beacon_interval <= 5)
918 s->beacon_interval = 5;
919 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
920 s->pre_tbtt = s->beacon_interval - 1;
921 if (s->atim_wnd_period >= s->pre_tbtt)
922 s->atim_wnd_period = s->pre_tbtt - 1;
923
924 reqs[0].addr = CR_ATIM_WND_PERIOD;
925 reqs[0].value = s->atim_wnd_period;
926 reqs[1].addr = CR_PRE_TBTT;
927 reqs[1].value = s->pre_tbtt;
928 reqs[2].addr = CR_BCN_INTERVAL;
929 reqs[2].value = s->beacon_interval;
930
931 dev_dbg_f(zd_chip_dev(chip),
932 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
933 s->beacon_interval);
934 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
935}
936
937
938static int set_beacon_interval(struct zd_chip *chip, u32 interval)
939{
940 int r;
941 struct aw_pt_bi s;
942
943 ZD_ASSERT(mutex_is_locked(&chip->mutex));
944 r = get_aw_pt_bi(chip, &s);
945 if (r)
946 return r;
947 s.beacon_interval = interval;
948 return set_aw_pt_bi(chip, &s);
949}
950
951int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
952{
953 int r;
954
955 mutex_lock(&chip->mutex);
956 r = set_beacon_interval(chip, interval);
957 mutex_unlock(&chip->mutex);
958 return r;
959}
960
961static int hw_init(struct zd_chip *chip)
962{
963 int r;
964
965 dev_dbg_f(zd_chip_dev(chip), "\n");
966 ZD_ASSERT(mutex_is_locked(&chip->mutex));
967 r = hw_reset_phy(chip);
968 if (r)
969 return r;
970
971 r = hw_init_hmac(chip);
972 if (r)
973 return r;
98227a90
DD		 974
975 /* Although the vendor driver defaults to a different value during
976 * init, it overwrites the IFS value with the following every time
977 * the channel changes. We should aim to be more intelligent... */
978 r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
e85d0918
DD		 979 if (r)
980 return r;
98227a90
DD		 981
982 return set_beacon_interval(chip, 100);
e85d0918
DD		 983}
984
985#ifdef DEBUG
986static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
987 const char *addr_string)
988{
989 int r;
990 u32 value;
991
992 r = zd_ioread32_locked(chip, &value, addr);
993 if (r) {
994 dev_dbg_f(zd_chip_dev(chip),
995 "error reading %s. Error number %d\n", addr_string, r);
996 return r;
997 }
998
999 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
1000 addr_string, (unsigned int)value);
1001 return 0;
1002}
1003
1004static int test_init(struct zd_chip *chip)
1005{
1006 int r;
1007
1008 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1009 if (r)
1010 return r;
1011 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1012 if (r)
1013 return r;
1014 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1015}
1016
1017static void dump_fw_registers(struct zd_chip *chip)
1018{
1019 static const zd_addr_t addr[4] = {
1020 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
1021 FW_LINK_STATUS
1022 };
1023
1024 int r;
1025 u16 values[4];
1026
1027 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1028 ARRAY_SIZE(addr));
1029 if (r) {
1030 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1031 r);
1032 return;
1033 }
1034
1035 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1036 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1037 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1038 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1039}
1040#endif /* DEBUG */
1041
1042static int print_fw_version(struct zd_chip *chip)
1043{
1044 int r;
1045 u16 version;
1046
1047 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1048 if (r)
1049 return r;
1050
1051 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1052 return 0;
1053}
1054
1055static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1056{
1057 u32 rates;
1058 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1059 /* This sets the mandatory rates, which only depend from the standard
1060 * that the device is supporting. Until further notice we should try
1061 * to support 802.11g also for full speed USB.
1062 */
1063 switch (std) {
1064 case IEEE80211B:
1065 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1066 break;
1067 case IEEE80211G:
1068 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1069 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1070 break;
1071 default:
1072 return -EINVAL;
1073 }
1074 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1075}
1076
1077int zd_chip_enable_hwint(struct zd_chip *chip)
1078{
1079 int r;
1080
1081 mutex_lock(&chip->mutex);
1082 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1083 mutex_unlock(&chip->mutex);
1084 return r;
1085}
1086
1087static int disable_hwint(struct zd_chip *chip)
1088{
1089 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1090}
1091
1092int zd_chip_disable_hwint(struct zd_chip *chip)
1093{
1094 int r;
1095
1096 mutex_lock(&chip->mutex);
1097 r = disable_hwint(chip);
1098 mutex_unlock(&chip->mutex);
1099 return r;
1100}
1101
1102int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1103{
1104 int r;
1105 u8 rf_type;
1106
1107 dev_dbg_f(zd_chip_dev(chip), "\n");
1108
1109 mutex_lock(&chip->mutex);
1110 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1111
1112#ifdef DEBUG
1113 r = test_init(chip);
1114 if (r)
1115 goto out;
1116#endif
1117 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1118 if (r)
1119 goto out;
1120
1121 r = zd_usb_init_hw(&chip->usb);
1122 if (r)
1123 goto out;
1124
1125 /* GPI is always disabled, also in the other driver.
1126 */
1127 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1128 if (r)
1129 goto out;
1130 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1131 if (r)
1132 goto out;
1133 /* Currently we support IEEE 802.11g for full and high speed USB.
1134 * It might be discussed, whether we should suppport pure b mode for
1135 * full speed USB.
1136 */
1137 r = set_mandatory_rates(chip, IEEE80211G);
1138 if (r)
1139 goto out;
1140 /* Disabling interrupts is certainly a smart thing here.
1141 */
1142 r = disable_hwint(chip);
1143 if (r)
1144 goto out;
1145 r = read_pod(chip, &rf_type);
1146 if (r)
1147 goto out;
1148 r = hw_init(chip);
1149 if (r)
1150 goto out;
1151 r = zd_rf_init_hw(&chip->rf, rf_type);
1152 if (r)
1153 goto out;
1154
1155 r = print_fw_version(chip);
1156 if (r)
1157 goto out;
1158
1159#ifdef DEBUG
1160 dump_fw_registers(chip);
1161 r = test_init(chip);
1162 if (r)
1163 goto out;
1164#endif /* DEBUG */
1165
1166 r = read_e2p_mac_addr(chip);
1167 if (r)
1168 goto out;
1169
1170 r = read_cal_int_tables(chip);
1171 if (r)
1172 goto out;
1173
1174 print_id(chip);
1175out:
1176 mutex_unlock(&chip->mutex);
1177 return r;
1178}
1179
1180static int update_pwr_int(struct zd_chip *chip, u8 channel)
1181{
1182 u8 value = chip->pwr_int_values[channel - 1];
1183 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1184 channel, value);
1185 return zd_iowrite32_locked(chip, value, CR31);
1186}
1187
1188static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1189{
1190 u8 value = chip->pwr_cal_values[channel-1];
1191 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1192 channel, value);
1193 return zd_iowrite32_locked(chip, value, CR68);
1194}
1195
1196static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1197{
1198 struct zd_ioreq32 ioreqs[3];
1199
1200 ioreqs[0].addr = CR67;
1201 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1202 ioreqs[1].addr = CR66;
1203 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1204 ioreqs[2].addr = CR65;
1205 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1206
1207 dev_dbg_f(zd_chip_dev(chip),
1208 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1209 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1210 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1211}
1212
1213static int update_channel_integration_and_calibration(struct zd_chip *chip,
1214 u8 channel)
1215{
1216 int r;
1217
1218 r = update_pwr_int(chip, channel);
1219 if (r)
1220 return r;
1221 if (chip->is_zd1211b) {
1222 static const struct zd_ioreq32 ioreqs[] = {
1223 { CR69, 0x28 },
1224 {},
1225 { CR69, 0x2a },
1226 };
1227
1228 r = update_ofdm_cal(chip, channel);
1229 if (r)
1230 return r;
1231 r = update_pwr_cal(chip, channel);
1232 if (r)
1233 return r;
1234 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1235 if (r)
1236 return r;
1237 }
1238
1239 return 0;
1240}
1241
1242/* The CCK baseband gain can be optionally patched by the EEPROM */
1243static int patch_cck_gain(struct zd_chip *chip)
1244{
1245 int r;
1246 u32 value;
1247
1248 if (!chip->patch_cck_gain)
1249 return 0;
1250
1251 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1252 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1253 if (r)
1254 return r;
1255 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1256 return zd_iowrite32_locked(chip, value & 0xff, CR47);
1257}
1258
1259int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1260{
1261 int r, t;
1262
1263 mutex_lock(&chip->mutex);
1264 r = zd_chip_lock_phy_regs(chip);
1265 if (r)
1266 goto out;
1267 r = zd_rf_set_channel(&chip->rf, channel);
1268 if (r)
1269 goto unlock;
1270 r = update_channel_integration_and_calibration(chip, channel);
1271 if (r)
1272 goto unlock;
1273 r = patch_cck_gain(chip);
1274 if (r)
1275 goto unlock;
1276 r = patch_6m_band_edge(chip, channel);
1277 if (r)
1278 goto unlock;
1279 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1280unlock:
1281 t = zd_chip_unlock_phy_regs(chip);
1282 if (t && !r)
1283 r = t;
1284out:
1285 mutex_unlock(&chip->mutex);
1286 return r;
1287}
1288
1289u8 zd_chip_get_channel(struct zd_chip *chip)
1290{
1291 u8 channel;
1292
1293 mutex_lock(&chip->mutex);
1294 channel = chip->rf.channel;
1295 mutex_unlock(&chip->mutex);
1296 return channel;
1297}
1298
1299static u16 led_mask(int led)
1300{
1301 switch (led) {
1302 case 1:
1303 return LED1;
1304 case 2:
1305 return LED2;
1306 default:
1307 return 0;
1308 }
1309}
1310
1311static int read_led_reg(struct zd_chip *chip, u16 *status)
1312{
1313 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1314 return zd_ioread16_locked(chip, status, CR_LED);
1315}
1316
1317static int write_led_reg(struct zd_chip *chip, u16 status)
1318{
1319 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1320 return zd_iowrite16_locked(chip, status, CR_LED);
1321}
1322
1323int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status)
1324{
1325 int r, ret;
1326 u16 mask = led_mask(led);
1327 u16 reg;
1328
1329 if (!mask)
1330 return -EINVAL;
1331 mutex_lock(&chip->mutex);
1332 r = read_led_reg(chip, &reg);
1333 if (r)
1334 return r;
1335 switch (status) {
1336 case LED_STATUS:
1337 return (reg & mask) ? LED_ON : LED_OFF;
1338 case LED_OFF:
1339 reg &= ~mask;
1340 ret = LED_OFF;
1341 break;
1342 case LED_FLIP:
1343 reg ^= mask;
1344 ret = (reg&mask) ? LED_ON : LED_OFF;
1345 break;
1346 case LED_ON:
1347 reg |= mask;
1348 ret = LED_ON;
1349 break;
1350 default:
1351 return -EINVAL;
1352 }
1353 r = write_led_reg(chip, reg);
1354 if (r) {
1355 ret = r;
1356 goto out;
1357 }
1358out:
1359 mutex_unlock(&chip->mutex);
1360 return r;
1361}
1362
1363int zd_chip_led_flip(struct zd_chip *chip, int led,
1364 const unsigned int *phases_msecs, unsigned int count)
1365{
1366 int i, r;
1367 enum led_status status;
1368
1369 r = zd_chip_led_status(chip, led, LED_STATUS);
1370 if (r)
1371 return r;
1372 status = r;
1373 for (i = 0; i < count; i++) {
1374 r = zd_chip_led_status(chip, led, LED_FLIP);
1375 if (r < 0)
1376 goto out;
1377 msleep(phases_msecs[i]);
1378 }
1379
1380out:
1381 zd_chip_led_status(chip, led, status);
1382 return r;
1383}
1384
1385int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1386{
1387 int r;
1388
1389 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1390 return -EINVAL;
1391
1392 mutex_lock(&chip->mutex);
1393 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1394 mutex_unlock(&chip->mutex);
1395 return r;
1396}
1397
1398static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1399{
1400 static const u16 constants[] = {
1401 715, 655, 585, 540, 470, 410, 360, 315,
1402 270, 235, 205, 175, 150, 125, 105, 85,
1403 65, 50, 40, 25, 15
1404 };
1405
1406 int i;
1407 u32 x;
1408
1409 /* It seems that their quality parameter is somehow per signal
1410 * and is now transferred per bit.
1411 */
1412 switch (rate) {
1413 case ZD_OFDM_RATE_6M:
1414 case ZD_OFDM_RATE_12M:
1415 case ZD_OFDM_RATE_24M:
1416 size *= 2;
1417 break;
1418 case ZD_OFDM_RATE_9M:
1419 case ZD_OFDM_RATE_18M:
1420 case ZD_OFDM_RATE_36M:
1421 case ZD_OFDM_RATE_54M:
1422 size *= 4;
1423 size /= 3;
1424 break;
1425 case ZD_OFDM_RATE_48M:
1426 size *= 3;
1427 size /= 2;
1428 break;
1429 default:
1430 return -EINVAL;
1431 }
1432
1433 x = (10000 * status_quality)/size;
1434 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1435 if (x > constants[i])
1436 break;
1437 }
1438
1439 return i;
1440}
1441
1442static unsigned int log10times100(unsigned int x)
1443{
1444 static const u8 log10[] = {
1445 0,
1446 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1447 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1448 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1449 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1450 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1451 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1452 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1453 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1454 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1455 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1456 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1457 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1458 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1459 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1460 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1461 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1462 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1463 223, 223, 223, 224, 224, 224, 224,
1464 };
1465
1466 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1467}
1468
1469enum {
1470 MAX_CCK_EVM_DB = 45,
1471};
1472
1473static int cck_evm_db(u8 status_quality)
1474{
1475 return (20 * log10times100(status_quality)) / 100;
1476}
1477
1478static int cck_snr_db(u8 status_quality)
1479{
1480 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1481 ZD_ASSERT(r >= 0);
1482 return r;
1483}
1484
1485static int rx_qual_db(const void *rx_frame, unsigned int size,
1486 const struct rx_status *status)
1487{
1488 return (status->frame_status&ZD_RX_OFDM) ?
1489 ofdm_qual_db(status->signal_quality_ofdm,
1490 zd_ofdm_plcp_header_rate(rx_frame),
1491 size) :
1492 cck_snr_db(status->signal_quality_cck);
1493}
1494
1495u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1496 const struct rx_status *status)
1497{
1498 int r = rx_qual_db(rx_frame, size, status);
1499 if (r < 0)
1500 r = 0;
1501 r = (r * 100) / 14;
1502 if (r > 100)
1503 r = 100;
1504 return r;
1505}
1506
1507u8 zd_rx_strength_percent(u8 rssi)
1508{
1509 int r = (rssi*100) / 30;
1510 if (r > 100)
1511 r = 100;
1512 return (u8) r;
1513}
1514
1515u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1516{
1517 static const u16 ofdm_rates[] = {
1518 [ZD_OFDM_RATE_6M] = 60,
1519 [ZD_OFDM_RATE_9M] = 90,
1520 [ZD_OFDM_RATE_12M] = 120,
1521 [ZD_OFDM_RATE_18M] = 180,
1522 [ZD_OFDM_RATE_24M] = 240,
1523 [ZD_OFDM_RATE_36M] = 360,
1524 [ZD_OFDM_RATE_48M] = 480,
1525 [ZD_OFDM_RATE_54M] = 540,
1526 };
1527 u16 rate;
1528 if (status->frame_status & ZD_RX_OFDM) {
1529 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1530 rate = ofdm_rates[ofdm_rate & 0xf];
1531 } else {
1532 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1533 switch (cck_rate) {
1534 case ZD_CCK_SIGNAL_1M:
1535 rate = 10;
1536 break;
1537 case ZD_CCK_SIGNAL_2M:
1538 rate = 20;
1539 break;
1540 case ZD_CCK_SIGNAL_5M5:
1541 rate = 55;
1542 break;
1543 case ZD_CCK_SIGNAL_11M:
1544 rate = 110;
1545 break;
1546 default:
1547 rate = 0;
1548 }
1549 }
1550
1551 return rate;
1552}
1553
1554int zd_chip_switch_radio_on(struct zd_chip *chip)
1555{
1556 int r;
1557
1558 mutex_lock(&chip->mutex);
1559 r = zd_switch_radio_on(&chip->rf);
1560 mutex_unlock(&chip->mutex);
1561 return r;
1562}
1563
1564int zd_chip_switch_radio_off(struct zd_chip *chip)
1565{
1566 int r;
1567
1568 mutex_lock(&chip->mutex);
1569 r = zd_switch_radio_off(&chip->rf);
1570 mutex_unlock(&chip->mutex);
1571 return r;
1572}
1573
1574int zd_chip_enable_int(struct zd_chip *chip)
1575{
1576 int r;
1577
1578 mutex_lock(&chip->mutex);
1579 r = zd_usb_enable_int(&chip->usb);
1580 mutex_unlock(&chip->mutex);
1581 return r;
1582}
1583
1584void zd_chip_disable_int(struct zd_chip *chip)
1585{
1586 mutex_lock(&chip->mutex);
1587 zd_usb_disable_int(&chip->usb);
1588 mutex_unlock(&chip->mutex);
1589}
1590
1591int zd_chip_enable_rx(struct zd_chip *chip)
1592{
1593 int r;
1594
1595 mutex_lock(&chip->mutex);
1596 r = zd_usb_enable_rx(&chip->usb);
1597 mutex_unlock(&chip->mutex);
1598 return r;
1599}
1600
1601void zd_chip_disable_rx(struct zd_chip *chip)
1602{
1603 mutex_lock(&chip->mutex);
1604 zd_usb_disable_rx(&chip->usb);
1605 mutex_unlock(&chip->mutex);
1606}
1607
1608int zd_rfwritev_locked(struct zd_chip *chip,
1609 const u32* values, unsigned int count, u8 bits)
1610{
1611 int r;
1612 unsigned int i;
1613
1614 for (i = 0; i < count; i++) {
1615 r = zd_rfwrite_locked(chip, values[i], bits);
1616 if (r)
1617 return r;
1618 }
1619
1620 return 0;
1621}
20fe2176
DD		 1622
1623/*
1624 * We can optionally program the RF directly through CR regs, if supported by
1625 * the hardware. This is much faster than the older method.
1626 */
ec62bd91 1627int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
20fe2176
DD		 1628{
1629 struct zd_ioreq16 ioreqs[] = {
1630 { CR244, (value >> 16) & 0xff },
1631 { CR243, (value >> 8) & 0xff },
1632 { CR242, value & 0xff },
1633 };
1634 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1635 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1636}
1637
1638int zd_rfwritev_cr_locked(struct zd_chip *chip,
1639 const u32 *values, unsigned int count)
1640{
1641 int r;
1642 unsigned int i;
1643
1644 for (i = 0; i < count; i++) {
1645 r = zd_rfwrite_cr_locked(chip, values[i]);
1646 if (r)
1647 return r;
1648 }
1649
1650 return 0;
1651}
1652
Linux kernel - Deliverables
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