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iwlwifi: remove twice defined CSR register
[deliverable/linux.git] / drivers / net / wireless / zd1211rw / zd_chip.c
CommitLineData
66bb42fd
DD		 1/* ZD1211 USB-WLAN driver for Linux
2 *
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
e85d0918
DD		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
24 */
25
26#include <linux/kernel.h>
27#include <linux/errno.h>
28
29#include "zd_def.h"
30#include "zd_chip.h"
31#include "zd_ieee80211.h"
32#include "zd_mac.h"
33#include "zd_rf.h"
e85d0918
DD		 34
35void zd_chip_init(struct zd_chip *chip,
459c51ad 36 struct ieee80211_hw *hw,
e85d0918
DD		 37 struct usb_interface *intf)
38{
39 memset(chip, 0, sizeof(*chip));
40 mutex_init(&chip->mutex);
459c51ad 41 zd_usb_init(&chip->usb, hw, intf);
e85d0918
DD		 42 zd_rf_init(&chip->rf);
43}
44
45void zd_chip_clear(struct zd_chip *chip)
46{
c48cf125 47 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
e85d0918
DD		 48 zd_usb_clear(&chip->usb);
49 zd_rf_clear(&chip->rf);
e85d0918 50 mutex_destroy(&chip->mutex);
c48cf125 51 ZD_MEMCLEAR(chip, sizeof(*chip));
e85d0918
DD		 52}
53
74553aed 54static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
e85d0918 55{
459c51ad 56 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
e85d0918
DD		 57 return scnprintf(buffer, size, "%02x-%02x-%02x",
58 addr[0], addr[1], addr[2]);
59}
60
61/* Prints an identifier line, which will support debugging. */
62static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
63{
64 int i = 0;
65
66 i = scnprintf(buffer, size, "zd1211%s chip ",
74553aed 67 zd_chip_is_zd1211b(chip) ? "b" : "");
e85d0918
DD		 68 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
74553aed 70 i += scnprint_mac_oui(chip, buffer+i, size-i);
e85d0918
DD		 71 i += scnprintf(buffer+i, size-i, " ");
72 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
f2a81a16 73 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
e85d0918
DD		 74 chip->patch_cck_gain ? 'g' : '-',
75 chip->patch_cr157 ? '7' : '-',
20fe2176 76 chip->patch_6m_band_edge ? '6' : '-',
f2a81a16
DD		 77 chip->new_phy_layout ? 'N' : '-',
78 chip->al2230s_bit ? 'S' : '-');
e85d0918
DD		 79 return i;
80}
81
82static void print_id(struct zd_chip *chip)
83{
84 char buffer[80];
85
86 scnprint_id(chip, buffer, sizeof(buffer));
87 buffer[sizeof(buffer)-1] = 0;
88 dev_info(zd_chip_dev(chip), "%s\n", buffer);
89}
90
0ce34bc8
DD		 91static zd_addr_t inc_addr(zd_addr_t addr)
92{
93 u16 a = (u16)addr;
94 /* Control registers use byte addressing, but everything else uses word
95 * addressing. */
96 if ((a & 0xf000) == CR_START)
97 a += 2;
98 else
99 a += 1;
100 return (zd_addr_t)a;
101}
102
e85d0918
DD		 103/* Read a variable number of 32-bit values. Parameter count is not allowed to
104 * exceed USB_MAX_IOREAD32_COUNT.
105 */
106int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
107 unsigned int count)
108{
109 int r;
110 int i;
fa46081c 111 zd_addr_t *a16;
e85d0918
DD		 112 u16 *v16;
113 unsigned int count16;
114
115 if (count > USB_MAX_IOREAD32_COUNT)
116 return -EINVAL;
117
118 /* Allocate a single memory block for values and addresses. */
119 count16 = 2*count;
44956855 120 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
35c3404e 121 GFP_KERNEL);
e85d0918
DD		 122 if (!a16) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error ENOMEM in allocation of a16\n");
125 r = -ENOMEM;
126 goto out;
127 }
128 v16 = (u16 *)(a16 + count16);
129
130 for (i = 0; i < count; i++) {
131 int j = 2*i;
132 /* We read the high word always first. */
0ce34bc8 133 a16[j] = inc_addr(addr[i]);
e85d0918
DD		 134 a16[j+1] = addr[i];
135 }
136
137 r = zd_ioread16v_locked(chip, v16, a16, count16);
138 if (r) {
139 dev_dbg_f(zd_chip_dev(chip),
140 "error: zd_ioread16v_locked. Error number %d\n", r);
141 goto out;
142 }
143
144 for (i = 0; i < count; i++) {
145 int j = 2*i;
146 values[i] = (v16[j] << 16) | v16[j+1];
147 }
148
149out:
150 kfree((void *)a16);
151 return r;
152}
153
154int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
155 unsigned int count)
156{
157 int i, j, r;
158 struct zd_ioreq16 *ioreqs16;
159 unsigned int count16;
160
161 ZD_ASSERT(mutex_is_locked(&chip->mutex));
162
163 if (count == 0)
164 return 0;
165 if (count > USB_MAX_IOWRITE32_COUNT)
166 return -EINVAL;
167
168 /* Allocate a single memory block for values and addresses. */
169 count16 = 2*count;
35c3404e 170 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
e85d0918
DD		 171 if (!ioreqs16) {
172 r = -ENOMEM;
173 dev_dbg_f(zd_chip_dev(chip),
174 "error %d in ioreqs16 allocation\n", r);
175 goto out;
176 }
177
178 for (i = 0; i < count; i++) {
179 j = 2*i;
180 /* We write the high word always first. */
181 ioreqs16[j].value = ioreqs[i].value >> 16;
0ce34bc8 182 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
e85d0918
DD		 183 ioreqs16[j+1].value = ioreqs[i].value;
184 ioreqs16[j+1].addr = ioreqs[i].addr;
185 }
186
187 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
188#ifdef DEBUG
189 if (r) {
190 dev_dbg_f(zd_chip_dev(chip),
191 "error %d in zd_usb_write16v\n", r);
192 }
193#endif /* DEBUG */
194out:
195 kfree(ioreqs16);
196 return r;
197}
198
199int zd_iowrite16a_locked(struct zd_chip *chip,
200 const struct zd_ioreq16 *ioreqs, unsigned int count)
201{
202 int r;
203 unsigned int i, j, t, max;
204
205 ZD_ASSERT(mutex_is_locked(&chip->mutex));
206 for (i = 0; i < count; i += j + t) {
207 t = 0;
208 max = count-i;
209 if (max > USB_MAX_IOWRITE16_COUNT)
210 max = USB_MAX_IOWRITE16_COUNT;
211 for (j = 0; j < max; j++) {
212 if (!ioreqs[i+j].addr) {
213 t = 1;
214 break;
215 }
216 }
217
218 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
219 if (r) {
220 dev_dbg_f(zd_chip_dev(chip),
221 "error zd_usb_iowrite16v. Error number %d\n",
222 r);
223 return r;
224 }
225 }
226
227 return 0;
228}
229
230/* Writes a variable number of 32 bit registers. The functions will split
231 * that in several USB requests. A split can be forced by inserting an IO
232 * request with an zero address field.
233 */
234int zd_iowrite32a_locked(struct zd_chip *chip,
235 const struct zd_ioreq32 *ioreqs, unsigned int count)
236{
237 int r;
238 unsigned int i, j, t, max;
239
240 for (i = 0; i < count; i += j + t) {
241 t = 0;
242 max = count-i;
243 if (max > USB_MAX_IOWRITE32_COUNT)
244 max = USB_MAX_IOWRITE32_COUNT;
245 for (j = 0; j < max; j++) {
246 if (!ioreqs[i+j].addr) {
247 t = 1;
248 break;
249 }
250 }
251
252 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
253 if (r) {
254 dev_dbg_f(zd_chip_dev(chip),
255 "error _zd_iowrite32v_locked."
256 " Error number %d\n", r);
257 return r;
258 }
259 }
260
261 return 0;
262}
263
264int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
265{
266 int r;
267
e85d0918
DD		 268 mutex_lock(&chip->mutex);
269 r = zd_ioread16_locked(chip, value, addr);
270 mutex_unlock(&chip->mutex);
271 return r;
272}
273
274int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
275{
276 int r;
277
e85d0918
DD		 278 mutex_lock(&chip->mutex);
279 r = zd_ioread32_locked(chip, value, addr);
280 mutex_unlock(&chip->mutex);
281 return r;
282}
283
284int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
285{
286 int r;
287
e85d0918
DD		 288 mutex_lock(&chip->mutex);
289 r = zd_iowrite16_locked(chip, value, addr);
290 mutex_unlock(&chip->mutex);
291 return r;
292}
293
294int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
295{
296 int r;
297
e85d0918
DD		 298 mutex_lock(&chip->mutex);
299 r = zd_iowrite32_locked(chip, value, addr);
300 mutex_unlock(&chip->mutex);
301 return r;
302}
303
304int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
305 u32 *values, unsigned int count)
306{
307 int r;
308
e85d0918
DD		 309 mutex_lock(&chip->mutex);
310 r = zd_ioread32v_locked(chip, values, addresses, count);
311 mutex_unlock(&chip->mutex);
312 return r;
313}
314
315int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
316 unsigned int count)
317{
318 int r;
319
e85d0918
DD		 320 mutex_lock(&chip->mutex);
321 r = zd_iowrite32a_locked(chip, ioreqs, count);
322 mutex_unlock(&chip->mutex);
323 return r;
324}
325
326static int read_pod(struct zd_chip *chip, u8 *rf_type)
327{
328 int r;
329 u32 value;
330
331 ZD_ASSERT(mutex_is_locked(&chip->mutex));
332 r = zd_ioread32_locked(chip, &value, E2P_POD);
333 if (r)
334 goto error;
335 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
336
337 /* FIXME: AL2230 handling (Bit 7 in POD) */
338 *rf_type = value & 0x0f;
339 chip->pa_type = (value >> 16) & 0x0f;
340 chip->patch_cck_gain = (value >> 8) & 0x1;
341 chip->patch_cr157 = (value >> 13) & 0x1;
342 chip->patch_6m_band_edge = (value >> 21) & 0x1;
20fe2176 343 chip->new_phy_layout = (value >> 31) & 0x1;
ae6ead46 344 chip->al2230s_bit = (value >> 7) & 0x1;
583afd1e
UK		 345 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
346 chip->supports_tx_led = 1;
347 if (value & (1 << 24)) { /* LED scenario */
348 if (value & (1 << 29))
349 chip->supports_tx_led = 0;
350 }
e85d0918
DD		 351
352 dev_dbg_f(zd_chip_dev(chip),
353 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
583afd1e 354 "patch 6M %d new PHY %d link LED%d tx led %d\n",
e85d0918
DD		 355 zd_rf_name(*rf_type), *rf_type,
356 chip->pa_type, chip->patch_cck_gain,
583afd1e
UK		 357 chip->patch_cr157, chip->patch_6m_band_edge,
358 chip->new_phy_layout,
359 chip->link_led == LED1 ? 1 : 2,
360 chip->supports_tx_led);
e85d0918
DD		 361 return 0;
362error:
363 *rf_type = 0;
364 chip->pa_type = 0;
365 chip->patch_cck_gain = 0;
366 chip->patch_cr157 = 0;
367 chip->patch_6m_band_edge = 0;
20fe2176 368 chip->new_phy_layout = 0;
e85d0918
DD		 369 return r;
370}
371
e85d0918
DD		 372/* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
373 * CR_MAC_ADDR_P2 must be overwritten
374 */
e85d0918
DD		 375int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
376{
377 int r;
378 struct zd_ioreq32 reqs[2] = {
379 [0] = { .addr = CR_MAC_ADDR_P1 },
380 [1] = { .addr = CR_MAC_ADDR_P2 },
381 };
0795af57 382 DECLARE_MAC_BUF(mac);
e85d0918 383
459c51ad
DD		 384 if (mac_addr) {
385 reqs[0].value = (mac_addr[3] << 24)
386 | (mac_addr[2] << 16)
387 | (mac_addr[1] << 8)
388 | mac_addr[0];
389 reqs[1].value = (mac_addr[5] << 8)
390 | mac_addr[4];
391 dev_dbg_f(zd_chip_dev(chip),
392 "mac addr %s\n", print_mac(mac, mac_addr));
393 } else {
394 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
395 }
e85d0918
DD		 396
397 mutex_lock(&chip->mutex);
398 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
e85d0918
DD		 399 mutex_unlock(&chip->mutex);
400 return r;
401}
402
403int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
404{
405 int r;
406 u32 value;
407
408 mutex_lock(&chip->mutex);
409 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
410 mutex_unlock(&chip->mutex);
411 if (r)
412 return r;
413
414 *regdomain = value >> 16;
415 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
416
417 return 0;
418}
419
420static int read_values(struct zd_chip *chip, u8 *values, size_t count,
421 zd_addr_t e2p_addr, u32 guard)
422{
423 int r;
424 int i;
425 u32 v;
426
427 ZD_ASSERT(mutex_is_locked(&chip->mutex));
428 for (i = 0;;) {
0ce34bc8
DD		 429 r = zd_ioread32_locked(chip, &v,
430 (zd_addr_t)((u16)e2p_addr+i/2));
e85d0918
DD		 431 if (r)
432 return r;
433 v -= guard;
434 if (i+4 < count) {
435 values[i++] = v;
436 values[i++] = v >> 8;
437 values[i++] = v >> 16;
438 values[i++] = v >> 24;
439 continue;
440 }
441 for (;i < count; i++)
442 values[i] = v >> (8*(i%3));
443 return 0;
444 }
445}
446
447static int read_pwr_cal_values(struct zd_chip *chip)
448{
449 return read_values(chip, chip->pwr_cal_values,
450 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
451 0);
452}
453
454static int read_pwr_int_values(struct zd_chip *chip)
455{
456 return read_values(chip, chip->pwr_int_values,
457 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
458 E2P_PWR_INT_GUARD);
459}
460
461static int read_ofdm_cal_values(struct zd_chip *chip)
462{
463 int r;
464 int i;
465 static const zd_addr_t addresses[] = {
466 E2P_36M_CAL_VALUE1,
467 E2P_48M_CAL_VALUE1,
468 E2P_54M_CAL_VALUE1,
469 };
470
471 for (i = 0; i < 3; i++) {
472 r = read_values(chip, chip->ofdm_cal_values[i],
473 E2P_CHANNEL_COUNT, addresses[i], 0);
474 if (r)
475 return r;
476 }
477 return 0;
478}
479
480static int read_cal_int_tables(struct zd_chip *chip)
481{
482 int r;
483
484 r = read_pwr_cal_values(chip);
485 if (r)
486 return r;
487 r = read_pwr_int_values(chip);
488 if (r)
489 return r;
490 r = read_ofdm_cal_values(chip);
491 if (r)
492 return r;
493 return 0;
494}
495
496/* phy means physical registers */
497int zd_chip_lock_phy_regs(struct zd_chip *chip)
498{
499 int r;
500 u32 tmp;
501
502 ZD_ASSERT(mutex_is_locked(&chip->mutex));
503 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
504 if (r) {
505 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
506 return r;
507 }
508
e85d0918
DD		 509 tmp &= ~UNLOCK_PHY_REGS;
510
511 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
512 if (r)
513 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
514 return r;
515}
516
517int zd_chip_unlock_phy_regs(struct zd_chip *chip)
518{
519 int r;
520 u32 tmp;
521
522 ZD_ASSERT(mutex_is_locked(&chip->mutex));
523 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
524 if (r) {
525 dev_err(zd_chip_dev(chip),
526 "error ioread32(CR_REG1): %d\n", r);
527 return r;
528 }
529
e85d0918
DD		 530 tmp |= UNLOCK_PHY_REGS;
531
532 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
533 if (r)
534 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
535 return r;
536}
537
92b3e2e9 538/* CR157 can be optionally patched by the EEPROM for original ZD1211 */
e85d0918
DD		 539static int patch_cr157(struct zd_chip *chip)
540{
541 int r;
92b3e2e9 542 u16 value;
e85d0918
DD		 543
544 if (!chip->patch_cr157)
545 return 0;
546
92b3e2e9 547 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
e85d0918
DD		 548 if (r)
549 return r;
550
551 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
552 return zd_iowrite32_locked(chip, value >> 8, CR157);
553}
554
555/*
556 * 6M band edge can be optionally overwritten for certain RF's
557 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
558 * bit (for AL2230, AL2230S)
559 */
72018b22
DD		 560static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
561{
562 ZD_ASSERT(mutex_is_locked(&chip->mutex));
563 if (!chip->patch_6m_band_edge)
564 return 0;
565
566 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
567}
568
569/* Generic implementation of 6M band edge patching, used by most RFs via
570 * zd_rf_generic_patch_6m() */
571int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
e85d0918
DD		 572{
573 struct zd_ioreq16 ioreqs[] = {
574 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
575 { CR47, 0x1e },
576 };
577
e85d0918
DD		 578 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
579 if (channel == 1 || channel == 11)
580 ioreqs[0].value = 0x12;
581
582 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
583 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
584}
585
586static int zd1211_hw_reset_phy(struct zd_chip *chip)
587{
588 static const struct zd_ioreq16 ioreqs[] = {
589 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
590 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
591 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
592 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
593 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
594 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
595 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
596 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
597 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
598 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
599 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
600 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
601 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
602 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
603 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
604 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
605 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
606 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
607 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
608 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
609 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
610 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
611 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
612 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
613 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
614 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
615 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
616 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
617 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
618 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
619 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
620 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
621 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
622 { },
623 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
624 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
625 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
626 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
627 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
628 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
629 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
630 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
631 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
632 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
633 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
634 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
635 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
636 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
dc536a70
DD		 637 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
638 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
639 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
640 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
641 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
642 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
643 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
644 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
645 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
646 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
647 { CR170, 0xba }, { CR171, 0xba },
e85d0918
DD		 648 /* Note: CR204 must lead the CR203 */
649 { CR204, 0x7d },
650 { },
651 { CR203, 0x30 },
652 };
653
654 int r, t;
655
656 dev_dbg_f(zd_chip_dev(chip), "\n");
657
658 r = zd_chip_lock_phy_regs(chip);
659 if (r)
660 goto out;
661
662 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
663 if (r)
664 goto unlock;
665
666 r = patch_cr157(chip);
667unlock:
668 t = zd_chip_unlock_phy_regs(chip);
669 if (t && !r)
670 r = t;
671out:
672 return r;
673}
674
675static int zd1211b_hw_reset_phy(struct zd_chip *chip)
676{
677 static const struct zd_ioreq16 ioreqs[] = {
678 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
679 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
680 { CR10, 0x81 },
681 /* power control { { CR11, 1 << 6 }, */
682 { CR11, 0x00 },
683 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
684 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
685 { CR18, 0x0a }, { CR19, 0x48 },
686 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
687 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
688 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
689 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
fe7215ca 690 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
e85d0918
DD		 691 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
692 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
693 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
694 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
695 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
696 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
697 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
698 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
699 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
700 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
701 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
702 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
703 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
704 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
705 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
706 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
707 { CR94, 0x01 },
708 { CR95, 0x20 }, /* ZD1211B */
709 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
710 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
711 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
712 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
713 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
714 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
715 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
716 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
717 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
718 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
719 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
720 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
721 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
722 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
723 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
724 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
725 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
726 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
727 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
728 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
729 { CR170, 0xba }, { CR171, 0xba },
730 /* Note: CR204 must lead the CR203 */
731 { CR204, 0x7d },
732 {},
733 { CR203, 0x30 },
734 };
735
736 int r, t;
737
738 dev_dbg_f(zd_chip_dev(chip), "\n");
739
740 r = zd_chip_lock_phy_regs(chip);
741 if (r)
742 goto out;
743
744 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 745 t = zd_chip_unlock_phy_regs(chip);
746 if (t && !r)
747 r = t;
748out:
749 return r;
750}
751
752static int hw_reset_phy(struct zd_chip *chip)
753{
74553aed 754 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
e85d0918
DD		 755 zd1211_hw_reset_phy(chip);
756}
757
758static int zd1211_hw_init_hmac(struct zd_chip *chip)
759{
760 static const struct zd_ioreq32 ioreqs[] = {
e85d0918 761 { CR_ZD1211_RETRY_MAX, 0x2 },
e85d0918 762 { CR_RX_THRESHOLD, 0x000c0640 },
e85d0918
DD		 763 };
764
e85d0918
DD		 765 dev_dbg_f(zd_chip_dev(chip), "\n");
766 ZD_ASSERT(mutex_is_locked(&chip->mutex));
34c44912 767 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 768}
769
770static int zd1211b_hw_init_hmac(struct zd_chip *chip)
771{
772 static const struct zd_ioreq32 ioreqs[] = {
e85d0918
DD		 773 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
774 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
775 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
776 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
777 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
778 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
779 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
780 { CR_ZD1211B_TXOP, 0x01800824 },
34c44912
DD		 781 { CR_RX_THRESHOLD, 0x000c0eff, },
782 };
783
784 dev_dbg_f(zd_chip_dev(chip), "\n");
785 ZD_ASSERT(mutex_is_locked(&chip->mutex));
786 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
787}
788
789static int hw_init_hmac(struct zd_chip *chip)
790{
791 int r;
792 static const struct zd_ioreq32 ioreqs[] = {
793 { CR_ACK_TIMEOUT_EXT, 0x20 },
794 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
e85d0918 795 { CR_SNIFFER_ON, 0 },
fde627b5 796 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 797 { CR_GROUP_HASH_P1, 0x00 },
798 { CR_GROUP_HASH_P2, 0x80000000 },
799 { CR_REG1, 0xa4 },
800 { CR_ADDA_PWR_DWN, 0x7f },
801 { CR_BCN_PLCP_CFG, 0x00f00401 },
802 { CR_PHY_DELAY, 0x00 },
803 { CR_ACK_TIMEOUT_EXT, 0x80 },
804 { CR_ADDA_PWR_DWN, 0x00 },
805 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 806 { CR_RX_PE_DELAY, 0x70 },
807 { CR_PS_CTRL, 0x10000000 },
808 { CR_RTS_CTS_RATE, 0x02030203 },
e85d0918
DD		 809 { CR_AFTER_PNP, 0x1 },
810 { CR_WEP_PROTECT, 0x114 },
34c44912 811 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
e85d0918
DD		 812 };
813
e85d0918
DD		 814 ZD_ASSERT(mutex_is_locked(&chip->mutex));
815 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
34c44912
DD		 816 if (r)
817 return r;
e85d0918 818
74553aed 819 return zd_chip_is_zd1211b(chip) ?
e85d0918
DD		 820 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
821}
822
823struct aw_pt_bi {
824 u32 atim_wnd_period;
825 u32 pre_tbtt;
826 u32 beacon_interval;
827};
828
829static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
830{
831 int r;
832 static const zd_addr_t aw_pt_bi_addr[] =
833 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
834 u32 values[3];
835
836 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
837 ARRAY_SIZE(aw_pt_bi_addr));
838 if (r) {
839 memset(s, 0, sizeof(*s));
840 return r;
841 }
842
843 s->atim_wnd_period = values[0];
844 s->pre_tbtt = values[1];
845 s->beacon_interval = values[2];
e85d0918
DD		 846 return 0;
847}
848
849static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
850{
851 struct zd_ioreq32 reqs[3];
852
853 if (s->beacon_interval <= 5)
854 s->beacon_interval = 5;
855 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
856 s->pre_tbtt = s->beacon_interval - 1;
857 if (s->atim_wnd_period >= s->pre_tbtt)
858 s->atim_wnd_period = s->pre_tbtt - 1;
859
860 reqs[0].addr = CR_ATIM_WND_PERIOD;
861 reqs[0].value = s->atim_wnd_period;
862 reqs[1].addr = CR_PRE_TBTT;
863 reqs[1].value = s->pre_tbtt;
864 reqs[2].addr = CR_BCN_INTERVAL;
865 reqs[2].value = s->beacon_interval;
866
e85d0918
DD		 867 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
868}
869
870
871static int set_beacon_interval(struct zd_chip *chip, u32 interval)
872{
873 int r;
874 struct aw_pt_bi s;
875
876 ZD_ASSERT(mutex_is_locked(&chip->mutex));
877 r = get_aw_pt_bi(chip, &s);
878 if (r)
879 return r;
880 s.beacon_interval = interval;
881 return set_aw_pt_bi(chip, &s);
882}
883
884int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
885{
886 int r;
887
888 mutex_lock(&chip->mutex);
889 r = set_beacon_interval(chip, interval);
890 mutex_unlock(&chip->mutex);
891 return r;
892}
893
894static int hw_init(struct zd_chip *chip)
895{
896 int r;
897
898 dev_dbg_f(zd_chip_dev(chip), "\n");
899 ZD_ASSERT(mutex_is_locked(&chip->mutex));
900 r = hw_reset_phy(chip);
901 if (r)
902 return r;
903
904 r = hw_init_hmac(chip);
905 if (r)
906 return r;
98227a90 907
98227a90 908 return set_beacon_interval(chip, 100);
e85d0918
DD		 909}
910
0ce34bc8
DD		 911static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
912{
913 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
914}
915
e85d0918
DD		 916#ifdef DEBUG
917static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
918 const char *addr_string)
919{
920 int r;
921 u32 value;
922
923 r = zd_ioread32_locked(chip, &value, addr);
924 if (r) {
925 dev_dbg_f(zd_chip_dev(chip),
926 "error reading %s. Error number %d\n", addr_string, r);
927 return r;
928 }
929
930 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
931 addr_string, (unsigned int)value);
932 return 0;
933}
934
935static int test_init(struct zd_chip *chip)
936{
937 int r;
938
939 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
940 if (r)
941 return r;
942 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
943 if (r)
944 return r;
945 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
946}
947
948static void dump_fw_registers(struct zd_chip *chip)
949{
0ce34bc8
DD		 950 const zd_addr_t addr[4] = {
951 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
952 fw_reg_addr(chip, FW_REG_USB_SPEED),
953 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
954 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
e85d0918
DD		 955 };
956
957 int r;
958 u16 values[4];
959
960 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
961 ARRAY_SIZE(addr));
962 if (r) {
963 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
964 r);
965 return;
966 }
967
968 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
969 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
970 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
971 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
972}
973#endif /* DEBUG */
974
975static int print_fw_version(struct zd_chip *chip)
976{
977 int r;
978 u16 version;
979
0ce34bc8
DD		 980 r = zd_ioread16_locked(chip, &version,
981 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
e85d0918
DD		 982 if (r)
983 return r;
984
985 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
986 return 0;
987}
988
8318d78a 989static int set_mandatory_rates(struct zd_chip *chip, int gmode)
e85d0918
DD		 990{
991 u32 rates;
992 ZD_ASSERT(mutex_is_locked(&chip->mutex));
993 /* This sets the mandatory rates, which only depend from the standard
994 * that the device is supporting. Until further notice we should try
995 * to support 802.11g also for full speed USB.
996 */
8318d78a 997 if (!gmode)
e85d0918 998 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
8318d78a 999 else
e85d0918
DD		 1000 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1001 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
8318d78a 1002
e85d0918
DD		 1003 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1004}
1005
b1382ede 1006int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
459c51ad 1007 int preamble)
b1382ede 1008{
b1382ede
DD		 1009 u32 value = 0;
1010
459c51ad 1011 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
b1382ede
DD		 1012 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1013 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1014
459c51ad
DD		 1015 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1016 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1017 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
64f222cc 1018 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
b1382ede
DD		 1019 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1020
1021 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1022}
1023
e85d0918
DD		 1024int zd_chip_enable_hwint(struct zd_chip *chip)
1025{
1026 int r;
1027
1028 mutex_lock(&chip->mutex);
1029 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1030 mutex_unlock(&chip->mutex);
1031 return r;
1032}
1033
1034static int disable_hwint(struct zd_chip *chip)
1035{
1036 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1037}
1038
1039int zd_chip_disable_hwint(struct zd_chip *chip)
1040{
1041 int r;
1042
1043 mutex_lock(&chip->mutex);
1044 r = disable_hwint(chip);
1045 mutex_unlock(&chip->mutex);
1046 return r;
1047}
1048
0ce34bc8
DD		 1049static int read_fw_regs_offset(struct zd_chip *chip)
1050{
1051 int r;
1052
1053 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1054 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1055 FWRAW_REGS_ADDR);
1056 if (r)
1057 return r;
1058 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1059 (u16)chip->fw_regs_base);
1060
1061 return 0;
1062}
1063
74553aed
DD		 1064/* Read mac address using pre-firmware interface */
1065int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1066{
1067 dev_dbg_f(zd_chip_dev(chip), "\n");
1068 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1069 ETH_ALEN);
1070}
0ce34bc8 1071
74553aed 1072int zd_chip_init_hw(struct zd_chip *chip)
e85d0918
DD		 1073{
1074 int r;
1075 u8 rf_type;
1076
1077 dev_dbg_f(zd_chip_dev(chip), "\n");
1078
1079 mutex_lock(&chip->mutex);
e85d0918
DD		 1080
1081#ifdef DEBUG
1082 r = test_init(chip);
1083 if (r)
1084 goto out;
1085#endif
1086 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1087 if (r)
1088 goto out;
1089
0ce34bc8 1090 r = read_fw_regs_offset(chip);
e85d0918
DD		 1091 if (r)
1092 goto out;
1093
1094 /* GPI is always disabled, also in the other driver.
1095 */
1096 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1097 if (r)
1098 goto out;
1099 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1100 if (r)
1101 goto out;
1102 /* Currently we support IEEE 802.11g for full and high speed USB.
1103 * It might be discussed, whether we should suppport pure b mode for
1104 * full speed USB.
1105 */
8318d78a 1106 r = set_mandatory_rates(chip, 1);
e85d0918
DD		 1107 if (r)
1108 goto out;
1109 /* Disabling interrupts is certainly a smart thing here.
1110 */
1111 r = disable_hwint(chip);
1112 if (r)
1113 goto out;
1114 r = read_pod(chip, &rf_type);
1115 if (r)
1116 goto out;
1117 r = hw_init(chip);
1118 if (r)
1119 goto out;
1120 r = zd_rf_init_hw(&chip->rf, rf_type);
1121 if (r)
1122 goto out;
1123
1124 r = print_fw_version(chip);
1125 if (r)
1126 goto out;
1127
1128#ifdef DEBUG
1129 dump_fw_registers(chip);
1130 r = test_init(chip);
1131 if (r)
1132 goto out;
1133#endif /* DEBUG */
1134
e85d0918
DD		 1135 r = read_cal_int_tables(chip);
1136 if (r)
1137 goto out;
1138
1139 print_id(chip);
1140out:
1141 mutex_unlock(&chip->mutex);
1142 return r;
1143}
1144
1145static int update_pwr_int(struct zd_chip *chip, u8 channel)
1146{
1147 u8 value = chip->pwr_int_values[channel - 1];
cbb5e6bb 1148 return zd_iowrite16_locked(chip, value, CR31);
e85d0918
DD		 1149}
1150
1151static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1152{
1153 u8 value = chip->pwr_cal_values[channel-1];
cbb5e6bb 1154 return zd_iowrite16_locked(chip, value, CR68);
e85d0918
DD		 1155}
1156
1157static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1158{
cbb5e6bb 1159 struct zd_ioreq16 ioreqs[3];
e85d0918
DD		 1160
1161 ioreqs[0].addr = CR67;
1162 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1163 ioreqs[1].addr = CR66;
1164 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1165 ioreqs[2].addr = CR65;
1166 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1167
cbb5e6bb 1168 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1169}
1170
1171static int update_channel_integration_and_calibration(struct zd_chip *chip,
1172 u8 channel)
1173{
1174 int r;
1175
9c8fc71d
DD		 1176 if (!zd_rf_should_update_pwr_int(&chip->rf))
1177 return 0;
1178
e85d0918
DD		 1179 r = update_pwr_int(chip, channel);
1180 if (r)
1181 return r;
74553aed 1182 if (zd_chip_is_zd1211b(chip)) {
cbb5e6bb 1183 static const struct zd_ioreq16 ioreqs[] = {
e85d0918
DD		 1184 { CR69, 0x28 },
1185 {},
1186 { CR69, 0x2a },
1187 };
1188
1189 r = update_ofdm_cal(chip, channel);
1190 if (r)
1191 return r;
1192 r = update_pwr_cal(chip, channel);
1193 if (r)
1194 return r;
cbb5e6bb 1195 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1196 if (r)
1197 return r;
1198 }
1199
1200 return 0;
1201}
1202
1203/* The CCK baseband gain can be optionally patched by the EEPROM */
1204static int patch_cck_gain(struct zd_chip *chip)
1205{
1206 int r;
1207 u32 value;
1208
aaf83d4f 1209 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
e85d0918
DD		 1210 return 0;
1211
1212 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1213 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1214 if (r)
1215 return r;
1216 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
cbb5e6bb 1217 return zd_iowrite16_locked(chip, value & 0xff, CR47);
e85d0918
DD		 1218}
1219
1220int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1221{
1222 int r, t;
1223
1224 mutex_lock(&chip->mutex);
1225 r = zd_chip_lock_phy_regs(chip);
1226 if (r)
1227 goto out;
1228 r = zd_rf_set_channel(&chip->rf, channel);
1229 if (r)
1230 goto unlock;
1231 r = update_channel_integration_and_calibration(chip, channel);
1232 if (r)
1233 goto unlock;
1234 r = patch_cck_gain(chip);
1235 if (r)
1236 goto unlock;
1237 r = patch_6m_band_edge(chip, channel);
1238 if (r)
1239 goto unlock;
1240 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1241unlock:
1242 t = zd_chip_unlock_phy_regs(chip);
1243 if (t && !r)
1244 r = t;
1245out:
1246 mutex_unlock(&chip->mutex);
1247 return r;
1248}
1249
1250u8 zd_chip_get_channel(struct zd_chip *chip)
1251{
1252 u8 channel;
1253
1254 mutex_lock(&chip->mutex);
1255 channel = chip->rf.channel;
1256 mutex_unlock(&chip->mutex);
1257 return channel;
1258}
1259
583afd1e 1260int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
e85d0918 1261{
0ce34bc8
DD		 1262 const zd_addr_t a[] = {
1263 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
583afd1e
UK		 1264 CR_LED,
1265 };
e85d0918 1266
583afd1e
UK		 1267 int r;
1268 u16 v[ARRAY_SIZE(a)];
1269 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
0ce34bc8 1270 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
583afd1e
UK		 1271 [1] = { CR_LED },
1272 };
1273 u16 other_led;
e85d0918 1274
e85d0918 1275 mutex_lock(&chip->mutex);
583afd1e 1276 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
e85d0918 1277 if (r)
583afd1e
UK		 1278 goto out;
1279
1280 other_led = chip->link_led == LED1 ? LED2 : LED1;
1281
e85d0918 1282 switch (status) {
e85d0918 1283 case LED_OFF:
583afd1e
UK		 1284 ioreqs[0].value = FW_LINK_OFF;
1285 ioreqs[1].value = v[1] & ~(LED1|LED2);
e85d0918 1286 break;
583afd1e
UK		 1287 case LED_SCANNING:
1288 ioreqs[0].value = FW_LINK_OFF;
1289 ioreqs[1].value = v[1] & ~other_led;
1290 if (get_seconds() % 3 == 0) {
1291 ioreqs[1].value &= ~chip->link_led;
1292 } else {
1293 ioreqs[1].value |= chip->link_led;
1294 }
e85d0918 1295 break;
583afd1e
UK		 1296 case LED_ASSOCIATED:
1297 ioreqs[0].value = FW_LINK_TX;
1298 ioreqs[1].value = v[1] & ~other_led;
1299 ioreqs[1].value |= chip->link_led;
e85d0918
DD		 1300 break;
1301 default:
583afd1e 1302 r = -EINVAL;
e85d0918
DD		 1303 goto out;
1304 }
e85d0918 1305
583afd1e
UK		 1306 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1307 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1308 if (r)
e85d0918 1309 goto out;
e85d0918 1310 }
583afd1e 1311 r = 0;
e85d0918 1312out:
583afd1e 1313 mutex_unlock(&chip->mutex);
e85d0918
DD		 1314 return r;
1315}
1316
459c51ad 1317int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
e85d0918 1318{
459c51ad
DD		 1319 int r;
1320
1321 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1322 return -EINVAL;
e85d0918 1323
459c51ad
DD		 1324 mutex_lock(&chip->mutex);
1325 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1326 mutex_unlock(&chip->mutex);
1327 return r;
e85d0918
DD		 1328}
1329
64f222cc 1330static int ofdm_qual_db(u8 status_quality, u8 zd_rate, unsigned int size)
e85d0918
DD		 1331{
1332 static const u16 constants[] = {
1333 715, 655, 585, 540, 470, 410, 360, 315,
1334 270, 235, 205, 175, 150, 125, 105, 85,
1335 65, 50, 40, 25, 15
1336 };
1337
1338 int i;
1339 u32 x;
1340
1341 /* It seems that their quality parameter is somehow per signal
1342 * and is now transferred per bit.
1343 */
64f222cc 1344 switch (zd_rate) {
e85d0918
DD		 1345 case ZD_OFDM_RATE_6M:
1346 case ZD_OFDM_RATE_12M:
1347 case ZD_OFDM_RATE_24M:
1348 size *= 2;
1349 break;
1350 case ZD_OFDM_RATE_9M:
1351 case ZD_OFDM_RATE_18M:
1352 case ZD_OFDM_RATE_36M:
1353 case ZD_OFDM_RATE_54M:
1354 size *= 4;
1355 size /= 3;
1356 break;
1357 case ZD_OFDM_RATE_48M:
1358 size *= 3;
1359 size /= 2;
1360 break;
1361 default:
1362 return -EINVAL;
1363 }
1364
1365 x = (10000 * status_quality)/size;
1366 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1367 if (x > constants[i])
1368 break;
1369 }
1370
64f222cc 1371 switch (zd_rate) {
db888aed
UK		 1372 case ZD_OFDM_RATE_6M:
1373 case ZD_OFDM_RATE_9M:
1374 i += 3;
1375 break;
1376 case ZD_OFDM_RATE_12M:
1377 case ZD_OFDM_RATE_18M:
1378 i += 5;
1379 break;
1380 case ZD_OFDM_RATE_24M:
1381 case ZD_OFDM_RATE_36M:
1382 i += 9;
1383 break;
1384 case ZD_OFDM_RATE_48M:
1385 case ZD_OFDM_RATE_54M:
1386 i += 15;
1387 break;
1388 default:
1389 return -EINVAL;
1390 }
1391
e85d0918
DD		 1392 return i;
1393}
1394
64f222cc 1395static int ofdm_qual_percent(u8 status_quality, u8 zd_rate, unsigned int size)
db888aed
UK		 1396{
1397 int r;
1398
64f222cc 1399 r = ofdm_qual_db(status_quality, zd_rate, size);
db888aed
UK		 1400 ZD_ASSERT(r >= 0);
1401 if (r < 0)
1402 r = 0;
1403
1404 r = (r * 100)/29;
1405 return r <= 100 ? r : 100;
1406}
1407
e85d0918
DD		 1408static unsigned int log10times100(unsigned int x)
1409{
1410 static const u8 log10[] = {
1411 0,
1412 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1413 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1414 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1415 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1416 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1417 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1418 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1419 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1420 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1421 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1422 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1423 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1424 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1425 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1426 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1427 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1428 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1429 223, 223, 223, 224, 224, 224, 224,
1430 };
1431
1432 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1433}
1434
1435enum {
1436 MAX_CCK_EVM_DB = 45,
1437};
1438
1439static int cck_evm_db(u8 status_quality)
1440{
1441 return (20 * log10times100(status_quality)) / 100;
1442}
1443
1444static int cck_snr_db(u8 status_quality)
1445{
1446 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1447 ZD_ASSERT(r >= 0);
1448 return r;
1449}
1450
db888aed 1451static int cck_qual_percent(u8 status_quality)
e85d0918 1452{
db888aed
UK		 1453 int r;
1454
1455 r = cck_snr_db(status_quality);
1456 r = (100*r)/17;
1457 return r <= 100 ? r : 100;
e85d0918
DD		 1458}
1459
64f222cc
UK		 1460static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1461{
1462 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1463}
1464
e85d0918
DD		 1465u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1466 const struct rx_status *status)
1467{
db888aed
UK		 1468 return (status->frame_status&ZD_RX_OFDM) ?
1469 ofdm_qual_percent(status->signal_quality_ofdm,
459c51ad 1470 zd_rate_from_ofdm_plcp_header(rx_frame),
db888aed
UK		 1471 size) :
1472 cck_qual_percent(status->signal_quality_cck);
e85d0918
DD		 1473}
1474
459c51ad
DD		 1475/**
1476 * zd_rx_rate - report zd-rate
1477 * @rx_frame - received frame
1478 * @rx_status - rx_status as given by the device
1479 *
1480 * This function converts the rate as encoded in the received packet to the
1481 * zd-rate, we are using on other places in the driver.
1482 */
1483u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
e85d0918 1484{
459c51ad 1485 u8 zd_rate;
e85d0918 1486 if (status->frame_status & ZD_RX_OFDM) {
459c51ad 1487 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
e85d0918 1488 } else {
64f222cc
UK		 1489 switch (zd_cck_plcp_header_signal(rx_frame)) {
1490 case ZD_CCK_PLCP_SIGNAL_1M:
459c51ad 1491 zd_rate = ZD_CCK_RATE_1M;
e85d0918 1492 break;
64f222cc 1493 case ZD_CCK_PLCP_SIGNAL_2M:
459c51ad 1494 zd_rate = ZD_CCK_RATE_2M;
e85d0918 1495 break;
64f222cc 1496 case ZD_CCK_PLCP_SIGNAL_5M5:
459c51ad 1497 zd_rate = ZD_CCK_RATE_5_5M;
e85d0918 1498 break;
64f222cc 1499 case ZD_CCK_PLCP_SIGNAL_11M:
459c51ad 1500 zd_rate = ZD_CCK_RATE_11M;
e85d0918
DD		 1501 break;
1502 default:
459c51ad 1503 zd_rate = 0;
e85d0918
DD		 1504 }
1505 }
1506
459c51ad 1507 return zd_rate;
e85d0918
DD		 1508}
1509
1510int zd_chip_switch_radio_on(struct zd_chip *chip)
1511{
1512 int r;
1513
1514 mutex_lock(&chip->mutex);
1515 r = zd_switch_radio_on(&chip->rf);
1516 mutex_unlock(&chip->mutex);
1517 return r;
1518}
1519
1520int zd_chip_switch_radio_off(struct zd_chip *chip)
1521{
1522 int r;
1523
1524 mutex_lock(&chip->mutex);
1525 r = zd_switch_radio_off(&chip->rf);
1526 mutex_unlock(&chip->mutex);
1527 return r;
1528}
1529
1530int zd_chip_enable_int(struct zd_chip *chip)
1531{
1532 int r;
1533
1534 mutex_lock(&chip->mutex);
1535 r = zd_usb_enable_int(&chip->usb);
1536 mutex_unlock(&chip->mutex);
1537 return r;
1538}
1539
1540void zd_chip_disable_int(struct zd_chip *chip)
1541{
1542 mutex_lock(&chip->mutex);
1543 zd_usb_disable_int(&chip->usb);
1544 mutex_unlock(&chip->mutex);
1545}
1546
459c51ad 1547int zd_chip_enable_rxtx(struct zd_chip *chip)
e85d0918
DD		 1548{
1549 int r;
1550
1551 mutex_lock(&chip->mutex);
459c51ad 1552 zd_usb_enable_tx(&chip->usb);
e85d0918
DD		 1553 r = zd_usb_enable_rx(&chip->usb);
1554 mutex_unlock(&chip->mutex);
1555 return r;
1556}
1557
459c51ad 1558void zd_chip_disable_rxtx(struct zd_chip *chip)
e85d0918
DD		 1559{
1560 mutex_lock(&chip->mutex);
1561 zd_usb_disable_rx(&chip->usb);
459c51ad 1562 zd_usb_disable_tx(&chip->usb);
e85d0918
DD		 1563 mutex_unlock(&chip->mutex);
1564}
1565
1566int zd_rfwritev_locked(struct zd_chip *chip,
1567 const u32* values, unsigned int count, u8 bits)
1568{
1569 int r;
1570 unsigned int i;
1571
1572 for (i = 0; i < count; i++) {
1573 r = zd_rfwrite_locked(chip, values[i], bits);
1574 if (r)
1575 return r;
1576 }
1577
1578 return 0;
1579}
20fe2176
DD		 1580
1581/*
1582 * We can optionally program the RF directly through CR regs, if supported by
1583 * the hardware. This is much faster than the older method.
1584 */
ec62bd91 1585int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
20fe2176
DD		 1586{
1587 struct zd_ioreq16 ioreqs[] = {
1588 { CR244, (value >> 16) & 0xff },
1589 { CR243, (value >> 8) & 0xff },
1590 { CR242, value & 0xff },
1591 };
1592 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1593 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1594}
1595
1596int zd_rfwritev_cr_locked(struct zd_chip *chip,
1597 const u32 *values, unsigned int count)
1598{
1599 int r;
1600 unsigned int i;
1601
1602 for (i = 0; i < count; i++) {
1603 r = zd_rfwrite_cr_locked(chip, values[i]);
1604 if (r)
1605 return r;
1606 }
1607
1608 return 0;
1609}
9cdac965
UK		 1610
1611int zd_chip_set_multicast_hash(struct zd_chip *chip,
1612 struct zd_mc_hash *hash)
1613{
1614 struct zd_ioreq32 ioreqs[] = {
1615 { CR_GROUP_HASH_P1, hash->low },
1616 { CR_GROUP_HASH_P2, hash->high },
1617 };
1618
9cdac965
UK		 1619 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1620}
Linux kernel - Deliverables
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