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[PATCH] zd1211rw: Added workqueue
[deliverable/linux.git] / drivers / net / wireless / zd1211rw / zd_chip.c
CommitLineData
e85d0918
DD		 1/* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18/* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25
26#include "zd_def.h"
27#include "zd_chip.h"
28#include "zd_ieee80211.h"
29#include "zd_mac.h"
30#include "zd_rf.h"
31#include "zd_util.h"
32
33void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36{
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41}
42
43void zd_chip_clear(struct zd_chip *chip)
44{
c48cf125 45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
e85d0918
DD		 46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
e85d0918 48 mutex_destroy(&chip->mutex);
c48cf125 49 ZD_MEMCLEAR(chip, sizeof(*chip));
e85d0918
DD		 50}
51
52static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
53{
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
56}
57
58/* Prints an identifier line, which will support debugging. */
59static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
60{
61 int i = 0;
62
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
20fe2176 70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type,
e85d0918
DD		 71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
20fe2176
DD		 73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-');
e85d0918
DD		 75 return i;
76}
77
78static void print_id(struct zd_chip *chip)
79{
80 char buffer[80];
81
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
85}
86
87/* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
89 */
90int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
91 unsigned int count)
92{
93 int r;
94 int i;
95 zd_addr_t *a16 = (zd_addr_t *)NULL;
96 u16 *v16;
97 unsigned int count16;
98
99 if (count > USB_MAX_IOREAD32_COUNT)
100 return -EINVAL;
101
102 /* Allocate a single memory block for values and addresses. */
103 count16 = 2*count;
104 a16 = (zd_addr_t *)kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
105 GFP_NOFS);
106 if (!a16) {
107 dev_dbg_f(zd_chip_dev(chip),
108 "error ENOMEM in allocation of a16\n");
109 r = -ENOMEM;
110 goto out;
111 }
112 v16 = (u16 *)(a16 + count16);
113
114 for (i = 0; i < count; i++) {
115 int j = 2*i;
116 /* We read the high word always first. */
117 a16[j] = zd_inc_word(addr[i]);
118 a16[j+1] = addr[i];
119 }
120
121 r = zd_ioread16v_locked(chip, v16, a16, count16);
122 if (r) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error: zd_ioread16v_locked. Error number %d\n", r);
125 goto out;
126 }
127
128 for (i = 0; i < count; i++) {
129 int j = 2*i;
130 values[i] = (v16[j] << 16) | v16[j+1];
131 }
132
133out:
134 kfree((void *)a16);
135 return r;
136}
137
138int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
139 unsigned int count)
140{
141 int i, j, r;
142 struct zd_ioreq16 *ioreqs16;
143 unsigned int count16;
144
145 ZD_ASSERT(mutex_is_locked(&chip->mutex));
146
147 if (count == 0)
148 return 0;
149 if (count > USB_MAX_IOWRITE32_COUNT)
150 return -EINVAL;
151
152 /* Allocate a single memory block for values and addresses. */
153 count16 = 2*count;
154 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
155 if (!ioreqs16) {
156 r = -ENOMEM;
157 dev_dbg_f(zd_chip_dev(chip),
158 "error %d in ioreqs16 allocation\n", r);
159 goto out;
160 }
161
162 for (i = 0; i < count; i++) {
163 j = 2*i;
164 /* We write the high word always first. */
165 ioreqs16[j].value = ioreqs[i].value >> 16;
166 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
167 ioreqs16[j+1].value = ioreqs[i].value;
168 ioreqs16[j+1].addr = ioreqs[i].addr;
169 }
170
171 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
172#ifdef DEBUG
173 if (r) {
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in zd_usb_write16v\n", r);
176 }
177#endif /* DEBUG */
178out:
179 kfree(ioreqs16);
180 return r;
181}
182
183int zd_iowrite16a_locked(struct zd_chip *chip,
184 const struct zd_ioreq16 *ioreqs, unsigned int count)
185{
186 int r;
187 unsigned int i, j, t, max;
188
189 ZD_ASSERT(mutex_is_locked(&chip->mutex));
190 for (i = 0; i < count; i += j + t) {
191 t = 0;
192 max = count-i;
193 if (max > USB_MAX_IOWRITE16_COUNT)
194 max = USB_MAX_IOWRITE16_COUNT;
195 for (j = 0; j < max; j++) {
196 if (!ioreqs[i+j].addr) {
197 t = 1;
198 break;
199 }
200 }
201
202 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
203 if (r) {
204 dev_dbg_f(zd_chip_dev(chip),
205 "error zd_usb_iowrite16v. Error number %d\n",
206 r);
207 return r;
208 }
209 }
210
211 return 0;
212}
213
214/* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
217 */
218int zd_iowrite32a_locked(struct zd_chip *chip,
219 const struct zd_ioreq32 *ioreqs, unsigned int count)
220{
221 int r;
222 unsigned int i, j, t, max;
223
224 for (i = 0; i < count; i += j + t) {
225 t = 0;
226 max = count-i;
227 if (max > USB_MAX_IOWRITE32_COUNT)
228 max = USB_MAX_IOWRITE32_COUNT;
229 for (j = 0; j < max; j++) {
230 if (!ioreqs[i+j].addr) {
231 t = 1;
232 break;
233 }
234 }
235
236 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
237 if (r) {
238 dev_dbg_f(zd_chip_dev(chip),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r);
241 return r;
242 }
243 }
244
245 return 0;
246}
247
248int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
249{
250 int r;
251
e85d0918
DD		 252 mutex_lock(&chip->mutex);
253 r = zd_ioread16_locked(chip, value, addr);
254 mutex_unlock(&chip->mutex);
255 return r;
256}
257
258int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
259{
260 int r;
261
e85d0918
DD		 262 mutex_lock(&chip->mutex);
263 r = zd_ioread32_locked(chip, value, addr);
264 mutex_unlock(&chip->mutex);
265 return r;
266}
267
268int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
269{
270 int r;
271
e85d0918
DD		 272 mutex_lock(&chip->mutex);
273 r = zd_iowrite16_locked(chip, value, addr);
274 mutex_unlock(&chip->mutex);
275 return r;
276}
277
278int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
279{
280 int r;
281
e85d0918
DD		 282 mutex_lock(&chip->mutex);
283 r = zd_iowrite32_locked(chip, value, addr);
284 mutex_unlock(&chip->mutex);
285 return r;
286}
287
288int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
289 u32 *values, unsigned int count)
290{
291 int r;
292
e85d0918
DD		 293 mutex_lock(&chip->mutex);
294 r = zd_ioread32v_locked(chip, values, addresses, count);
295 mutex_unlock(&chip->mutex);
296 return r;
297}
298
299int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
300 unsigned int count)
301{
302 int r;
303
e85d0918
DD		 304 mutex_lock(&chip->mutex);
305 r = zd_iowrite32a_locked(chip, ioreqs, count);
306 mutex_unlock(&chip->mutex);
307 return r;
308}
309
310static int read_pod(struct zd_chip *chip, u8 *rf_type)
311{
312 int r;
313 u32 value;
314
315 ZD_ASSERT(mutex_is_locked(&chip->mutex));
316 r = zd_ioread32_locked(chip, &value, E2P_POD);
317 if (r)
318 goto error;
319 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
320
321 /* FIXME: AL2230 handling (Bit 7 in POD) */
322 *rf_type = value & 0x0f;
323 chip->pa_type = (value >> 16) & 0x0f;
324 chip->patch_cck_gain = (value >> 8) & 0x1;
325 chip->patch_cr157 = (value >> 13) & 0x1;
326 chip->patch_6m_band_edge = (value >> 21) & 0x1;
20fe2176 327 chip->new_phy_layout = (value >> 31) & 0x1;
e85d0918
DD		 328
329 dev_dbg_f(zd_chip_dev(chip),
330 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
20fe2176 331 "patch 6M %d new PHY %d\n",
e85d0918
DD		 332 zd_rf_name(*rf_type), *rf_type,
333 chip->pa_type, chip->patch_cck_gain,
20fe2176 334 chip->patch_cr157, chip->patch_6m_band_edge, chip->new_phy_layout);
e85d0918
DD		 335 return 0;
336error:
337 *rf_type = 0;
338 chip->pa_type = 0;
339 chip->patch_cck_gain = 0;
340 chip->patch_cr157 = 0;
341 chip->patch_6m_band_edge = 0;
20fe2176 342 chip->new_phy_layout = 0;
e85d0918
DD		 343 return r;
344}
345
346static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
347 const zd_addr_t *addr)
348{
349 int r;
350 u32 parts[2];
351
352 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
353 if (r) {
354 dev_dbg_f(zd_chip_dev(chip),
355 "error: couldn't read e2p macs. Error number %d\n", r);
356 return r;
357 }
358
359 mac_addr[0] = parts[0];
360 mac_addr[1] = parts[0] >> 8;
361 mac_addr[2] = parts[0] >> 16;
362 mac_addr[3] = parts[0] >> 24;
363 mac_addr[4] = parts[1];
364 mac_addr[5] = parts[1] >> 8;
365
366 return 0;
367}
368
369static int read_e2p_mac_addr(struct zd_chip *chip)
370{
371 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
372
373 ZD_ASSERT(mutex_is_locked(&chip->mutex));
374 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
375}
376
377/* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
378 * CR_MAC_ADDR_P2 must be overwritten
379 */
380void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
381{
382 mutex_lock(&chip->mutex);
383 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
384 mutex_unlock(&chip->mutex);
385}
386
387static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
388{
389 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
390 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
391}
392
393int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
394{
395 int r;
396
397 dev_dbg_f(zd_chip_dev(chip), "\n");
398 mutex_lock(&chip->mutex);
399 r = read_mac_addr(chip, mac_addr);
400 mutex_unlock(&chip->mutex);
401 return r;
402}
403
404int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
405{
406 int r;
407 struct zd_ioreq32 reqs[2] = {
408 [0] = { .addr = CR_MAC_ADDR_P1 },
409 [1] = { .addr = CR_MAC_ADDR_P2 },
410 };
411
412 reqs[0].value = (mac_addr[3] << 24)
413 | (mac_addr[2] << 16)
414 | (mac_addr[1] << 8)
415 | mac_addr[0];
416 reqs[1].value = (mac_addr[5] << 8)
417 | mac_addr[4];
418
419 dev_dbg_f(zd_chip_dev(chip),
420 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
421
422 mutex_lock(&chip->mutex);
423 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
424#ifdef DEBUG
425 {
426 u8 tmp[ETH_ALEN];
427 read_mac_addr(chip, tmp);
428 }
429#endif /* DEBUG */
430 mutex_unlock(&chip->mutex);
431 return r;
432}
433
434int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
435{
436 int r;
437 u32 value;
438
439 mutex_lock(&chip->mutex);
440 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
441 mutex_unlock(&chip->mutex);
442 if (r)
443 return r;
444
445 *regdomain = value >> 16;
446 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
447
448 return 0;
449}
450
451static int read_values(struct zd_chip *chip, u8 *values, size_t count,
452 zd_addr_t e2p_addr, u32 guard)
453{
454 int r;
455 int i;
456 u32 v;
457
458 ZD_ASSERT(mutex_is_locked(&chip->mutex));
459 for (i = 0;;) {
460 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
461 if (r)
462 return r;
463 v -= guard;
464 if (i+4 < count) {
465 values[i++] = v;
466 values[i++] = v >> 8;
467 values[i++] = v >> 16;
468 values[i++] = v >> 24;
469 continue;
470 }
471 for (;i < count; i++)
472 values[i] = v >> (8*(i%3));
473 return 0;
474 }
475}
476
477static int read_pwr_cal_values(struct zd_chip *chip)
478{
479 return read_values(chip, chip->pwr_cal_values,
480 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
481 0);
482}
483
484static int read_pwr_int_values(struct zd_chip *chip)
485{
486 return read_values(chip, chip->pwr_int_values,
487 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
488 E2P_PWR_INT_GUARD);
489}
490
491static int read_ofdm_cal_values(struct zd_chip *chip)
492{
493 int r;
494 int i;
495 static const zd_addr_t addresses[] = {
496 E2P_36M_CAL_VALUE1,
497 E2P_48M_CAL_VALUE1,
498 E2P_54M_CAL_VALUE1,
499 };
500
501 for (i = 0; i < 3; i++) {
502 r = read_values(chip, chip->ofdm_cal_values[i],
503 E2P_CHANNEL_COUNT, addresses[i], 0);
504 if (r)
505 return r;
506 }
507 return 0;
508}
509
510static int read_cal_int_tables(struct zd_chip *chip)
511{
512 int r;
513
514 r = read_pwr_cal_values(chip);
515 if (r)
516 return r;
517 r = read_pwr_int_values(chip);
518 if (r)
519 return r;
520 r = read_ofdm_cal_values(chip);
521 if (r)
522 return r;
523 return 0;
524}
525
526/* phy means physical registers */
527int zd_chip_lock_phy_regs(struct zd_chip *chip)
528{
529 int r;
530 u32 tmp;
531
532 ZD_ASSERT(mutex_is_locked(&chip->mutex));
533 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
534 if (r) {
535 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
536 return r;
537 }
538
539 dev_dbg_f(zd_chip_dev(chip),
540 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
541 tmp &= ~UNLOCK_PHY_REGS;
542
543 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
544 if (r)
545 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
546 return r;
547}
548
549int zd_chip_unlock_phy_regs(struct zd_chip *chip)
550{
551 int r;
552 u32 tmp;
553
554 ZD_ASSERT(mutex_is_locked(&chip->mutex));
555 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
556 if (r) {
557 dev_err(zd_chip_dev(chip),
558 "error ioread32(CR_REG1): %d\n", r);
559 return r;
560 }
561
562 dev_dbg_f(zd_chip_dev(chip),
563 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
564 tmp |= UNLOCK_PHY_REGS;
565
566 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
567 if (r)
568 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
569 return r;
570}
571
572/* CR157 can be optionally patched by the EEPROM */
573static int patch_cr157(struct zd_chip *chip)
574{
575 int r;
576 u32 value;
577
578 if (!chip->patch_cr157)
579 return 0;
580
581 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
582 if (r)
583 return r;
584
585 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
586 return zd_iowrite32_locked(chip, value >> 8, CR157);
587}
588
589/*
590 * 6M band edge can be optionally overwritten for certain RF's
591 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
592 * bit (for AL2230, AL2230S)
593 */
594static int patch_6m_band_edge(struct zd_chip *chip, int channel)
595{
596 struct zd_ioreq16 ioreqs[] = {
597 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
598 { CR47, 0x1e },
599 };
600
601 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
602 return 0;
603
604 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
605 if (channel == 1 || channel == 11)
606 ioreqs[0].value = 0x12;
607
608 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
609 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
610}
611
612static int zd1211_hw_reset_phy(struct zd_chip *chip)
613{
614 static const struct zd_ioreq16 ioreqs[] = {
615 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
616 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
617 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
618 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
619 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
620 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
621 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
622 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
623 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
624 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
625 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
626 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
627 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
628 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
629 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
630 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
631 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
632 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
633 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
634 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
635 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
636 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
637 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
638 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
639 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
640 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
641 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
642 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
643 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
644 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
645 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
646 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
647 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
648 { },
649 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
650 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
651 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
652 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
653 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
654 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
655 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
656 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
657 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
658 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
659 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
660 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
661 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
662 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
663 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
664 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
665 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
666 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
667 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
668 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
669 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
670 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
671 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
672 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
673 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
674 /* Note: CR204 must lead the CR203 */
675 { CR204, 0x7d },
676 { },
677 { CR203, 0x30 },
678 };
679
680 int r, t;
681
682 dev_dbg_f(zd_chip_dev(chip), "\n");
683
684 r = zd_chip_lock_phy_regs(chip);
685 if (r)
686 goto out;
687
688 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
689 if (r)
690 goto unlock;
691
692 r = patch_cr157(chip);
693unlock:
694 t = zd_chip_unlock_phy_regs(chip);
695 if (t && !r)
696 r = t;
697out:
698 return r;
699}
700
701static int zd1211b_hw_reset_phy(struct zd_chip *chip)
702{
703 static const struct zd_ioreq16 ioreqs[] = {
704 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
705 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
706 { CR10, 0x81 },
707 /* power control { { CR11, 1 << 6 }, */
708 { CR11, 0x00 },
709 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
710 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
711 { CR18, 0x0a }, { CR19, 0x48 },
712 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
713 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
714 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
715 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
fe7215ca 716 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
e85d0918
DD		 717 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
718 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
719 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
720 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
721 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
722 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
723 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
724 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
725 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
726 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
727 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
728 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
729 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
730 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
731 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
732 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
733 { CR94, 0x01 },
734 { CR95, 0x20 }, /* ZD1211B */
735 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
736 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
737 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
738 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
739 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
740 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
741 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
742 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
743 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
744 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
745 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
746 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
747 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
748 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
749 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
750 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
751 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
752 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
753 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
754 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
755 { CR170, 0xba }, { CR171, 0xba },
756 /* Note: CR204 must lead the CR203 */
757 { CR204, 0x7d },
758 {},
759 { CR203, 0x30 },
760 };
761
762 int r, t;
763
764 dev_dbg_f(zd_chip_dev(chip), "\n");
765
766 r = zd_chip_lock_phy_regs(chip);
767 if (r)
768 goto out;
769
770 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
771 if (r)
772 goto unlock;
773
774 r = patch_cr157(chip);
775unlock:
776 t = zd_chip_unlock_phy_regs(chip);
777 if (t && !r)
778 r = t;
779out:
780 return r;
781}
782
783static int hw_reset_phy(struct zd_chip *chip)
784{
785 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
786 zd1211_hw_reset_phy(chip);
787}
788
789static int zd1211_hw_init_hmac(struct zd_chip *chip)
790{
791 static const struct zd_ioreq32 ioreqs[] = {
792 { CR_ACK_TIMEOUT_EXT, 0x20 },
793 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
794 { CR_ZD1211_RETRY_MAX, 0x2 },
795 { CR_SNIFFER_ON, 0 },
fde627b5 796 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 797 { CR_GROUP_HASH_P1, 0x00 },
798 { CR_GROUP_HASH_P2, 0x80000000 },
799 { CR_REG1, 0xa4 },
800 { CR_ADDA_PWR_DWN, 0x7f },
801 { CR_BCN_PLCP_CFG, 0x00f00401 },
802 { CR_PHY_DELAY, 0x00 },
803 { CR_ACK_TIMEOUT_EXT, 0x80 },
804 { CR_ADDA_PWR_DWN, 0x00 },
805 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 806 { CR_RX_PE_DELAY, 0x70 },
807 { CR_PS_CTRL, 0x10000000 },
808 { CR_RTS_CTS_RATE, 0x02030203 },
809 { CR_RX_THRESHOLD, 0x000c0640 },
810 { CR_AFTER_PNP, 0x1 },
811 { CR_WEP_PROTECT, 0x114 },
812 };
813
814 int r;
815
816 dev_dbg_f(zd_chip_dev(chip), "\n");
817 ZD_ASSERT(mutex_is_locked(&chip->mutex));
818 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
819#ifdef DEBUG
820 if (r) {
821 dev_err(zd_chip_dev(chip),
822 "error in zd_iowrite32a_locked. Error number %d\n", r);
823 }
824#endif /* DEBUG */
825 return r;
826}
827
828static int zd1211b_hw_init_hmac(struct zd_chip *chip)
829{
830 static const struct zd_ioreq32 ioreqs[] = {
831 { CR_ACK_TIMEOUT_EXT, 0x20 },
832 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
833 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
834 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
835 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
836 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
837 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
838 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
839 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
840 { CR_ZD1211B_TXOP, 0x01800824 },
841 { CR_SNIFFER_ON, 0 },
fde627b5 842 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 843 { CR_GROUP_HASH_P1, 0x00 },
844 { CR_GROUP_HASH_P2, 0x80000000 },
845 { CR_REG1, 0xa4 },
846 { CR_ADDA_PWR_DWN, 0x7f },
847 { CR_BCN_PLCP_CFG, 0x00f00401 },
848 { CR_PHY_DELAY, 0x00 },
849 { CR_ACK_TIMEOUT_EXT, 0x80 },
850 { CR_ADDA_PWR_DWN, 0x00 },
851 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 852 { CR_RX_PE_DELAY, 0x70 },
853 { CR_PS_CTRL, 0x10000000 },
854 { CR_RTS_CTS_RATE, 0x02030203 },
20fe2176 855 { CR_RX_THRESHOLD, 0x000c0eff, },
e85d0918
DD		 856 { CR_AFTER_PNP, 0x1 },
857 { CR_WEP_PROTECT, 0x114 },
858 };
859
860 int r;
861
862 dev_dbg_f(zd_chip_dev(chip), "\n");
863 ZD_ASSERT(mutex_is_locked(&chip->mutex));
864 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
865 if (r) {
866 dev_dbg_f(zd_chip_dev(chip),
867 "error in zd_iowrite32a_locked. Error number %d\n", r);
868 }
869 return r;
870}
871
872static int hw_init_hmac(struct zd_chip *chip)
873{
874 return chip->is_zd1211b ?
875 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
876}
877
878struct aw_pt_bi {
879 u32 atim_wnd_period;
880 u32 pre_tbtt;
881 u32 beacon_interval;
882};
883
884static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
885{
886 int r;
887 static const zd_addr_t aw_pt_bi_addr[] =
888 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
889 u32 values[3];
890
891 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
892 ARRAY_SIZE(aw_pt_bi_addr));
893 if (r) {
894 memset(s, 0, sizeof(*s));
895 return r;
896 }
897
898 s->atim_wnd_period = values[0];
899 s->pre_tbtt = values[1];
900 s->beacon_interval = values[2];
901 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
902 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
903 return 0;
904}
905
906static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
907{
908 struct zd_ioreq32 reqs[3];
909
910 if (s->beacon_interval <= 5)
911 s->beacon_interval = 5;
912 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
913 s->pre_tbtt = s->beacon_interval - 1;
914 if (s->atim_wnd_period >= s->pre_tbtt)
915 s->atim_wnd_period = s->pre_tbtt - 1;
916
917 reqs[0].addr = CR_ATIM_WND_PERIOD;
918 reqs[0].value = s->atim_wnd_period;
919 reqs[1].addr = CR_PRE_TBTT;
920 reqs[1].value = s->pre_tbtt;
921 reqs[2].addr = CR_BCN_INTERVAL;
922 reqs[2].value = s->beacon_interval;
923
924 dev_dbg_f(zd_chip_dev(chip),
925 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
926 s->beacon_interval);
927 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
928}
929
930
931static int set_beacon_interval(struct zd_chip *chip, u32 interval)
932{
933 int r;
934 struct aw_pt_bi s;
935
936 ZD_ASSERT(mutex_is_locked(&chip->mutex));
937 r = get_aw_pt_bi(chip, &s);
938 if (r)
939 return r;
940 s.beacon_interval = interval;
941 return set_aw_pt_bi(chip, &s);
942}
943
944int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
945{
946 int r;
947
948 mutex_lock(&chip->mutex);
949 r = set_beacon_interval(chip, interval);
950 mutex_unlock(&chip->mutex);
951 return r;
952}
953
954static int hw_init(struct zd_chip *chip)
955{
956 int r;
957
958 dev_dbg_f(zd_chip_dev(chip), "\n");
959 ZD_ASSERT(mutex_is_locked(&chip->mutex));
960 r = hw_reset_phy(chip);
961 if (r)
962 return r;
963
964 r = hw_init_hmac(chip);
965 if (r)
966 return r;
98227a90
DD		 967
968 /* Although the vendor driver defaults to a different value during
969 * init, it overwrites the IFS value with the following every time
970 * the channel changes. We should aim to be more intelligent... */
971 r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
e85d0918
DD		 972 if (r)
973 return r;
98227a90
DD		 974
975 return set_beacon_interval(chip, 100);
e85d0918
DD		 976}
977
978#ifdef DEBUG
979static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
980 const char *addr_string)
981{
982 int r;
983 u32 value;
984
985 r = zd_ioread32_locked(chip, &value, addr);
986 if (r) {
987 dev_dbg_f(zd_chip_dev(chip),
988 "error reading %s. Error number %d\n", addr_string, r);
989 return r;
990 }
991
992 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
993 addr_string, (unsigned int)value);
994 return 0;
995}
996
997static int test_init(struct zd_chip *chip)
998{
999 int r;
1000
1001 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1002 if (r)
1003 return r;
1004 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1005 if (r)
1006 return r;
1007 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1008}
1009
1010static void dump_fw_registers(struct zd_chip *chip)
1011{
1012 static const zd_addr_t addr[4] = {
1013 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
1014 FW_LINK_STATUS
1015 };
1016
1017 int r;
1018 u16 values[4];
1019
1020 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1021 ARRAY_SIZE(addr));
1022 if (r) {
1023 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1024 r);
1025 return;
1026 }
1027
1028 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1029 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1030 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1031 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1032}
1033#endif /* DEBUG */
1034
1035static int print_fw_version(struct zd_chip *chip)
1036{
1037 int r;
1038 u16 version;
1039
1040 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1041 if (r)
1042 return r;
1043
1044 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1045 return 0;
1046}
1047
1048static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1049{
1050 u32 rates;
1051 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1052 /* This sets the mandatory rates, which only depend from the standard
1053 * that the device is supporting. Until further notice we should try
1054 * to support 802.11g also for full speed USB.
1055 */
1056 switch (std) {
1057 case IEEE80211B:
1058 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1059 break;
1060 case IEEE80211G:
1061 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1062 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1063 break;
1064 default:
1065 return -EINVAL;
1066 }
1067 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1068}
1069
1070int zd_chip_enable_hwint(struct zd_chip *chip)
1071{
1072 int r;
1073
1074 mutex_lock(&chip->mutex);
1075 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1076 mutex_unlock(&chip->mutex);
1077 return r;
1078}
1079
1080static int disable_hwint(struct zd_chip *chip)
1081{
1082 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1083}
1084
1085int zd_chip_disable_hwint(struct zd_chip *chip)
1086{
1087 int r;
1088
1089 mutex_lock(&chip->mutex);
1090 r = disable_hwint(chip);
1091 mutex_unlock(&chip->mutex);
1092 return r;
1093}
1094
1095int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1096{
1097 int r;
1098 u8 rf_type;
1099
1100 dev_dbg_f(zd_chip_dev(chip), "\n");
1101
1102 mutex_lock(&chip->mutex);
1103 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1104
1105#ifdef DEBUG
1106 r = test_init(chip);
1107 if (r)
1108 goto out;
1109#endif
1110 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1111 if (r)
1112 goto out;
1113
1114 r = zd_usb_init_hw(&chip->usb);
1115 if (r)
1116 goto out;
1117
1118 /* GPI is always disabled, also in the other driver.
1119 */
1120 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1121 if (r)
1122 goto out;
1123 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1124 if (r)
1125 goto out;
1126 /* Currently we support IEEE 802.11g for full and high speed USB.
1127 * It might be discussed, whether we should suppport pure b mode for
1128 * full speed USB.
1129 */
1130 r = set_mandatory_rates(chip, IEEE80211G);
1131 if (r)
1132 goto out;
1133 /* Disabling interrupts is certainly a smart thing here.
1134 */
1135 r = disable_hwint(chip);
1136 if (r)
1137 goto out;
1138 r = read_pod(chip, &rf_type);
1139 if (r)
1140 goto out;
1141 r = hw_init(chip);
1142 if (r)
1143 goto out;
1144 r = zd_rf_init_hw(&chip->rf, rf_type);
1145 if (r)
1146 goto out;
1147
1148 r = print_fw_version(chip);
1149 if (r)
1150 goto out;
1151
1152#ifdef DEBUG
1153 dump_fw_registers(chip);
1154 r = test_init(chip);
1155 if (r)
1156 goto out;
1157#endif /* DEBUG */
1158
1159 r = read_e2p_mac_addr(chip);
1160 if (r)
1161 goto out;
1162
1163 r = read_cal_int_tables(chip);
1164 if (r)
1165 goto out;
1166
1167 print_id(chip);
1168out:
1169 mutex_unlock(&chip->mutex);
1170 return r;
1171}
1172
1173static int update_pwr_int(struct zd_chip *chip, u8 channel)
1174{
1175 u8 value = chip->pwr_int_values[channel - 1];
1176 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1177 channel, value);
cbb5e6bb 1178 return zd_iowrite16_locked(chip, value, CR31);
e85d0918
DD		 1179}
1180
1181static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1182{
1183 u8 value = chip->pwr_cal_values[channel-1];
1184 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1185 channel, value);
cbb5e6bb 1186 return zd_iowrite16_locked(chip, value, CR68);
e85d0918
DD		 1187}
1188
1189static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1190{
cbb5e6bb 1191 struct zd_ioreq16 ioreqs[3];
e85d0918
DD		 1192
1193 ioreqs[0].addr = CR67;
1194 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1195 ioreqs[1].addr = CR66;
1196 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1197 ioreqs[2].addr = CR65;
1198 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1199
1200 dev_dbg_f(zd_chip_dev(chip),
1201 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1202 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
cbb5e6bb 1203 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1204}
1205
1206static int update_channel_integration_and_calibration(struct zd_chip *chip,
1207 u8 channel)
1208{
1209 int r;
1210
1211 r = update_pwr_int(chip, channel);
1212 if (r)
1213 return r;
1214 if (chip->is_zd1211b) {
cbb5e6bb 1215 static const struct zd_ioreq16 ioreqs[] = {
e85d0918
DD		 1216 { CR69, 0x28 },
1217 {},
1218 { CR69, 0x2a },
1219 };
1220
1221 r = update_ofdm_cal(chip, channel);
1222 if (r)
1223 return r;
1224 r = update_pwr_cal(chip, channel);
1225 if (r)
1226 return r;
cbb5e6bb 1227 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1228 if (r)
1229 return r;
1230 }
1231
1232 return 0;
1233}
1234
1235/* The CCK baseband gain can be optionally patched by the EEPROM */
1236static int patch_cck_gain(struct zd_chip *chip)
1237{
1238 int r;
1239 u32 value;
1240
1241 if (!chip->patch_cck_gain)
1242 return 0;
1243
1244 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1245 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1246 if (r)
1247 return r;
1248 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
cbb5e6bb 1249 return zd_iowrite16_locked(chip, value & 0xff, CR47);
e85d0918
DD		 1250}
1251
1252int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1253{
1254 int r, t;
1255
1256 mutex_lock(&chip->mutex);
1257 r = zd_chip_lock_phy_regs(chip);
1258 if (r)
1259 goto out;
1260 r = zd_rf_set_channel(&chip->rf, channel);
1261 if (r)
1262 goto unlock;
1263 r = update_channel_integration_and_calibration(chip, channel);
1264 if (r)
1265 goto unlock;
1266 r = patch_cck_gain(chip);
1267 if (r)
1268 goto unlock;
1269 r = patch_6m_band_edge(chip, channel);
1270 if (r)
1271 goto unlock;
1272 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1273unlock:
1274 t = zd_chip_unlock_phy_regs(chip);
1275 if (t && !r)
1276 r = t;
1277out:
1278 mutex_unlock(&chip->mutex);
1279 return r;
1280}
1281
1282u8 zd_chip_get_channel(struct zd_chip *chip)
1283{
1284 u8 channel;
1285
1286 mutex_lock(&chip->mutex);
1287 channel = chip->rf.channel;
1288 mutex_unlock(&chip->mutex);
1289 return channel;
1290}
1291
1292static u16 led_mask(int led)
1293{
1294 switch (led) {
1295 case 1:
1296 return LED1;
1297 case 2:
1298 return LED2;
1299 default:
1300 return 0;
1301 }
1302}
1303
1304static int read_led_reg(struct zd_chip *chip, u16 *status)
1305{
1306 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1307 return zd_ioread16_locked(chip, status, CR_LED);
1308}
1309
1310static int write_led_reg(struct zd_chip *chip, u16 status)
1311{
1312 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1313 return zd_iowrite16_locked(chip, status, CR_LED);
1314}
1315
1316int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status)
1317{
1318 int r, ret;
1319 u16 mask = led_mask(led);
1320 u16 reg;
1321
1322 if (!mask)
1323 return -EINVAL;
1324 mutex_lock(&chip->mutex);
1325 r = read_led_reg(chip, &reg);
1326 if (r)
1327 return r;
1328 switch (status) {
1329 case LED_STATUS:
1330 return (reg & mask) ? LED_ON : LED_OFF;
1331 case LED_OFF:
1332 reg &= ~mask;
1333 ret = LED_OFF;
1334 break;
1335 case LED_FLIP:
1336 reg ^= mask;
1337 ret = (reg&mask) ? LED_ON : LED_OFF;
1338 break;
1339 case LED_ON:
1340 reg |= mask;
1341 ret = LED_ON;
1342 break;
1343 default:
1344 return -EINVAL;
1345 }
1346 r = write_led_reg(chip, reg);
1347 if (r) {
1348 ret = r;
1349 goto out;
1350 }
1351out:
1352 mutex_unlock(&chip->mutex);
1353 return r;
1354}
1355
1356int zd_chip_led_flip(struct zd_chip *chip, int led,
1357 const unsigned int *phases_msecs, unsigned int count)
1358{
1359 int i, r;
1360 enum led_status status;
1361
1362 r = zd_chip_led_status(chip, led, LED_STATUS);
1363 if (r)
1364 return r;
1365 status = r;
1366 for (i = 0; i < count; i++) {
1367 r = zd_chip_led_status(chip, led, LED_FLIP);
1368 if (r < 0)
1369 goto out;
1370 msleep(phases_msecs[i]);
1371 }
1372
1373out:
1374 zd_chip_led_status(chip, led, status);
1375 return r;
1376}
1377
1378int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1379{
1380 int r;
1381
1382 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1383 return -EINVAL;
1384
1385 mutex_lock(&chip->mutex);
1386 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1387 mutex_unlock(&chip->mutex);
1388 return r;
1389}
1390
1391static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1392{
1393 static const u16 constants[] = {
1394 715, 655, 585, 540, 470, 410, 360, 315,
1395 270, 235, 205, 175, 150, 125, 105, 85,
1396 65, 50, 40, 25, 15
1397 };
1398
1399 int i;
1400 u32 x;
1401
1402 /* It seems that their quality parameter is somehow per signal
1403 * and is now transferred per bit.
1404 */
1405 switch (rate) {
1406 case ZD_OFDM_RATE_6M:
1407 case ZD_OFDM_RATE_12M:
1408 case ZD_OFDM_RATE_24M:
1409 size *= 2;
1410 break;
1411 case ZD_OFDM_RATE_9M:
1412 case ZD_OFDM_RATE_18M:
1413 case ZD_OFDM_RATE_36M:
1414 case ZD_OFDM_RATE_54M:
1415 size *= 4;
1416 size /= 3;
1417 break;
1418 case ZD_OFDM_RATE_48M:
1419 size *= 3;
1420 size /= 2;
1421 break;
1422 default:
1423 return -EINVAL;
1424 }
1425
1426 x = (10000 * status_quality)/size;
1427 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1428 if (x > constants[i])
1429 break;
1430 }
1431
db888aed
UK		 1432 switch (rate) {
1433 case ZD_OFDM_RATE_6M:
1434 case ZD_OFDM_RATE_9M:
1435 i += 3;
1436 break;
1437 case ZD_OFDM_RATE_12M:
1438 case ZD_OFDM_RATE_18M:
1439 i += 5;
1440 break;
1441 case ZD_OFDM_RATE_24M:
1442 case ZD_OFDM_RATE_36M:
1443 i += 9;
1444 break;
1445 case ZD_OFDM_RATE_48M:
1446 case ZD_OFDM_RATE_54M:
1447 i += 15;
1448 break;
1449 default:
1450 return -EINVAL;
1451 }
1452
e85d0918
DD		 1453 return i;
1454}
1455
db888aed
UK		 1456static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1457{
1458 int r;
1459
1460 r = ofdm_qual_db(status_quality, rate, size);
1461 ZD_ASSERT(r >= 0);
1462 if (r < 0)
1463 r = 0;
1464
1465 r = (r * 100)/29;
1466 return r <= 100 ? r : 100;
1467}
1468
e85d0918
DD		 1469static unsigned int log10times100(unsigned int x)
1470{
1471 static const u8 log10[] = {
1472 0,
1473 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1474 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1475 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1476 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1477 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1478 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1479 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1480 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1481 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1482 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1483 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1484 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1485 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1486 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1487 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1488 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1489 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1490 223, 223, 223, 224, 224, 224, 224,
1491 };
1492
1493 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1494}
1495
1496enum {
1497 MAX_CCK_EVM_DB = 45,
1498};
1499
1500static int cck_evm_db(u8 status_quality)
1501{
1502 return (20 * log10times100(status_quality)) / 100;
1503}
1504
1505static int cck_snr_db(u8 status_quality)
1506{
1507 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1508 ZD_ASSERT(r >= 0);
1509 return r;
1510}
1511
db888aed 1512static int cck_qual_percent(u8 status_quality)
e85d0918 1513{
db888aed
UK		 1514 int r;
1515
1516 r = cck_snr_db(status_quality);
1517 r = (100*r)/17;
1518 return r <= 100 ? r : 100;
e85d0918
DD		 1519}
1520
1521u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1522 const struct rx_status *status)
1523{
db888aed
UK		 1524 return (status->frame_status&ZD_RX_OFDM) ?
1525 ofdm_qual_percent(status->signal_quality_ofdm,
1526 zd_ofdm_plcp_header_rate(rx_frame),
1527 size) :
1528 cck_qual_percent(status->signal_quality_cck);
e85d0918
DD		 1529}
1530
1531u8 zd_rx_strength_percent(u8 rssi)
1532{
db888aed 1533 int r = (rssi*100) / 41;
e85d0918
DD		 1534 if (r > 100)
1535 r = 100;
1536 return (u8) r;
1537}
1538
1539u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1540{
1541 static const u16 ofdm_rates[] = {
1542 [ZD_OFDM_RATE_6M] = 60,
1543 [ZD_OFDM_RATE_9M] = 90,
1544 [ZD_OFDM_RATE_12M] = 120,
1545 [ZD_OFDM_RATE_18M] = 180,
1546 [ZD_OFDM_RATE_24M] = 240,
1547 [ZD_OFDM_RATE_36M] = 360,
1548 [ZD_OFDM_RATE_48M] = 480,
1549 [ZD_OFDM_RATE_54M] = 540,
1550 };
1551 u16 rate;
1552 if (status->frame_status & ZD_RX_OFDM) {
1553 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1554 rate = ofdm_rates[ofdm_rate & 0xf];
1555 } else {
1556 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1557 switch (cck_rate) {
1558 case ZD_CCK_SIGNAL_1M:
1559 rate = 10;
1560 break;
1561 case ZD_CCK_SIGNAL_2M:
1562 rate = 20;
1563 break;
1564 case ZD_CCK_SIGNAL_5M5:
1565 rate = 55;
1566 break;
1567 case ZD_CCK_SIGNAL_11M:
1568 rate = 110;
1569 break;
1570 default:
1571 rate = 0;
1572 }
1573 }
1574
1575 return rate;
1576}
1577
1578int zd_chip_switch_radio_on(struct zd_chip *chip)
1579{
1580 int r;
1581
1582 mutex_lock(&chip->mutex);
1583 r = zd_switch_radio_on(&chip->rf);
1584 mutex_unlock(&chip->mutex);
1585 return r;
1586}
1587
1588int zd_chip_switch_radio_off(struct zd_chip *chip)
1589{
1590 int r;
1591
1592 mutex_lock(&chip->mutex);
1593 r = zd_switch_radio_off(&chip->rf);
1594 mutex_unlock(&chip->mutex);
1595 return r;
1596}
1597
1598int zd_chip_enable_int(struct zd_chip *chip)
1599{
1600 int r;
1601
1602 mutex_lock(&chip->mutex);
1603 r = zd_usb_enable_int(&chip->usb);
1604 mutex_unlock(&chip->mutex);
1605 return r;
1606}
1607
1608void zd_chip_disable_int(struct zd_chip *chip)
1609{
1610 mutex_lock(&chip->mutex);
1611 zd_usb_disable_int(&chip->usb);
1612 mutex_unlock(&chip->mutex);
1613}
1614
1615int zd_chip_enable_rx(struct zd_chip *chip)
1616{
1617 int r;
1618
1619 mutex_lock(&chip->mutex);
1620 r = zd_usb_enable_rx(&chip->usb);
1621 mutex_unlock(&chip->mutex);
1622 return r;
1623}
1624
1625void zd_chip_disable_rx(struct zd_chip *chip)
1626{
1627 mutex_lock(&chip->mutex);
1628 zd_usb_disable_rx(&chip->usb);
1629 mutex_unlock(&chip->mutex);
1630}
1631
1632int zd_rfwritev_locked(struct zd_chip *chip,
1633 const u32* values, unsigned int count, u8 bits)
1634{
1635 int r;
1636 unsigned int i;
1637
1638 for (i = 0; i < count; i++) {
1639 r = zd_rfwrite_locked(chip, values[i], bits);
1640 if (r)
1641 return r;
1642 }
1643
1644 return 0;
1645}
20fe2176
DD		 1646
1647/*
1648 * We can optionally program the RF directly through CR regs, if supported by
1649 * the hardware. This is much faster than the older method.
1650 */
ec62bd91 1651int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
20fe2176
DD		 1652{
1653 struct zd_ioreq16 ioreqs[] = {
1654 { CR244, (value >> 16) & 0xff },
1655 { CR243, (value >> 8) & 0xff },
1656 { CR242, value & 0xff },
1657 };
1658 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1659 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1660}
1661
1662int zd_rfwritev_cr_locked(struct zd_chip *chip,
1663 const u32 *values, unsigned int count)
1664{
1665 int r;
1666 unsigned int i;
1667
1668 for (i = 0; i < count; i++) {
1669 r = zd_rfwrite_cr_locked(chip, values[i]);
1670 if (r)
1671 return r;
1672 }
1673
1674 return 0;
1675}
1676
Linux kernel - Deliverables
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