projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 66bb42fd DD |
1 | /* ZD1211 USB-WLAN driver for Linux |
| 2 | * | |
| 3 | * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> | |
| 4 | * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> | |
| e85d0918 DD |
5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License as published by | |
| 8 | * the Free Software Foundation; either version 2 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 19 | */ | |
| 20 | ||
| 21 | #ifndef _ZD_CHIP_H | |
| 22 | #define _ZD_CHIP_H | |
| 23 | ||
| e85d0918 DD |
24 | #include "zd_rf.h" |
| 25 | #include "zd_usb.h" | |
| 26 | ||
| 27 | /* Header for the Media Access Controller (MAC) and the Baseband Processor | |
| 28 | * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and | |
| 29 | * adds a processor for handling the USB protocol. | |
| 30 | */ | |
| 31 | ||
| 0ce34bc8 DD |
32 | /* Address space */ |
| 33 | enum { | |
| 34 | /* CONTROL REGISTERS */ | |
| 35 | CR_START = 0x9000, | |
| 36 | ||
| 37 | ||
| 38 | /* FIRMWARE */ | |
| 39 | FW_START = 0xee00, | |
| 40 | ||
| 41 | ||
| 42 | /* EEPROM */ | |
| 43 | E2P_START = 0xf800, | |
| 44 | E2P_LEN = 0x800, | |
| 45 | ||
| 46 | /* EEPROM layout */ | |
| 47 | E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */ | |
| 48 | E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */ | |
| 49 | /* E2P_DATA indexes into this */ | |
| 50 | E2P_DATA_LEN = 0x7e, /* base 0xf817 */ | |
| 51 | E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */ | |
| 52 | E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */ | |
| 53 | ||
| 54 | /* Some precomputed offsets into the EEPROM */ | |
| 55 | E2P_DATA_OFFSET = E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN, | |
| 56 | E2P_BOOT_CODE_OFFSET = E2P_DATA_OFFSET + E2P_DATA_LEN, | |
| 57 | }; | |
| 58 | ||
| 59 | #define CTL_REG(offset) ((zd_addr_t)(CR_START + (offset))) | |
| 60 | #define E2P_DATA(offset) ((zd_addr_t)(E2P_START + E2P_DATA_OFFSET + (offset))) | |
| 61 | #define FWRAW_DATA(offset) ((zd_addr_t)(FW_START + (offset))) | |
| 62 | ||
| e85d0918 DD |
63 | /* 8-bit hardware registers */ |
| 64 | #define CR0 CTL_REG(0x0000) | |
| 65 | #define CR1 CTL_REG(0x0004) | |
| 66 | #define CR2 CTL_REG(0x0008) | |
| 67 | #define CR3 CTL_REG(0x000C) | |
| 68 | ||
| 69 | #define CR5 CTL_REG(0x0010) | |
| 70 | /* bit 5: if set short preamble used | |
| 71 | * bit 6: filter band - Japan channel 14 on, else off | |
| 72 | */ | |
| 73 | #define CR6 CTL_REG(0x0014) | |
| 74 | #define CR7 CTL_REG(0x0018) | |
| 75 | #define CR8 CTL_REG(0x001C) | |
| 76 | ||
| 77 | #define CR4 CTL_REG(0x0020) | |
| 78 | ||
| 79 | #define CR9 CTL_REG(0x0024) | |
| 80 | /* bit 2: antenna switch (together with CR10) */ | |
| 81 | #define CR10 CTL_REG(0x0028) | |
| 82 | /* bit 1: antenna switch (together with CR9) | |
| 83 | * RF2959 controls with CR11 radion on and off | |
| 84 | */ | |
| 85 | #define CR11 CTL_REG(0x002C) | |
| 86 | /* bit 6: TX power control for OFDM | |
| 87 | * RF2959 controls with CR10 radio on and off | |
| 88 | */ | |
| 89 | #define CR12 CTL_REG(0x0030) | |
| 90 | #define CR13 CTL_REG(0x0034) | |
| 91 | #define CR14 CTL_REG(0x0038) | |
| 92 | #define CR15 CTL_REG(0x003C) | |
| 93 | #define CR16 CTL_REG(0x0040) | |
| 94 | #define CR17 CTL_REG(0x0044) | |
| 95 | #define CR18 CTL_REG(0x0048) | |
| 96 | #define CR19 CTL_REG(0x004C) | |
| 97 | #define CR20 CTL_REG(0x0050) | |
| 98 | #define CR21 CTL_REG(0x0054) | |
| 99 | #define CR22 CTL_REG(0x0058) | |
| 100 | #define CR23 CTL_REG(0x005C) | |
| 101 | #define CR24 CTL_REG(0x0060) /* CCA threshold */ | |
| 102 | #define CR25 CTL_REG(0x0064) | |
| 103 | #define CR26 CTL_REG(0x0068) | |
| 104 | #define CR27 CTL_REG(0x006C) | |
| 105 | #define CR28 CTL_REG(0x0070) | |
| 106 | #define CR29 CTL_REG(0x0074) | |
| 107 | #define CR30 CTL_REG(0x0078) | |
| 108 | #define CR31 CTL_REG(0x007C) /* TX power control for RF in CCK mode */ | |
| 109 | #define CR32 CTL_REG(0x0080) | |
| 110 | #define CR33 CTL_REG(0x0084) | |
| 111 | #define CR34 CTL_REG(0x0088) | |
| 112 | #define CR35 CTL_REG(0x008C) | |
| 113 | #define CR36 CTL_REG(0x0090) | |
| 114 | #define CR37 CTL_REG(0x0094) | |
| 115 | #define CR38 CTL_REG(0x0098) | |
| 116 | #define CR39 CTL_REG(0x009C) | |
| 117 | #define CR40 CTL_REG(0x00A0) | |
| 118 | #define CR41 CTL_REG(0x00A4) | |
| 119 | #define CR42 CTL_REG(0x00A8) | |
| 120 | #define CR43 CTL_REG(0x00AC) | |
| 121 | #define CR44 CTL_REG(0x00B0) | |
| 122 | #define CR45 CTL_REG(0x00B4) | |
| 123 | #define CR46 CTL_REG(0x00B8) | |
| 124 | #define CR47 CTL_REG(0x00BC) /* CCK baseband gain | |
| 125 | * (patch value might be in EEPROM) | |
| 126 | */ | |
| 127 | #define CR48 CTL_REG(0x00C0) | |
| 128 | #define CR49 CTL_REG(0x00C4) | |
| 129 | #define CR50 CTL_REG(0x00C8) | |
| 130 | #define CR51 CTL_REG(0x00CC) /* TX power control for RF in 6-36M modes */ | |
| 131 | #define CR52 CTL_REG(0x00D0) /* TX power control for RF in 48M mode */ | |
| 132 | #define CR53 CTL_REG(0x00D4) /* TX power control for RF in 54M mode */ | |
| 133 | #define CR54 CTL_REG(0x00D8) | |
| 134 | #define CR55 CTL_REG(0x00DC) | |
| 135 | #define CR56 CTL_REG(0x00E0) | |
| 136 | #define CR57 CTL_REG(0x00E4) | |
| 137 | #define CR58 CTL_REG(0x00E8) | |
| 138 | #define CR59 CTL_REG(0x00EC) | |
| 139 | #define CR60 CTL_REG(0x00F0) | |
| 140 | #define CR61 CTL_REG(0x00F4) | |
| 141 | #define CR62 CTL_REG(0x00F8) | |
| 142 | #define CR63 CTL_REG(0x00FC) | |
| 143 | #define CR64 CTL_REG(0x0100) | |
| 144 | #define CR65 CTL_REG(0x0104) /* OFDM 54M calibration */ | |
| 145 | #define CR66 CTL_REG(0x0108) /* OFDM 48M calibration */ | |
| 146 | #define CR67 CTL_REG(0x010C) /* OFDM 36M calibration */ | |
| 147 | #define CR68 CTL_REG(0x0110) /* CCK calibration */ | |
| 148 | #define CR69 CTL_REG(0x0114) | |
| 149 | #define CR70 CTL_REG(0x0118) | |
| 150 | #define CR71 CTL_REG(0x011C) | |
| 151 | #define CR72 CTL_REG(0x0120) | |
| 152 | #define CR73 CTL_REG(0x0124) | |
| 153 | #define CR74 CTL_REG(0x0128) | |
| 154 | #define CR75 CTL_REG(0x012C) | |
| 155 | #define CR76 CTL_REG(0x0130) | |
| 156 | #define CR77 CTL_REG(0x0134) | |
| 157 | #define CR78 CTL_REG(0x0138) | |
| 158 | #define CR79 CTL_REG(0x013C) | |
| 159 | #define CR80 CTL_REG(0x0140) | |
| 160 | #define CR81 CTL_REG(0x0144) | |
| 161 | #define CR82 CTL_REG(0x0148) | |
| 162 | #define CR83 CTL_REG(0x014C) | |
| 163 | #define CR84 CTL_REG(0x0150) | |
| 164 | #define CR85 CTL_REG(0x0154) | |
| 165 | #define CR86 CTL_REG(0x0158) | |
| 166 | #define CR87 CTL_REG(0x015C) | |
| 167 | #define CR88 CTL_REG(0x0160) | |
| 168 | #define CR89 CTL_REG(0x0164) | |
| 169 | #define CR90 CTL_REG(0x0168) | |
| 170 | #define CR91 CTL_REG(0x016C) | |
| 171 | #define CR92 CTL_REG(0x0170) | |
| 172 | #define CR93 CTL_REG(0x0174) | |
| 173 | #define CR94 CTL_REG(0x0178) | |
| 174 | #define CR95 CTL_REG(0x017C) | |
| 175 | #define CR96 CTL_REG(0x0180) | |
| 176 | #define CR97 CTL_REG(0x0184) | |
| 177 | #define CR98 CTL_REG(0x0188) | |
| 178 | #define CR99 CTL_REG(0x018C) | |
| 179 | #define CR100 CTL_REG(0x0190) | |
| 180 | #define CR101 CTL_REG(0x0194) | |
| 181 | #define CR102 CTL_REG(0x0198) | |
| 182 | #define CR103 CTL_REG(0x019C) | |
| 183 | #define CR104 CTL_REG(0x01A0) | |
| 184 | #define CR105 CTL_REG(0x01A4) | |
| 185 | #define CR106 CTL_REG(0x01A8) | |
| 186 | #define CR107 CTL_REG(0x01AC) | |
| 187 | #define CR108 CTL_REG(0x01B0) | |
| 188 | #define CR109 CTL_REG(0x01B4) | |
| 189 | #define CR110 CTL_REG(0x01B8) | |
| 190 | #define CR111 CTL_REG(0x01BC) | |
| 191 | #define CR112 CTL_REG(0x01C0) | |
| 192 | #define CR113 CTL_REG(0x01C4) | |
| 193 | #define CR114 CTL_REG(0x01C8) | |
| 194 | #define CR115 CTL_REG(0x01CC) | |
| 195 | #define CR116 CTL_REG(0x01D0) | |
| 196 | #define CR117 CTL_REG(0x01D4) | |
| 197 | #define CR118 CTL_REG(0x01D8) | |
| 198 | #define CR119 CTL_REG(0x01DC) | |
| 199 | #define CR120 CTL_REG(0x01E0) | |
| 200 | #define CR121 CTL_REG(0x01E4) | |
| 201 | #define CR122 CTL_REG(0x01E8) | |
| 202 | #define CR123 CTL_REG(0x01EC) | |
| 203 | #define CR124 CTL_REG(0x01F0) | |
| 204 | #define CR125 CTL_REG(0x01F4) | |
| 205 | #define CR126 CTL_REG(0x01F8) | |
| 206 | #define CR127 CTL_REG(0x01FC) | |
| 207 | #define CR128 CTL_REG(0x0200) | |
| 208 | #define CR129 CTL_REG(0x0204) | |
| 209 | #define CR130 CTL_REG(0x0208) | |
| 210 | #define CR131 CTL_REG(0x020C) | |
| 211 | #define CR132 CTL_REG(0x0210) | |
| 212 | #define CR133 CTL_REG(0x0214) | |
| 213 | #define CR134 CTL_REG(0x0218) | |
| 214 | #define CR135 CTL_REG(0x021C) | |
| 215 | #define CR136 CTL_REG(0x0220) | |
| 216 | #define CR137 CTL_REG(0x0224) | |
| 217 | #define CR138 CTL_REG(0x0228) | |
| 218 | #define CR139 CTL_REG(0x022C) | |
| 219 | #define CR140 CTL_REG(0x0230) | |
| 220 | #define CR141 CTL_REG(0x0234) | |
| 221 | #define CR142 CTL_REG(0x0238) | |
| 222 | #define CR143 CTL_REG(0x023C) | |
| 223 | #define CR144 CTL_REG(0x0240) | |
| 224 | #define CR145 CTL_REG(0x0244) | |
| 225 | #define CR146 CTL_REG(0x0248) | |
| 226 | #define CR147 CTL_REG(0x024C) | |
| 227 | #define CR148 CTL_REG(0x0250) | |
| 228 | #define CR149 CTL_REG(0x0254) | |
| 229 | #define CR150 CTL_REG(0x0258) | |
| 230 | #define CR151 CTL_REG(0x025C) | |
| 231 | #define CR152 CTL_REG(0x0260) | |
| 232 | #define CR153 CTL_REG(0x0264) | |
| 233 | #define CR154 CTL_REG(0x0268) | |
| 234 | #define CR155 CTL_REG(0x026C) | |
| 235 | #define CR156 CTL_REG(0x0270) | |
| 236 | #define CR157 CTL_REG(0x0274) | |
| 237 | #define CR158 CTL_REG(0x0278) | |
| 238 | #define CR159 CTL_REG(0x027C) | |
| 239 | #define CR160 CTL_REG(0x0280) | |
| 240 | #define CR161 CTL_REG(0x0284) | |
| 241 | #define CR162 CTL_REG(0x0288) | |
| 242 | #define CR163 CTL_REG(0x028C) | |
| 243 | #define CR164 CTL_REG(0x0290) | |
| 244 | #define CR165 CTL_REG(0x0294) | |
| 245 | #define CR166 CTL_REG(0x0298) | |
| 246 | #define CR167 CTL_REG(0x029C) | |
| 247 | #define CR168 CTL_REG(0x02A0) | |
| 248 | #define CR169 CTL_REG(0x02A4) | |
| 249 | #define CR170 CTL_REG(0x02A8) | |
| 250 | #define CR171 CTL_REG(0x02AC) | |
| 251 | #define CR172 CTL_REG(0x02B0) | |
| 252 | #define CR173 CTL_REG(0x02B4) | |
| 253 | #define CR174 CTL_REG(0x02B8) | |
| 254 | #define CR175 CTL_REG(0x02BC) | |
| 255 | #define CR176 CTL_REG(0x02C0) | |
| 256 | #define CR177 CTL_REG(0x02C4) | |
| 257 | #define CR178 CTL_REG(0x02C8) | |
| 258 | #define CR179 CTL_REG(0x02CC) | |
| 259 | #define CR180 CTL_REG(0x02D0) | |
| 260 | #define CR181 CTL_REG(0x02D4) | |
| 261 | #define CR182 CTL_REG(0x02D8) | |
| 262 | #define CR183 CTL_REG(0x02DC) | |
| 263 | #define CR184 CTL_REG(0x02E0) | |
| 264 | #define CR185 CTL_REG(0x02E4) | |
| 265 | #define CR186 CTL_REG(0x02E8) | |
| 266 | #define CR187 CTL_REG(0x02EC) | |
| 267 | #define CR188 CTL_REG(0x02F0) | |
| 268 | #define CR189 CTL_REG(0x02F4) | |
| 269 | #define CR190 CTL_REG(0x02F8) | |
| 270 | #define CR191 CTL_REG(0x02FC) | |
| 271 | #define CR192 CTL_REG(0x0300) | |
| 272 | #define CR193 CTL_REG(0x0304) | |
| 273 | #define CR194 CTL_REG(0x0308) | |
| 274 | #define CR195 CTL_REG(0x030C) | |
| 275 | #define CR196 CTL_REG(0x0310) | |
| 276 | #define CR197 CTL_REG(0x0314) | |
| 277 | #define CR198 CTL_REG(0x0318) | |
| 278 | #define CR199 CTL_REG(0x031C) | |
| 279 | #define CR200 CTL_REG(0x0320) | |
| 280 | #define CR201 CTL_REG(0x0324) | |
| 281 | #define CR202 CTL_REG(0x0328) | |
| 282 | #define CR203 CTL_REG(0x032C) /* I2C bus template value & flash control */ | |
| 283 | #define CR204 CTL_REG(0x0330) | |
| 284 | #define CR205 CTL_REG(0x0334) | |
| 285 | #define CR206 CTL_REG(0x0338) | |
| 286 | #define CR207 CTL_REG(0x033C) | |
| 287 | #define CR208 CTL_REG(0x0340) | |
| 288 | #define CR209 CTL_REG(0x0344) | |
| 289 | #define CR210 CTL_REG(0x0348) | |
| 290 | #define CR211 CTL_REG(0x034C) | |
| 291 | #define CR212 CTL_REG(0x0350) | |
| 292 | #define CR213 CTL_REG(0x0354) | |
| 293 | #define CR214 CTL_REG(0x0358) | |
| 294 | #define CR215 CTL_REG(0x035C) | |
| 295 | #define CR216 CTL_REG(0x0360) | |
| 296 | #define CR217 CTL_REG(0x0364) | |
| 297 | #define CR218 CTL_REG(0x0368) | |
| 298 | #define CR219 CTL_REG(0x036C) | |
| 299 | #define CR220 CTL_REG(0x0370) | |
| 300 | #define CR221 CTL_REG(0x0374) | |
| 301 | #define CR222 CTL_REG(0x0378) | |
| 302 | #define CR223 CTL_REG(0x037C) | |
| 303 | #define CR224 CTL_REG(0x0380) | |
| 304 | #define CR225 CTL_REG(0x0384) | |
| 305 | #define CR226 CTL_REG(0x0388) | |
| 306 | #define CR227 CTL_REG(0x038C) | |
| 307 | #define CR228 CTL_REG(0x0390) | |
| 308 | #define CR229 CTL_REG(0x0394) | |
| 309 | #define CR230 CTL_REG(0x0398) | |
| 310 | #define CR231 CTL_REG(0x039C) | |
| 311 | #define CR232 CTL_REG(0x03A0) | |
| 312 | #define CR233 CTL_REG(0x03A4) | |
| 313 | #define CR234 CTL_REG(0x03A8) | |
| 314 | #define CR235 CTL_REG(0x03AC) | |
| 315 | #define CR236 CTL_REG(0x03B0) | |
| 316 | ||
| 317 | #define CR240 CTL_REG(0x03C0) | |
| 318 | /* bit 7: host-controlled RF register writes | |
| 319 | * CR241-CR245: for hardware controlled writing of RF bits, not needed for | |
| 320 | * USB | |
| 321 | */ | |
| 322 | #define CR241 CTL_REG(0x03C4) | |
| 323 | #define CR242 CTL_REG(0x03C8) | |
| 324 | #define CR243 CTL_REG(0x03CC) | |
| 325 | #define CR244 CTL_REG(0x03D0) | |
| 326 | #define CR245 CTL_REG(0x03D4) | |
| 327 | ||
| 328 | #define CR251 CTL_REG(0x03EC) /* only used for activation and deactivation of | |
| 329 | * Airoha RFs AL2230 and AL7230B | |
| 330 | */ | |
| 331 | #define CR252 CTL_REG(0x03F0) | |
| 332 | #define CR253 CTL_REG(0x03F4) | |
| 333 | #define CR254 CTL_REG(0x03F8) | |
| 334 | #define CR255 CTL_REG(0x03FC) | |
| 335 | ||
| 336 | #define CR_MAX_PHY_REG 255 | |
| 337 | ||
| 0ce34bc8 | 338 | /* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211 |
| e85d0918 DD |
339 | * driver. |
| 340 | */ | |
| 341 | ||
| 342 | #define CR_RF_IF_CLK CTL_REG(0x0400) | |
| 343 | #define CR_RF_IF_DATA CTL_REG(0x0404) | |
| 344 | #define CR_PE1_PE2 CTL_REG(0x0408) | |
| 345 | #define CR_PE2_DLY CTL_REG(0x040C) | |
| 346 | #define CR_LE1 CTL_REG(0x0410) | |
| 347 | #define CR_LE2 CTL_REG(0x0414) | |
| 348 | /* Seems to enable/disable GPI (General Purpose IO?) */ | |
| 349 | #define CR_GPI_EN CTL_REG(0x0418) | |
| 350 | #define CR_RADIO_PD CTL_REG(0x042C) | |
| 351 | #define CR_RF2948_PD CTL_REG(0x042C) | |
| 352 | #define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C) | |
| 353 | #define CR_CONFIG_PHILIPS CTL_REG(0x0440) | |
| 354 | #define CR_SA2400_SER_AP CTL_REG(0x0444) | |
| 355 | #define CR_I2C_WRITE CTL_REG(0x0444) | |
| 356 | #define CR_SA2400_SER_RP CTL_REG(0x0448) | |
| 357 | #define CR_RADIO_PE CTL_REG(0x0458) | |
| 358 | #define CR_RST_BUS_MASTER CTL_REG(0x045C) | |
| 359 | #define CR_RFCFG CTL_REG(0x0464) | |
| 360 | #define CR_HSTSCHG CTL_REG(0x046C) | |
| 361 | #define CR_PHY_ON CTL_REG(0x0474) | |
| 362 | #define CR_RX_DELAY CTL_REG(0x0478) | |
| 363 | #define CR_RX_PE_DELAY CTL_REG(0x047C) | |
| 364 | #define CR_GPIO_1 CTL_REG(0x0490) | |
| 365 | #define CR_GPIO_2 CTL_REG(0x0494) | |
| 366 | #define CR_EncryBufMux CTL_REG(0x04A8) | |
| 367 | #define CR_PS_CTRL CTL_REG(0x0500) | |
| 368 | #define CR_ADDA_PWR_DWN CTL_REG(0x0504) | |
| 369 | #define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508) | |
| 370 | #define CR_MAC_PS_STATE CTL_REG(0x050C) | |
| 371 | ||
| 372 | #define CR_INTERRUPT CTL_REG(0x0510) | |
| 741fec53 UK |
373 | #define INT_TX_COMPLETE (1 << 0) |
| 374 | #define INT_RX_COMPLETE (1 << 1) | |
| 375 | #define INT_RETRY_FAIL (1 << 2) | |
| 376 | #define INT_WAKEUP (1 << 3) | |
| 377 | #define INT_DTIM_NOTIFY (1 << 5) | |
| 378 | #define INT_CFG_NEXT_BCN (1 << 6) | |
| 379 | #define INT_BUS_ABORT (1 << 7) | |
| 380 | #define INT_TX_FIFO_READY (1 << 8) | |
| 381 | #define INT_UART (1 << 9) | |
| 382 | #define INT_TX_COMPLETE_EN (1 << 16) | |
| 383 | #define INT_RX_COMPLETE_EN (1 << 17) | |
| 384 | #define INT_RETRY_FAIL_EN (1 << 18) | |
| 385 | #define INT_WAKEUP_EN (1 << 19) | |
| 386 | #define INT_DTIM_NOTIFY_EN (1 << 21) | |
| 387 | #define INT_CFG_NEXT_BCN_EN (1 << 22) | |
| 388 | #define INT_BUS_ABORT_EN (1 << 23) | |
| 389 | #define INT_TX_FIFO_READY_EN (1 << 24) | |
| 390 | #define INT_UART_EN (1 << 25) | |
| e85d0918 DD |
391 | |
| 392 | #define CR_TSF_LOW_PART CTL_REG(0x0514) | |
| 393 | #define CR_TSF_HIGH_PART CTL_REG(0x0518) | |
| 394 | ||
| 395 | /* Following three values are in time units (1024us) | |
| 396 | * Following condition must be met: | |
| 397 | * atim < tbtt < bcn | |
| 398 | */ | |
| 399 | #define CR_ATIM_WND_PERIOD CTL_REG(0x051C) | |
| 400 | #define CR_BCN_INTERVAL CTL_REG(0x0520) | |
| 401 | #define CR_PRE_TBTT CTL_REG(0x0524) | |
| 402 | /* in units of TU(1024us) */ | |
| 403 | ||
| 404 | /* for UART support */ | |
| 405 | #define CR_UART_RBR_THR_DLL CTL_REG(0x0540) | |
| 406 | #define CR_UART_DLM_IER CTL_REG(0x0544) | |
| 407 | #define CR_UART_IIR_FCR CTL_REG(0x0548) | |
| 408 | #define CR_UART_LCR CTL_REG(0x054c) | |
| 409 | #define CR_UART_MCR CTL_REG(0x0550) | |
| 410 | #define CR_UART_LSR CTL_REG(0x0554) | |
| 411 | #define CR_UART_MSR CTL_REG(0x0558) | |
| 412 | #define CR_UART_ECR CTL_REG(0x055c) | |
| 413 | #define CR_UART_STATUS CTL_REG(0x0560) | |
| 414 | ||
| 415 | #define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600) | |
| 416 | #define CR_PCI_TX_AddR_P2 CTL_REG(0x0604) | |
| 417 | #define CR_PCI_RX_AddR_P1 CTL_REG(0x0608) | |
| 418 | #define CR_PCI_RX_AddR_P2 CTL_REG(0x060C) | |
| 419 | ||
| 420 | /* must be overwritten if custom MAC address will be used */ | |
| 421 | #define CR_MAC_ADDR_P1 CTL_REG(0x0610) | |
| 422 | #define CR_MAC_ADDR_P2 CTL_REG(0x0614) | |
| 423 | #define CR_BSSID_P1 CTL_REG(0x0618) | |
| 424 | #define CR_BSSID_P2 CTL_REG(0x061C) | |
| 425 | #define CR_BCN_PLCP_CFG CTL_REG(0x0620) | |
| 9cdac965 UK |
426 | |
| 427 | /* Group hash table for filtering incoming packets. | |
| 428 | * | |
| 429 | * The group hash table is 64 bit large and split over two parts. The first | |
| 430 | * part is the lower part. The upper 6 bits of the last byte of the target | |
| 431 | * address are used as index. Packets are received if the hash table bit is | |
| 432 | * set. This is used for multicast handling, but for broadcasts (address | |
| 433 | * ff:ff:ff:ff:ff:ff) the highest bit in the second table must also be set. | |
| 434 | */ | |
| e85d0918 DD |
435 | #define CR_GROUP_HASH_P1 CTL_REG(0x0624) |
| 436 | #define CR_GROUP_HASH_P2 CTL_REG(0x0628) | |
| e85d0918 | 437 | |
| 9cdac965 | 438 | #define CR_RX_TIMEOUT CTL_REG(0x062C) |
| 459c51ad | 439 | |
| e85d0918 DD |
440 | /* Basic rates supported by the BSS. When producing ACK or CTS messages, the |
| 441 | * device will use a rate in this table that is less than or equal to the rate | |
| 459c51ad | 442 | * of the incoming frame which prompted the response. */ |
| e85d0918 | 443 | #define CR_BASIC_RATE_TBL CTL_REG(0x0630) |
| 741fec53 UK |
444 | #define CR_RATE_1M (1 << 0) /* 802.11b */ |
| 445 | #define CR_RATE_2M (1 << 1) /* 802.11b */ | |
| 446 | #define CR_RATE_5_5M (1 << 2) /* 802.11b */ | |
| 447 | #define CR_RATE_11M (1 << 3) /* 802.11b */ | |
| 448 | #define CR_RATE_6M (1 << 8) /* 802.11g */ | |
| 449 | #define CR_RATE_9M (1 << 9) /* 802.11g */ | |
| 450 | #define CR_RATE_12M (1 << 10) /* 802.11g */ | |
| 451 | #define CR_RATE_18M (1 << 11) /* 802.11g */ | |
| 452 | #define CR_RATE_24M (1 << 12) /* 802.11g */ | |
| 453 | #define CR_RATE_36M (1 << 13) /* 802.11g */ | |
| 454 | #define CR_RATE_48M (1 << 14) /* 802.11g */ | |
| 455 | #define CR_RATE_54M (1 << 15) /* 802.11g */ | |
| e85d0918 DD |
456 | #define CR_RATES_80211G 0xff00 |
| 457 | #define CR_RATES_80211B 0x000f | |
| 458 | ||
| 459 | /* Mandatory rates required in the BSS. When producing ACK or CTS messages, if | |
| 460 | * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will | |
| 461 | * look for a rate in this table that is less than or equal to the rate of | |
| 462 | * the incoming frame. */ | |
| 463 | #define CR_MANDATORY_RATE_TBL CTL_REG(0x0634) | |
| 464 | #define CR_RTS_CTS_RATE CTL_REG(0x0638) | |
| 465 | ||
| b1382ede DD |
466 | /* These are all bit indexes in CR_RTS_CTS_RATE, so remember to shift. */ |
| 467 | #define RTSCTS_SH_RTS_RATE 0 | |
| 468 | #define RTSCTS_SH_EXP_CTS_RATE 4 | |
| 469 | #define RTSCTS_SH_RTS_MOD_TYPE 8 | |
| 470 | #define RTSCTS_SH_RTS_PMB_TYPE 9 | |
| 471 | #define RTSCTS_SH_CTS_RATE 16 | |
| 472 | #define RTSCTS_SH_CTS_MOD_TYPE 24 | |
| 473 | #define RTSCTS_SH_CTS_PMB_TYPE 25 | |
| 474 | ||
| e85d0918 DD |
475 | #define CR_WEP_PROTECT CTL_REG(0x063C) |
| 476 | #define CR_RX_THRESHOLD CTL_REG(0x0640) | |
| 477 | ||
| 478 | /* register for controlling the LEDS */ | |
| 479 | #define CR_LED CTL_REG(0x0644) | |
| 480 | /* masks for controlling LEDs */ | |
| 741fec53 UK |
481 | #define LED1 (1 << 8) |
| 482 | #define LED2 (1 << 9) | |
| 483 | #define LED_SW (1 << 10) | |
| e85d0918 DD |
484 | |
| 485 | /* Seems to indicate that the configuration is over. | |
| 486 | */ | |
| 487 | #define CR_AFTER_PNP CTL_REG(0x0648) | |
| 488 | #define CR_ACK_TIME_80211 CTL_REG(0x0658) | |
| 489 | ||
| 490 | #define CR_RX_OFFSET CTL_REG(0x065c) | |
| 491 | ||
| 72e77a8a | 492 | #define CR_BCN_LENGTH CTL_REG(0x0664) |
| e85d0918 DD |
493 | #define CR_PHY_DELAY CTL_REG(0x066C) |
| 494 | #define CR_BCN_FIFO CTL_REG(0x0670) | |
| 495 | #define CR_SNIFFER_ON CTL_REG(0x0674) | |
| 496 | ||
| 497 | #define CR_ENCRYPTION_TYPE CTL_REG(0x0678) | |
| 498 | #define NO_WEP 0 | |
| 499 | #define WEP64 1 | |
| 500 | #define WEP128 5 | |
| 501 | #define WEP256 6 | |
| 502 | #define ENC_SNIFFER 8 | |
| 503 | ||
| 504 | #define CR_ZD1211_RETRY_MAX CTL_REG(0x067C) | |
| 505 | ||
| 506 | #define CR_REG1 CTL_REG(0x0680) | |
| 507 | /* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical | |
| 508 | * registers, so one could argue it is a LOCK bit. But calling it | |
| 509 | * LOCK_PHY_REGS makes it confusing. | |
| 510 | */ | |
| 741fec53 | 511 | #define UNLOCK_PHY_REGS (1 << 7) |
| e85d0918 DD |
512 | |
| 513 | #define CR_DEVICE_STATE CTL_REG(0x0684) | |
| 514 | #define CR_UNDERRUN_CNT CTL_REG(0x0688) | |
| 515 | ||
| 516 | #define CR_RX_FILTER CTL_REG(0x068c) | |
| 459c51ad | 517 | #define RX_FILTER_ASSOC_REQUEST (1 << 0) |
| 741fec53 | 518 | #define RX_FILTER_ASSOC_RESPONSE (1 << 1) |
| 459c51ad | 519 | #define RX_FILTER_REASSOC_REQUEST (1 << 2) |
| 741fec53 | 520 | #define RX_FILTER_REASSOC_RESPONSE (1 << 3) |
| 459c51ad | 521 | #define RX_FILTER_PROBE_REQUEST (1 << 4) |
| 741fec53 | 522 | #define RX_FILTER_PROBE_RESPONSE (1 << 5) |
| 459c51ad | 523 | /* bits 6 and 7 reserved */ |
| 741fec53 | 524 | #define RX_FILTER_BEACON (1 << 8) |
| 459c51ad | 525 | #define RX_FILTER_ATIM (1 << 9) |
| 741fec53 UK |
526 | #define RX_FILTER_DISASSOC (1 << 10) |
| 527 | #define RX_FILTER_AUTH (1 << 11) | |
| 459c51ad DD |
528 | #define RX_FILTER_DEAUTH (1 << 12) |
| 529 | #define RX_FILTER_PSPOLL (1 << 26) | |
| 530 | #define RX_FILTER_RTS (1 << 27) | |
| 531 | #define RX_FILTER_CTS (1 << 28) | |
| 532 | #define RX_FILTER_ACK (1 << 29) | |
| 533 | #define RX_FILTER_CFEND (1 << 30) | |
| 534 | #define RX_FILTER_CFACK (1 << 31) | |
| 535 | ||
| 536 | /* Enable bits for all frames you are interested in. */ | |
| 537 | #define STA_RX_FILTER (RX_FILTER_ASSOC_REQUEST | RX_FILTER_ASSOC_RESPONSE | \ | |
| 538 | RX_FILTER_REASSOC_REQUEST | RX_FILTER_REASSOC_RESPONSE | \ | |
| 539 | RX_FILTER_PROBE_REQUEST | RX_FILTER_PROBE_RESPONSE | \ | |
| 540 | (0x3 << 6) /* vendor driver sets these reserved bits */ | \ | |
| 541 | RX_FILTER_BEACON | RX_FILTER_ATIM | RX_FILTER_DISASSOC | \ | |
| 542 | RX_FILTER_AUTH | RX_FILTER_DEAUTH | \ | |
| 543 | (0x7 << 13) /* vendor driver sets these reserved bits */ | \ | |
| 544 | RX_FILTER_PSPOLL | RX_FILTER_ACK) /* 0x2400ffff */ | |
| 545 | ||
| 546 | #define RX_FILTER_CTRL (RX_FILTER_RTS | RX_FILTER_CTS | \ | |
| 547 | RX_FILTER_CFEND | RX_FILTER_CFACK) | |
| fde627b5 | 548 | |
| 72e77a8a LCC |
549 | #define BCN_MODE_IBSS 0x2000000 |
| 550 | ||
| 71eae25e | 551 | /* Monitor mode sets filter to 0xfffff */ |
| e85d0918 DD |
552 | |
| 553 | #define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690) | |
| 554 | #define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694) | |
| 98227a90 | 555 | |
| e85d0918 | 556 | #define CR_IFS_VALUE CTL_REG(0x0698) |
| 98227a90 DD |
557 | #define IFS_VALUE_DIFS_SH 0 |
| 558 | #define IFS_VALUE_EIFS_SH 12 | |
| 559 | #define IFS_VALUE_SIFS_SH 24 | |
| 560 | #define IFS_VALUE_DEFAULT (( 50 << IFS_VALUE_DIFS_SH) | \ | |
| 561 | (1148 << IFS_VALUE_EIFS_SH) | \ | |
| 562 | ( 10 << IFS_VALUE_SIFS_SH)) | |
| 563 | ||
| e85d0918 DD |
564 | #define CR_RX_TIME_OUT CTL_REG(0x069C) |
| 565 | #define CR_TOTAL_RX_FRM CTL_REG(0x06A0) | |
| 566 | #define CR_CRC32_CNT CTL_REG(0x06A4) | |
| 567 | #define CR_CRC16_CNT CTL_REG(0x06A8) | |
| 568 | #define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC) | |
| 569 | #define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0) | |
| 570 | ||
| 571 | #define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC) | |
| 572 | ||
| 573 | #define CR_NAV_CNT CTL_REG(0x06C4) | |
| 574 | #define CR_NAV_CCA CTL_REG(0x06C8) | |
| 575 | #define CR_RETRY_CNT CTL_REG(0x06CC) | |
| 576 | ||
| 577 | #define CR_READ_TCB_ADDR CTL_REG(0x06E8) | |
| 578 | #define CR_READ_RFD_ADDR CTL_REG(0x06EC) | |
| 579 | #define CR_CWMIN_CWMAX CTL_REG(0x06F0) | |
| 580 | #define CR_TOTAL_TX_FRM CTL_REG(0x06F4) | |
| 581 | ||
| 582 | /* CAM: Continuous Access Mode (power management) */ | |
| 583 | #define CR_CAM_MODE CTL_REG(0x0700) | |
| 72e77a8a LCC |
584 | #define MODE_IBSS 0x0 |
| 585 | #define MODE_AP 0x1 | |
| 586 | #define MODE_STA 0x2 | |
| 587 | #define MODE_AP_WDS 0x3 | |
| 588 | ||
| e85d0918 DD |
589 | #define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704) |
| 590 | #define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708) | |
| 591 | #define CR_CAM_ADDRESS CTL_REG(0x070C) | |
| 592 | #define CR_CAM_DATA CTL_REG(0x0710) | |
| 593 | ||
| 594 | #define CR_ROMDIR CTL_REG(0x0714) | |
| 595 | ||
| 596 | #define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714) | |
| 597 | #define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718) | |
| 598 | ||
| 599 | #define CR_WEPKEY0 CTL_REG(0x0720) | |
| 600 | #define CR_WEPKEY1 CTL_REG(0x0724) | |
| 601 | #define CR_WEPKEY2 CTL_REG(0x0728) | |
| 602 | #define CR_WEPKEY3 CTL_REG(0x072C) | |
| 603 | #define CR_WEPKEY4 CTL_REG(0x0730) | |
| 604 | #define CR_WEPKEY5 CTL_REG(0x0734) | |
| 605 | #define CR_WEPKEY6 CTL_REG(0x0738) | |
| 606 | #define CR_WEPKEY7 CTL_REG(0x073C) | |
| 607 | #define CR_WEPKEY8 CTL_REG(0x0740) | |
| 608 | #define CR_WEPKEY9 CTL_REG(0x0744) | |
| 609 | #define CR_WEPKEY10 CTL_REG(0x0748) | |
| 610 | #define CR_WEPKEY11 CTL_REG(0x074C) | |
| 611 | #define CR_WEPKEY12 CTL_REG(0x0750) | |
| 612 | #define CR_WEPKEY13 CTL_REG(0x0754) | |
| 613 | #define CR_WEPKEY14 CTL_REG(0x0758) | |
| 614 | #define CR_WEPKEY15 CTL_REG(0x075c) | |
| 615 | #define CR_TKIP_MODE CTL_REG(0x0760) | |
| 616 | ||
| 617 | #define CR_EEPROM_PROTECT0 CTL_REG(0x0758) | |
| 618 | #define CR_EEPROM_PROTECT1 CTL_REG(0x075C) | |
| 619 | ||
| 620 | #define CR_DBG_FIFO_RD CTL_REG(0x0800) | |
| 621 | #define CR_DBG_SELECT CTL_REG(0x0804) | |
| 622 | #define CR_FIFO_Length CTL_REG(0x0808) | |
| 623 | ||
| 624 | ||
| 625 | #define CR_RSSI_MGC CTL_REG(0x0810) | |
| 626 | ||
| 627 | #define CR_PON CTL_REG(0x0818) | |
| 628 | #define CR_RX_ON CTL_REG(0x081C) | |
| 629 | #define CR_TX_ON CTL_REG(0x0820) | |
| 630 | #define CR_CHIP_EN CTL_REG(0x0824) | |
| 631 | #define CR_LO_SW CTL_REG(0x0828) | |
| 632 | #define CR_TXRX_SW CTL_REG(0x082C) | |
| 633 | #define CR_S_MD CTL_REG(0x0830) | |
| 634 | ||
| 635 | #define CR_USB_DEBUG_PORT CTL_REG(0x0888) | |
| e51c6837 JC |
636 | #define CR_ZD1211B_CWIN_MAX_MIN_AC0 CTL_REG(0x0b00) |
| 637 | #define CR_ZD1211B_CWIN_MAX_MIN_AC1 CTL_REG(0x0b04) | |
| 638 | #define CR_ZD1211B_CWIN_MAX_MIN_AC2 CTL_REG(0x0b08) | |
| 639 | #define CR_ZD1211B_CWIN_MAX_MIN_AC3 CTL_REG(0x0b0c) | |
| e85d0918 DD |
640 | #define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10) |
| 641 | #define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14) | |
| 642 | #define CR_ZD1211B_TXOP CTL_REG(0x0b20) | |
| 643 | #define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28) | |
| 644 | ||
| 4481d609 DD |
645 | /* Used to detect PLL lock */ |
| 646 | #define UW2453_INTR_REG ((zd_addr_t)0x85c1) | |
| 647 | ||
| e85d0918 DD |
648 | #define CWIN_SIZE 0x007f043f |
| 649 | ||
| 650 | ||
| 651 | #define HWINT_ENABLED 0x004f0000 | |
| 652 | #define HWINT_DISABLED 0 | |
| 653 | ||
| 654 | #define E2P_PWR_INT_GUARD 8 | |
| 655 | #define E2P_CHANNEL_COUNT 14 | |
| 656 | ||
| 657 | /* If you compare this addresses with the ZYDAS orignal driver, please notify | |
| 658 | * that we use word mapping for the EEPROM. | |
| 659 | */ | |
| 660 | ||
| 661 | /* | |
| 662 | * Upper 16 bit contains the regulatory domain. | |
| 663 | */ | |
| ee302767 DD |
664 | #define E2P_SUBID E2P_DATA(0x00) |
| 665 | #define E2P_POD E2P_DATA(0x02) | |
| 666 | #define E2P_MAC_ADDR_P1 E2P_DATA(0x04) | |
| 667 | #define E2P_MAC_ADDR_P2 E2P_DATA(0x06) | |
| 668 | #define E2P_PWR_CAL_VALUE1 E2P_DATA(0x08) | |
| 669 | #define E2P_PWR_CAL_VALUE2 E2P_DATA(0x0a) | |
| 670 | #define E2P_PWR_CAL_VALUE3 E2P_DATA(0x0c) | |
| 671 | #define E2P_PWR_CAL_VALUE4 E2P_DATA(0x0e) | |
| 672 | #define E2P_PWR_INT_VALUE1 E2P_DATA(0x10) | |
| 673 | #define E2P_PWR_INT_VALUE2 E2P_DATA(0x12) | |
| 674 | #define E2P_PWR_INT_VALUE3 E2P_DATA(0x14) | |
| 675 | #define E2P_PWR_INT_VALUE4 E2P_DATA(0x16) | |
| e85d0918 DD |
676 | |
| 677 | /* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) | |
| 678 | * also only 11 channels. */ | |
| ee302767 DD |
679 | #define E2P_ALLOWED_CHANNEL E2P_DATA(0x18) |
| 680 | ||
| ee302767 | 681 | #define E2P_DEVICE_VER E2P_DATA(0x20) |
| 92b3e2e9 | 682 | #define E2P_PHY_REG E2P_DATA(0x25) |
| ee302767 DD |
683 | #define E2P_36M_CAL_VALUE1 E2P_DATA(0x28) |
| 684 | #define E2P_36M_CAL_VALUE2 E2P_DATA(0x2a) | |
| 685 | #define E2P_36M_CAL_VALUE3 E2P_DATA(0x2c) | |
| 686 | #define E2P_36M_CAL_VALUE4 E2P_DATA(0x2e) | |
| 687 | #define E2P_11A_INT_VALUE1 E2P_DATA(0x30) | |
| 688 | #define E2P_11A_INT_VALUE2 E2P_DATA(0x32) | |
| 689 | #define E2P_11A_INT_VALUE3 E2P_DATA(0x34) | |
| 690 | #define E2P_11A_INT_VALUE4 E2P_DATA(0x36) | |
| 691 | #define E2P_48M_CAL_VALUE1 E2P_DATA(0x38) | |
| 692 | #define E2P_48M_CAL_VALUE2 E2P_DATA(0x3a) | |
| 693 | #define E2P_48M_CAL_VALUE3 E2P_DATA(0x3c) | |
| 694 | #define E2P_48M_CAL_VALUE4 E2P_DATA(0x3e) | |
| 695 | #define E2P_48M_INT_VALUE1 E2P_DATA(0x40) | |
| 696 | #define E2P_48M_INT_VALUE2 E2P_DATA(0x42) | |
| 697 | #define E2P_48M_INT_VALUE3 E2P_DATA(0x44) | |
| 698 | #define E2P_48M_INT_VALUE4 E2P_DATA(0x46) | |
| 699 | #define E2P_54M_CAL_VALUE1 E2P_DATA(0x48) /* ??? */ | |
| 700 | #define E2P_54M_CAL_VALUE2 E2P_DATA(0x4a) | |
| 701 | #define E2P_54M_CAL_VALUE3 E2P_DATA(0x4c) | |
| 702 | #define E2P_54M_CAL_VALUE4 E2P_DATA(0x4e) | |
| 703 | #define E2P_54M_INT_VALUE1 E2P_DATA(0x50) | |
| 704 | #define E2P_54M_INT_VALUE2 E2P_DATA(0x52) | |
| 705 | #define E2P_54M_INT_VALUE3 E2P_DATA(0x54) | |
| 706 | #define E2P_54M_INT_VALUE4 E2P_DATA(0x56) | |
| e85d0918 | 707 | |
| 0ce34bc8 DD |
708 | /* This word contains the base address of the FW_REG_ registers below */ |
| 709 | #define FWRAW_REGS_ADDR FWRAW_DATA(0x1d) | |
| 710 | ||
| 711 | /* All 16 bit values, offset from the address in FWRAW_REGS_ADDR */ | |
| 712 | enum { | |
| 713 | FW_REG_FIRMWARE_VER = 0, | |
| 714 | /* non-zero if USB high speed connection */ | |
| 715 | FW_REG_USB_SPEED = 1, | |
| 716 | FW_REG_FIX_TX_RATE = 2, | |
| 717 | /* Seems to be able to control LEDs over the firmware */ | |
| 718 | FW_REG_LED_LINK_STATUS = 3, | |
| 719 | FW_REG_SOFT_RESET = 4, | |
| 720 | FW_REG_FLASH_CHK = 5, | |
| 721 | }; | |
| e85d0918 | 722 | |
| 0ce34bc8 | 723 | /* Values for FW_LINK_STATUS */ |
| 583afd1e UK |
724 | #define FW_LINK_OFF 0x0 |
| 725 | #define FW_LINK_TX 0x1 | |
| 726 | /* 0x2 - link led on? */ | |
| 727 | ||
| e85d0918 DD |
728 | enum { |
| 729 | /* indices for ofdm_cal_values */ | |
| 730 | OFDM_36M_INDEX = 0, | |
| 731 | OFDM_48M_INDEX = 1, | |
| 732 | OFDM_54M_INDEX = 2, | |
| 733 | }; | |
| 734 | ||
| 735 | struct zd_chip { | |
| 736 | struct zd_usb usb; | |
| 737 | struct zd_rf rf; | |
| 738 | struct mutex mutex; | |
| 0ce34bc8 DD |
739 | /* Base address of FW_REG_ registers */ |
| 740 | zd_addr_t fw_regs_base; | |
| e85d0918 DD |
741 | /* EepSetPoint in the vendor driver */ |
| 742 | u8 pwr_cal_values[E2P_CHANNEL_COUNT]; | |
| 743 | /* integration values in the vendor driver */ | |
| 744 | u8 pwr_int_values[E2P_CHANNEL_COUNT]; | |
| 745 | /* SetPointOFDM in the vendor driver */ | |
| 746 | u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT]; | |
| 583afd1e UK |
747 | u16 link_led; |
| 748 | unsigned int pa_type:4, | |
| 749 | patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1, | |
| ae6ead46 | 750 | new_phy_layout:1, al2230s_bit:1, |
| 74553aed | 751 | supports_tx_led:1; |
| e85d0918 DD |
752 | }; |
| 753 | ||
| 754 | static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb) | |
| 755 | { | |
| 756 | return container_of(usb, struct zd_chip, usb); | |
| 757 | } | |
| 758 | ||
| 759 | static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf) | |
| 760 | { | |
| 761 | return container_of(rf, struct zd_chip, rf); | |
| 762 | } | |
| 763 | ||
| 764 | #define zd_chip_dev(chip) (&(chip)->usb.intf->dev) | |
| 765 | ||
| 766 | void zd_chip_init(struct zd_chip *chip, | |
| 459c51ad | 767 | struct ieee80211_hw *hw, |
| e85d0918 DD |
768 | struct usb_interface *intf); |
| 769 | void zd_chip_clear(struct zd_chip *chip); | |
| 74553aed DD |
770 | int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr); |
| 771 | int zd_chip_init_hw(struct zd_chip *chip); | |
| e85d0918 DD |
772 | int zd_chip_reset(struct zd_chip *chip); |
| 773 | ||
| 74553aed DD |
774 | static inline int zd_chip_is_zd1211b(struct zd_chip *chip) |
| 775 | { | |
| 776 | return chip->usb.is_zd1211b; | |
| 777 | } | |
| 778 | ||
| e85d0918 DD |
779 | static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, |
| 780 | const zd_addr_t *addresses, | |
| 781 | unsigned int count) | |
| 782 | { | |
| 783 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
| 784 | return zd_usb_ioread16v(&chip->usb, values, addresses, count); | |
| 785 | } | |
| 786 | ||
| 787 | static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, | |
| 788 | const zd_addr_t addr) | |
| 789 | { | |
| 790 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
| 791 | return zd_usb_ioread16(&chip->usb, value, addr); | |
| 792 | } | |
| 793 | ||
| 794 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, | |
| 795 | const zd_addr_t *addresses, unsigned int count); | |
| 796 | ||
| 797 | static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, | |
| 798 | const zd_addr_t addr) | |
| 799 | { | |
| 800 | return zd_ioread32v_locked(chip, value, (const zd_addr_t *)&addr, 1); | |
| 801 | } | |
| 802 | ||
| 803 | static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, | |
| 804 | zd_addr_t addr) | |
| 805 | { | |
| 806 | struct zd_ioreq16 ioreq; | |
| 807 | ||
| 808 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
| 809 | ioreq.addr = addr; | |
| 810 | ioreq.value = value; | |
| 811 | ||
| 812 | return zd_usb_iowrite16v(&chip->usb, &ioreq, 1); | |
| 813 | } | |
| 814 | ||
| 815 | int zd_iowrite16a_locked(struct zd_chip *chip, | |
| 816 | const struct zd_ioreq16 *ioreqs, unsigned int count); | |
| 817 | ||
| 818 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
| 819 | unsigned int count); | |
| 820 | ||
| 821 | static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, | |
| 822 | zd_addr_t addr) | |
| 823 | { | |
| 824 | struct zd_ioreq32 ioreq; | |
| 825 | ||
| 826 | ioreq.addr = addr; | |
| 827 | ioreq.value = value; | |
| 828 | ||
| 829 | return _zd_iowrite32v_locked(chip, &ioreq, 1); | |
| 830 | } | |
| 831 | ||
| 832 | int zd_iowrite32a_locked(struct zd_chip *chip, | |
| 833 | const struct zd_ioreq32 *ioreqs, unsigned int count); | |
| 834 | ||
| 835 | static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits) | |
| 836 | { | |
| 837 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | |
| 838 | return zd_usb_rfwrite(&chip->usb, value, bits); | |
| 839 | } | |
| 840 | ||
| ec62bd91 DD |
841 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value); |
| 842 | ||
| e85d0918 DD |
843 | int zd_rfwritev_locked(struct zd_chip *chip, |
| 844 | const u32* values, unsigned int count, u8 bits); | |
| 20fe2176 DD |
845 | int zd_rfwritev_cr_locked(struct zd_chip *chip, |
| 846 | const u32* values, unsigned int count); | |
| e85d0918 DD |
847 | |
| 848 | /* Locking functions for reading and writing registers. | |
| 849 | * The different parameters are intentional. | |
| 850 | */ | |
| 851 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value); | |
| 852 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value); | |
| 853 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value); | |
| 854 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value); | |
| 855 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, | |
| 856 | u32 *values, unsigned int count); | |
| 857 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |
| 858 | unsigned int count); | |
| 859 | ||
| 860 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel); | |
| 861 | static inline u8 _zd_chip_get_channel(struct zd_chip *chip) | |
| 862 | { | |
| 863 | return chip->rf.channel; | |
| 864 | } | |
| 865 | u8 zd_chip_get_channel(struct zd_chip *chip); | |
| 866 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain); | |
| e85d0918 DD |
867 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr); |
| 868 | int zd_chip_switch_radio_on(struct zd_chip *chip); | |
| 869 | int zd_chip_switch_radio_off(struct zd_chip *chip); | |
| 870 | int zd_chip_enable_int(struct zd_chip *chip); | |
| 871 | void zd_chip_disable_int(struct zd_chip *chip); | |
| 459c51ad DD |
872 | int zd_chip_enable_rxtx(struct zd_chip *chip); |
| 873 | void zd_chip_disable_rxtx(struct zd_chip *chip); | |
| e85d0918 DD |
874 | int zd_chip_enable_hwint(struct zd_chip *chip); |
| 875 | int zd_chip_disable_hwint(struct zd_chip *chip); | |
| 72018b22 | 876 | int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel); |
| 459c51ad | 877 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, int preamble); |
| b1382ede | 878 | |
| e85d0918 DD |
879 | static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type) |
| 880 | { | |
| 881 | return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type); | |
| 882 | } | |
| 883 | ||
| 884 | static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type) | |
| 885 | { | |
| 886 | return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type); | |
| 887 | } | |
| 888 | ||
| 889 | static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates) | |
| 890 | { | |
| 891 | return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates); | |
| 892 | } | |
| 893 | ||
| 459c51ad | 894 | int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates); |
| e85d0918 | 895 | |
| e85d0918 DD |
896 | int zd_chip_lock_phy_regs(struct zd_chip *chip); |
| 897 | int zd_chip_unlock_phy_regs(struct zd_chip *chip); | |
| 898 | ||
| 899 | enum led_status { | |
| 14b46c8a LR |
900 | ZD_LED_OFF = 0, |
| 901 | ZD_LED_SCANNING = 1, | |
| 902 | ZD_LED_ASSOCIATED = 2, | |
| e85d0918 DD |
903 | }; |
| 904 | ||
| 583afd1e | 905 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status); |
| e85d0918 DD |
906 | |
| 907 | int zd_set_beacon_interval(struct zd_chip *chip, u32 interval); | |
| 908 | ||
| 909 | static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval) | |
| 910 | { | |
| 911 | return zd_ioread32(chip, CR_BCN_INTERVAL, interval); | |
| 912 | } | |
| 913 | ||
| 914 | struct rx_status; | |
| 915 | ||
| 916 | u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, | |
| 917 | const struct rx_status *status); | |
| e85d0918 | 918 | |
| 459c51ad | 919 | u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status); |
| e85d0918 | 920 | |
| 9cdac965 UK |
921 | struct zd_mc_hash { |
| 922 | u32 low; | |
| 923 | u32 high; | |
| 924 | }; | |
| 925 | ||
| 926 | static inline void zd_mc_clear(struct zd_mc_hash *hash) | |
| 927 | { | |
| 928 | hash->low = 0; | |
| 929 | /* The interfaces must always received broadcasts. | |
| 930 | * The hash of the broadcast address ff:ff:ff:ff:ff:ff is 63. | |
| 931 | */ | |
| 932 | hash->high = 0x80000000; | |
| 933 | } | |
| 934 | ||
| 935 | static inline void zd_mc_add_all(struct zd_mc_hash *hash) | |
| 936 | { | |
| 937 | hash->low = hash->high = 0xffffffff; | |
| 938 | } | |
| 939 | ||
| 940 | static inline void zd_mc_add_addr(struct zd_mc_hash *hash, u8 *addr) | |
| 941 | { | |
| 942 | unsigned int i = addr[5] >> 2; | |
| 943 | if (i < 32) { | |
| 944 | hash->low |= 1 << i; | |
| 945 | } else { | |
| 946 | hash->high |= 1 << (i-32); | |
| 947 | } | |
| 948 | } | |
| 949 | ||
| 950 | int zd_chip_set_multicast_hash(struct zd_chip *chip, | |
| 951 | struct zd_mc_hash *hash); | |
| 952 | ||
| 5fe73197 AF |
953 | u64 zd_chip_get_tsf(struct zd_chip *chip); |
| 954 | ||
| e85d0918 | 955 | #endif /* _ZD_CHIP_H */ |