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1 | /* ZD1211 USB-WLAN driver for Linux |
2 | * | |
3 | * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> | |
4 | * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> | |
4481d609 DD |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
4481d609 DD |
23 | |
24 | #include "zd_rf.h" | |
25 | #include "zd_usb.h" | |
26 | #include "zd_chip.h" | |
27 | ||
28 | /* This RF programming code is based upon the code found in v2.16.0.0 of the | |
29 | * ZyDAS vendor driver. Unlike other RF's, Ubec publish full technical specs | |
30 | * for this RF on their website, so we're able to understand more than | |
31 | * usual as to what is going on. Thumbs up for Ubec for doing that. */ | |
32 | ||
33 | /* The 3-wire serial interface provides access to 8 write-only registers. | |
34 | * The data format is a 4 bit register address followed by a 20 bit value. */ | |
35 | #define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff)) | |
36 | ||
37 | /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth | |
38 | * fractional divide ratio) and 3 (VCO config). | |
39 | * | |
40 | * We configure the RF to produce an interrupt when the PLL is locked onto | |
41 | * the configured frequency. During initialization, we run through a variety | |
42 | * of different VCO configurations on channel 1 until we detect a PLL lock. | |
43 | * When this happens, we remember which VCO configuration produced the lock | |
44 | * and use it later. Actually, we use the configuration *after* the one that | |
45 | * produced the lock, which seems odd, but it works. | |
46 | * | |
47 | * If we do not see a PLL lock on any standard VCO config, we fall back on an | |
48 | * autocal configuration, which has a fixed (as opposed to per-channel) VCO | |
49 | * config and different synth values from the standard set (divide ratio | |
50 | * is still shared with the standard set). */ | |
51 | ||
52 | /* The per-channel synth values for all standard VCO configurations. These get | |
53 | * written to register 1. */ | |
54 | static const u8 uw2453_std_synth[] = { | |
55 | RF_CHANNEL( 1) = 0x47, | |
56 | RF_CHANNEL( 2) = 0x47, | |
57 | RF_CHANNEL( 3) = 0x67, | |
58 | RF_CHANNEL( 4) = 0x67, | |
59 | RF_CHANNEL( 5) = 0x67, | |
60 | RF_CHANNEL( 6) = 0x67, | |
61 | RF_CHANNEL( 7) = 0x57, | |
62 | RF_CHANNEL( 8) = 0x57, | |
63 | RF_CHANNEL( 9) = 0x57, | |
64 | RF_CHANNEL(10) = 0x57, | |
65 | RF_CHANNEL(11) = 0x77, | |
66 | RF_CHANNEL(12) = 0x77, | |
67 | RF_CHANNEL(13) = 0x77, | |
68 | RF_CHANNEL(14) = 0x4f, | |
69 | }; | |
70 | ||
71 | /* This table stores the synthesizer fractional divide ratio for *all* VCO | |
72 | * configurations (both standard and autocal). These get written to register 2. | |
73 | */ | |
74 | static const u16 uw2453_synth_divide[] = { | |
75 | RF_CHANNEL( 1) = 0x999, | |
76 | RF_CHANNEL( 2) = 0x99b, | |
77 | RF_CHANNEL( 3) = 0x998, | |
78 | RF_CHANNEL( 4) = 0x99a, | |
79 | RF_CHANNEL( 5) = 0x999, | |
80 | RF_CHANNEL( 6) = 0x99b, | |
81 | RF_CHANNEL( 7) = 0x998, | |
82 | RF_CHANNEL( 8) = 0x99a, | |
83 | RF_CHANNEL( 9) = 0x999, | |
84 | RF_CHANNEL(10) = 0x99b, | |
85 | RF_CHANNEL(11) = 0x998, | |
86 | RF_CHANNEL(12) = 0x99a, | |
87 | RF_CHANNEL(13) = 0x999, | |
88 | RF_CHANNEL(14) = 0xccc, | |
89 | }; | |
90 | ||
91 | /* Here is the data for all the standard VCO configurations. We shrink our | |
92 | * table a little by observing that both channels in a consecutive pair share | |
93 | * the same value. We also observe that the high 4 bits ([0:3] in the specs) | |
94 | * are all 'Reserved' and are always set to 0x4 - we chop them off in the data | |
95 | * below. */ | |
96 | #define CHAN_TO_PAIRIDX(a) ((a - 1) / 2) | |
97 | #define RF_CHANPAIR(a,b) [CHAN_TO_PAIRIDX(a)] | |
98 | static const u16 uw2453_std_vco_cfg[][7] = { | |
99 | { /* table 1 */ | |
100 | RF_CHANPAIR( 1, 2) = 0x664d, | |
101 | RF_CHANPAIR( 3, 4) = 0x604d, | |
102 | RF_CHANPAIR( 5, 6) = 0x6675, | |
103 | RF_CHANPAIR( 7, 8) = 0x6475, | |
104 | RF_CHANPAIR( 9, 10) = 0x6655, | |
105 | RF_CHANPAIR(11, 12) = 0x6455, | |
106 | RF_CHANPAIR(13, 14) = 0x6665, | |
107 | }, | |
108 | { /* table 2 */ | |
109 | RF_CHANPAIR( 1, 2) = 0x666d, | |
110 | RF_CHANPAIR( 3, 4) = 0x606d, | |
111 | RF_CHANPAIR( 5, 6) = 0x664d, | |
112 | RF_CHANPAIR( 7, 8) = 0x644d, | |
113 | RF_CHANPAIR( 9, 10) = 0x6675, | |
114 | RF_CHANPAIR(11, 12) = 0x6475, | |
115 | RF_CHANPAIR(13, 14) = 0x6655, | |
116 | }, | |
117 | { /* table 3 */ | |
118 | RF_CHANPAIR( 1, 2) = 0x665d, | |
119 | RF_CHANPAIR( 3, 4) = 0x605d, | |
120 | RF_CHANPAIR( 5, 6) = 0x666d, | |
121 | RF_CHANPAIR( 7, 8) = 0x646d, | |
122 | RF_CHANPAIR( 9, 10) = 0x664d, | |
123 | RF_CHANPAIR(11, 12) = 0x644d, | |
124 | RF_CHANPAIR(13, 14) = 0x6675, | |
125 | }, | |
126 | { /* table 4 */ | |
127 | RF_CHANPAIR( 1, 2) = 0x667d, | |
128 | RF_CHANPAIR( 3, 4) = 0x607d, | |
129 | RF_CHANPAIR( 5, 6) = 0x665d, | |
130 | RF_CHANPAIR( 7, 8) = 0x645d, | |
131 | RF_CHANPAIR( 9, 10) = 0x666d, | |
132 | RF_CHANPAIR(11, 12) = 0x646d, | |
133 | RF_CHANPAIR(13, 14) = 0x664d, | |
134 | }, | |
135 | { /* table 5 */ | |
136 | RF_CHANPAIR( 1, 2) = 0x6643, | |
137 | RF_CHANPAIR( 3, 4) = 0x6043, | |
138 | RF_CHANPAIR( 5, 6) = 0x667d, | |
139 | RF_CHANPAIR( 7, 8) = 0x647d, | |
140 | RF_CHANPAIR( 9, 10) = 0x665d, | |
141 | RF_CHANPAIR(11, 12) = 0x645d, | |
142 | RF_CHANPAIR(13, 14) = 0x666d, | |
143 | }, | |
144 | { /* table 6 */ | |
145 | RF_CHANPAIR( 1, 2) = 0x6663, | |
146 | RF_CHANPAIR( 3, 4) = 0x6063, | |
147 | RF_CHANPAIR( 5, 6) = 0x6643, | |
148 | RF_CHANPAIR( 7, 8) = 0x6443, | |
149 | RF_CHANPAIR( 9, 10) = 0x667d, | |
150 | RF_CHANPAIR(11, 12) = 0x647d, | |
151 | RF_CHANPAIR(13, 14) = 0x665d, | |
152 | }, | |
153 | { /* table 7 */ | |
154 | RF_CHANPAIR( 1, 2) = 0x6653, | |
155 | RF_CHANPAIR( 3, 4) = 0x6053, | |
156 | RF_CHANPAIR( 5, 6) = 0x6663, | |
157 | RF_CHANPAIR( 7, 8) = 0x6463, | |
158 | RF_CHANPAIR( 9, 10) = 0x6643, | |
159 | RF_CHANPAIR(11, 12) = 0x6443, | |
160 | RF_CHANPAIR(13, 14) = 0x667d, | |
161 | }, | |
162 | { /* table 8 */ | |
163 | RF_CHANPAIR( 1, 2) = 0x6673, | |
164 | RF_CHANPAIR( 3, 4) = 0x6073, | |
165 | RF_CHANPAIR( 5, 6) = 0x6653, | |
166 | RF_CHANPAIR( 7, 8) = 0x6453, | |
167 | RF_CHANPAIR( 9, 10) = 0x6663, | |
168 | RF_CHANPAIR(11, 12) = 0x6463, | |
169 | RF_CHANPAIR(13, 14) = 0x6643, | |
170 | }, | |
171 | { /* table 9 */ | |
172 | RF_CHANPAIR( 1, 2) = 0x664b, | |
173 | RF_CHANPAIR( 3, 4) = 0x604b, | |
174 | RF_CHANPAIR( 5, 6) = 0x6673, | |
175 | RF_CHANPAIR( 7, 8) = 0x6473, | |
176 | RF_CHANPAIR( 9, 10) = 0x6653, | |
177 | RF_CHANPAIR(11, 12) = 0x6453, | |
178 | RF_CHANPAIR(13, 14) = 0x6663, | |
179 | }, | |
180 | { /* table 10 */ | |
181 | RF_CHANPAIR( 1, 2) = 0x666b, | |
182 | RF_CHANPAIR( 3, 4) = 0x606b, | |
183 | RF_CHANPAIR( 5, 6) = 0x664b, | |
184 | RF_CHANPAIR( 7, 8) = 0x644b, | |
185 | RF_CHANPAIR( 9, 10) = 0x6673, | |
186 | RF_CHANPAIR(11, 12) = 0x6473, | |
187 | RF_CHANPAIR(13, 14) = 0x6653, | |
188 | }, | |
189 | { /* table 11 */ | |
190 | RF_CHANPAIR( 1, 2) = 0x665b, | |
191 | RF_CHANPAIR( 3, 4) = 0x605b, | |
192 | RF_CHANPAIR( 5, 6) = 0x666b, | |
193 | RF_CHANPAIR( 7, 8) = 0x646b, | |
194 | RF_CHANPAIR( 9, 10) = 0x664b, | |
195 | RF_CHANPAIR(11, 12) = 0x644b, | |
196 | RF_CHANPAIR(13, 14) = 0x6673, | |
197 | }, | |
198 | ||
199 | }; | |
200 | ||
201 | /* The per-channel synth values for autocal. These get written to register 1. */ | |
202 | static const u16 uw2453_autocal_synth[] = { | |
203 | RF_CHANNEL( 1) = 0x6847, | |
204 | RF_CHANNEL( 2) = 0x6847, | |
205 | RF_CHANNEL( 3) = 0x6867, | |
206 | RF_CHANNEL( 4) = 0x6867, | |
207 | RF_CHANNEL( 5) = 0x6867, | |
208 | RF_CHANNEL( 6) = 0x6867, | |
209 | RF_CHANNEL( 7) = 0x6857, | |
210 | RF_CHANNEL( 8) = 0x6857, | |
211 | RF_CHANNEL( 9) = 0x6857, | |
212 | RF_CHANNEL(10) = 0x6857, | |
213 | RF_CHANNEL(11) = 0x6877, | |
214 | RF_CHANNEL(12) = 0x6877, | |
215 | RF_CHANNEL(13) = 0x6877, | |
216 | RF_CHANNEL(14) = 0x684f, | |
217 | }; | |
218 | ||
219 | /* The VCO configuration for autocal (all channels) */ | |
220 | static const u16 UW2453_AUTOCAL_VCO_CFG = 0x6662; | |
221 | ||
222 | /* TX gain settings. The array index corresponds to the TX power integration | |
223 | * values found in the EEPROM. The values get written to register 7. */ | |
224 | static u32 uw2453_txgain[] = { | |
225 | [0x00] = 0x0e313, | |
226 | [0x01] = 0x0fb13, | |
227 | [0x02] = 0x0e093, | |
228 | [0x03] = 0x0f893, | |
229 | [0x04] = 0x0ea93, | |
230 | [0x05] = 0x1f093, | |
231 | [0x06] = 0x1f493, | |
232 | [0x07] = 0x1f693, | |
233 | [0x08] = 0x1f393, | |
234 | [0x09] = 0x1f35b, | |
235 | [0x0a] = 0x1e6db, | |
236 | [0x0b] = 0x1ff3f, | |
237 | [0x0c] = 0x1ffff, | |
238 | [0x0d] = 0x361d7, | |
239 | [0x0e] = 0x37fbf, | |
240 | [0x0f] = 0x3ff8b, | |
241 | [0x10] = 0x3ff33, | |
242 | [0x11] = 0x3fb3f, | |
243 | [0x12] = 0x3ffff, | |
244 | }; | |
245 | ||
246 | /* RF-specific structure */ | |
247 | struct uw2453_priv { | |
248 | /* index into synth/VCO config tables where PLL lock was found | |
249 | * -1 means autocal */ | |
250 | int config; | |
251 | }; | |
252 | ||
253 | #define UW2453_PRIV(rf) ((struct uw2453_priv *) (rf)->priv) | |
254 | ||
255 | static int uw2453_synth_set_channel(struct zd_chip *chip, int channel, | |
256 | bool autocal) | |
257 | { | |
258 | int r; | |
259 | int idx = channel - 1; | |
260 | u32 val; | |
261 | ||
262 | if (autocal) | |
263 | val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]); | |
264 | else | |
265 | val = UW2453_REGWRITE(1, uw2453_std_synth[idx]); | |
266 | ||
267 | r = zd_rfwrite_locked(chip, val, RF_RV_BITS); | |
268 | if (r) | |
269 | return r; | |
270 | ||
271 | return zd_rfwrite_locked(chip, | |
272 | UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS); | |
273 | } | |
274 | ||
275 | static int uw2453_write_vco_cfg(struct zd_chip *chip, u16 value) | |
276 | { | |
277 | /* vendor driver always sets these upper bits even though the specs say | |
278 | * they are reserved */ | |
279 | u32 val = 0x40000 | value; | |
280 | return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS); | |
281 | } | |
282 | ||
283 | static int uw2453_init_mode(struct zd_chip *chip) | |
284 | { | |
285 | static const u32 rv[] = { | |
286 | UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */ | |
287 | UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */ | |
288 | UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */ | |
289 | UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */ | |
290 | }; | |
291 | ||
292 | return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); | |
293 | } | |
294 | ||
295 | static int uw2453_set_tx_gain_level(struct zd_chip *chip, int channel) | |
296 | { | |
297 | u8 int_value = chip->pwr_int_values[channel - 1]; | |
298 | ||
299 | if (int_value >= ARRAY_SIZE(uw2453_txgain)) { | |
300 | dev_dbg_f(zd_chip_dev(chip), "can't configure TX gain for " | |
301 | "int value %x on channel %d\n", int_value, channel); | |
302 | return 0; | |
303 | } | |
304 | ||
305 | return zd_rfwrite_locked(chip, | |
306 | UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS); | |
307 | } | |
308 | ||
309 | static int uw2453_init_hw(struct zd_rf *rf) | |
310 | { | |
311 | int i, r; | |
312 | int found_config = -1; | |
313 | u16 intr_status; | |
314 | struct zd_chip *chip = zd_rf_to_chip(rf); | |
315 | ||
316 | static const struct zd_ioreq16 ioreqs[] = { | |
fbd5d17b JK |
317 | { ZD_CR10, 0x89 }, { ZD_CR15, 0x20 }, |
318 | { ZD_CR17, 0x28 }, /* 6112 no change */ | |
319 | { ZD_CR23, 0x38 }, { ZD_CR24, 0x20 }, { ZD_CR26, 0x93 }, | |
320 | { ZD_CR27, 0x15 }, { ZD_CR28, 0x3e }, { ZD_CR29, 0x00 }, | |
321 | { ZD_CR33, 0x28 }, { ZD_CR34, 0x30 }, | |
322 | { ZD_CR35, 0x43 }, /* 6112 3e->43 */ | |
323 | { ZD_CR41, 0x24 }, { ZD_CR44, 0x32 }, | |
324 | { ZD_CR46, 0x92 }, /* 6112 96->92 */ | |
325 | { ZD_CR47, 0x1e }, | |
326 | { ZD_CR48, 0x04 }, /* 5602 Roger */ | |
327 | { ZD_CR49, 0xfa }, { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 }, | |
328 | { ZD_CR81, 0x30 }, { ZD_CR87, 0x0a }, { ZD_CR89, 0x04 }, | |
329 | { ZD_CR91, 0x00 }, { ZD_CR92, 0x0a }, { ZD_CR98, 0x8d }, | |
330 | { ZD_CR99, 0x28 }, { ZD_CR100, 0x02 }, | |
331 | { ZD_CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */ | |
332 | { ZD_CR102, 0x27 }, | |
333 | { ZD_CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f | |
334 | * 6221 1f->1c | |
335 | */ | |
336 | { ZD_CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */ | |
337 | { ZD_CR109, 0x13 }, | |
338 | { ZD_CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */ | |
339 | { ZD_CR111, 0x13 }, { ZD_CR112, 0x1f }, { ZD_CR113, 0x27 }, | |
340 | { ZD_CR114, 0x23 }, /* 6221 27->23 */ | |
341 | { ZD_CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */ | |
342 | { ZD_CR116, 0x24 }, /* 6220 1c->24 */ | |
343 | { ZD_CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */ | |
344 | { ZD_CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */ | |
345 | { ZD_CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */ | |
346 | { ZD_CR120, 0x4f }, | |
347 | { ZD_CR121, 0x1f }, /* 6220 4f->1f */ | |
348 | { ZD_CR122, 0xf0 }, { ZD_CR123, 0x57 }, { ZD_CR125, 0xad }, | |
349 | { ZD_CR126, 0x6c }, { ZD_CR127, 0x03 }, | |
350 | { ZD_CR128, 0x14 }, /* 6302 12->11 */ | |
351 | { ZD_CR129, 0x12 }, /* 6301 10->0f */ | |
352 | { ZD_CR130, 0x10 }, { ZD_CR137, 0x50 }, { ZD_CR138, 0xa8 }, | |
353 | { ZD_CR144, 0xac }, { ZD_CR146, 0x20 }, { ZD_CR252, 0xff }, | |
354 | { ZD_CR253, 0xff }, | |
4481d609 DD |
355 | }; |
356 | ||
357 | static const u32 rv[] = { | |
25985edc | 358 | UW2453_REGWRITE(4, 0x2b), /* configure receiver gain */ |
4481d609 DD |
359 | UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */ |
360 | UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */ | |
361 | UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */ | |
362 | ||
363 | /* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins, | |
364 | * RSSI circuit powered down, reduced RSSI range */ | |
365 | UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */ | |
366 | ||
367 | /* synthesizer configuration for channel 1 */ | |
368 | UW2453_REGWRITE(1, 0x47), | |
369 | UW2453_REGWRITE(2, 0x999), | |
370 | ||
371 | /* disable manual VCO band selection */ | |
372 | UW2453_REGWRITE(3, 0x7602), | |
373 | ||
374 | /* enable manual VCO band selection, configure current level */ | |
375 | UW2453_REGWRITE(3, 0x46063), | |
376 | }; | |
377 | ||
378 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
379 | if (r) | |
380 | return r; | |
381 | ||
382 | r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); | |
383 | if (r) | |
384 | return r; | |
385 | ||
386 | r = uw2453_init_mode(chip); | |
387 | if (r) | |
388 | return r; | |
389 | ||
390 | /* Try all standard VCO configuration settings on channel 1 */ | |
391 | for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) { | |
392 | /* Configure synthesizer for channel 1 */ | |
393 | r = uw2453_synth_set_channel(chip, 1, false); | |
394 | if (r) | |
395 | return r; | |
396 | ||
397 | /* Write VCO config */ | |
398 | r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]); | |
399 | if (r) | |
400 | return r; | |
401 | ||
402 | /* ack interrupt event */ | |
403 | r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG); | |
404 | if (r) | |
405 | return r; | |
406 | ||
407 | /* check interrupt status */ | |
408 | r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG); | |
409 | if (r) | |
410 | return r; | |
411 | ||
f59d9782 | 412 | if (!(intr_status & 0xf)) { |
4481d609 DD |
413 | dev_dbg_f(zd_chip_dev(chip), |
414 | "PLL locked on configuration %d\n", i); | |
415 | found_config = i; | |
416 | break; | |
417 | } | |
418 | } | |
419 | ||
420 | if (found_config == -1) { | |
421 | /* autocal */ | |
422 | dev_dbg_f(zd_chip_dev(chip), | |
423 | "PLL did not lock, using autocal\n"); | |
424 | ||
425 | r = uw2453_synth_set_channel(chip, 1, true); | |
426 | if (r) | |
427 | return r; | |
428 | ||
429 | r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG); | |
430 | if (r) | |
431 | return r; | |
432 | } | |
433 | ||
434 | /* To match the vendor driver behaviour, we use the configuration after | |
435 | * the one that produced a lock. */ | |
436 | UW2453_PRIV(rf)->config = found_config + 1; | |
437 | ||
fbd5d17b | 438 | return zd_iowrite16_locked(chip, 0x06, ZD_CR203); |
4481d609 DD |
439 | } |
440 | ||
441 | static int uw2453_set_channel(struct zd_rf *rf, u8 channel) | |
442 | { | |
443 | int r; | |
444 | u16 vco_cfg; | |
445 | int config = UW2453_PRIV(rf)->config; | |
446 | bool autocal = (config == -1); | |
447 | struct zd_chip *chip = zd_rf_to_chip(rf); | |
448 | ||
449 | static const struct zd_ioreq16 ioreqs[] = { | |
fbd5d17b JK |
450 | { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 }, { ZD_CR79, 0x58 }, |
451 | { ZD_CR12, 0xf0 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x58 }, | |
4481d609 DD |
452 | }; |
453 | ||
454 | r = uw2453_synth_set_channel(chip, channel, autocal); | |
455 | if (r) | |
456 | return r; | |
457 | ||
458 | if (autocal) | |
459 | vco_cfg = UW2453_AUTOCAL_VCO_CFG; | |
460 | else | |
461 | vco_cfg = uw2453_std_vco_cfg[config][CHAN_TO_PAIRIDX(channel)]; | |
462 | ||
463 | r = uw2453_write_vco_cfg(chip, vco_cfg); | |
464 | if (r) | |
465 | return r; | |
466 | ||
467 | r = uw2453_init_mode(chip); | |
468 | if (r) | |
469 | return r; | |
470 | ||
471 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
472 | if (r) | |
473 | return r; | |
474 | ||
475 | r = uw2453_set_tx_gain_level(chip, channel); | |
476 | if (r) | |
477 | return r; | |
478 | ||
fbd5d17b | 479 | return zd_iowrite16_locked(chip, 0x06, ZD_CR203); |
4481d609 DD |
480 | } |
481 | ||
482 | static int uw2453_switch_radio_on(struct zd_rf *rf) | |
483 | { | |
484 | int r; | |
485 | struct zd_chip *chip = zd_rf_to_chip(rf); | |
486 | struct zd_ioreq16 ioreqs[] = { | |
fbd5d17b | 487 | { ZD_CR11, 0x00 }, { ZD_CR251, 0x3f }, |
4481d609 DD |
488 | }; |
489 | ||
490 | /* enter RXTX mode */ | |
491 | r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS); | |
492 | if (r) | |
493 | return r; | |
494 | ||
74553aed | 495 | if (zd_chip_is_zd1211b(chip)) |
4481d609 DD |
496 | ioreqs[1].value = 0x7f; |
497 | ||
498 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
499 | } | |
500 | ||
501 | static int uw2453_switch_radio_off(struct zd_rf *rf) | |
502 | { | |
503 | int r; | |
504 | struct zd_chip *chip = zd_rf_to_chip(rf); | |
505 | static const struct zd_ioreq16 ioreqs[] = { | |
fbd5d17b | 506 | { ZD_CR11, 0x04 }, { ZD_CR251, 0x2f }, |
4481d609 DD |
507 | }; |
508 | ||
509 | /* enter IDLE mode */ | |
510 | /* FIXME: shouldn't we go to SLEEP? sent email to zydas */ | |
511 | r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS); | |
512 | if (r) | |
513 | return r; | |
514 | ||
515 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | |
516 | } | |
517 | ||
518 | static void uw2453_clear(struct zd_rf *rf) | |
519 | { | |
520 | kfree(rf->priv); | |
521 | } | |
522 | ||
523 | int zd_rf_init_uw2453(struct zd_rf *rf) | |
524 | { | |
525 | rf->init_hw = uw2453_init_hw; | |
526 | rf->set_channel = uw2453_set_channel; | |
527 | rf->switch_radio_on = uw2453_switch_radio_on; | |
528 | rf->switch_radio_off = uw2453_switch_radio_off; | |
529 | rf->patch_6m_band_edge = zd_rf_generic_patch_6m; | |
530 | rf->clear = uw2453_clear; | |
531 | /* we have our own TX integration code */ | |
532 | rf->update_channel_int = 0; | |
533 | ||
534 | rf->priv = kmalloc(sizeof(struct uw2453_priv), GFP_KERNEL); | |
535 | if (rf->priv == NULL) | |
536 | return -ENOMEM; | |
537 | ||
538 | return 0; | |
539 | } | |
540 |