Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
77bf25ea | 34 | #include <linux/mutex.h> |
b60503ba | 35 | #include <linux/pci.h> |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
2d55cd5f | 41 | #include <linux/timer.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
57 | #define NVME_NR_AEN_COMMANDS 1 | |
58 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 59 | |
58ffacb5 MW |
60 | static int use_threaded_interrupts; |
61 | module_param(use_threaded_interrupts, int, 0); | |
62 | ||
8ffaadf7 JD |
63 | static bool use_cmb_sqes = true; |
64 | module_param(use_cmb_sqes, bool, 0644); | |
65 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
66 | ||
9a6b9458 | 67 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 68 | |
1c63dc66 CH |
69 | struct nvme_dev; |
70 | struct nvme_queue; | |
b3fffdef | 71 | |
4cc06521 | 72 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 73 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 74 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 75 | |
1c63dc66 CH |
76 | /* |
77 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
78 | */ | |
79 | struct nvme_dev { | |
1c63dc66 CH |
80 | struct nvme_queue **queues; |
81 | struct blk_mq_tag_set tagset; | |
82 | struct blk_mq_tag_set admin_tagset; | |
83 | u32 __iomem *dbs; | |
84 | struct device *dev; | |
85 | struct dma_pool *prp_page_pool; | |
86 | struct dma_pool *prp_small_pool; | |
87 | unsigned queue_count; | |
88 | unsigned online_queues; | |
89 | unsigned max_qid; | |
90 | int q_depth; | |
91 | u32 db_stride; | |
1c63dc66 CH |
92 | struct msix_entry *entry; |
93 | void __iomem *bar; | |
1c63dc66 | 94 | struct work_struct reset_work; |
1c63dc66 | 95 | struct work_struct scan_work; |
5c8809e6 | 96 | struct work_struct remove_work; |
9396dec9 | 97 | struct work_struct async_work; |
2d55cd5f | 98 | struct timer_list watchdog_timer; |
77bf25ea | 99 | struct mutex shutdown_lock; |
1c63dc66 | 100 | bool subsystem; |
1c63dc66 CH |
101 | void __iomem *cmb; |
102 | dma_addr_t cmb_dma_addr; | |
103 | u64 cmb_size; | |
104 | u32 cmbsz; | |
fd634f41 | 105 | unsigned long flags; |
db3cbfff | 106 | |
fd634f41 | 107 | #define NVME_CTRL_RESETTING 0 |
646017a6 | 108 | #define NVME_CTRL_REMOVING 1 |
1c63dc66 CH |
109 | |
110 | struct nvme_ctrl ctrl; | |
db3cbfff | 111 | struct completion ioq_wait; |
4d115420 | 112 | }; |
1fa6aead | 113 | |
1c63dc66 CH |
114 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
115 | { | |
116 | return container_of(ctrl, struct nvme_dev, ctrl); | |
117 | } | |
118 | ||
b60503ba MW |
119 | /* |
120 | * An NVM Express queue. Each device has at least two (one for admin | |
121 | * commands and one for I/O commands). | |
122 | */ | |
123 | struct nvme_queue { | |
124 | struct device *q_dmadev; | |
091b6092 | 125 | struct nvme_dev *dev; |
3193f07b | 126 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
127 | spinlock_t q_lock; |
128 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 129 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 130 | volatile struct nvme_completion *cqes; |
42483228 | 131 | struct blk_mq_tags **tags; |
b60503ba MW |
132 | dma_addr_t sq_dma_addr; |
133 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
134 | u32 __iomem *q_db; |
135 | u16 q_depth; | |
6222d172 | 136 | s16 cq_vector; |
b60503ba MW |
137 | u16 sq_tail; |
138 | u16 cq_head; | |
c30341dc | 139 | u16 qid; |
e9539f47 MW |
140 | u8 cq_phase; |
141 | u8 cqe_seen; | |
b60503ba MW |
142 | }; |
143 | ||
71bd150c CH |
144 | /* |
145 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
146 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 147 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
148 | * allocated to store the PRP list. |
149 | */ | |
150 | struct nvme_iod { | |
f4800d6d CH |
151 | struct nvme_queue *nvmeq; |
152 | int aborted; | |
71bd150c | 153 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
154 | int nents; /* Used in scatterlist */ |
155 | int length; /* Of data, in bytes */ | |
156 | dma_addr_t first_dma; | |
bf684057 | 157 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
158 | struct scatterlist *sg; |
159 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
160 | }; |
161 | ||
162 | /* | |
163 | * Check we didin't inadvertently grow the command struct | |
164 | */ | |
165 | static inline void _nvme_check_size(void) | |
166 | { | |
167 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
168 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
169 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
170 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
171 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 172 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 173 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
174 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
175 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
176 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
177 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 178 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
179 | } |
180 | ||
ac3dd5bd JA |
181 | /* |
182 | * Max size of iod being embedded in the request payload | |
183 | */ | |
184 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 185 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
186 | |
187 | /* | |
188 | * Will slightly overestimate the number of pages needed. This is OK | |
189 | * as it only leads to a small amount of wasted memory for the lifetime of | |
190 | * the I/O. | |
191 | */ | |
192 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
193 | { | |
5fd4ce1b CH |
194 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
195 | dev->ctrl.page_size); | |
ac3dd5bd JA |
196 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
197 | } | |
198 | ||
f4800d6d CH |
199 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
200 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 201 | { |
f4800d6d CH |
202 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
203 | sizeof(struct scatterlist) * nseg; | |
204 | } | |
ac3dd5bd | 205 | |
f4800d6d CH |
206 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
207 | { | |
208 | return sizeof(struct nvme_iod) + | |
209 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
210 | } |
211 | ||
a4aea562 MB |
212 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
213 | unsigned int hctx_idx) | |
e85248e5 | 214 | { |
a4aea562 MB |
215 | struct nvme_dev *dev = data; |
216 | struct nvme_queue *nvmeq = dev->queues[0]; | |
217 | ||
42483228 KB |
218 | WARN_ON(hctx_idx != 0); |
219 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
220 | WARN_ON(nvmeq->tags); | |
221 | ||
a4aea562 | 222 | hctx->driver_data = nvmeq; |
42483228 | 223 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 224 | return 0; |
e85248e5 MW |
225 | } |
226 | ||
4af0e21c KB |
227 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
228 | { | |
229 | struct nvme_queue *nvmeq = hctx->driver_data; | |
230 | ||
231 | nvmeq->tags = NULL; | |
232 | } | |
233 | ||
a4aea562 MB |
234 | static int nvme_admin_init_request(void *data, struct request *req, |
235 | unsigned int hctx_idx, unsigned int rq_idx, | |
236 | unsigned int numa_node) | |
22404274 | 237 | { |
a4aea562 | 238 | struct nvme_dev *dev = data; |
f4800d6d | 239 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
240 | struct nvme_queue *nvmeq = dev->queues[0]; |
241 | ||
242 | BUG_ON(!nvmeq); | |
f4800d6d | 243 | iod->nvmeq = nvmeq; |
a4aea562 | 244 | return 0; |
22404274 KB |
245 | } |
246 | ||
a4aea562 MB |
247 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
248 | unsigned int hctx_idx) | |
b60503ba | 249 | { |
a4aea562 | 250 | struct nvme_dev *dev = data; |
42483228 | 251 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 252 | |
42483228 KB |
253 | if (!nvmeq->tags) |
254 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 255 | |
42483228 | 256 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
257 | hctx->driver_data = nvmeq; |
258 | return 0; | |
b60503ba MW |
259 | } |
260 | ||
a4aea562 MB |
261 | static int nvme_init_request(void *data, struct request *req, |
262 | unsigned int hctx_idx, unsigned int rq_idx, | |
263 | unsigned int numa_node) | |
b60503ba | 264 | { |
a4aea562 | 265 | struct nvme_dev *dev = data; |
f4800d6d | 266 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
267 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
268 | ||
269 | BUG_ON(!nvmeq); | |
f4800d6d | 270 | iod->nvmeq = nvmeq; |
a4aea562 MB |
271 | return 0; |
272 | } | |
273 | ||
646017a6 KB |
274 | static void nvme_queue_scan(struct nvme_dev *dev) |
275 | { | |
276 | /* | |
277 | * Do not queue new scan work when a controller is reset during | |
278 | * removal. | |
279 | */ | |
280 | if (test_bit(NVME_CTRL_REMOVING, &dev->flags)) | |
281 | return; | |
282 | queue_work(nvme_workq, &dev->scan_work); | |
283 | } | |
284 | ||
adf68f21 CH |
285 | static void nvme_complete_async_event(struct nvme_dev *dev, |
286 | struct nvme_completion *cqe) | |
a4aea562 | 287 | { |
adf68f21 CH |
288 | u16 status = le16_to_cpu(cqe->status) >> 1; |
289 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 | 290 | |
9396dec9 | 291 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) { |
adf68f21 | 292 | ++dev->ctrl.event_limit; |
9396dec9 CH |
293 | queue_work(nvme_workq, &dev->async_work); |
294 | } | |
295 | ||
a5768aa8 KB |
296 | if (status != NVME_SC_SUCCESS) |
297 | return; | |
298 | ||
299 | switch (result & 0xff07) { | |
300 | case NVME_AER_NOTICE_NS_CHANGED: | |
1b3c47c1 | 301 | dev_info(dev->ctrl.device, "rescanning\n"); |
646017a6 | 302 | nvme_queue_scan(dev); |
a5768aa8 | 303 | default: |
1b3c47c1 | 304 | dev_warn(dev->ctrl.device, "async event result %08x\n", result); |
a4aea562 | 305 | } |
b60503ba MW |
306 | } |
307 | ||
308 | /** | |
adf68f21 | 309 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
310 | * @nvmeq: The queue to use |
311 | * @cmd: The command to send | |
312 | * | |
313 | * Safe to use from interrupt context | |
314 | */ | |
e3f879bf SB |
315 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
316 | struct nvme_command *cmd) | |
b60503ba | 317 | { |
a4aea562 MB |
318 | u16 tail = nvmeq->sq_tail; |
319 | ||
8ffaadf7 JD |
320 | if (nvmeq->sq_cmds_io) |
321 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
322 | else | |
323 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
324 | ||
b60503ba MW |
325 | if (++tail == nvmeq->q_depth) |
326 | tail = 0; | |
7547881d | 327 | writel(tail, nvmeq->q_db); |
b60503ba | 328 | nvmeq->sq_tail = tail; |
b60503ba MW |
329 | } |
330 | ||
f4800d6d | 331 | static __le64 **iod_list(struct request *req) |
b60503ba | 332 | { |
f4800d6d CH |
333 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
334 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
335 | } |
336 | ||
f4800d6d | 337 | static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 338 | { |
f4800d6d CH |
339 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
340 | int nseg = rq->nr_phys_segments; | |
341 | unsigned size; | |
ac3dd5bd | 342 | |
f4800d6d CH |
343 | if (rq->cmd_flags & REQ_DISCARD) |
344 | size = sizeof(struct nvme_dsm_range); | |
345 | else | |
346 | size = blk_rq_bytes(rq); | |
ac3dd5bd | 347 | |
f4800d6d CH |
348 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
349 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
350 | if (!iod->sg) | |
351 | return BLK_MQ_RQ_QUEUE_BUSY; | |
352 | } else { | |
353 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
354 | } |
355 | ||
f4800d6d CH |
356 | iod->aborted = 0; |
357 | iod->npages = -1; | |
358 | iod->nents = 0; | |
359 | iod->length = size; | |
360 | return 0; | |
ac3dd5bd JA |
361 | } |
362 | ||
f4800d6d | 363 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 364 | { |
f4800d6d | 365 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 366 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 367 | int i; |
f4800d6d | 368 | __le64 **list = iod_list(req); |
eca18b23 MW |
369 | dma_addr_t prp_dma = iod->first_dma; |
370 | ||
371 | if (iod->npages == 0) | |
372 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
373 | for (i = 0; i < iod->npages; i++) { | |
374 | __le64 *prp_list = list[i]; | |
375 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
376 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
377 | prp_dma = next_prp_dma; | |
378 | } | |
ac3dd5bd | 379 | |
f4800d6d CH |
380 | if (iod->sg != iod->inline_sg) |
381 | kfree(iod->sg); | |
b4ff9c8d KB |
382 | } |
383 | ||
52b68d7e | 384 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
385 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
386 | { | |
387 | if (be32_to_cpu(pi->ref_tag) == v) | |
388 | pi->ref_tag = cpu_to_be32(p); | |
389 | } | |
390 | ||
391 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
392 | { | |
393 | if (be32_to_cpu(pi->ref_tag) == p) | |
394 | pi->ref_tag = cpu_to_be32(v); | |
395 | } | |
396 | ||
397 | /** | |
398 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
399 | * | |
400 | * The virtual start sector is the one that was originally submitted by the | |
401 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
402 | * start sector may be different. Remap protection information to match the | |
403 | * physical LBA on writes, and back to the original seed on reads. | |
404 | * | |
405 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
406 | */ | |
407 | static void nvme_dif_remap(struct request *req, | |
408 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
409 | { | |
410 | struct nvme_ns *ns = req->rq_disk->private_data; | |
411 | struct bio_integrity_payload *bip; | |
412 | struct t10_pi_tuple *pi; | |
413 | void *p, *pmap; | |
414 | u32 i, nlb, ts, phys, virt; | |
415 | ||
416 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
417 | return; | |
418 | ||
419 | bip = bio_integrity(req->bio); | |
420 | if (!bip) | |
421 | return; | |
422 | ||
423 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
424 | |
425 | p = pmap; | |
426 | virt = bip_get_seed(bip); | |
427 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
428 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 429 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
430 | |
431 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
432 | pi = (struct t10_pi_tuple *)p; | |
433 | dif_swap(phys, virt, pi); | |
434 | p += ts; | |
435 | } | |
436 | kunmap_atomic(pmap); | |
437 | } | |
52b68d7e KB |
438 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
439 | static void nvme_dif_remap(struct request *req, | |
440 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
441 | { | |
442 | } | |
443 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
444 | { | |
445 | } | |
446 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
447 | { | |
448 | } | |
52b68d7e KB |
449 | #endif |
450 | ||
f4800d6d | 451 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 452 | int total_len) |
ff22b54f | 453 | { |
f4800d6d | 454 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 455 | struct dma_pool *pool; |
eca18b23 MW |
456 | int length = total_len; |
457 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
458 | int dma_len = sg_dma_len(sg); |
459 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 460 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 461 | int offset = dma_addr & (page_size - 1); |
e025344c | 462 | __le64 *prp_list; |
f4800d6d | 463 | __le64 **list = iod_list(req); |
e025344c | 464 | dma_addr_t prp_dma; |
eca18b23 | 465 | int nprps, i; |
ff22b54f | 466 | |
1d090624 | 467 | length -= (page_size - offset); |
ff22b54f | 468 | if (length <= 0) |
69d2b571 | 469 | return true; |
ff22b54f | 470 | |
1d090624 | 471 | dma_len -= (page_size - offset); |
ff22b54f | 472 | if (dma_len) { |
1d090624 | 473 | dma_addr += (page_size - offset); |
ff22b54f MW |
474 | } else { |
475 | sg = sg_next(sg); | |
476 | dma_addr = sg_dma_address(sg); | |
477 | dma_len = sg_dma_len(sg); | |
478 | } | |
479 | ||
1d090624 | 480 | if (length <= page_size) { |
edd10d33 | 481 | iod->first_dma = dma_addr; |
69d2b571 | 482 | return true; |
e025344c SMM |
483 | } |
484 | ||
1d090624 | 485 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
486 | if (nprps <= (256 / 8)) { |
487 | pool = dev->prp_small_pool; | |
eca18b23 | 488 | iod->npages = 0; |
99802a7a MW |
489 | } else { |
490 | pool = dev->prp_page_pool; | |
eca18b23 | 491 | iod->npages = 1; |
99802a7a MW |
492 | } |
493 | ||
69d2b571 | 494 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 495 | if (!prp_list) { |
edd10d33 | 496 | iod->first_dma = dma_addr; |
eca18b23 | 497 | iod->npages = -1; |
69d2b571 | 498 | return false; |
b77954cb | 499 | } |
eca18b23 MW |
500 | list[0] = prp_list; |
501 | iod->first_dma = prp_dma; | |
e025344c SMM |
502 | i = 0; |
503 | for (;;) { | |
1d090624 | 504 | if (i == page_size >> 3) { |
e025344c | 505 | __le64 *old_prp_list = prp_list; |
69d2b571 | 506 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 507 | if (!prp_list) |
69d2b571 | 508 | return false; |
eca18b23 | 509 | list[iod->npages++] = prp_list; |
7523d834 MW |
510 | prp_list[0] = old_prp_list[i - 1]; |
511 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
512 | i = 1; | |
e025344c SMM |
513 | } |
514 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
515 | dma_len -= page_size; |
516 | dma_addr += page_size; | |
517 | length -= page_size; | |
e025344c SMM |
518 | if (length <= 0) |
519 | break; | |
520 | if (dma_len > 0) | |
521 | continue; | |
522 | BUG_ON(dma_len < 0); | |
523 | sg = sg_next(sg); | |
524 | dma_addr = sg_dma_address(sg); | |
525 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
526 | } |
527 | ||
69d2b571 | 528 | return true; |
ff22b54f MW |
529 | } |
530 | ||
f4800d6d | 531 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
ba1ca37e | 532 | struct nvme_command *cmnd) |
d29ec824 | 533 | { |
f4800d6d | 534 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
535 | struct request_queue *q = req->q; |
536 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
537 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
538 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 539 | |
ba1ca37e CH |
540 | sg_init_table(iod->sg, req->nr_phys_segments); |
541 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
542 | if (!iod->nents) | |
543 | goto out; | |
d29ec824 | 544 | |
ba1ca37e CH |
545 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
546 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
547 | goto out; | |
d29ec824 | 548 | |
f4800d6d | 549 | if (!nvme_setup_prps(dev, req, blk_rq_bytes(req))) |
ba1ca37e | 550 | goto out_unmap; |
0e5e4f0e | 551 | |
ba1ca37e CH |
552 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
553 | if (blk_integrity_rq(req)) { | |
554 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
555 | goto out_unmap; | |
0e5e4f0e | 556 | |
bf684057 CH |
557 | sg_init_table(&iod->meta_sg, 1); |
558 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 559 | goto out_unmap; |
0e5e4f0e | 560 | |
ba1ca37e CH |
561 | if (rq_data_dir(req)) |
562 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 563 | |
bf684057 | 564 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 565 | goto out_unmap; |
d29ec824 | 566 | } |
00df5cb4 | 567 | |
ba1ca37e CH |
568 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
569 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
570 | if (blk_integrity_rq(req)) | |
bf684057 | 571 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 572 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 573 | |
ba1ca37e CH |
574 | out_unmap: |
575 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
576 | out: | |
577 | return ret; | |
00df5cb4 MW |
578 | } |
579 | ||
f4800d6d | 580 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 581 | { |
f4800d6d | 582 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
583 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
584 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
585 | ||
586 | if (iod->nents) { | |
587 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
588 | if (blk_integrity_rq(req)) { | |
589 | if (!rq_data_dir(req)) | |
590 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 591 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 592 | } |
e19b127f | 593 | } |
e1e5e564 | 594 | |
f4800d6d | 595 | nvme_free_iod(dev, req); |
d4f6c3ab | 596 | } |
b60503ba | 597 | |
a4aea562 MB |
598 | /* |
599 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
600 | * worth having a special pool for these or additional cases to handle freeing | |
601 | * the iod. | |
602 | */ | |
ba1ca37e | 603 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
f4800d6d | 604 | struct request *req, struct nvme_command *cmnd) |
0e5e4f0e | 605 | { |
f4800d6d | 606 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e | 607 | struct nvme_dsm_range *range; |
b60503ba | 608 | |
ba1ca37e CH |
609 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, |
610 | &iod->first_dma); | |
611 | if (!range) | |
612 | return BLK_MQ_RQ_QUEUE_BUSY; | |
f4800d6d | 613 | iod_list(req)[0] = (__le64 *)range; |
ba1ca37e | 614 | iod->npages = 0; |
0e5e4f0e | 615 | |
0e5e4f0e | 616 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
617 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
618 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 619 | |
ba1ca37e CH |
620 | memset(cmnd, 0, sizeof(*cmnd)); |
621 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
622 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
623 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
624 | cmnd->dsm.nr = 0; | |
625 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
626 | return BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 KB |
627 | } |
628 | ||
d29ec824 CH |
629 | /* |
630 | * NOTE: ns is NULL when called on the admin queue. | |
631 | */ | |
a4aea562 MB |
632 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
633 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 634 | { |
a4aea562 MB |
635 | struct nvme_ns *ns = hctx->queue->queuedata; |
636 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 637 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 638 | struct request *req = bd->rq; |
ba1ca37e CH |
639 | struct nvme_command cmnd; |
640 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 641 | |
e1e5e564 KB |
642 | /* |
643 | * If formated with metadata, require the block layer provide a buffer | |
644 | * unless this namespace is formated such that the metadata can be | |
645 | * stripped/generated by the controller with PRACT=1. | |
646 | */ | |
d29ec824 | 647 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
648 | if (!(ns->pi_type && ns->ms == 8) && |
649 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 650 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
651 | return BLK_MQ_RQ_QUEUE_OK; |
652 | } | |
653 | } | |
654 | ||
f4800d6d CH |
655 | ret = nvme_init_iod(req, dev); |
656 | if (ret) | |
657 | return ret; | |
a4aea562 | 658 | |
a4aea562 | 659 | if (req->cmd_flags & REQ_DISCARD) { |
f4800d6d | 660 | ret = nvme_setup_discard(nvmeq, ns, req, &cmnd); |
ba1ca37e CH |
661 | } else { |
662 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
663 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
664 | else if (req->cmd_flags & REQ_FLUSH) | |
665 | nvme_setup_flush(ns, &cmnd); | |
666 | else | |
667 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 668 | |
ba1ca37e | 669 | if (req->nr_phys_segments) |
f4800d6d | 670 | ret = nvme_map_data(dev, req, &cmnd); |
edd10d33 | 671 | } |
a4aea562 | 672 | |
ba1ca37e CH |
673 | if (ret) |
674 | goto out; | |
a4aea562 | 675 | |
ba1ca37e | 676 | cmnd.common.command_id = req->tag; |
aae239e1 | 677 | blk_mq_start_request(req); |
a4aea562 | 678 | |
ba1ca37e | 679 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 680 | if (unlikely(nvmeq->cq_vector < 0)) { |
69d9a99c KB |
681 | if (ns && !test_bit(NVME_NS_DEAD, &ns->flags)) |
682 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
683 | else | |
684 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
ae1fba20 KB |
685 | spin_unlock_irq(&nvmeq->q_lock); |
686 | goto out; | |
687 | } | |
ba1ca37e | 688 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
689 | nvme_process_cq(nvmeq); |
690 | spin_unlock_irq(&nvmeq->q_lock); | |
691 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 692 | out: |
f4800d6d | 693 | nvme_free_iod(dev, req); |
ba1ca37e | 694 | return ret; |
b60503ba | 695 | } |
e1e5e564 | 696 | |
eee417b0 CH |
697 | static void nvme_complete_rq(struct request *req) |
698 | { | |
f4800d6d CH |
699 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
700 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 701 | int error = 0; |
e1e5e564 | 702 | |
f4800d6d | 703 | nvme_unmap_data(dev, req); |
e1e5e564 | 704 | |
eee417b0 CH |
705 | if (unlikely(req->errors)) { |
706 | if (nvme_req_needs_retry(req, req->errors)) { | |
707 | nvme_requeue_req(req); | |
708 | return; | |
e1e5e564 | 709 | } |
1974b1ae | 710 | |
eee417b0 CH |
711 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
712 | error = req->errors; | |
713 | else | |
714 | error = nvme_error_status(req->errors); | |
715 | } | |
a4aea562 | 716 | |
f4800d6d | 717 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 718 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
719 | "completing aborted command with status: %04x\n", |
720 | req->errors); | |
721 | } | |
a4aea562 | 722 | |
eee417b0 | 723 | blk_mq_end_request(req, error); |
b60503ba MW |
724 | } |
725 | ||
d783e0bd MR |
726 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
727 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
728 | u16 phase) | |
729 | { | |
730 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
731 | } | |
732 | ||
a0fa9647 | 733 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 734 | { |
82123460 | 735 | u16 head, phase; |
b60503ba | 736 | |
b60503ba | 737 | head = nvmeq->cq_head; |
82123460 | 738 | phase = nvmeq->cq_phase; |
b60503ba | 739 | |
d783e0bd | 740 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 741 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 742 | struct request *req; |
adf68f21 | 743 | |
b60503ba MW |
744 | if (++head == nvmeq->q_depth) { |
745 | head = 0; | |
82123460 | 746 | phase = !phase; |
b60503ba | 747 | } |
adf68f21 | 748 | |
a0fa9647 JA |
749 | if (tag && *tag == cqe.command_id) |
750 | *tag = -1; | |
adf68f21 | 751 | |
aae239e1 | 752 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 753 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
754 | "invalid id %d completed on queue %d\n", |
755 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
756 | continue; | |
757 | } | |
758 | ||
adf68f21 CH |
759 | /* |
760 | * AEN requests are special as they don't time out and can | |
761 | * survive any kind of queue freeze and often don't respond to | |
762 | * aborts. We don't even bother to allocate a struct request | |
763 | * for them but rather special case them here. | |
764 | */ | |
765 | if (unlikely(nvmeq->qid == 0 && | |
766 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
767 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
768 | continue; | |
769 | } | |
770 | ||
eee417b0 | 771 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
1cb3cce5 CH |
772 | if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special) |
773 | memcpy(req->special, &cqe, sizeof(cqe)); | |
d783e0bd | 774 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
eee417b0 | 775 | |
b60503ba MW |
776 | } |
777 | ||
778 | /* If the controller ignores the cq head doorbell and continuously | |
779 | * writes to the queue, it is theoretically possible to wrap around | |
780 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
781 | * requires that 0.1% of your interrupts are handled, so this isn't | |
782 | * a big problem. | |
783 | */ | |
82123460 | 784 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 785 | return; |
b60503ba | 786 | |
604e8c8d KB |
787 | if (likely(nvmeq->cq_vector >= 0)) |
788 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 789 | nvmeq->cq_head = head; |
82123460 | 790 | nvmeq->cq_phase = phase; |
b60503ba | 791 | |
e9539f47 | 792 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
793 | } |
794 | ||
795 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
796 | { | |
797 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
798 | } |
799 | ||
800 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
801 | { |
802 | irqreturn_t result; | |
803 | struct nvme_queue *nvmeq = data; | |
804 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
805 | nvme_process_cq(nvmeq); |
806 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
807 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
808 | spin_unlock(&nvmeq->q_lock); |
809 | return result; | |
810 | } | |
811 | ||
812 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
813 | { | |
814 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
815 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
816 | return IRQ_WAKE_THREAD; | |
817 | return IRQ_NONE; | |
58ffacb5 MW |
818 | } |
819 | ||
a0fa9647 JA |
820 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
821 | { | |
822 | struct nvme_queue *nvmeq = hctx->driver_data; | |
823 | ||
d783e0bd | 824 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
825 | spin_lock_irq(&nvmeq->q_lock); |
826 | __nvme_process_cq(nvmeq, &tag); | |
827 | spin_unlock_irq(&nvmeq->q_lock); | |
828 | ||
829 | if (tag == -1) | |
830 | return 1; | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
9396dec9 | 836 | static void nvme_async_event_work(struct work_struct *work) |
b60503ba | 837 | { |
9396dec9 CH |
838 | struct nvme_dev *dev = container_of(work, struct nvme_dev, async_work); |
839 | struct nvme_queue *nvmeq = dev->queues[0]; | |
a4aea562 | 840 | struct nvme_command c; |
b60503ba | 841 | |
a4aea562 MB |
842 | memset(&c, 0, sizeof(c)); |
843 | c.common.opcode = nvme_admin_async_event; | |
3c0cf138 | 844 | |
9396dec9 CH |
845 | spin_lock_irq(&nvmeq->q_lock); |
846 | while (dev->ctrl.event_limit > 0) { | |
847 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + | |
848 | --dev->ctrl.event_limit; | |
849 | __nvme_submit_cmd(nvmeq, &c); | |
850 | } | |
851 | spin_unlock_irq(&nvmeq->q_lock); | |
f705f837 CH |
852 | } |
853 | ||
b60503ba | 854 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 855 | { |
b60503ba MW |
856 | struct nvme_command c; |
857 | ||
858 | memset(&c, 0, sizeof(c)); | |
859 | c.delete_queue.opcode = opcode; | |
860 | c.delete_queue.qid = cpu_to_le16(id); | |
861 | ||
1c63dc66 | 862 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
863 | } |
864 | ||
b60503ba MW |
865 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
866 | struct nvme_queue *nvmeq) | |
867 | { | |
b60503ba MW |
868 | struct nvme_command c; |
869 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
870 | ||
d29ec824 CH |
871 | /* |
872 | * Note: we (ab)use the fact the the prp fields survive if no data | |
873 | * is attached to the request. | |
874 | */ | |
b60503ba MW |
875 | memset(&c, 0, sizeof(c)); |
876 | c.create_cq.opcode = nvme_admin_create_cq; | |
877 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
878 | c.create_cq.cqid = cpu_to_le16(qid); | |
879 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
880 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
881 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
882 | ||
1c63dc66 | 883 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
884 | } |
885 | ||
886 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
887 | struct nvme_queue *nvmeq) | |
888 | { | |
b60503ba MW |
889 | struct nvme_command c; |
890 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
891 | ||
d29ec824 CH |
892 | /* |
893 | * Note: we (ab)use the fact the the prp fields survive if no data | |
894 | * is attached to the request. | |
895 | */ | |
b60503ba MW |
896 | memset(&c, 0, sizeof(c)); |
897 | c.create_sq.opcode = nvme_admin_create_sq; | |
898 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
899 | c.create_sq.sqid = cpu_to_le16(qid); | |
900 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
901 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
902 | c.create_sq.cqid = cpu_to_le16(qid); | |
903 | ||
1c63dc66 | 904 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
905 | } |
906 | ||
907 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
908 | { | |
909 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
910 | } | |
911 | ||
912 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
913 | { | |
914 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
915 | } | |
916 | ||
e7a2a87d | 917 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 918 | { |
f4800d6d CH |
919 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
920 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 921 | u16 status = req->errors; |
e44ac588 | 922 | |
1cb3cce5 | 923 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 924 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 925 | blk_mq_free_request(req); |
bc5fc7e4 MW |
926 | } |
927 | ||
31c7c7d2 | 928 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 929 | { |
f4800d6d CH |
930 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
931 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 932 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 933 | struct request *abort_req; |
a4aea562 | 934 | struct nvme_command cmd; |
c30341dc | 935 | |
31c7c7d2 | 936 | /* |
fd634f41 CH |
937 | * Shutdown immediately if controller times out while starting. The |
938 | * reset work will see the pci device disabled when it gets the forced | |
939 | * cancellation error. All outstanding requests are completed on | |
940 | * shutdown, so we return BLK_EH_HANDLED. | |
941 | */ | |
942 | if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) { | |
1b3c47c1 | 943 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
944 | "I/O %d QID %d timeout, disable controller\n", |
945 | req->tag, nvmeq->qid); | |
a5cdb68c | 946 | nvme_dev_disable(dev, false); |
fd634f41 CH |
947 | req->errors = NVME_SC_CANCELLED; |
948 | return BLK_EH_HANDLED; | |
c30341dc KB |
949 | } |
950 | ||
fd634f41 CH |
951 | /* |
952 | * Shutdown the controller immediately and schedule a reset if the | |
953 | * command was already aborted once before and still hasn't been | |
954 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 955 | */ |
f4800d6d | 956 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 957 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
958 | "I/O %d QID %d timeout, reset controller\n", |
959 | req->tag, nvmeq->qid); | |
a5cdb68c | 960 | nvme_dev_disable(dev, false); |
e1569a16 | 961 | queue_work(nvme_workq, &dev->reset_work); |
c30341dc | 962 | |
e1569a16 KB |
963 | /* |
964 | * Mark the request as handled, since the inline shutdown | |
965 | * forces all outstanding requests to complete. | |
966 | */ | |
967 | req->errors = NVME_SC_CANCELLED; | |
968 | return BLK_EH_HANDLED; | |
c30341dc | 969 | } |
c30341dc | 970 | |
f4800d6d | 971 | iod->aborted = 1; |
c30341dc | 972 | |
e7a2a87d | 973 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 974 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 975 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 976 | } |
a4aea562 | 977 | |
c30341dc KB |
978 | memset(&cmd, 0, sizeof(cmd)); |
979 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 980 | cmd.abort.cid = req->tag; |
c30341dc | 981 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 982 | |
1b3c47c1 SG |
983 | dev_warn(nvmeq->dev->ctrl.device, |
984 | "I/O %d QID %d timeout, aborting\n", | |
985 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
986 | |
987 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
988 | BLK_MQ_REQ_NOWAIT); | |
989 | if (IS_ERR(abort_req)) { | |
990 | atomic_inc(&dev->ctrl.abort_limit); | |
991 | return BLK_EH_RESET_TIMER; | |
992 | } | |
993 | ||
994 | abort_req->timeout = ADMIN_TIMEOUT; | |
995 | abort_req->end_io_data = NULL; | |
996 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 997 | |
31c7c7d2 CH |
998 | /* |
999 | * The aborted req will be completed on receiving the abort req. | |
1000 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1001 | * as the device then is in a faulty state. | |
1002 | */ | |
1003 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1004 | } |
1005 | ||
42483228 | 1006 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1007 | { |
a4aea562 | 1008 | struct nvme_queue *nvmeq = data; |
aae239e1 | 1009 | int status; |
cef6a948 KB |
1010 | |
1011 | if (!blk_mq_request_started(req)) | |
1012 | return; | |
a09115b2 | 1013 | |
237045fc | 1014 | dev_dbg_ratelimited(nvmeq->dev->ctrl.device, |
aae239e1 | 1015 | "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); |
a4aea562 | 1016 | |
1d49c38c | 1017 | status = NVME_SC_ABORT_REQ; |
cef6a948 | 1018 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
1019 | status |= NVME_SC_DNR; |
1020 | blk_mq_complete_request(req, status); | |
a4aea562 | 1021 | } |
22404274 | 1022 | |
a4aea562 MB |
1023 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1024 | { | |
9e866774 MW |
1025 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1026 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1027 | if (nvmeq->sq_cmds) |
1028 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1029 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1030 | kfree(nvmeq); | |
1031 | } | |
1032 | ||
a1a5ef99 | 1033 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1034 | { |
1035 | int i; | |
1036 | ||
a1a5ef99 | 1037 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1038 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1039 | dev->queue_count--; |
a4aea562 | 1040 | dev->queues[i] = NULL; |
f435c282 | 1041 | nvme_free_queue(nvmeq); |
121c7ad4 | 1042 | } |
22404274 KB |
1043 | } |
1044 | ||
4d115420 KB |
1045 | /** |
1046 | * nvme_suspend_queue - put queue into suspended state | |
1047 | * @nvmeq - queue to suspend | |
4d115420 KB |
1048 | */ |
1049 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1050 | { |
2b25d981 | 1051 | int vector; |
b60503ba | 1052 | |
a09115b2 | 1053 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1054 | if (nvmeq->cq_vector == -1) { |
1055 | spin_unlock_irq(&nvmeq->q_lock); | |
1056 | return 1; | |
1057 | } | |
1058 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1059 | nvmeq->dev->online_queues--; |
2b25d981 | 1060 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1061 | spin_unlock_irq(&nvmeq->q_lock); |
1062 | ||
1c63dc66 | 1063 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 1064 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1065 | |
aba2080f MW |
1066 | irq_set_affinity_hint(vector, NULL); |
1067 | free_irq(vector, nvmeq); | |
b60503ba | 1068 | |
4d115420 KB |
1069 | return 0; |
1070 | } | |
b60503ba | 1071 | |
4d115420 KB |
1072 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1073 | { | |
22404274 | 1074 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1075 | if (nvmeq->tags && *nvmeq->tags) |
1076 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1077 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1078 | } |
1079 | ||
a5cdb68c | 1080 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1081 | { |
a5cdb68c | 1082 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1083 | |
1084 | if (!nvmeq) | |
1085 | return; | |
1086 | if (nvme_suspend_queue(nvmeq)) | |
1087 | return; | |
1088 | ||
a5cdb68c KB |
1089 | if (shutdown) |
1090 | nvme_shutdown_ctrl(&dev->ctrl); | |
1091 | else | |
1092 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1093 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1094 | |
1095 | spin_lock_irq(&nvmeq->q_lock); | |
1096 | nvme_process_cq(nvmeq); | |
1097 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1098 | } |
1099 | ||
8ffaadf7 JD |
1100 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1101 | int entry_size) | |
1102 | { | |
1103 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1104 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1105 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1106 | |
1107 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1108 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1109 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1110 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1111 | |
1112 | /* | |
1113 | * Ensure the reduced q_depth is above some threshold where it | |
1114 | * would be better to map queues in system memory with the | |
1115 | * original depth | |
1116 | */ | |
1117 | if (q_depth < 64) | |
1118 | return -ENOMEM; | |
1119 | } | |
1120 | ||
1121 | return q_depth; | |
1122 | } | |
1123 | ||
1124 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1125 | int qid, int depth) | |
1126 | { | |
1127 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1128 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1129 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1130 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1131 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1132 | } else { | |
1133 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1134 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1135 | if (!nvmeq->sq_cmds) | |
1136 | return -ENOMEM; | |
1137 | } | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
b60503ba | 1142 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1143 | int depth) |
b60503ba | 1144 | { |
a4aea562 | 1145 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1146 | if (!nvmeq) |
1147 | return NULL; | |
1148 | ||
e75ec752 | 1149 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1150 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1151 | if (!nvmeq->cqes) |
1152 | goto free_nvmeq; | |
b60503ba | 1153 | |
8ffaadf7 | 1154 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1155 | goto free_cqdma; |
1156 | ||
e75ec752 | 1157 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1158 | nvmeq->dev = dev; |
3193f07b | 1159 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1160 | dev->ctrl.instance, qid); |
b60503ba MW |
1161 | spin_lock_init(&nvmeq->q_lock); |
1162 | nvmeq->cq_head = 0; | |
82123460 | 1163 | nvmeq->cq_phase = 1; |
b80d5ccc | 1164 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1165 | nvmeq->q_depth = depth; |
c30341dc | 1166 | nvmeq->qid = qid; |
758dd7fd | 1167 | nvmeq->cq_vector = -1; |
a4aea562 | 1168 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1169 | dev->queue_count++; |
1170 | ||
b60503ba MW |
1171 | return nvmeq; |
1172 | ||
1173 | free_cqdma: | |
e75ec752 | 1174 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1175 | nvmeq->cq_dma_addr); |
1176 | free_nvmeq: | |
1177 | kfree(nvmeq); | |
1178 | return NULL; | |
1179 | } | |
1180 | ||
3001082c MW |
1181 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1182 | const char *name) | |
1183 | { | |
58ffacb5 MW |
1184 | if (use_threaded_interrupts) |
1185 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1186 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1187 | name, nvmeq); |
3001082c | 1188 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1189 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1190 | } |
1191 | ||
22404274 | 1192 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1193 | { |
22404274 | 1194 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1195 | |
7be50e93 | 1196 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1197 | nvmeq->sq_tail = 0; |
1198 | nvmeq->cq_head = 0; | |
1199 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1200 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1201 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1202 | dev->online_queues++; |
7be50e93 | 1203 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1204 | } |
1205 | ||
1206 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1207 | { | |
1208 | struct nvme_dev *dev = nvmeq->dev; | |
1209 | int result; | |
3f85d50b | 1210 | |
2b25d981 | 1211 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1212 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1213 | if (result < 0) | |
22404274 | 1214 | return result; |
b60503ba MW |
1215 | |
1216 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1217 | if (result < 0) | |
1218 | goto release_cq; | |
1219 | ||
3193f07b | 1220 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1221 | if (result < 0) |
1222 | goto release_sq; | |
1223 | ||
22404274 | 1224 | nvme_init_queue(nvmeq, qid); |
22404274 | 1225 | return result; |
b60503ba MW |
1226 | |
1227 | release_sq: | |
1228 | adapter_delete_sq(dev, qid); | |
1229 | release_cq: | |
1230 | adapter_delete_cq(dev, qid); | |
22404274 | 1231 | return result; |
b60503ba MW |
1232 | } |
1233 | ||
a4aea562 | 1234 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1235 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1236 | .complete = nvme_complete_rq, |
a4aea562 MB |
1237 | .map_queue = blk_mq_map_queue, |
1238 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1239 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1240 | .init_request = nvme_admin_init_request, |
1241 | .timeout = nvme_timeout, | |
1242 | }; | |
1243 | ||
1244 | static struct blk_mq_ops nvme_mq_ops = { | |
1245 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1246 | .complete = nvme_complete_rq, |
a4aea562 MB |
1247 | .map_queue = blk_mq_map_queue, |
1248 | .init_hctx = nvme_init_hctx, | |
1249 | .init_request = nvme_init_request, | |
1250 | .timeout = nvme_timeout, | |
a0fa9647 | 1251 | .poll = nvme_poll, |
a4aea562 MB |
1252 | }; |
1253 | ||
ea191d2f KB |
1254 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1255 | { | |
1c63dc66 | 1256 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1257 | /* |
1258 | * If the controller was reset during removal, it's possible | |
1259 | * user requests may be waiting on a stopped queue. Start the | |
1260 | * queue to flush these to completion. | |
1261 | */ | |
1262 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1263 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1264 | blk_mq_free_tag_set(&dev->admin_tagset); |
1265 | } | |
1266 | } | |
1267 | ||
a4aea562 MB |
1268 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1269 | { | |
1c63dc66 | 1270 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1271 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1272 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1273 | |
1274 | /* | |
1275 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1276 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1277 | */ | |
1278 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1279 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1280 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1281 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1282 | dev->admin_tagset.driver_data = dev; |
1283 | ||
1284 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1285 | return -ENOMEM; | |
1286 | ||
1c63dc66 CH |
1287 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1288 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1289 | blk_mq_free_tag_set(&dev->admin_tagset); |
1290 | return -ENOMEM; | |
1291 | } | |
1c63dc66 | 1292 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1293 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1294 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1295 | return -ENODEV; |
1296 | } | |
0fb59cbc | 1297 | } else |
25646264 | 1298 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1299 | |
1300 | return 0; | |
1301 | } | |
1302 | ||
8d85fce7 | 1303 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1304 | { |
ba47e386 | 1305 | int result; |
b60503ba | 1306 | u32 aqa; |
7a67cbea | 1307 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1308 | struct nvme_queue *nvmeq; |
1309 | ||
7a67cbea | 1310 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1311 | NVME_CAP_NSSRC(cap) : 0; |
1312 | ||
7a67cbea CH |
1313 | if (dev->subsystem && |
1314 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1315 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1316 | |
5fd4ce1b | 1317 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1318 | if (result < 0) |
1319 | return result; | |
b60503ba | 1320 | |
a4aea562 | 1321 | nvmeq = dev->queues[0]; |
cd638946 | 1322 | if (!nvmeq) { |
2b25d981 | 1323 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1324 | if (!nvmeq) |
1325 | return -ENOMEM; | |
cd638946 | 1326 | } |
b60503ba MW |
1327 | |
1328 | aqa = nvmeq->q_depth - 1; | |
1329 | aqa |= aqa << 16; | |
1330 | ||
7a67cbea CH |
1331 | writel(aqa, dev->bar + NVME_REG_AQA); |
1332 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1333 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1334 | |
5fd4ce1b | 1335 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1336 | if (result) |
a4aea562 MB |
1337 | goto free_nvmeq; |
1338 | ||
2b25d981 | 1339 | nvmeq->cq_vector = 0; |
3193f07b | 1340 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1341 | if (result) { |
1342 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1343 | goto free_nvmeq; |
758dd7fd | 1344 | } |
025c557a | 1345 | |
b60503ba | 1346 | return result; |
a4aea562 | 1347 | |
a4aea562 MB |
1348 | free_nvmeq: |
1349 | nvme_free_queues(dev, 0); | |
1350 | return result; | |
b60503ba MW |
1351 | } |
1352 | ||
2d55cd5f | 1353 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1354 | { |
2d55cd5f CH |
1355 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1356 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1357 | |
2d55cd5f CH |
1358 | /* |
1359 | * Skip controllers currently under reset. | |
1360 | */ | |
1361 | if (!work_pending(&dev->reset_work) && !work_busy(&dev->reset_work) && | |
1362 | ((csts & NVME_CSTS_CFS) || | |
1363 | (dev->subsystem && (csts & NVME_CSTS_NSSRO)))) { | |
1364 | if (queue_work(nvme_workq, &dev->reset_work)) { | |
1365 | dev_warn(dev->dev, | |
1366 | "Failed status: 0x%x, reset controller.\n", | |
1367 | csts); | |
1fa6aead | 1368 | } |
2d55cd5f | 1369 | return; |
1fa6aead | 1370 | } |
2d55cd5f CH |
1371 | |
1372 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1373 | } |
1374 | ||
749941f2 | 1375 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1376 | { |
949928c1 | 1377 | unsigned i, max; |
749941f2 | 1378 | int ret = 0; |
42f61420 | 1379 | |
749941f2 CH |
1380 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1381 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1382 | ret = -ENOMEM; | |
42f61420 | 1383 | break; |
749941f2 CH |
1384 | } |
1385 | } | |
42f61420 | 1386 | |
949928c1 KB |
1387 | max = min(dev->max_qid, dev->queue_count - 1); |
1388 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 CH |
1389 | ret = nvme_create_queue(dev->queues[i], i); |
1390 | if (ret) { | |
2659e57b | 1391 | nvme_free_queues(dev, i); |
42f61420 | 1392 | break; |
2659e57b | 1393 | } |
27e8166c | 1394 | } |
749941f2 CH |
1395 | |
1396 | /* | |
1397 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1398 | * than the desired aount of queues, and even a controller without | |
1399 | * I/O queues an still be used to issue admin commands. This might | |
1400 | * be useful to upgrade a buggy firmware for example. | |
1401 | */ | |
1402 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1403 | } |
1404 | ||
8ffaadf7 JD |
1405 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1406 | { | |
1407 | u64 szu, size, offset; | |
1408 | u32 cmbloc; | |
1409 | resource_size_t bar_size; | |
1410 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1411 | void __iomem *cmb; | |
1412 | dma_addr_t dma_addr; | |
1413 | ||
1414 | if (!use_cmb_sqes) | |
1415 | return NULL; | |
1416 | ||
7a67cbea | 1417 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1418 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1419 | return NULL; | |
1420 | ||
7a67cbea | 1421 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1422 | |
1423 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1424 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1425 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1426 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1427 | ||
1428 | if (offset > bar_size) | |
1429 | return NULL; | |
1430 | ||
1431 | /* | |
1432 | * Controllers may support a CMB size larger than their BAR, | |
1433 | * for example, due to being behind a bridge. Reduce the CMB to | |
1434 | * the reported size of the BAR | |
1435 | */ | |
1436 | if (size > bar_size - offset) | |
1437 | size = bar_size - offset; | |
1438 | ||
1439 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1440 | cmb = ioremap_wc(dma_addr, size); | |
1441 | if (!cmb) | |
1442 | return NULL; | |
1443 | ||
1444 | dev->cmb_dma_addr = dma_addr; | |
1445 | dev->cmb_size = size; | |
1446 | return cmb; | |
1447 | } | |
1448 | ||
1449 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1450 | { | |
1451 | if (dev->cmb) { | |
1452 | iounmap(dev->cmb); | |
1453 | dev->cmb = NULL; | |
1454 | } | |
1455 | } | |
1456 | ||
9d713c2b KB |
1457 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1458 | { | |
b80d5ccc | 1459 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1460 | } |
1461 | ||
8d85fce7 | 1462 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1463 | { |
a4aea562 | 1464 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1465 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1466 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1467 | |
42f61420 | 1468 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1469 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1470 | if (result < 0) | |
1b23484b | 1471 | return result; |
9a0be7ab CH |
1472 | |
1473 | /* | |
1474 | * Degraded controllers might return an error when setting the queue | |
1475 | * count. We still want to be able to bring them online and offer | |
1476 | * access to the admin queue, as that might be only way to fix them up. | |
1477 | */ | |
1478 | if (result > 0) { | |
1b3c47c1 SG |
1479 | dev_err(dev->ctrl.device, |
1480 | "Could not set queue count (%d)\n", result); | |
a5229050 | 1481 | return 0; |
9a0be7ab | 1482 | } |
b60503ba | 1483 | |
8ffaadf7 JD |
1484 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1485 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1486 | sizeof(struct nvme_command)); | |
1487 | if (result > 0) | |
1488 | dev->q_depth = result; | |
1489 | else | |
1490 | nvme_release_cmb(dev); | |
1491 | } | |
1492 | ||
9d713c2b KB |
1493 | size = db_bar_size(dev, nr_io_queues); |
1494 | if (size > 8192) { | |
f1938f6e | 1495 | iounmap(dev->bar); |
9d713c2b KB |
1496 | do { |
1497 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1498 | if (dev->bar) | |
1499 | break; | |
1500 | if (!--nr_io_queues) | |
1501 | return -ENOMEM; | |
1502 | size = db_bar_size(dev, nr_io_queues); | |
1503 | } while (1); | |
7a67cbea | 1504 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1505 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1506 | } |
1507 | ||
9d713c2b | 1508 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1509 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1510 | |
e32efbfc JA |
1511 | /* |
1512 | * If we enable msix early due to not intx, disable it again before | |
1513 | * setting up the full range we need. | |
1514 | */ | |
a5229050 KB |
1515 | if (pdev->msi_enabled) |
1516 | pci_disable_msi(pdev); | |
1517 | else if (pdev->msix_enabled) | |
e32efbfc JA |
1518 | pci_disable_msix(pdev); |
1519 | ||
be577fab | 1520 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1521 | dev->entry[i].entry = i; |
be577fab AG |
1522 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1523 | if (vecs < 0) { | |
1524 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1525 | if (vecs < 0) { | |
1526 | vecs = 1; | |
1527 | } else { | |
1528 | for (i = 0; i < vecs; i++) | |
1529 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1530 | } |
1531 | } | |
1532 | ||
063a8096 MW |
1533 | /* |
1534 | * Should investigate if there's a performance win from allocating | |
1535 | * more queues than interrupt vectors; it might allow the submission | |
1536 | * path to scale better, even if the receive path is limited by the | |
1537 | * number of interrupts. | |
1538 | */ | |
1539 | nr_io_queues = vecs; | |
42f61420 | 1540 | dev->max_qid = nr_io_queues; |
063a8096 | 1541 | |
3193f07b | 1542 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1543 | if (result) { |
1544 | adminq->cq_vector = -1; | |
22404274 | 1545 | goto free_queues; |
758dd7fd | 1546 | } |
749941f2 | 1547 | return nvme_create_io_queues(dev); |
b60503ba | 1548 | |
22404274 | 1549 | free_queues: |
a1a5ef99 | 1550 | nvme_free_queues(dev, 1); |
22404274 | 1551 | return result; |
b60503ba MW |
1552 | } |
1553 | ||
bda4e0fb | 1554 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
a5768aa8 | 1555 | { |
bda4e0fb KB |
1556 | struct nvme_queue *nvmeq; |
1557 | int i; | |
a5768aa8 | 1558 | |
bda4e0fb KB |
1559 | for (i = 0; i < dev->online_queues; i++) { |
1560 | nvmeq = dev->queues[i]; | |
a5768aa8 | 1561 | |
bda4e0fb KB |
1562 | if (!nvmeq->tags || !(*nvmeq->tags)) |
1563 | continue; | |
a5768aa8 | 1564 | |
bda4e0fb KB |
1565 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, |
1566 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
a5768aa8 | 1567 | } |
a5768aa8 KB |
1568 | } |
1569 | ||
a5768aa8 | 1570 | static void nvme_dev_scan(struct work_struct *work) |
a5768aa8 | 1571 | { |
a5768aa8 | 1572 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); |
a5768aa8 KB |
1573 | |
1574 | if (!dev->tagset.tags) | |
1575 | return; | |
5bae7f73 | 1576 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1577 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1578 | } |
1579 | ||
db3cbfff | 1580 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1581 | { |
db3cbfff | 1582 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1583 | |
db3cbfff KB |
1584 | blk_mq_free_request(req); |
1585 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1586 | } |
1587 | ||
db3cbfff | 1588 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1589 | { |
db3cbfff | 1590 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1591 | |
db3cbfff KB |
1592 | if (!error) { |
1593 | unsigned long flags; | |
1594 | ||
1595 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
1596 | nvme_process_cq(nvmeq); | |
1597 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1598 | } |
db3cbfff KB |
1599 | |
1600 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1601 | } |
1602 | ||
db3cbfff | 1603 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1604 | { |
db3cbfff KB |
1605 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1606 | struct request *req; | |
1607 | struct nvme_command cmd; | |
bda4e0fb | 1608 | |
db3cbfff KB |
1609 | memset(&cmd, 0, sizeof(cmd)); |
1610 | cmd.delete_queue.opcode = opcode; | |
1611 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1612 | |
db3cbfff KB |
1613 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); |
1614 | if (IS_ERR(req)) | |
1615 | return PTR_ERR(req); | |
bda4e0fb | 1616 | |
db3cbfff KB |
1617 | req->timeout = ADMIN_TIMEOUT; |
1618 | req->end_io_data = nvmeq; | |
1619 | ||
1620 | blk_execute_rq_nowait(q, NULL, req, false, | |
1621 | opcode == nvme_admin_delete_cq ? | |
1622 | nvme_del_cq_end : nvme_del_queue_end); | |
1623 | return 0; | |
bda4e0fb KB |
1624 | } |
1625 | ||
db3cbfff | 1626 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
a5768aa8 | 1627 | { |
db3cbfff KB |
1628 | int pass; |
1629 | unsigned long timeout; | |
1630 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1631 | |
db3cbfff KB |
1632 | for (pass = 0; pass < 2; pass++) { |
1633 | int sent = 0, i = dev->queue_count - 1; | |
1634 | ||
1635 | reinit_completion(&dev->ioq_wait); | |
1636 | retry: | |
1637 | timeout = ADMIN_TIMEOUT; | |
1638 | for (; i > 0; i--) { | |
1639 | struct nvme_queue *nvmeq = dev->queues[i]; | |
1640 | ||
1641 | if (!pass) | |
1642 | nvme_suspend_queue(nvmeq); | |
1643 | if (nvme_delete_queue(nvmeq, opcode)) | |
1644 | break; | |
1645 | ++sent; | |
1646 | } | |
1647 | while (sent--) { | |
1648 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1649 | if (timeout == 0) | |
1650 | return; | |
1651 | if (i) | |
1652 | goto retry; | |
1653 | } | |
1654 | opcode = nvme_admin_delete_cq; | |
1655 | } | |
a5768aa8 KB |
1656 | } |
1657 | ||
422ef0c7 MW |
1658 | /* |
1659 | * Return: error value if an error occurred setting up the queues or calling | |
1660 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1661 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1662 | * failures should be reported. | |
1663 | */ | |
8d85fce7 | 1664 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1665 | { |
5bae7f73 | 1666 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1667 | dev->tagset.ops = &nvme_mq_ops; |
1668 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1669 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1670 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1671 | dev->tagset.queue_depth = | |
a4aea562 | 1672 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1673 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1674 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1675 | dev->tagset.driver_data = dev; | |
b60503ba | 1676 | |
ffe7704d KB |
1677 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1678 | return 0; | |
5bae7f73 | 1679 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1680 | } else { |
1681 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1682 | ||
1683 | /* Free previously allocated queues that are no longer usable */ | |
1684 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1685 | } |
949928c1 | 1686 | |
646017a6 | 1687 | nvme_queue_scan(dev); |
e1e5e564 | 1688 | return 0; |
b60503ba MW |
1689 | } |
1690 | ||
b00a726a | 1691 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1692 | { |
42f61420 | 1693 | u64 cap; |
b00a726a | 1694 | int result = -ENOMEM; |
e75ec752 | 1695 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1696 | |
1697 | if (pci_enable_device_mem(pdev)) | |
1698 | return result; | |
1699 | ||
0877cb0d | 1700 | pci_set_master(pdev); |
0877cb0d | 1701 | |
e75ec752 CH |
1702 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1703 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1704 | goto disable; |
0877cb0d | 1705 | |
7a67cbea | 1706 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1707 | result = -ENODEV; |
b00a726a | 1708 | goto disable; |
0e53d180 | 1709 | } |
e32efbfc JA |
1710 | |
1711 | /* | |
a5229050 KB |
1712 | * Some devices and/or platforms don't advertise or work with INTx |
1713 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1714 | * adjust this later. | |
e32efbfc | 1715 | */ |
a5229050 KB |
1716 | if (pci_enable_msix(pdev, dev->entry, 1)) { |
1717 | pci_enable_msi(pdev); | |
1718 | dev->entry[0].vector = pdev->irq; | |
1719 | } | |
1720 | ||
1721 | if (!dev->entry[0].vector) { | |
1722 | result = -ENODEV; | |
1723 | goto disable; | |
e32efbfc JA |
1724 | } |
1725 | ||
7a67cbea CH |
1726 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1727 | ||
42f61420 KB |
1728 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1729 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1730 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1731 | |
1732 | /* | |
1733 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1734 | * some MacBook7,1 to avoid controller resets and data loss. | |
1735 | */ | |
1736 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1737 | dev->q_depth = 2; | |
1738 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1739 | "queue depth=%u to work around controller resets\n", | |
1740 | dev->q_depth); | |
1741 | } | |
1742 | ||
7a67cbea | 1743 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) |
8ffaadf7 | 1744 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1745 | |
a0a3408e KB |
1746 | pci_enable_pcie_error_reporting(pdev); |
1747 | pci_save_state(pdev); | |
0877cb0d KB |
1748 | return 0; |
1749 | ||
1750 | disable: | |
0877cb0d KB |
1751 | pci_disable_device(pdev); |
1752 | return result; | |
1753 | } | |
1754 | ||
1755 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1756 | { |
1757 | if (dev->bar) | |
1758 | iounmap(dev->bar); | |
1759 | pci_release_regions(to_pci_dev(dev->dev)); | |
1760 | } | |
1761 | ||
1762 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1763 | { |
e75ec752 CH |
1764 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1765 | ||
1766 | if (pdev->msi_enabled) | |
1767 | pci_disable_msi(pdev); | |
1768 | else if (pdev->msix_enabled) | |
1769 | pci_disable_msix(pdev); | |
0877cb0d | 1770 | |
a0a3408e KB |
1771 | if (pci_is_enabled(pdev)) { |
1772 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1773 | pci_disable_device(pdev); |
4d115420 | 1774 | } |
4d115420 KB |
1775 | } |
1776 | ||
a5cdb68c | 1777 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1778 | { |
22404274 | 1779 | int i; |
7c1b2450 | 1780 | u32 csts = -1; |
22404274 | 1781 | |
2d55cd5f | 1782 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1783 | |
77bf25ea | 1784 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 1785 | if (pci_is_enabled(to_pci_dev(dev->dev))) { |
25646264 | 1786 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1787 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1788 | } |
7c1b2450 | 1789 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1790 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1791 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1792 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1793 | } |
1794 | } else { | |
1795 | nvme_disable_io_queues(dev); | |
a5cdb68c | 1796 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1797 | } |
b00a726a | 1798 | nvme_pci_disable(dev); |
07836e65 KB |
1799 | |
1800 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1801 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 1802 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1803 | } |
1804 | ||
091b6092 MW |
1805 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1806 | { | |
e75ec752 | 1807 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1808 | PAGE_SIZE, PAGE_SIZE, 0); |
1809 | if (!dev->prp_page_pool) | |
1810 | return -ENOMEM; | |
1811 | ||
99802a7a | 1812 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1813 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1814 | 256, 256, 0); |
1815 | if (!dev->prp_small_pool) { | |
1816 | dma_pool_destroy(dev->prp_page_pool); | |
1817 | return -ENOMEM; | |
1818 | } | |
091b6092 MW |
1819 | return 0; |
1820 | } | |
1821 | ||
1822 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1823 | { | |
1824 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1825 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1826 | } |
1827 | ||
1673f1f0 | 1828 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1829 | { |
1673f1f0 | 1830 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1831 | |
e75ec752 | 1832 | put_device(dev->dev); |
4af0e21c KB |
1833 | if (dev->tagset.tags) |
1834 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1835 | if (dev->ctrl.admin_q) |
1836 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1837 | kfree(dev->queues); |
1838 | kfree(dev->entry); | |
1839 | kfree(dev); | |
1840 | } | |
1841 | ||
f58944e2 KB |
1842 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1843 | { | |
237045fc | 1844 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1845 | |
1846 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1847 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1848 | if (!schedule_work(&dev->remove_work)) |
1849 | nvme_put_ctrl(&dev->ctrl); | |
1850 | } | |
1851 | ||
fd634f41 | 1852 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1853 | { |
fd634f41 | 1854 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
f58944e2 | 1855 | int result = -ENODEV; |
5e82e952 | 1856 | |
fd634f41 CH |
1857 | if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags))) |
1858 | goto out; | |
5e82e952 | 1859 | |
fd634f41 CH |
1860 | /* |
1861 | * If we're called to reset a live controller first shut it down before | |
1862 | * moving on. | |
1863 | */ | |
b00a726a | 1864 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1865 | nvme_dev_disable(dev, false); |
5e82e952 | 1866 | |
9bf2b972 KB |
1867 | if (test_bit(NVME_CTRL_REMOVING, &dev->flags)) |
1868 | goto out; | |
1869 | ||
fd634f41 | 1870 | set_bit(NVME_CTRL_RESETTING, &dev->flags); |
f0b50732 | 1871 | |
b00a726a | 1872 | result = nvme_pci_enable(dev); |
f0b50732 | 1873 | if (result) |
3cf519b5 | 1874 | goto out; |
f0b50732 KB |
1875 | |
1876 | result = nvme_configure_admin_queue(dev); | |
1877 | if (result) | |
f58944e2 | 1878 | goto out; |
f0b50732 | 1879 | |
a4aea562 | 1880 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1881 | result = nvme_alloc_admin_tags(dev); |
1882 | if (result) | |
f58944e2 | 1883 | goto out; |
b9afca3e | 1884 | |
ce4541f4 CH |
1885 | result = nvme_init_identify(&dev->ctrl); |
1886 | if (result) | |
f58944e2 | 1887 | goto out; |
ce4541f4 | 1888 | |
f0b50732 | 1889 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1890 | if (result) |
f58944e2 | 1891 | goto out; |
f0b50732 | 1892 | |
adf68f21 | 1893 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; |
9396dec9 | 1894 | queue_work(nvme_workq, &dev->async_work); |
3cf519b5 | 1895 | |
2d55cd5f | 1896 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1897 | |
2659e57b CH |
1898 | /* |
1899 | * Keep the controller around but remove all namespaces if we don't have | |
1900 | * any working I/O queue. | |
1901 | */ | |
3cf519b5 | 1902 | if (dev->online_queues < 2) { |
1b3c47c1 | 1903 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
5bae7f73 | 1904 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1905 | } else { |
25646264 | 1906 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1907 | nvme_dev_add(dev); |
1908 | } | |
1909 | ||
fd634f41 | 1910 | clear_bit(NVME_CTRL_RESETTING, &dev->flags); |
3cf519b5 | 1911 | return; |
f0b50732 | 1912 | |
3cf519b5 | 1913 | out: |
f58944e2 | 1914 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1915 | } |
1916 | ||
5c8809e6 | 1917 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1918 | { |
5c8809e6 | 1919 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1920 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1921 | |
69d9a99c | 1922 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1923 | if (pci_get_drvdata(pdev)) |
c81f4975 | 1924 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 1925 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1926 | } |
1927 | ||
4cc06521 | 1928 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1929 | { |
1c63dc66 | 1930 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1931 | return -ENODEV; |
ffe7704d | 1932 | |
846cc05f CH |
1933 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1934 | return -EBUSY; | |
ffe7704d | 1935 | |
846cc05f | 1936 | flush_work(&dev->reset_work); |
846cc05f | 1937 | return 0; |
9a6b9458 KB |
1938 | } |
1939 | ||
1c63dc66 | 1940 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1941 | { |
1c63dc66 | 1942 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1943 | return 0; |
9ca97374 TH |
1944 | } |
1945 | ||
5fd4ce1b | 1946 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 1947 | { |
5fd4ce1b CH |
1948 | writel(val, to_nvme_dev(ctrl)->bar + off); |
1949 | return 0; | |
1950 | } | |
4cc06521 | 1951 | |
7fd8930f CH |
1952 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
1953 | { | |
1954 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
1955 | return 0; | |
4cc06521 KB |
1956 | } |
1957 | ||
5bae7f73 | 1958 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
4cc06521 | 1959 | { |
5bae7f73 | 1960 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
4cc06521 | 1961 | |
5bae7f73 CH |
1962 | return !dev->bar || dev->online_queues < 2; |
1963 | } | |
4cc06521 | 1964 | |
f3ca80fc CH |
1965 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
1966 | { | |
1967 | return nvme_reset(to_nvme_dev(ctrl)); | |
4cc06521 | 1968 | } |
f3ca80fc | 1969 | |
1c63dc66 | 1970 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
e439bb12 | 1971 | .module = THIS_MODULE, |
1c63dc66 | 1972 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 1973 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 1974 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 1975 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 1976 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 1977 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 | 1978 | }; |
4cc06521 | 1979 | |
b00a726a KB |
1980 | static int nvme_dev_map(struct nvme_dev *dev) |
1981 | { | |
1982 | int bars; | |
1983 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1984 | ||
1985 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
1986 | if (!bars) | |
1987 | return -ENODEV; | |
1988 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1989 | return -ENODEV; | |
1990 | ||
1991 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1992 | if (!dev->bar) | |
1993 | goto release; | |
1994 | ||
1995 | return 0; | |
1996 | release: | |
1997 | pci_release_regions(pdev); | |
1998 | return -ENODEV; | |
1999 | } | |
2000 | ||
8d85fce7 | 2001 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2002 | { |
a4aea562 | 2003 | int node, result = -ENOMEM; |
b60503ba MW |
2004 | struct nvme_dev *dev; |
2005 | ||
a4aea562 MB |
2006 | node = dev_to_node(&pdev->dev); |
2007 | if (node == NUMA_NO_NODE) | |
2008 | set_dev_node(&pdev->dev, 0); | |
2009 | ||
2010 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2011 | if (!dev) |
2012 | return -ENOMEM; | |
a4aea562 MB |
2013 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2014 | GFP_KERNEL, node); | |
b60503ba MW |
2015 | if (!dev->entry) |
2016 | goto free; | |
a4aea562 MB |
2017 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2018 | GFP_KERNEL, node); | |
b60503ba MW |
2019 | if (!dev->queues) |
2020 | goto free; | |
2021 | ||
e75ec752 | 2022 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2023 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2024 | |
b00a726a KB |
2025 | result = nvme_dev_map(dev); |
2026 | if (result) | |
2027 | goto free; | |
2028 | ||
f3ca80fc | 2029 | INIT_WORK(&dev->scan_work, nvme_dev_scan); |
f3ca80fc | 2030 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2031 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
9396dec9 | 2032 | INIT_WORK(&dev->async_work, nvme_async_event_work); |
2d55cd5f CH |
2033 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
2034 | (unsigned long)dev); | |
77bf25ea | 2035 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2036 | init_completion(&dev->ioq_wait); |
b60503ba | 2037 | |
091b6092 MW |
2038 | result = nvme_setup_prp_pools(dev); |
2039 | if (result) | |
a96d4f5c | 2040 | goto put_pci; |
4cc06521 | 2041 | |
f3ca80fc CH |
2042 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2043 | id->driver_data); | |
4cc06521 | 2044 | if (result) |
2e1d8448 | 2045 | goto release_pools; |
740216fc | 2046 | |
1b3c47c1 SG |
2047 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2048 | ||
92f7a162 | 2049 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2050 | return 0; |
2051 | ||
0877cb0d | 2052 | release_pools: |
091b6092 | 2053 | nvme_release_prp_pools(dev); |
a96d4f5c | 2054 | put_pci: |
e75ec752 | 2055 | put_device(dev->dev); |
b00a726a | 2056 | nvme_dev_unmap(dev); |
b60503ba MW |
2057 | free: |
2058 | kfree(dev->queues); | |
2059 | kfree(dev->entry); | |
2060 | kfree(dev); | |
2061 | return result; | |
2062 | } | |
2063 | ||
f0d54a54 KB |
2064 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2065 | { | |
a6739479 | 2066 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2067 | |
a6739479 | 2068 | if (prepare) |
a5cdb68c | 2069 | nvme_dev_disable(dev, false); |
a6739479 | 2070 | else |
92f7a162 | 2071 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2072 | } |
2073 | ||
09ece142 KB |
2074 | static void nvme_shutdown(struct pci_dev *pdev) |
2075 | { | |
2076 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2077 | nvme_dev_disable(dev, true); |
09ece142 KB |
2078 | } |
2079 | ||
f58944e2 KB |
2080 | /* |
2081 | * The driver's remove may be called on a device in a partially initialized | |
2082 | * state. This function must not have any dependencies on the device state in | |
2083 | * order to proceed. | |
2084 | */ | |
8d85fce7 | 2085 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2086 | { |
2087 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2088 | |
646017a6 | 2089 | set_bit(NVME_CTRL_REMOVING, &dev->flags); |
9a6b9458 | 2090 | pci_set_drvdata(pdev, NULL); |
9396dec9 | 2091 | flush_work(&dev->async_work); |
9bf2b972 | 2092 | flush_work(&dev->reset_work); |
a5768aa8 | 2093 | flush_work(&dev->scan_work); |
5bae7f73 | 2094 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2095 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2096 | nvme_dev_disable(dev, true); |
ff23a2a1 | 2097 | flush_work(&dev->reset_work); |
a4aea562 | 2098 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2099 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2100 | nvme_release_cmb(dev); |
9a6b9458 | 2101 | nvme_release_prp_pools(dev); |
b00a726a | 2102 | nvme_dev_unmap(dev); |
1673f1f0 | 2103 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2104 | } |
2105 | ||
671a6018 | 2106 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2107 | static int nvme_suspend(struct device *dev) |
2108 | { | |
2109 | struct pci_dev *pdev = to_pci_dev(dev); | |
2110 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2111 | ||
a5cdb68c | 2112 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2113 | return 0; |
2114 | } | |
2115 | ||
2116 | static int nvme_resume(struct device *dev) | |
2117 | { | |
2118 | struct pci_dev *pdev = to_pci_dev(dev); | |
2119 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2120 | |
92f7a162 | 2121 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2122 | return 0; |
cd638946 | 2123 | } |
671a6018 | 2124 | #endif |
cd638946 KB |
2125 | |
2126 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2127 | |
a0a3408e KB |
2128 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2129 | pci_channel_state_t state) | |
2130 | { | |
2131 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2132 | ||
2133 | /* | |
2134 | * A frozen channel requires a reset. When detected, this method will | |
2135 | * shutdown the controller to quiesce. The controller will be restarted | |
2136 | * after the slot reset through driver's slot_reset callback. | |
2137 | */ | |
1b3c47c1 | 2138 | dev_warn(dev->ctrl.device, "error detected: state:%d\n", state); |
a0a3408e KB |
2139 | switch (state) { |
2140 | case pci_channel_io_normal: | |
2141 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2142 | case pci_channel_io_frozen: | |
a5cdb68c | 2143 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2144 | return PCI_ERS_RESULT_NEED_RESET; |
2145 | case pci_channel_io_perm_failure: | |
2146 | return PCI_ERS_RESULT_DISCONNECT; | |
2147 | } | |
2148 | return PCI_ERS_RESULT_NEED_RESET; | |
2149 | } | |
2150 | ||
2151 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2152 | { | |
2153 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2154 | ||
1b3c47c1 | 2155 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e KB |
2156 | pci_restore_state(pdev); |
2157 | queue_work(nvme_workq, &dev->reset_work); | |
2158 | return PCI_ERS_RESULT_RECOVERED; | |
2159 | } | |
2160 | ||
2161 | static void nvme_error_resume(struct pci_dev *pdev) | |
2162 | { | |
2163 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2164 | } | |
2165 | ||
1d352035 | 2166 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2167 | .error_detected = nvme_error_detected, |
b60503ba MW |
2168 | .slot_reset = nvme_slot_reset, |
2169 | .resume = nvme_error_resume, | |
f0d54a54 | 2170 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2171 | }; |
2172 | ||
2173 | /* Move to pci_ids.h later */ | |
2174 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2175 | ||
6eb0d698 | 2176 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2177 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2178 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2179 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2180 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2181 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2182 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2183 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2184 | { 0, } |
2185 | }; | |
2186 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2187 | ||
2188 | static struct pci_driver nvme_driver = { | |
2189 | .name = "nvme", | |
2190 | .id_table = nvme_id_table, | |
2191 | .probe = nvme_probe, | |
8d85fce7 | 2192 | .remove = nvme_remove, |
09ece142 | 2193 | .shutdown = nvme_shutdown, |
cd638946 KB |
2194 | .driver = { |
2195 | .pm = &nvme_dev_pm_ops, | |
2196 | }, | |
b60503ba MW |
2197 | .err_handler = &nvme_err_handler, |
2198 | }; | |
2199 | ||
2200 | static int __init nvme_init(void) | |
2201 | { | |
0ac13140 | 2202 | int result; |
1fa6aead | 2203 | |
92f7a162 | 2204 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2205 | if (!nvme_workq) |
b9afca3e | 2206 | return -ENOMEM; |
9a6b9458 | 2207 | |
f3db22fe KB |
2208 | result = pci_register_driver(&nvme_driver); |
2209 | if (result) | |
576d55d6 | 2210 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2211 | return result; |
2212 | } | |
2213 | ||
2214 | static void __exit nvme_exit(void) | |
2215 | { | |
2216 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2217 | destroy_workqueue(nvme_workq); |
21bd78bc | 2218 | _nvme_check_size(); |
b60503ba MW |
2219 | } |
2220 | ||
2221 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2222 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2223 | MODULE_VERSION("1.0"); |
b60503ba MW |
2224 | module_init(nvme_init); |
2225 | module_exit(nvme_exit); |