Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
77bf25ea | 34 | #include <linux/mutex.h> |
b60503ba | 35 | #include <linux/pci.h> |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
2d55cd5f | 41 | #include <linux/timer.h> |
b60503ba | 42 | #include <linux/types.h> |
2f8e2c87 | 43 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 44 | #include <asm/unaligned.h> |
797a796a | 45 | |
f11bb3e2 CH |
46 | #include "nvme.h" |
47 | ||
9d43cf64 | 48 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 49 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
50 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
51 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
52 | |
53 | /* | |
54 | * We handle AEN commands ourselves and don't even let the | |
55 | * block layer know about them. | |
56 | */ | |
f866fc42 | 57 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 58 | |
58ffacb5 MW |
59 | static int use_threaded_interrupts; |
60 | module_param(use_threaded_interrupts, int, 0); | |
61 | ||
8ffaadf7 JD |
62 | static bool use_cmb_sqes = true; |
63 | module_param(use_cmb_sqes, bool, 0644); | |
64 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
65 | ||
9a6b9458 | 66 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 67 | |
1c63dc66 CH |
68 | struct nvme_dev; |
69 | struct nvme_queue; | |
b3fffdef | 70 | |
4cc06521 | 71 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 72 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 73 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 74 | |
1c63dc66 CH |
75 | /* |
76 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
77 | */ | |
78 | struct nvme_dev { | |
1c63dc66 CH |
79 | struct nvme_queue **queues; |
80 | struct blk_mq_tag_set tagset; | |
81 | struct blk_mq_tag_set admin_tagset; | |
82 | u32 __iomem *dbs; | |
83 | struct device *dev; | |
84 | struct dma_pool *prp_page_pool; | |
85 | struct dma_pool *prp_small_pool; | |
86 | unsigned queue_count; | |
87 | unsigned online_queues; | |
88 | unsigned max_qid; | |
89 | int q_depth; | |
90 | u32 db_stride; | |
1c63dc66 CH |
91 | struct msix_entry *entry; |
92 | void __iomem *bar; | |
1c63dc66 | 93 | struct work_struct reset_work; |
5c8809e6 | 94 | struct work_struct remove_work; |
2d55cd5f | 95 | struct timer_list watchdog_timer; |
77bf25ea | 96 | struct mutex shutdown_lock; |
1c63dc66 | 97 | bool subsystem; |
1c63dc66 CH |
98 | void __iomem *cmb; |
99 | dma_addr_t cmb_dma_addr; | |
100 | u64 cmb_size; | |
101 | u32 cmbsz; | |
1c63dc66 | 102 | struct nvme_ctrl ctrl; |
db3cbfff | 103 | struct completion ioq_wait; |
4d115420 | 104 | }; |
1fa6aead | 105 | |
1c63dc66 CH |
106 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
107 | { | |
108 | return container_of(ctrl, struct nvme_dev, ctrl); | |
109 | } | |
110 | ||
b60503ba MW |
111 | /* |
112 | * An NVM Express queue. Each device has at least two (one for admin | |
113 | * commands and one for I/O commands). | |
114 | */ | |
115 | struct nvme_queue { | |
116 | struct device *q_dmadev; | |
091b6092 | 117 | struct nvme_dev *dev; |
3193f07b | 118 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
119 | spinlock_t q_lock; |
120 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 121 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 122 | volatile struct nvme_completion *cqes; |
42483228 | 123 | struct blk_mq_tags **tags; |
b60503ba MW |
124 | dma_addr_t sq_dma_addr; |
125 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
126 | u32 __iomem *q_db; |
127 | u16 q_depth; | |
6222d172 | 128 | s16 cq_vector; |
b60503ba MW |
129 | u16 sq_tail; |
130 | u16 cq_head; | |
c30341dc | 131 | u16 qid; |
e9539f47 MW |
132 | u8 cq_phase; |
133 | u8 cqe_seen; | |
b60503ba MW |
134 | }; |
135 | ||
71bd150c CH |
136 | /* |
137 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
138 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 139 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
140 | * allocated to store the PRP list. |
141 | */ | |
142 | struct nvme_iod { | |
f4800d6d CH |
143 | struct nvme_queue *nvmeq; |
144 | int aborted; | |
71bd150c | 145 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
146 | int nents; /* Used in scatterlist */ |
147 | int length; /* Of data, in bytes */ | |
148 | dma_addr_t first_dma; | |
bf684057 | 149 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
150 | struct scatterlist *sg; |
151 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
152 | }; |
153 | ||
154 | /* | |
155 | * Check we didin't inadvertently grow the command struct | |
156 | */ | |
157 | static inline void _nvme_check_size(void) | |
158 | { | |
159 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
160 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
161 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
162 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
163 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 164 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 165 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
166 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
167 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
168 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
169 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 170 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
171 | } |
172 | ||
ac3dd5bd JA |
173 | /* |
174 | * Max size of iod being embedded in the request payload | |
175 | */ | |
176 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 177 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
178 | |
179 | /* | |
180 | * Will slightly overestimate the number of pages needed. This is OK | |
181 | * as it only leads to a small amount of wasted memory for the lifetime of | |
182 | * the I/O. | |
183 | */ | |
184 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
185 | { | |
5fd4ce1b CH |
186 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
187 | dev->ctrl.page_size); | |
ac3dd5bd JA |
188 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
189 | } | |
190 | ||
f4800d6d CH |
191 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
192 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 193 | { |
f4800d6d CH |
194 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
195 | sizeof(struct scatterlist) * nseg; | |
196 | } | |
ac3dd5bd | 197 | |
f4800d6d CH |
198 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
199 | { | |
200 | return sizeof(struct nvme_iod) + | |
201 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
202 | } |
203 | ||
a4aea562 MB |
204 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
205 | unsigned int hctx_idx) | |
e85248e5 | 206 | { |
a4aea562 MB |
207 | struct nvme_dev *dev = data; |
208 | struct nvme_queue *nvmeq = dev->queues[0]; | |
209 | ||
42483228 KB |
210 | WARN_ON(hctx_idx != 0); |
211 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
212 | WARN_ON(nvmeq->tags); | |
213 | ||
a4aea562 | 214 | hctx->driver_data = nvmeq; |
42483228 | 215 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 216 | return 0; |
e85248e5 MW |
217 | } |
218 | ||
4af0e21c KB |
219 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
220 | { | |
221 | struct nvme_queue *nvmeq = hctx->driver_data; | |
222 | ||
223 | nvmeq->tags = NULL; | |
224 | } | |
225 | ||
a4aea562 MB |
226 | static int nvme_admin_init_request(void *data, struct request *req, |
227 | unsigned int hctx_idx, unsigned int rq_idx, | |
228 | unsigned int numa_node) | |
22404274 | 229 | { |
a4aea562 | 230 | struct nvme_dev *dev = data; |
f4800d6d | 231 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
232 | struct nvme_queue *nvmeq = dev->queues[0]; |
233 | ||
234 | BUG_ON(!nvmeq); | |
f4800d6d | 235 | iod->nvmeq = nvmeq; |
a4aea562 | 236 | return 0; |
22404274 KB |
237 | } |
238 | ||
a4aea562 MB |
239 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
240 | unsigned int hctx_idx) | |
b60503ba | 241 | { |
a4aea562 | 242 | struct nvme_dev *dev = data; |
42483228 | 243 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 244 | |
42483228 KB |
245 | if (!nvmeq->tags) |
246 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 247 | |
42483228 | 248 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
249 | hctx->driver_data = nvmeq; |
250 | return 0; | |
b60503ba MW |
251 | } |
252 | ||
a4aea562 MB |
253 | static int nvme_init_request(void *data, struct request *req, |
254 | unsigned int hctx_idx, unsigned int rq_idx, | |
255 | unsigned int numa_node) | |
b60503ba | 256 | { |
a4aea562 | 257 | struct nvme_dev *dev = data; |
f4800d6d | 258 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 MB |
259 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
260 | ||
261 | BUG_ON(!nvmeq); | |
f4800d6d | 262 | iod->nvmeq = nvmeq; |
a4aea562 MB |
263 | return 0; |
264 | } | |
265 | ||
b60503ba | 266 | /** |
adf68f21 | 267 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
268 | * @nvmeq: The queue to use |
269 | * @cmd: The command to send | |
270 | * | |
271 | * Safe to use from interrupt context | |
272 | */ | |
e3f879bf SB |
273 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
274 | struct nvme_command *cmd) | |
b60503ba | 275 | { |
a4aea562 MB |
276 | u16 tail = nvmeq->sq_tail; |
277 | ||
8ffaadf7 JD |
278 | if (nvmeq->sq_cmds_io) |
279 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
280 | else | |
281 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
282 | ||
b60503ba MW |
283 | if (++tail == nvmeq->q_depth) |
284 | tail = 0; | |
7547881d | 285 | writel(tail, nvmeq->q_db); |
b60503ba | 286 | nvmeq->sq_tail = tail; |
b60503ba MW |
287 | } |
288 | ||
f4800d6d | 289 | static __le64 **iod_list(struct request *req) |
b60503ba | 290 | { |
f4800d6d CH |
291 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
292 | return (__le64 **)(iod->sg + req->nr_phys_segments); | |
b60503ba MW |
293 | } |
294 | ||
58b45602 ML |
295 | static int nvme_init_iod(struct request *rq, unsigned size, |
296 | struct nvme_dev *dev) | |
ac3dd5bd | 297 | { |
f4800d6d CH |
298 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
299 | int nseg = rq->nr_phys_segments; | |
ac3dd5bd | 300 | |
f4800d6d CH |
301 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
302 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
303 | if (!iod->sg) | |
304 | return BLK_MQ_RQ_QUEUE_BUSY; | |
305 | } else { | |
306 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
307 | } |
308 | ||
f4800d6d CH |
309 | iod->aborted = 0; |
310 | iod->npages = -1; | |
311 | iod->nents = 0; | |
312 | iod->length = size; | |
313 | return 0; | |
ac3dd5bd JA |
314 | } |
315 | ||
f4800d6d | 316 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 317 | { |
f4800d6d | 318 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 319 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 320 | int i; |
f4800d6d | 321 | __le64 **list = iod_list(req); |
eca18b23 MW |
322 | dma_addr_t prp_dma = iod->first_dma; |
323 | ||
6904242d | 324 | nvme_cleanup_cmd(req); |
03b5929e | 325 | |
eca18b23 MW |
326 | if (iod->npages == 0) |
327 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
328 | for (i = 0; i < iod->npages; i++) { | |
329 | __le64 *prp_list = list[i]; | |
330 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
331 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
332 | prp_dma = next_prp_dma; | |
333 | } | |
ac3dd5bd | 334 | |
f4800d6d CH |
335 | if (iod->sg != iod->inline_sg) |
336 | kfree(iod->sg); | |
b4ff9c8d KB |
337 | } |
338 | ||
52b68d7e | 339 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
340 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
341 | { | |
342 | if (be32_to_cpu(pi->ref_tag) == v) | |
343 | pi->ref_tag = cpu_to_be32(p); | |
344 | } | |
345 | ||
346 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
347 | { | |
348 | if (be32_to_cpu(pi->ref_tag) == p) | |
349 | pi->ref_tag = cpu_to_be32(v); | |
350 | } | |
351 | ||
352 | /** | |
353 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
354 | * | |
355 | * The virtual start sector is the one that was originally submitted by the | |
356 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
357 | * start sector may be different. Remap protection information to match the | |
358 | * physical LBA on writes, and back to the original seed on reads. | |
359 | * | |
360 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
361 | */ | |
362 | static void nvme_dif_remap(struct request *req, | |
363 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
364 | { | |
365 | struct nvme_ns *ns = req->rq_disk->private_data; | |
366 | struct bio_integrity_payload *bip; | |
367 | struct t10_pi_tuple *pi; | |
368 | void *p, *pmap; | |
369 | u32 i, nlb, ts, phys, virt; | |
370 | ||
371 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
372 | return; | |
373 | ||
374 | bip = bio_integrity(req->bio); | |
375 | if (!bip) | |
376 | return; | |
377 | ||
378 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
379 | |
380 | p = pmap; | |
381 | virt = bip_get_seed(bip); | |
382 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
383 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 384 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
385 | |
386 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
387 | pi = (struct t10_pi_tuple *)p; | |
388 | dif_swap(phys, virt, pi); | |
389 | p += ts; | |
390 | } | |
391 | kunmap_atomic(pmap); | |
392 | } | |
52b68d7e KB |
393 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
394 | static void nvme_dif_remap(struct request *req, | |
395 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
396 | { | |
397 | } | |
398 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
399 | { | |
400 | } | |
401 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
402 | { | |
403 | } | |
52b68d7e KB |
404 | #endif |
405 | ||
f4800d6d | 406 | static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req, |
69d2b571 | 407 | int total_len) |
ff22b54f | 408 | { |
f4800d6d | 409 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 410 | struct dma_pool *pool; |
eca18b23 MW |
411 | int length = total_len; |
412 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
413 | int dma_len = sg_dma_len(sg); |
414 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 415 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 416 | int offset = dma_addr & (page_size - 1); |
e025344c | 417 | __le64 *prp_list; |
f4800d6d | 418 | __le64 **list = iod_list(req); |
e025344c | 419 | dma_addr_t prp_dma; |
eca18b23 | 420 | int nprps, i; |
ff22b54f | 421 | |
1d090624 | 422 | length -= (page_size - offset); |
ff22b54f | 423 | if (length <= 0) |
69d2b571 | 424 | return true; |
ff22b54f | 425 | |
1d090624 | 426 | dma_len -= (page_size - offset); |
ff22b54f | 427 | if (dma_len) { |
1d090624 | 428 | dma_addr += (page_size - offset); |
ff22b54f MW |
429 | } else { |
430 | sg = sg_next(sg); | |
431 | dma_addr = sg_dma_address(sg); | |
432 | dma_len = sg_dma_len(sg); | |
433 | } | |
434 | ||
1d090624 | 435 | if (length <= page_size) { |
edd10d33 | 436 | iod->first_dma = dma_addr; |
69d2b571 | 437 | return true; |
e025344c SMM |
438 | } |
439 | ||
1d090624 | 440 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
441 | if (nprps <= (256 / 8)) { |
442 | pool = dev->prp_small_pool; | |
eca18b23 | 443 | iod->npages = 0; |
99802a7a MW |
444 | } else { |
445 | pool = dev->prp_page_pool; | |
eca18b23 | 446 | iod->npages = 1; |
99802a7a MW |
447 | } |
448 | ||
69d2b571 | 449 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 450 | if (!prp_list) { |
edd10d33 | 451 | iod->first_dma = dma_addr; |
eca18b23 | 452 | iod->npages = -1; |
69d2b571 | 453 | return false; |
b77954cb | 454 | } |
eca18b23 MW |
455 | list[0] = prp_list; |
456 | iod->first_dma = prp_dma; | |
e025344c SMM |
457 | i = 0; |
458 | for (;;) { | |
1d090624 | 459 | if (i == page_size >> 3) { |
e025344c | 460 | __le64 *old_prp_list = prp_list; |
69d2b571 | 461 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 462 | if (!prp_list) |
69d2b571 | 463 | return false; |
eca18b23 | 464 | list[iod->npages++] = prp_list; |
7523d834 MW |
465 | prp_list[0] = old_prp_list[i - 1]; |
466 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
467 | i = 1; | |
e025344c SMM |
468 | } |
469 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
470 | dma_len -= page_size; |
471 | dma_addr += page_size; | |
472 | length -= page_size; | |
e025344c SMM |
473 | if (length <= 0) |
474 | break; | |
475 | if (dma_len > 0) | |
476 | continue; | |
477 | BUG_ON(dma_len < 0); | |
478 | sg = sg_next(sg); | |
479 | dma_addr = sg_dma_address(sg); | |
480 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
481 | } |
482 | ||
69d2b571 | 483 | return true; |
ff22b54f MW |
484 | } |
485 | ||
f4800d6d | 486 | static int nvme_map_data(struct nvme_dev *dev, struct request *req, |
03b5929e | 487 | unsigned size, struct nvme_command *cmnd) |
d29ec824 | 488 | { |
f4800d6d | 489 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
490 | struct request_queue *q = req->q; |
491 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
492 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
493 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
d29ec824 | 494 | |
ba1ca37e CH |
495 | sg_init_table(iod->sg, req->nr_phys_segments); |
496 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
497 | if (!iod->nents) | |
498 | goto out; | |
d29ec824 | 499 | |
ba1ca37e CH |
500 | ret = BLK_MQ_RQ_QUEUE_BUSY; |
501 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
502 | goto out; | |
d29ec824 | 503 | |
03b5929e | 504 | if (!nvme_setup_prps(dev, req, size)) |
ba1ca37e | 505 | goto out_unmap; |
0e5e4f0e | 506 | |
ba1ca37e CH |
507 | ret = BLK_MQ_RQ_QUEUE_ERROR; |
508 | if (blk_integrity_rq(req)) { | |
509 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
510 | goto out_unmap; | |
0e5e4f0e | 511 | |
bf684057 CH |
512 | sg_init_table(&iod->meta_sg, 1); |
513 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 514 | goto out_unmap; |
0e5e4f0e | 515 | |
ba1ca37e CH |
516 | if (rq_data_dir(req)) |
517 | nvme_dif_remap(req, nvme_dif_prep); | |
0e5e4f0e | 518 | |
bf684057 | 519 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 520 | goto out_unmap; |
d29ec824 | 521 | } |
00df5cb4 | 522 | |
ba1ca37e CH |
523 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
524 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
525 | if (blk_integrity_rq(req)) | |
bf684057 | 526 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e | 527 | return BLK_MQ_RQ_QUEUE_OK; |
00df5cb4 | 528 | |
ba1ca37e CH |
529 | out_unmap: |
530 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
531 | out: | |
532 | return ret; | |
00df5cb4 MW |
533 | } |
534 | ||
f4800d6d | 535 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 536 | { |
f4800d6d | 537 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
538 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
539 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
540 | ||
541 | if (iod->nents) { | |
542 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
543 | if (blk_integrity_rq(req)) { | |
544 | if (!rq_data_dir(req)) | |
545 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 546 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 547 | } |
e19b127f | 548 | } |
e1e5e564 | 549 | |
f4800d6d | 550 | nvme_free_iod(dev, req); |
d4f6c3ab | 551 | } |
b60503ba | 552 | |
d29ec824 CH |
553 | /* |
554 | * NOTE: ns is NULL when called on the admin queue. | |
555 | */ | |
a4aea562 MB |
556 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
557 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 558 | { |
a4aea562 MB |
559 | struct nvme_ns *ns = hctx->queue->queuedata; |
560 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 561 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 562 | struct request *req = bd->rq; |
ba1ca37e | 563 | struct nvme_command cmnd; |
58b45602 | 564 | unsigned map_len; |
ba1ca37e | 565 | int ret = BLK_MQ_RQ_QUEUE_OK; |
edd10d33 | 566 | |
e1e5e564 KB |
567 | /* |
568 | * If formated with metadata, require the block layer provide a buffer | |
569 | * unless this namespace is formated such that the metadata can be | |
570 | * stripped/generated by the controller with PRACT=1. | |
571 | */ | |
d29ec824 | 572 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
573 | if (!(ns->pi_type && ns->ms == 8) && |
574 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 575 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
576 | return BLK_MQ_RQ_QUEUE_OK; |
577 | } | |
578 | } | |
579 | ||
58b45602 ML |
580 | map_len = nvme_map_len(req); |
581 | ret = nvme_init_iod(req, map_len, dev); | |
f4800d6d CH |
582 | if (ret) |
583 | return ret; | |
a4aea562 | 584 | |
8093f7ca | 585 | ret = nvme_setup_cmd(ns, req, &cmnd); |
03b5929e ML |
586 | if (ret) |
587 | goto out; | |
a4aea562 | 588 | |
03b5929e ML |
589 | if (req->nr_phys_segments) |
590 | ret = nvme_map_data(dev, req, map_len, &cmnd); | |
a4aea562 | 591 | |
ba1ca37e CH |
592 | if (ret) |
593 | goto out; | |
a4aea562 | 594 | |
ba1ca37e | 595 | cmnd.common.command_id = req->tag; |
aae239e1 | 596 | blk_mq_start_request(req); |
a4aea562 | 597 | |
ba1ca37e | 598 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 599 | if (unlikely(nvmeq->cq_vector < 0)) { |
69d9a99c KB |
600 | if (ns && !test_bit(NVME_NS_DEAD, &ns->flags)) |
601 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
602 | else | |
603 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
ae1fba20 KB |
604 | spin_unlock_irq(&nvmeq->q_lock); |
605 | goto out; | |
606 | } | |
ba1ca37e | 607 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
608 | nvme_process_cq(nvmeq); |
609 | spin_unlock_irq(&nvmeq->q_lock); | |
610 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 611 | out: |
f4800d6d | 612 | nvme_free_iod(dev, req); |
ba1ca37e | 613 | return ret; |
b60503ba | 614 | } |
e1e5e564 | 615 | |
eee417b0 CH |
616 | static void nvme_complete_rq(struct request *req) |
617 | { | |
f4800d6d CH |
618 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
619 | struct nvme_dev *dev = iod->nvmeq->dev; | |
eee417b0 | 620 | int error = 0; |
e1e5e564 | 621 | |
f4800d6d | 622 | nvme_unmap_data(dev, req); |
e1e5e564 | 623 | |
eee417b0 CH |
624 | if (unlikely(req->errors)) { |
625 | if (nvme_req_needs_retry(req, req->errors)) { | |
626 | nvme_requeue_req(req); | |
627 | return; | |
e1e5e564 | 628 | } |
1974b1ae | 629 | |
eee417b0 CH |
630 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
631 | error = req->errors; | |
632 | else | |
633 | error = nvme_error_status(req->errors); | |
634 | } | |
a4aea562 | 635 | |
f4800d6d | 636 | if (unlikely(iod->aborted)) { |
1b3c47c1 | 637 | dev_warn(dev->ctrl.device, |
eee417b0 CH |
638 | "completing aborted command with status: %04x\n", |
639 | req->errors); | |
640 | } | |
a4aea562 | 641 | |
eee417b0 | 642 | blk_mq_end_request(req, error); |
b60503ba MW |
643 | } |
644 | ||
d783e0bd MR |
645 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
646 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
647 | u16 phase) | |
648 | { | |
649 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
650 | } | |
651 | ||
a0fa9647 | 652 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 653 | { |
82123460 | 654 | u16 head, phase; |
b60503ba | 655 | |
b60503ba | 656 | head = nvmeq->cq_head; |
82123460 | 657 | phase = nvmeq->cq_phase; |
b60503ba | 658 | |
d783e0bd | 659 | while (nvme_cqe_valid(nvmeq, head, phase)) { |
b60503ba | 660 | struct nvme_completion cqe = nvmeq->cqes[head]; |
eee417b0 | 661 | struct request *req; |
adf68f21 | 662 | |
b60503ba MW |
663 | if (++head == nvmeq->q_depth) { |
664 | head = 0; | |
82123460 | 665 | phase = !phase; |
b60503ba | 666 | } |
adf68f21 | 667 | |
a0fa9647 JA |
668 | if (tag && *tag == cqe.command_id) |
669 | *tag = -1; | |
adf68f21 | 670 | |
aae239e1 | 671 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
1b3c47c1 | 672 | dev_warn(nvmeq->dev->ctrl.device, |
aae239e1 CH |
673 | "invalid id %d completed on queue %d\n", |
674 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
675 | continue; | |
676 | } | |
677 | ||
adf68f21 CH |
678 | /* |
679 | * AEN requests are special as they don't time out and can | |
680 | * survive any kind of queue freeze and often don't respond to | |
681 | * aborts. We don't even bother to allocate a struct request | |
682 | * for them but rather special case them here. | |
683 | */ | |
684 | if (unlikely(nvmeq->qid == 0 && | |
685 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
f866fc42 | 686 | nvme_complete_async_event(&nvmeq->dev->ctrl, &cqe); |
adf68f21 CH |
687 | continue; |
688 | } | |
689 | ||
eee417b0 | 690 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
1cb3cce5 CH |
691 | if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special) |
692 | memcpy(req->special, &cqe, sizeof(cqe)); | |
d783e0bd | 693 | blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1); |
eee417b0 | 694 | |
b60503ba MW |
695 | } |
696 | ||
697 | /* If the controller ignores the cq head doorbell and continuously | |
698 | * writes to the queue, it is theoretically possible to wrap around | |
699 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
700 | * requires that 0.1% of your interrupts are handled, so this isn't | |
701 | * a big problem. | |
702 | */ | |
82123460 | 703 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 704 | return; |
b60503ba | 705 | |
604e8c8d KB |
706 | if (likely(nvmeq->cq_vector >= 0)) |
707 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 708 | nvmeq->cq_head = head; |
82123460 | 709 | nvmeq->cq_phase = phase; |
b60503ba | 710 | |
e9539f47 | 711 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
712 | } |
713 | ||
714 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
715 | { | |
716 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
717 | } |
718 | ||
719 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
720 | { |
721 | irqreturn_t result; | |
722 | struct nvme_queue *nvmeq = data; | |
723 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
724 | nvme_process_cq(nvmeq); |
725 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
726 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
727 | spin_unlock(&nvmeq->q_lock); |
728 | return result; | |
729 | } | |
730 | ||
731 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
732 | { | |
733 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
734 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
735 | return IRQ_WAKE_THREAD; | |
736 | return IRQ_NONE; | |
58ffacb5 MW |
737 | } |
738 | ||
a0fa9647 JA |
739 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
740 | { | |
741 | struct nvme_queue *nvmeq = hctx->driver_data; | |
742 | ||
d783e0bd | 743 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
a0fa9647 JA |
744 | spin_lock_irq(&nvmeq->q_lock); |
745 | __nvme_process_cq(nvmeq, &tag); | |
746 | spin_unlock_irq(&nvmeq->q_lock); | |
747 | ||
748 | if (tag == -1) | |
749 | return 1; | |
750 | } | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
f866fc42 | 755 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 756 | { |
f866fc42 | 757 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 758 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 759 | struct nvme_command c; |
b60503ba | 760 | |
a4aea562 MB |
761 | memset(&c, 0, sizeof(c)); |
762 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 763 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 764 | |
9396dec9 | 765 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 766 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 767 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
768 | } |
769 | ||
b60503ba | 770 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 771 | { |
b60503ba MW |
772 | struct nvme_command c; |
773 | ||
774 | memset(&c, 0, sizeof(c)); | |
775 | c.delete_queue.opcode = opcode; | |
776 | c.delete_queue.qid = cpu_to_le16(id); | |
777 | ||
1c63dc66 | 778 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
779 | } |
780 | ||
b60503ba MW |
781 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
782 | struct nvme_queue *nvmeq) | |
783 | { | |
b60503ba MW |
784 | struct nvme_command c; |
785 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
786 | ||
d29ec824 CH |
787 | /* |
788 | * Note: we (ab)use the fact the the prp fields survive if no data | |
789 | * is attached to the request. | |
790 | */ | |
b60503ba MW |
791 | memset(&c, 0, sizeof(c)); |
792 | c.create_cq.opcode = nvme_admin_create_cq; | |
793 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
794 | c.create_cq.cqid = cpu_to_le16(qid); | |
795 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
796 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
797 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
798 | ||
1c63dc66 | 799 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
800 | } |
801 | ||
802 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
803 | struct nvme_queue *nvmeq) | |
804 | { | |
b60503ba MW |
805 | struct nvme_command c; |
806 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
807 | ||
d29ec824 CH |
808 | /* |
809 | * Note: we (ab)use the fact the the prp fields survive if no data | |
810 | * is attached to the request. | |
811 | */ | |
b60503ba MW |
812 | memset(&c, 0, sizeof(c)); |
813 | c.create_sq.opcode = nvme_admin_create_sq; | |
814 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
815 | c.create_sq.sqid = cpu_to_le16(qid); | |
816 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
817 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
818 | c.create_sq.cqid = cpu_to_le16(qid); | |
819 | ||
1c63dc66 | 820 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
821 | } |
822 | ||
823 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
824 | { | |
825 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
826 | } | |
827 | ||
828 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
829 | { | |
830 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
831 | } | |
832 | ||
e7a2a87d | 833 | static void abort_endio(struct request *req, int error) |
bc5fc7e4 | 834 | { |
f4800d6d CH |
835 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
836 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e7a2a87d | 837 | u16 status = req->errors; |
e44ac588 | 838 | |
1cb3cce5 | 839 | dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status); |
e7a2a87d | 840 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 841 | blk_mq_free_request(req); |
bc5fc7e4 MW |
842 | } |
843 | ||
31c7c7d2 | 844 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 845 | { |
f4800d6d CH |
846 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
847 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 848 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 849 | struct request *abort_req; |
a4aea562 | 850 | struct nvme_command cmd; |
c30341dc | 851 | |
31c7c7d2 | 852 | /* |
fd634f41 CH |
853 | * Shutdown immediately if controller times out while starting. The |
854 | * reset work will see the pci device disabled when it gets the forced | |
855 | * cancellation error. All outstanding requests are completed on | |
856 | * shutdown, so we return BLK_EH_HANDLED. | |
857 | */ | |
bb8d261e | 858 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 859 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
860 | "I/O %d QID %d timeout, disable controller\n", |
861 | req->tag, nvmeq->qid); | |
a5cdb68c | 862 | nvme_dev_disable(dev, false); |
fd634f41 CH |
863 | req->errors = NVME_SC_CANCELLED; |
864 | return BLK_EH_HANDLED; | |
c30341dc KB |
865 | } |
866 | ||
fd634f41 CH |
867 | /* |
868 | * Shutdown the controller immediately and schedule a reset if the | |
869 | * command was already aborted once before and still hasn't been | |
870 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 871 | */ |
f4800d6d | 872 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 873 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
874 | "I/O %d QID %d timeout, reset controller\n", |
875 | req->tag, nvmeq->qid); | |
a5cdb68c | 876 | nvme_dev_disable(dev, false); |
e1569a16 | 877 | queue_work(nvme_workq, &dev->reset_work); |
c30341dc | 878 | |
e1569a16 KB |
879 | /* |
880 | * Mark the request as handled, since the inline shutdown | |
881 | * forces all outstanding requests to complete. | |
882 | */ | |
883 | req->errors = NVME_SC_CANCELLED; | |
884 | return BLK_EH_HANDLED; | |
c30341dc | 885 | } |
c30341dc | 886 | |
f4800d6d | 887 | iod->aborted = 1; |
c30341dc | 888 | |
e7a2a87d | 889 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 890 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 891 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 892 | } |
a4aea562 | 893 | |
c30341dc KB |
894 | memset(&cmd, 0, sizeof(cmd)); |
895 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 896 | cmd.abort.cid = req->tag; |
c30341dc | 897 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 898 | |
1b3c47c1 SG |
899 | dev_warn(nvmeq->dev->ctrl.device, |
900 | "I/O %d QID %d timeout, aborting\n", | |
901 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
902 | |
903 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
904 | BLK_MQ_REQ_NOWAIT); | |
905 | if (IS_ERR(abort_req)) { | |
906 | atomic_inc(&dev->ctrl.abort_limit); | |
907 | return BLK_EH_RESET_TIMER; | |
908 | } | |
909 | ||
910 | abort_req->timeout = ADMIN_TIMEOUT; | |
911 | abort_req->end_io_data = NULL; | |
912 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 913 | |
31c7c7d2 CH |
914 | /* |
915 | * The aborted req will be completed on receiving the abort req. | |
916 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
917 | * as the device then is in a faulty state. | |
918 | */ | |
919 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
920 | } |
921 | ||
82b4552b | 922 | static void nvme_cancel_io(struct request *req, void *data, bool reserved) |
a09115b2 | 923 | { |
aae239e1 | 924 | int status; |
cef6a948 KB |
925 | |
926 | if (!blk_mq_request_started(req)) | |
927 | return; | |
a09115b2 | 928 | |
7e197930 JA |
929 | dev_dbg_ratelimited(((struct nvme_dev *) data)->ctrl.device, |
930 | "Cancelling I/O %d", req->tag); | |
a4aea562 | 931 | |
1d49c38c | 932 | status = NVME_SC_ABORT_REQ; |
cef6a948 | 933 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
934 | status |= NVME_SC_DNR; |
935 | blk_mq_complete_request(req, status); | |
a4aea562 | 936 | } |
22404274 | 937 | |
a4aea562 MB |
938 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
939 | { | |
9e866774 MW |
940 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
941 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
942 | if (nvmeq->sq_cmds) |
943 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
944 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
945 | kfree(nvmeq); | |
946 | } | |
947 | ||
a1a5ef99 | 948 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
949 | { |
950 | int i; | |
951 | ||
a1a5ef99 | 952 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 953 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 954 | dev->queue_count--; |
a4aea562 | 955 | dev->queues[i] = NULL; |
f435c282 | 956 | nvme_free_queue(nvmeq); |
121c7ad4 | 957 | } |
22404274 KB |
958 | } |
959 | ||
4d115420 KB |
960 | /** |
961 | * nvme_suspend_queue - put queue into suspended state | |
962 | * @nvmeq - queue to suspend | |
4d115420 KB |
963 | */ |
964 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 965 | { |
2b25d981 | 966 | int vector; |
b60503ba | 967 | |
a09115b2 | 968 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
969 | if (nvmeq->cq_vector == -1) { |
970 | spin_unlock_irq(&nvmeq->q_lock); | |
971 | return 1; | |
972 | } | |
973 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 974 | nvmeq->dev->online_queues--; |
2b25d981 | 975 | nvmeq->cq_vector = -1; |
a09115b2 MW |
976 | spin_unlock_irq(&nvmeq->q_lock); |
977 | ||
1c63dc66 | 978 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
25646264 | 979 | blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 980 | |
aba2080f MW |
981 | irq_set_affinity_hint(vector, NULL); |
982 | free_irq(vector, nvmeq); | |
b60503ba | 983 | |
4d115420 KB |
984 | return 0; |
985 | } | |
b60503ba | 986 | |
a5cdb68c | 987 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 988 | { |
a5cdb68c | 989 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
990 | |
991 | if (!nvmeq) | |
992 | return; | |
993 | if (nvme_suspend_queue(nvmeq)) | |
994 | return; | |
995 | ||
a5cdb68c KB |
996 | if (shutdown) |
997 | nvme_shutdown_ctrl(&dev->ctrl); | |
998 | else | |
999 | nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( | |
1000 | dev->bar + NVME_REG_CAP)); | |
07836e65 KB |
1001 | |
1002 | spin_lock_irq(&nvmeq->q_lock); | |
1003 | nvme_process_cq(nvmeq); | |
1004 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1005 | } |
1006 | ||
8ffaadf7 JD |
1007 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1008 | int entry_size) | |
1009 | { | |
1010 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1011 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1012 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1013 | |
1014 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1015 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1016 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1017 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1018 | |
1019 | /* | |
1020 | * Ensure the reduced q_depth is above some threshold where it | |
1021 | * would be better to map queues in system memory with the | |
1022 | * original depth | |
1023 | */ | |
1024 | if (q_depth < 64) | |
1025 | return -ENOMEM; | |
1026 | } | |
1027 | ||
1028 | return q_depth; | |
1029 | } | |
1030 | ||
1031 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1032 | int qid, int depth) | |
1033 | { | |
1034 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1035 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1036 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1037 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1038 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1039 | } else { | |
1040 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1041 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1042 | if (!nvmeq->sq_cmds) | |
1043 | return -ENOMEM; | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
b60503ba | 1049 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1050 | int depth) |
b60503ba | 1051 | { |
a4aea562 | 1052 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1053 | if (!nvmeq) |
1054 | return NULL; | |
1055 | ||
e75ec752 | 1056 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1057 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1058 | if (!nvmeq->cqes) |
1059 | goto free_nvmeq; | |
b60503ba | 1060 | |
8ffaadf7 | 1061 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1062 | goto free_cqdma; |
1063 | ||
e75ec752 | 1064 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1065 | nvmeq->dev = dev; |
3193f07b | 1066 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1067 | dev->ctrl.instance, qid); |
b60503ba MW |
1068 | spin_lock_init(&nvmeq->q_lock); |
1069 | nvmeq->cq_head = 0; | |
82123460 | 1070 | nvmeq->cq_phase = 1; |
b80d5ccc | 1071 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1072 | nvmeq->q_depth = depth; |
c30341dc | 1073 | nvmeq->qid = qid; |
758dd7fd | 1074 | nvmeq->cq_vector = -1; |
a4aea562 | 1075 | dev->queues[qid] = nvmeq; |
36a7e993 JD |
1076 | dev->queue_count++; |
1077 | ||
b60503ba MW |
1078 | return nvmeq; |
1079 | ||
1080 | free_cqdma: | |
e75ec752 | 1081 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1082 | nvmeq->cq_dma_addr); |
1083 | free_nvmeq: | |
1084 | kfree(nvmeq); | |
1085 | return NULL; | |
1086 | } | |
1087 | ||
3001082c MW |
1088 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1089 | const char *name) | |
1090 | { | |
58ffacb5 MW |
1091 | if (use_threaded_interrupts) |
1092 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1093 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1094 | name, nvmeq); |
3001082c | 1095 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1096 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1097 | } |
1098 | ||
22404274 | 1099 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1100 | { |
22404274 | 1101 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1102 | |
7be50e93 | 1103 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1104 | nvmeq->sq_tail = 0; |
1105 | nvmeq->cq_head = 0; | |
1106 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1107 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1108 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1109 | dev->online_queues++; |
7be50e93 | 1110 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1111 | } |
1112 | ||
1113 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1114 | { | |
1115 | struct nvme_dev *dev = nvmeq->dev; | |
1116 | int result; | |
3f85d50b | 1117 | |
2b25d981 | 1118 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1119 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1120 | if (result < 0) | |
22404274 | 1121 | return result; |
b60503ba MW |
1122 | |
1123 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1124 | if (result < 0) | |
1125 | goto release_cq; | |
1126 | ||
3193f07b | 1127 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1128 | if (result < 0) |
1129 | goto release_sq; | |
1130 | ||
22404274 | 1131 | nvme_init_queue(nvmeq, qid); |
22404274 | 1132 | return result; |
b60503ba MW |
1133 | |
1134 | release_sq: | |
1135 | adapter_delete_sq(dev, qid); | |
1136 | release_cq: | |
1137 | adapter_delete_cq(dev, qid); | |
22404274 | 1138 | return result; |
b60503ba MW |
1139 | } |
1140 | ||
a4aea562 | 1141 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1142 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1143 | .complete = nvme_complete_rq, |
a4aea562 MB |
1144 | .map_queue = blk_mq_map_queue, |
1145 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1146 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1147 | .init_request = nvme_admin_init_request, |
1148 | .timeout = nvme_timeout, | |
1149 | }; | |
1150 | ||
1151 | static struct blk_mq_ops nvme_mq_ops = { | |
1152 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1153 | .complete = nvme_complete_rq, |
a4aea562 MB |
1154 | .map_queue = blk_mq_map_queue, |
1155 | .init_hctx = nvme_init_hctx, | |
1156 | .init_request = nvme_init_request, | |
1157 | .timeout = nvme_timeout, | |
a0fa9647 | 1158 | .poll = nvme_poll, |
a4aea562 MB |
1159 | }; |
1160 | ||
ea191d2f KB |
1161 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1162 | { | |
1c63dc66 | 1163 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1164 | /* |
1165 | * If the controller was reset during removal, it's possible | |
1166 | * user requests may be waiting on a stopped queue. Start the | |
1167 | * queue to flush these to completion. | |
1168 | */ | |
1169 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); | |
1c63dc66 | 1170 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1171 | blk_mq_free_tag_set(&dev->admin_tagset); |
1172 | } | |
1173 | } | |
1174 | ||
a4aea562 MB |
1175 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1176 | { | |
1c63dc66 | 1177 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1178 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1179 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1180 | |
1181 | /* | |
1182 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1183 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1184 | */ | |
1185 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1186 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1187 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1188 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1189 | dev->admin_tagset.driver_data = dev; |
1190 | ||
1191 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1192 | return -ENOMEM; | |
1193 | ||
1c63dc66 CH |
1194 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1195 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1196 | blk_mq_free_tag_set(&dev->admin_tagset); |
1197 | return -ENOMEM; | |
1198 | } | |
1c63dc66 | 1199 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1200 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1201 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1202 | return -ENODEV; |
1203 | } | |
0fb59cbc | 1204 | } else |
25646264 | 1205 | blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); |
a4aea562 MB |
1206 | |
1207 | return 0; | |
1208 | } | |
1209 | ||
8d85fce7 | 1210 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1211 | { |
ba47e386 | 1212 | int result; |
b60503ba | 1213 | u32 aqa; |
7a67cbea | 1214 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1215 | struct nvme_queue *nvmeq; |
1216 | ||
7a67cbea | 1217 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1218 | NVME_CAP_NSSRC(cap) : 0; |
1219 | ||
7a67cbea CH |
1220 | if (dev->subsystem && |
1221 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1222 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1223 | |
5fd4ce1b | 1224 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1225 | if (result < 0) |
1226 | return result; | |
b60503ba | 1227 | |
a4aea562 | 1228 | nvmeq = dev->queues[0]; |
cd638946 | 1229 | if (!nvmeq) { |
2b25d981 | 1230 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1231 | if (!nvmeq) |
1232 | return -ENOMEM; | |
cd638946 | 1233 | } |
b60503ba MW |
1234 | |
1235 | aqa = nvmeq->q_depth - 1; | |
1236 | aqa |= aqa << 16; | |
1237 | ||
7a67cbea CH |
1238 | writel(aqa, dev->bar + NVME_REG_AQA); |
1239 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1240 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1241 | |
5fd4ce1b | 1242 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1243 | if (result) |
a4aea562 MB |
1244 | goto free_nvmeq; |
1245 | ||
2b25d981 | 1246 | nvmeq->cq_vector = 0; |
3193f07b | 1247 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1248 | if (result) { |
1249 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1250 | goto free_nvmeq; |
758dd7fd | 1251 | } |
025c557a | 1252 | |
b60503ba | 1253 | return result; |
a4aea562 | 1254 | |
a4aea562 MB |
1255 | free_nvmeq: |
1256 | nvme_free_queues(dev, 0); | |
1257 | return result; | |
b60503ba MW |
1258 | } |
1259 | ||
c875a709 GP |
1260 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1261 | { | |
1262 | ||
1263 | /* If true, indicates loss of adapter communication, possibly by a | |
1264 | * NVMe Subsystem reset. | |
1265 | */ | |
1266 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1267 | ||
1268 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1269 | if (work_busy(&dev->reset_work)) | |
1270 | return false; | |
1271 | ||
1272 | /* We shouldn't reset unless the controller is on fatal error state | |
1273 | * _or_ if we lost the communication with it. | |
1274 | */ | |
1275 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1276 | return false; | |
1277 | ||
1278 | /* If PCI error recovery process is happening, we cannot reset or | |
1279 | * the recovery mechanism will surely fail. | |
1280 | */ | |
1281 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1282 | return false; | |
1283 | ||
1284 | return true; | |
1285 | } | |
1286 | ||
2d55cd5f | 1287 | static void nvme_watchdog_timer(unsigned long data) |
1fa6aead | 1288 | { |
2d55cd5f CH |
1289 | struct nvme_dev *dev = (struct nvme_dev *)data; |
1290 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
1fa6aead | 1291 | |
c875a709 GP |
1292 | /* Skip controllers under certain specific conditions. */ |
1293 | if (nvme_should_reset(dev, csts)) { | |
1294 | if (queue_work(nvme_workq, &dev->reset_work)) | |
2d55cd5f CH |
1295 | dev_warn(dev->dev, |
1296 | "Failed status: 0x%x, reset controller.\n", | |
1297 | csts); | |
2d55cd5f | 1298 | return; |
1fa6aead | 1299 | } |
2d55cd5f CH |
1300 | |
1301 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); | |
1fa6aead MW |
1302 | } |
1303 | ||
749941f2 | 1304 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1305 | { |
949928c1 | 1306 | unsigned i, max; |
749941f2 | 1307 | int ret = 0; |
42f61420 | 1308 | |
749941f2 CH |
1309 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1310 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1311 | ret = -ENOMEM; | |
42f61420 | 1312 | break; |
749941f2 CH |
1313 | } |
1314 | } | |
42f61420 | 1315 | |
949928c1 KB |
1316 | max = min(dev->max_qid, dev->queue_count - 1); |
1317 | for (i = dev->online_queues; i <= max; i++) { | |
749941f2 CH |
1318 | ret = nvme_create_queue(dev->queues[i], i); |
1319 | if (ret) { | |
2659e57b | 1320 | nvme_free_queues(dev, i); |
42f61420 | 1321 | break; |
2659e57b | 1322 | } |
27e8166c | 1323 | } |
749941f2 CH |
1324 | |
1325 | /* | |
1326 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1327 | * than the desired aount of queues, and even a controller without | |
1328 | * I/O queues an still be used to issue admin commands. This might | |
1329 | * be useful to upgrade a buggy firmware for example. | |
1330 | */ | |
1331 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1332 | } |
1333 | ||
8ffaadf7 JD |
1334 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1335 | { | |
1336 | u64 szu, size, offset; | |
1337 | u32 cmbloc; | |
1338 | resource_size_t bar_size; | |
1339 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1340 | void __iomem *cmb; | |
1341 | dma_addr_t dma_addr; | |
1342 | ||
1343 | if (!use_cmb_sqes) | |
1344 | return NULL; | |
1345 | ||
7a67cbea | 1346 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1347 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1348 | return NULL; | |
1349 | ||
7a67cbea | 1350 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1351 | |
1352 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1353 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1354 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1355 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1356 | ||
1357 | if (offset > bar_size) | |
1358 | return NULL; | |
1359 | ||
1360 | /* | |
1361 | * Controllers may support a CMB size larger than their BAR, | |
1362 | * for example, due to being behind a bridge. Reduce the CMB to | |
1363 | * the reported size of the BAR | |
1364 | */ | |
1365 | if (size > bar_size - offset) | |
1366 | size = bar_size - offset; | |
1367 | ||
1368 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1369 | cmb = ioremap_wc(dma_addr, size); | |
1370 | if (!cmb) | |
1371 | return NULL; | |
1372 | ||
1373 | dev->cmb_dma_addr = dma_addr; | |
1374 | dev->cmb_size = size; | |
1375 | return cmb; | |
1376 | } | |
1377 | ||
1378 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1379 | { | |
1380 | if (dev->cmb) { | |
1381 | iounmap(dev->cmb); | |
1382 | dev->cmb = NULL; | |
1383 | } | |
1384 | } | |
1385 | ||
9d713c2b KB |
1386 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1387 | { | |
b80d5ccc | 1388 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1389 | } |
1390 | ||
8d85fce7 | 1391 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1392 | { |
a4aea562 | 1393 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1394 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1395 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1396 | |
2800b8e7 | 1397 | nr_io_queues = num_online_cpus(); |
9a0be7ab CH |
1398 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1399 | if (result < 0) | |
1b23484b | 1400 | return result; |
9a0be7ab CH |
1401 | |
1402 | /* | |
1403 | * Degraded controllers might return an error when setting the queue | |
1404 | * count. We still want to be able to bring them online and offer | |
1405 | * access to the admin queue, as that might be only way to fix them up. | |
1406 | */ | |
1407 | if (result > 0) { | |
1b3c47c1 SG |
1408 | dev_err(dev->ctrl.device, |
1409 | "Could not set queue count (%d)\n", result); | |
a5229050 | 1410 | return 0; |
9a0be7ab | 1411 | } |
b60503ba | 1412 | |
8ffaadf7 JD |
1413 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1414 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1415 | sizeof(struct nvme_command)); | |
1416 | if (result > 0) | |
1417 | dev->q_depth = result; | |
1418 | else | |
1419 | nvme_release_cmb(dev); | |
1420 | } | |
1421 | ||
9d713c2b KB |
1422 | size = db_bar_size(dev, nr_io_queues); |
1423 | if (size > 8192) { | |
f1938f6e | 1424 | iounmap(dev->bar); |
9d713c2b KB |
1425 | do { |
1426 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1427 | if (dev->bar) | |
1428 | break; | |
1429 | if (!--nr_io_queues) | |
1430 | return -ENOMEM; | |
1431 | size = db_bar_size(dev, nr_io_queues); | |
1432 | } while (1); | |
7a67cbea | 1433 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1434 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1435 | } |
1436 | ||
9d713c2b | 1437 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1438 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1439 | |
e32efbfc JA |
1440 | /* |
1441 | * If we enable msix early due to not intx, disable it again before | |
1442 | * setting up the full range we need. | |
1443 | */ | |
a5229050 KB |
1444 | if (pdev->msi_enabled) |
1445 | pci_disable_msi(pdev); | |
1446 | else if (pdev->msix_enabled) | |
e32efbfc JA |
1447 | pci_disable_msix(pdev); |
1448 | ||
be577fab | 1449 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1450 | dev->entry[i].entry = i; |
be577fab AG |
1451 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1452 | if (vecs < 0) { | |
1453 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1454 | if (vecs < 0) { | |
1455 | vecs = 1; | |
1456 | } else { | |
1457 | for (i = 0; i < vecs; i++) | |
1458 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1459 | } |
1460 | } | |
1461 | ||
063a8096 MW |
1462 | /* |
1463 | * Should investigate if there's a performance win from allocating | |
1464 | * more queues than interrupt vectors; it might allow the submission | |
1465 | * path to scale better, even if the receive path is limited by the | |
1466 | * number of interrupts. | |
1467 | */ | |
1468 | nr_io_queues = vecs; | |
42f61420 | 1469 | dev->max_qid = nr_io_queues; |
063a8096 | 1470 | |
3193f07b | 1471 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1472 | if (result) { |
1473 | adminq->cq_vector = -1; | |
22404274 | 1474 | goto free_queues; |
758dd7fd | 1475 | } |
749941f2 | 1476 | return nvme_create_io_queues(dev); |
b60503ba | 1477 | |
22404274 | 1478 | free_queues: |
a1a5ef99 | 1479 | nvme_free_queues(dev, 1); |
22404274 | 1480 | return result; |
b60503ba MW |
1481 | } |
1482 | ||
5955be21 | 1483 | static void nvme_pci_post_scan(struct nvme_ctrl *ctrl) |
a5768aa8 | 1484 | { |
5955be21 | 1485 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
bda4e0fb KB |
1486 | struct nvme_queue *nvmeq; |
1487 | int i; | |
a5768aa8 | 1488 | |
bda4e0fb KB |
1489 | for (i = 0; i < dev->online_queues; i++) { |
1490 | nvmeq = dev->queues[i]; | |
a5768aa8 | 1491 | |
bda4e0fb KB |
1492 | if (!nvmeq->tags || !(*nvmeq->tags)) |
1493 | continue; | |
a5768aa8 | 1494 | |
bda4e0fb KB |
1495 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, |
1496 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
a5768aa8 | 1497 | } |
a5768aa8 KB |
1498 | } |
1499 | ||
db3cbfff | 1500 | static void nvme_del_queue_end(struct request *req, int error) |
a5768aa8 | 1501 | { |
db3cbfff | 1502 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1503 | |
db3cbfff KB |
1504 | blk_mq_free_request(req); |
1505 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1506 | } |
1507 | ||
db3cbfff | 1508 | static void nvme_del_cq_end(struct request *req, int error) |
a5768aa8 | 1509 | { |
db3cbfff | 1510 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1511 | |
db3cbfff KB |
1512 | if (!error) { |
1513 | unsigned long flags; | |
1514 | ||
2e39e0f6 ML |
1515 | /* |
1516 | * We might be called with the AQ q_lock held | |
1517 | * and the I/O queue q_lock should always | |
1518 | * nest inside the AQ one. | |
1519 | */ | |
1520 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1521 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1522 | nvme_process_cq(nvmeq); |
1523 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1524 | } |
db3cbfff KB |
1525 | |
1526 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1527 | } |
1528 | ||
db3cbfff | 1529 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1530 | { |
db3cbfff KB |
1531 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1532 | struct request *req; | |
1533 | struct nvme_command cmd; | |
bda4e0fb | 1534 | |
db3cbfff KB |
1535 | memset(&cmd, 0, sizeof(cmd)); |
1536 | cmd.delete_queue.opcode = opcode; | |
1537 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1538 | |
db3cbfff KB |
1539 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); |
1540 | if (IS_ERR(req)) | |
1541 | return PTR_ERR(req); | |
bda4e0fb | 1542 | |
db3cbfff KB |
1543 | req->timeout = ADMIN_TIMEOUT; |
1544 | req->end_io_data = nvmeq; | |
1545 | ||
1546 | blk_execute_rq_nowait(q, NULL, req, false, | |
1547 | opcode == nvme_admin_delete_cq ? | |
1548 | nvme_del_cq_end : nvme_del_queue_end); | |
1549 | return 0; | |
bda4e0fb KB |
1550 | } |
1551 | ||
db3cbfff | 1552 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
a5768aa8 | 1553 | { |
014a0d60 | 1554 | int pass, queues = dev->online_queues - 1; |
db3cbfff KB |
1555 | unsigned long timeout; |
1556 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1557 | |
db3cbfff | 1558 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1559 | int sent = 0, i = queues; |
db3cbfff KB |
1560 | |
1561 | reinit_completion(&dev->ioq_wait); | |
1562 | retry: | |
1563 | timeout = ADMIN_TIMEOUT; | |
1564 | for (; i > 0; i--) { | |
1565 | struct nvme_queue *nvmeq = dev->queues[i]; | |
1566 | ||
1567 | if (!pass) | |
1568 | nvme_suspend_queue(nvmeq); | |
1569 | if (nvme_delete_queue(nvmeq, opcode)) | |
1570 | break; | |
1571 | ++sent; | |
1572 | } | |
1573 | while (sent--) { | |
1574 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1575 | if (timeout == 0) | |
1576 | return; | |
1577 | if (i) | |
1578 | goto retry; | |
1579 | } | |
1580 | opcode = nvme_admin_delete_cq; | |
1581 | } | |
a5768aa8 KB |
1582 | } |
1583 | ||
422ef0c7 MW |
1584 | /* |
1585 | * Return: error value if an error occurred setting up the queues or calling | |
1586 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1587 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1588 | * failures should be reported. | |
1589 | */ | |
8d85fce7 | 1590 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1591 | { |
5bae7f73 | 1592 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1593 | dev->tagset.ops = &nvme_mq_ops; |
1594 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1595 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1596 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1597 | dev->tagset.queue_depth = | |
a4aea562 | 1598 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1599 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1600 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1601 | dev->tagset.driver_data = dev; | |
b60503ba | 1602 | |
ffe7704d KB |
1603 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1604 | return 0; | |
5bae7f73 | 1605 | dev->ctrl.tagset = &dev->tagset; |
949928c1 KB |
1606 | } else { |
1607 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1608 | ||
1609 | /* Free previously allocated queues that are no longer usable */ | |
1610 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1611 | } |
949928c1 | 1612 | |
e1e5e564 | 1613 | return 0; |
b60503ba MW |
1614 | } |
1615 | ||
b00a726a | 1616 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1617 | { |
42f61420 | 1618 | u64 cap; |
b00a726a | 1619 | int result = -ENOMEM; |
e75ec752 | 1620 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1621 | |
1622 | if (pci_enable_device_mem(pdev)) | |
1623 | return result; | |
1624 | ||
0877cb0d | 1625 | pci_set_master(pdev); |
0877cb0d | 1626 | |
e75ec752 CH |
1627 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1628 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1629 | goto disable; |
0877cb0d | 1630 | |
7a67cbea | 1631 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1632 | result = -ENODEV; |
b00a726a | 1633 | goto disable; |
0e53d180 | 1634 | } |
e32efbfc JA |
1635 | |
1636 | /* | |
a5229050 KB |
1637 | * Some devices and/or platforms don't advertise or work with INTx |
1638 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1639 | * adjust this later. | |
e32efbfc | 1640 | */ |
a5229050 KB |
1641 | if (pci_enable_msix(pdev, dev->entry, 1)) { |
1642 | pci_enable_msi(pdev); | |
1643 | dev->entry[0].vector = pdev->irq; | |
1644 | } | |
1645 | ||
1646 | if (!dev->entry[0].vector) { | |
1647 | result = -ENODEV; | |
1648 | goto disable; | |
e32efbfc JA |
1649 | } |
1650 | ||
7a67cbea CH |
1651 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1652 | ||
42f61420 KB |
1653 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1654 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea | 1655 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1656 | |
1657 | /* | |
1658 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1659 | * some MacBook7,1 to avoid controller resets and data loss. | |
1660 | */ | |
1661 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1662 | dev->q_depth = 2; | |
1663 | dev_warn(dev->dev, "detected Apple NVMe controller, set " | |
1664 | "queue depth=%u to work around controller resets\n", | |
1665 | dev->q_depth); | |
1666 | } | |
1667 | ||
7a67cbea | 1668 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) |
8ffaadf7 | 1669 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d | 1670 | |
a0a3408e KB |
1671 | pci_enable_pcie_error_reporting(pdev); |
1672 | pci_save_state(pdev); | |
0877cb0d KB |
1673 | return 0; |
1674 | ||
1675 | disable: | |
0877cb0d KB |
1676 | pci_disable_device(pdev); |
1677 | return result; | |
1678 | } | |
1679 | ||
1680 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
1681 | { |
1682 | if (dev->bar) | |
1683 | iounmap(dev->bar); | |
1684 | pci_release_regions(to_pci_dev(dev->dev)); | |
1685 | } | |
1686 | ||
1687 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 1688 | { |
e75ec752 CH |
1689 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1690 | ||
1691 | if (pdev->msi_enabled) | |
1692 | pci_disable_msi(pdev); | |
1693 | else if (pdev->msix_enabled) | |
1694 | pci_disable_msix(pdev); | |
0877cb0d | 1695 | |
a0a3408e KB |
1696 | if (pci_is_enabled(pdev)) { |
1697 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 1698 | pci_disable_device(pdev); |
4d115420 | 1699 | } |
4d115420 KB |
1700 | } |
1701 | ||
a5cdb68c | 1702 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 1703 | { |
22404274 | 1704 | int i; |
7c1b2450 | 1705 | u32 csts = -1; |
22404274 | 1706 | |
2d55cd5f | 1707 | del_timer_sync(&dev->watchdog_timer); |
1fa6aead | 1708 | |
77bf25ea | 1709 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 1710 | if (pci_is_enabled(to_pci_dev(dev->dev))) { |
25646264 | 1711 | nvme_stop_queues(&dev->ctrl); |
7a67cbea | 1712 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1713 | } |
7c1b2450 | 1714 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1715 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1716 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1717 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1718 | } |
1719 | } else { | |
1720 | nvme_disable_io_queues(dev); | |
a5cdb68c | 1721 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 1722 | } |
b00a726a | 1723 | nvme_pci_disable(dev); |
07836e65 | 1724 | |
82b4552b SG |
1725 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_io, dev); |
1726 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_io, dev); | |
77bf25ea | 1727 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
1728 | } |
1729 | ||
091b6092 MW |
1730 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1731 | { | |
e75ec752 | 1732 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1733 | PAGE_SIZE, PAGE_SIZE, 0); |
1734 | if (!dev->prp_page_pool) | |
1735 | return -ENOMEM; | |
1736 | ||
99802a7a | 1737 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 1738 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
1739 | 256, 256, 0); |
1740 | if (!dev->prp_small_pool) { | |
1741 | dma_pool_destroy(dev->prp_page_pool); | |
1742 | return -ENOMEM; | |
1743 | } | |
091b6092 MW |
1744 | return 0; |
1745 | } | |
1746 | ||
1747 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1748 | { | |
1749 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1750 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1751 | } |
1752 | ||
1673f1f0 | 1753 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 1754 | { |
1673f1f0 | 1755 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 1756 | |
e75ec752 | 1757 | put_device(dev->dev); |
4af0e21c KB |
1758 | if (dev->tagset.tags) |
1759 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
1760 | if (dev->ctrl.admin_q) |
1761 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
1762 | kfree(dev->queues); |
1763 | kfree(dev->entry); | |
1764 | kfree(dev); | |
1765 | } | |
1766 | ||
f58944e2 KB |
1767 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
1768 | { | |
237045fc | 1769 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
1770 | |
1771 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 1772 | nvme_dev_disable(dev, false); |
f58944e2 KB |
1773 | if (!schedule_work(&dev->remove_work)) |
1774 | nvme_put_ctrl(&dev->ctrl); | |
1775 | } | |
1776 | ||
fd634f41 | 1777 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 1778 | { |
fd634f41 | 1779 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
f58944e2 | 1780 | int result = -ENODEV; |
5e82e952 | 1781 | |
bb8d261e | 1782 | if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) |
fd634f41 | 1783 | goto out; |
5e82e952 | 1784 | |
fd634f41 CH |
1785 | /* |
1786 | * If we're called to reset a live controller first shut it down before | |
1787 | * moving on. | |
1788 | */ | |
b00a726a | 1789 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 1790 | nvme_dev_disable(dev, false); |
5e82e952 | 1791 | |
bb8d261e | 1792 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) |
9bf2b972 KB |
1793 | goto out; |
1794 | ||
b00a726a | 1795 | result = nvme_pci_enable(dev); |
f0b50732 | 1796 | if (result) |
3cf519b5 | 1797 | goto out; |
f0b50732 KB |
1798 | |
1799 | result = nvme_configure_admin_queue(dev); | |
1800 | if (result) | |
f58944e2 | 1801 | goto out; |
f0b50732 | 1802 | |
a4aea562 | 1803 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
1804 | result = nvme_alloc_admin_tags(dev); |
1805 | if (result) | |
f58944e2 | 1806 | goto out; |
b9afca3e | 1807 | |
ce4541f4 CH |
1808 | result = nvme_init_identify(&dev->ctrl); |
1809 | if (result) | |
f58944e2 | 1810 | goto out; |
ce4541f4 | 1811 | |
f0b50732 | 1812 | result = nvme_setup_io_queues(dev); |
badc34d4 | 1813 | if (result) |
f58944e2 | 1814 | goto out; |
f0b50732 | 1815 | |
21f033f7 KB |
1816 | /* |
1817 | * A controller that can not execute IO typically requires user | |
1818 | * intervention to correct. For such degraded controllers, the driver | |
1819 | * should not submit commands the user did not request, so skip | |
1820 | * registering for asynchronous event notification on this condition. | |
1821 | */ | |
f866fc42 CH |
1822 | if (dev->online_queues > 1) |
1823 | nvme_queue_async_events(&dev->ctrl); | |
3cf519b5 | 1824 | |
2d55cd5f | 1825 | mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); |
3cf519b5 | 1826 | |
2659e57b CH |
1827 | /* |
1828 | * Keep the controller around but remove all namespaces if we don't have | |
1829 | * any working I/O queue. | |
1830 | */ | |
3cf519b5 | 1831 | if (dev->online_queues < 2) { |
1b3c47c1 | 1832 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 1833 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 1834 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 1835 | } else { |
25646264 | 1836 | nvme_start_queues(&dev->ctrl); |
3cf519b5 CH |
1837 | nvme_dev_add(dev); |
1838 | } | |
1839 | ||
bb8d261e CH |
1840 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
1841 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
1842 | goto out; | |
1843 | } | |
92911a55 CH |
1844 | |
1845 | if (dev->online_queues > 1) | |
5955be21 | 1846 | nvme_queue_scan(&dev->ctrl); |
3cf519b5 | 1847 | return; |
f0b50732 | 1848 | |
3cf519b5 | 1849 | out: |
f58944e2 | 1850 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
1851 | } |
1852 | ||
5c8809e6 | 1853 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 1854 | { |
5c8809e6 | 1855 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 1856 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 1857 | |
69d9a99c | 1858 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 1859 | if (pci_get_drvdata(pdev)) |
921920ab | 1860 | device_release_driver(&pdev->dev); |
1673f1f0 | 1861 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
1862 | } |
1863 | ||
4cc06521 | 1864 | static int nvme_reset(struct nvme_dev *dev) |
9a6b9458 | 1865 | { |
1c63dc66 | 1866 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 | 1867 | return -ENODEV; |
ffe7704d | 1868 | |
846cc05f CH |
1869 | if (!queue_work(nvme_workq, &dev->reset_work)) |
1870 | return -EBUSY; | |
ffe7704d | 1871 | |
846cc05f | 1872 | flush_work(&dev->reset_work); |
846cc05f | 1873 | return 0; |
9a6b9458 KB |
1874 | } |
1875 | ||
1c63dc66 | 1876 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 1877 | { |
1c63dc66 | 1878 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 1879 | return 0; |
9ca97374 TH |
1880 | } |
1881 | ||
5fd4ce1b | 1882 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 1883 | { |
5fd4ce1b CH |
1884 | writel(val, to_nvme_dev(ctrl)->bar + off); |
1885 | return 0; | |
1886 | } | |
4cc06521 | 1887 | |
7fd8930f CH |
1888 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
1889 | { | |
1890 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
1891 | return 0; | |
4cc06521 KB |
1892 | } |
1893 | ||
f3ca80fc CH |
1894 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
1895 | { | |
1896 | return nvme_reset(to_nvme_dev(ctrl)); | |
4cc06521 | 1897 | } |
f3ca80fc | 1898 | |
1c63dc66 | 1899 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
e439bb12 | 1900 | .module = THIS_MODULE, |
1c63dc66 | 1901 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 1902 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 1903 | .reg_read64 = nvme_pci_reg_read64, |
f3ca80fc | 1904 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 1905 | .free_ctrl = nvme_pci_free_ctrl, |
5955be21 | 1906 | .post_scan = nvme_pci_post_scan, |
f866fc42 | 1907 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 1908 | }; |
4cc06521 | 1909 | |
b00a726a KB |
1910 | static int nvme_dev_map(struct nvme_dev *dev) |
1911 | { | |
1912 | int bars; | |
1913 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1914 | ||
1915 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
1916 | if (!bars) | |
1917 | return -ENODEV; | |
1918 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1919 | return -ENODEV; | |
1920 | ||
1921 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1922 | if (!dev->bar) | |
1923 | goto release; | |
1924 | ||
1925 | return 0; | |
1926 | release: | |
1927 | pci_release_regions(pdev); | |
1928 | return -ENODEV; | |
1929 | } | |
1930 | ||
8d85fce7 | 1931 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1932 | { |
a4aea562 | 1933 | int node, result = -ENOMEM; |
b60503ba MW |
1934 | struct nvme_dev *dev; |
1935 | ||
a4aea562 MB |
1936 | node = dev_to_node(&pdev->dev); |
1937 | if (node == NUMA_NO_NODE) | |
1938 | set_dev_node(&pdev->dev, 0); | |
1939 | ||
1940 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
1941 | if (!dev) |
1942 | return -ENOMEM; | |
a4aea562 MB |
1943 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
1944 | GFP_KERNEL, node); | |
b60503ba MW |
1945 | if (!dev->entry) |
1946 | goto free; | |
a4aea562 MB |
1947 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
1948 | GFP_KERNEL, node); | |
b60503ba MW |
1949 | if (!dev->queues) |
1950 | goto free; | |
1951 | ||
e75ec752 | 1952 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 1953 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 1954 | |
b00a726a KB |
1955 | result = nvme_dev_map(dev); |
1956 | if (result) | |
1957 | goto free; | |
1958 | ||
f3ca80fc | 1959 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 1960 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
2d55cd5f CH |
1961 | setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, |
1962 | (unsigned long)dev); | |
77bf25ea | 1963 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 1964 | init_completion(&dev->ioq_wait); |
b60503ba | 1965 | |
091b6092 MW |
1966 | result = nvme_setup_prp_pools(dev); |
1967 | if (result) | |
a96d4f5c | 1968 | goto put_pci; |
4cc06521 | 1969 | |
f3ca80fc CH |
1970 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
1971 | id->driver_data); | |
4cc06521 | 1972 | if (result) |
2e1d8448 | 1973 | goto release_pools; |
740216fc | 1974 | |
1b3c47c1 SG |
1975 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
1976 | ||
92f7a162 | 1977 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
1978 | return 0; |
1979 | ||
0877cb0d | 1980 | release_pools: |
091b6092 | 1981 | nvme_release_prp_pools(dev); |
a96d4f5c | 1982 | put_pci: |
e75ec752 | 1983 | put_device(dev->dev); |
b00a726a | 1984 | nvme_dev_unmap(dev); |
b60503ba MW |
1985 | free: |
1986 | kfree(dev->queues); | |
1987 | kfree(dev->entry); | |
1988 | kfree(dev); | |
1989 | return result; | |
1990 | } | |
1991 | ||
f0d54a54 KB |
1992 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
1993 | { | |
a6739479 | 1994 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 1995 | |
a6739479 | 1996 | if (prepare) |
a5cdb68c | 1997 | nvme_dev_disable(dev, false); |
a6739479 | 1998 | else |
92f7a162 | 1999 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2000 | } |
2001 | ||
09ece142 KB |
2002 | static void nvme_shutdown(struct pci_dev *pdev) |
2003 | { | |
2004 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2005 | nvme_dev_disable(dev, true); |
09ece142 KB |
2006 | } |
2007 | ||
f58944e2 KB |
2008 | /* |
2009 | * The driver's remove may be called on a device in a partially initialized | |
2010 | * state. This function must not have any dependencies on the device state in | |
2011 | * order to proceed. | |
2012 | */ | |
8d85fce7 | 2013 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2014 | { |
2015 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2016 | |
bb8d261e CH |
2017 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2018 | ||
9a6b9458 | 2019 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 KB |
2020 | |
2021 | if (!pci_device_is_present(pdev)) | |
2022 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); | |
2023 | ||
9bf2b972 | 2024 | flush_work(&dev->reset_work); |
53029b04 | 2025 | nvme_uninit_ctrl(&dev->ctrl); |
a5cdb68c | 2026 | nvme_dev_disable(dev, true); |
a4aea562 | 2027 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2028 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2029 | nvme_release_cmb(dev); |
9a6b9458 | 2030 | nvme_release_prp_pools(dev); |
b00a726a | 2031 | nvme_dev_unmap(dev); |
1673f1f0 | 2032 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2033 | } |
2034 | ||
671a6018 | 2035 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2036 | static int nvme_suspend(struct device *dev) |
2037 | { | |
2038 | struct pci_dev *pdev = to_pci_dev(dev); | |
2039 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2040 | ||
a5cdb68c | 2041 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2042 | return 0; |
2043 | } | |
2044 | ||
2045 | static int nvme_resume(struct device *dev) | |
2046 | { | |
2047 | struct pci_dev *pdev = to_pci_dev(dev); | |
2048 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2049 | |
92f7a162 | 2050 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2051 | return 0; |
cd638946 | 2052 | } |
671a6018 | 2053 | #endif |
cd638946 KB |
2054 | |
2055 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2056 | |
a0a3408e KB |
2057 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2058 | pci_channel_state_t state) | |
2059 | { | |
2060 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2061 | ||
2062 | /* | |
2063 | * A frozen channel requires a reset. When detected, this method will | |
2064 | * shutdown the controller to quiesce. The controller will be restarted | |
2065 | * after the slot reset through driver's slot_reset callback. | |
2066 | */ | |
a0a3408e KB |
2067 | switch (state) { |
2068 | case pci_channel_io_normal: | |
2069 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2070 | case pci_channel_io_frozen: | |
d011fb31 KB |
2071 | dev_warn(dev->ctrl.device, |
2072 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2073 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2074 | return PCI_ERS_RESULT_NEED_RESET; |
2075 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2076 | dev_warn(dev->ctrl.device, |
2077 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2078 | return PCI_ERS_RESULT_DISCONNECT; |
2079 | } | |
2080 | return PCI_ERS_RESULT_NEED_RESET; | |
2081 | } | |
2082 | ||
2083 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2084 | { | |
2085 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2086 | ||
1b3c47c1 | 2087 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e KB |
2088 | pci_restore_state(pdev); |
2089 | queue_work(nvme_workq, &dev->reset_work); | |
2090 | return PCI_ERS_RESULT_RECOVERED; | |
2091 | } | |
2092 | ||
2093 | static void nvme_error_resume(struct pci_dev *pdev) | |
2094 | { | |
2095 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2096 | } | |
2097 | ||
1d352035 | 2098 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2099 | .error_detected = nvme_error_detected, |
b60503ba MW |
2100 | .slot_reset = nvme_slot_reset, |
2101 | .resume = nvme_error_resume, | |
f0d54a54 | 2102 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2103 | }; |
2104 | ||
2105 | /* Move to pci_ids.h later */ | |
2106 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2107 | ||
6eb0d698 | 2108 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2109 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 KB |
2110 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
2111 | NVME_QUIRK_DISCARD_ZEROES, }, | |
99466e70 KB |
2112 | { PCI_VDEVICE(INTEL, 0x0a53), |
2113 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2114 | NVME_QUIRK_DISCARD_ZEROES, }, | |
2115 | { PCI_VDEVICE(INTEL, 0x0a54), | |
2116 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2117 | NVME_QUIRK_DISCARD_ZEROES, }, | |
540c801c KB |
2118 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2119 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2120 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2121 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2122 | { 0, } |
2123 | }; | |
2124 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2125 | ||
2126 | static struct pci_driver nvme_driver = { | |
2127 | .name = "nvme", | |
2128 | .id_table = nvme_id_table, | |
2129 | .probe = nvme_probe, | |
8d85fce7 | 2130 | .remove = nvme_remove, |
09ece142 | 2131 | .shutdown = nvme_shutdown, |
cd638946 KB |
2132 | .driver = { |
2133 | .pm = &nvme_dev_pm_ops, | |
2134 | }, | |
b60503ba MW |
2135 | .err_handler = &nvme_err_handler, |
2136 | }; | |
2137 | ||
2138 | static int __init nvme_init(void) | |
2139 | { | |
0ac13140 | 2140 | int result; |
1fa6aead | 2141 | |
92f7a162 | 2142 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2143 | if (!nvme_workq) |
b9afca3e | 2144 | return -ENOMEM; |
9a6b9458 | 2145 | |
f3db22fe KB |
2146 | result = pci_register_driver(&nvme_driver); |
2147 | if (result) | |
576d55d6 | 2148 | destroy_workqueue(nvme_workq); |
b60503ba MW |
2149 | return result; |
2150 | } | |
2151 | ||
2152 | static void __exit nvme_exit(void) | |
2153 | { | |
2154 | pci_unregister_driver(&nvme_driver); | |
9a6b9458 | 2155 | destroy_workqueue(nvme_workq); |
21bd78bc | 2156 | _nvme_check_size(); |
b60503ba MW |
2157 | } |
2158 | ||
2159 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2160 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2161 | MODULE_VERSION("1.0"); |
b60503ba MW |
2162 | module_init(nvme_init); |
2163 | module_exit(nvme_exit); |