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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
8de05535 | 15 | #include <linux/bitops.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
42f61420 | 18 | #include <linux/cpu.h> |
fd63e9ce | 19 | #include <linux/delay.h> |
b60503ba MW |
20 | #include <linux/errno.h> |
21 | #include <linux/fs.h> | |
22 | #include <linux/genhd.h> | |
4cc09e2d | 23 | #include <linux/hdreg.h> |
5aff9382 | 24 | #include <linux/idr.h> |
b60503ba MW |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
1fa6aead | 29 | #include <linux/kthread.h> |
b60503ba | 30 | #include <linux/kernel.h> |
a5768aa8 | 31 | #include <linux/list_sort.h> |
b60503ba MW |
32 | #include <linux/mm.h> |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/pci.h> | |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
b60503ba | 41 | #include <linux/types.h> |
1d277a63 | 42 | #include <linux/pr.h> |
5d0f6131 | 43 | #include <scsi/sg.h> |
2f8e2c87 | 44 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 45 | #include <asm/unaligned.h> |
797a796a | 46 | |
9d99a8dd | 47 | #include <uapi/linux/nvme_ioctl.h> |
f11bb3e2 CH |
48 | #include "nvme.h" |
49 | ||
b3fffdef | 50 | #define NVME_MINORS (1U << MINORBITS) |
9d43cf64 | 51 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 52 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
53 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
54 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
2484f407 | 55 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) |
9d43cf64 | 56 | |
21d34711 | 57 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
58 | module_param(admin_timeout, byte, 0644); |
59 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 60 | |
bd67608a MW |
61 | unsigned char nvme_io_timeout = 30; |
62 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 63 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 64 | |
2484f407 DM |
65 | static unsigned char shutdown_timeout = 5; |
66 | module_param(shutdown_timeout, byte, 0644); | |
67 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
68 | ||
b60503ba MW |
69 | static int nvme_major; |
70 | module_param(nvme_major, int, 0); | |
71 | ||
b3fffdef KB |
72 | static int nvme_char_major; |
73 | module_param(nvme_char_major, int, 0); | |
74 | ||
58ffacb5 MW |
75 | static int use_threaded_interrupts; |
76 | module_param(use_threaded_interrupts, int, 0); | |
77 | ||
8ffaadf7 JD |
78 | static bool use_cmb_sqes = true; |
79 | module_param(use_cmb_sqes, bool, 0644); | |
80 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
81 | ||
1fa6aead MW |
82 | static DEFINE_SPINLOCK(dev_list_lock); |
83 | static LIST_HEAD(dev_list); | |
84 | static struct task_struct *nvme_thread; | |
9a6b9458 | 85 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 86 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 87 | |
b3fffdef KB |
88 | static struct class *nvme_class; |
89 | ||
1c63dc66 CH |
90 | struct nvme_dev; |
91 | struct nvme_queue; | |
92 | ||
90667892 | 93 | static int __nvme_reset(struct nvme_dev *dev); |
4cc06521 | 94 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 95 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
3cf519b5 | 96 | static void nvme_dead_ctrl(struct nvme_dev *dev); |
d4b4ff8e | 97 | |
4d115420 KB |
98 | struct async_cmd_info { |
99 | struct kthread_work work; | |
100 | struct kthread_worker *worker; | |
a4aea562 | 101 | struct request *req; |
4d115420 KB |
102 | u32 result; |
103 | int status; | |
104 | void *ctx; | |
105 | }; | |
1fa6aead | 106 | |
1c63dc66 CH |
107 | /* |
108 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
109 | */ | |
110 | struct nvme_dev { | |
111 | struct list_head node; | |
112 | struct nvme_queue **queues; | |
113 | struct blk_mq_tag_set tagset; | |
114 | struct blk_mq_tag_set admin_tagset; | |
115 | u32 __iomem *dbs; | |
116 | struct device *dev; | |
117 | struct dma_pool *prp_page_pool; | |
118 | struct dma_pool *prp_small_pool; | |
119 | unsigned queue_count; | |
120 | unsigned online_queues; | |
121 | unsigned max_qid; | |
122 | int q_depth; | |
123 | u32 db_stride; | |
124 | u32 ctrl_config; | |
125 | struct msix_entry *entry; | |
126 | void __iomem *bar; | |
127 | struct list_head namespaces; | |
128 | struct kref kref; | |
129 | struct device *device; | |
130 | struct work_struct reset_work; | |
131 | struct work_struct probe_work; | |
132 | struct work_struct scan_work; | |
133 | bool subsystem; | |
134 | u32 max_hw_sectors; | |
135 | u32 stripe_size; | |
136 | u32 page_size; | |
137 | void __iomem *cmb; | |
138 | dma_addr_t cmb_dma_addr; | |
139 | u64 cmb_size; | |
140 | u32 cmbsz; | |
141 | ||
142 | struct nvme_ctrl ctrl; | |
143 | }; | |
144 | ||
145 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
146 | { | |
147 | return container_of(ctrl, struct nvme_dev, ctrl); | |
148 | } | |
149 | ||
b60503ba MW |
150 | /* |
151 | * An NVM Express queue. Each device has at least two (one for admin | |
152 | * commands and one for I/O commands). | |
153 | */ | |
154 | struct nvme_queue { | |
155 | struct device *q_dmadev; | |
091b6092 | 156 | struct nvme_dev *dev; |
3193f07b | 157 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
158 | spinlock_t q_lock; |
159 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 160 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 161 | volatile struct nvme_completion *cqes; |
42483228 | 162 | struct blk_mq_tags **tags; |
b60503ba MW |
163 | dma_addr_t sq_dma_addr; |
164 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
165 | u32 __iomem *q_db; |
166 | u16 q_depth; | |
6222d172 | 167 | s16 cq_vector; |
b60503ba MW |
168 | u16 sq_head; |
169 | u16 sq_tail; | |
170 | u16 cq_head; | |
c30341dc | 171 | u16 qid; |
e9539f47 MW |
172 | u8 cq_phase; |
173 | u8 cqe_seen; | |
4d115420 | 174 | struct async_cmd_info cmdinfo; |
b60503ba MW |
175 | }; |
176 | ||
71bd150c CH |
177 | /* |
178 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
179 | * entries. You can't see it in this data structure because C doesn't let | |
180 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
181 | * allocated to store the PRP list. | |
182 | */ | |
183 | struct nvme_iod { | |
184 | unsigned long private; /* For the use of the submitter of the I/O */ | |
185 | int npages; /* In the PRP list. 0 means small pool in use */ | |
186 | int offset; /* Of PRP list */ | |
187 | int nents; /* Used in scatterlist */ | |
188 | int length; /* Of data, in bytes */ | |
189 | dma_addr_t first_dma; | |
190 | struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ | |
191 | struct scatterlist sg[0]; | |
192 | }; | |
193 | ||
b60503ba MW |
194 | /* |
195 | * Check we didin't inadvertently grow the command struct | |
196 | */ | |
197 | static inline void _nvme_check_size(void) | |
198 | { | |
199 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
200 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
201 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
202 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
203 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 204 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 205 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
206 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
207 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
208 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
209 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 210 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
211 | } |
212 | ||
edd10d33 | 213 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
214 | struct nvme_completion *); |
215 | ||
e85248e5 | 216 | struct nvme_cmd_info { |
c2f5b650 MW |
217 | nvme_completion_fn fn; |
218 | void *ctx; | |
c30341dc | 219 | int aborted; |
a4aea562 | 220 | struct nvme_queue *nvmeq; |
ac3dd5bd | 221 | struct nvme_iod iod[0]; |
e85248e5 MW |
222 | }; |
223 | ||
ac3dd5bd JA |
224 | /* |
225 | * Max size of iod being embedded in the request payload | |
226 | */ | |
227 | #define NVME_INT_PAGES 2 | |
228 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size) | |
fda631ff | 229 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
230 | |
231 | /* | |
232 | * Will slightly overestimate the number of pages needed. This is OK | |
233 | * as it only leads to a small amount of wasted memory for the lifetime of | |
234 | * the I/O. | |
235 | */ | |
236 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
237 | { | |
238 | unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size); | |
239 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
240 | } | |
241 | ||
242 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
243 | { | |
244 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
245 | ||
246 | ret += sizeof(struct nvme_iod); | |
247 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
248 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
a4aea562 MB |
253 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
254 | unsigned int hctx_idx) | |
e85248e5 | 255 | { |
a4aea562 MB |
256 | struct nvme_dev *dev = data; |
257 | struct nvme_queue *nvmeq = dev->queues[0]; | |
258 | ||
42483228 KB |
259 | WARN_ON(hctx_idx != 0); |
260 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
261 | WARN_ON(nvmeq->tags); | |
262 | ||
a4aea562 | 263 | hctx->driver_data = nvmeq; |
42483228 | 264 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 265 | return 0; |
e85248e5 MW |
266 | } |
267 | ||
4af0e21c KB |
268 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
269 | { | |
270 | struct nvme_queue *nvmeq = hctx->driver_data; | |
271 | ||
272 | nvmeq->tags = NULL; | |
273 | } | |
274 | ||
a4aea562 MB |
275 | static int nvme_admin_init_request(void *data, struct request *req, |
276 | unsigned int hctx_idx, unsigned int rq_idx, | |
277 | unsigned int numa_node) | |
22404274 | 278 | { |
a4aea562 MB |
279 | struct nvme_dev *dev = data; |
280 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
281 | struct nvme_queue *nvmeq = dev->queues[0]; | |
282 | ||
283 | BUG_ON(!nvmeq); | |
284 | cmd->nvmeq = nvmeq; | |
285 | return 0; | |
22404274 KB |
286 | } |
287 | ||
a4aea562 MB |
288 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
289 | unsigned int hctx_idx) | |
b60503ba | 290 | { |
a4aea562 | 291 | struct nvme_dev *dev = data; |
42483228 | 292 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 293 | |
42483228 KB |
294 | if (!nvmeq->tags) |
295 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 296 | |
42483228 | 297 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
298 | hctx->driver_data = nvmeq; |
299 | return 0; | |
b60503ba MW |
300 | } |
301 | ||
a4aea562 MB |
302 | static int nvme_init_request(void *data, struct request *req, |
303 | unsigned int hctx_idx, unsigned int rq_idx, | |
304 | unsigned int numa_node) | |
b60503ba | 305 | { |
a4aea562 MB |
306 | struct nvme_dev *dev = data; |
307 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
308 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
309 | ||
310 | BUG_ON(!nvmeq); | |
311 | cmd->nvmeq = nvmeq; | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
316 | nvme_completion_fn handler) | |
317 | { | |
318 | cmd->fn = handler; | |
319 | cmd->ctx = ctx; | |
320 | cmd->aborted = 0; | |
c917dfe5 | 321 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
322 | } |
323 | ||
ac3dd5bd JA |
324 | static void *iod_get_private(struct nvme_iod *iod) |
325 | { | |
326 | return (void *) (iod->private & ~0x1UL); | |
327 | } | |
328 | ||
329 | /* | |
330 | * If bit 0 is set, the iod is embedded in the request payload. | |
331 | */ | |
332 | static bool iod_should_kfree(struct nvme_iod *iod) | |
333 | { | |
fda631ff | 334 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
335 | } |
336 | ||
c2f5b650 MW |
337 | /* Special values must be less than 0x1000 */ |
338 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
339 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
340 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
341 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 342 | |
edd10d33 | 343 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
344 | struct nvme_completion *cqe) |
345 | { | |
346 | if (ctx == CMD_CTX_CANCELLED) | |
347 | return; | |
c2f5b650 | 348 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 349 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
350 | "completed id %d twice on queue %d\n", |
351 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
352 | return; | |
353 | } | |
354 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 355 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
356 | "invalid id %d completed on queue %d\n", |
357 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
358 | return; | |
359 | } | |
edd10d33 | 360 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
361 | } |
362 | ||
a4aea562 | 363 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 364 | { |
c2f5b650 | 365 | void *ctx; |
b60503ba | 366 | |
859361a2 | 367 | if (fn) |
a4aea562 MB |
368 | *fn = cmd->fn; |
369 | ctx = cmd->ctx; | |
370 | cmd->fn = special_completion; | |
371 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 372 | return ctx; |
b60503ba MW |
373 | } |
374 | ||
a4aea562 MB |
375 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
376 | struct nvme_completion *cqe) | |
3c0cf138 | 377 | { |
a4aea562 MB |
378 | u32 result = le32_to_cpup(&cqe->result); |
379 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
380 | ||
381 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
1c63dc66 | 382 | ++nvmeq->dev->ctrl.event_limit; |
a5768aa8 KB |
383 | if (status != NVME_SC_SUCCESS) |
384 | return; | |
385 | ||
386 | switch (result & 0xff07) { | |
387 | case NVME_AER_NOTICE_NS_CHANGED: | |
388 | dev_info(nvmeq->q_dmadev, "rescanning\n"); | |
389 | schedule_work(&nvmeq->dev->scan_work); | |
390 | default: | |
391 | dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); | |
392 | } | |
b60503ba MW |
393 | } |
394 | ||
a4aea562 MB |
395 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
396 | struct nvme_completion *cqe) | |
5a92e700 | 397 | { |
a4aea562 MB |
398 | struct request *req = ctx; |
399 | ||
400 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
401 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 402 | |
42483228 | 403 | blk_mq_free_request(req); |
a51afb54 | 404 | |
a4aea562 | 405 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
1c63dc66 | 406 | ++nvmeq->dev->ctrl.abort_limit; |
5a92e700 KB |
407 | } |
408 | ||
a4aea562 MB |
409 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
410 | struct nvme_completion *cqe) | |
b60503ba | 411 | { |
a4aea562 MB |
412 | struct async_cmd_info *cmdinfo = ctx; |
413 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
414 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
415 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
42483228 | 416 | blk_mq_free_request(cmdinfo->req); |
b60503ba MW |
417 | } |
418 | ||
a4aea562 MB |
419 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
420 | unsigned int tag) | |
b60503ba | 421 | { |
42483228 | 422 | struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); |
a51afb54 | 423 | |
a4aea562 | 424 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
425 | } |
426 | ||
a4aea562 MB |
427 | /* |
428 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
429 | */ | |
430 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
431 | nvme_completion_fn *fn) | |
4f5099af | 432 | { |
a4aea562 MB |
433 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
434 | void *ctx; | |
435 | if (tag >= nvmeq->q_depth) { | |
436 | *fn = special_completion; | |
437 | return CMD_CTX_INVALID; | |
438 | } | |
439 | if (fn) | |
440 | *fn = cmd->fn; | |
441 | ctx = cmd->ctx; | |
442 | cmd->fn = special_completion; | |
443 | cmd->ctx = CMD_CTX_COMPLETED; | |
444 | return ctx; | |
b60503ba MW |
445 | } |
446 | ||
447 | /** | |
714a7a22 | 448 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
449 | * @nvmeq: The queue to use |
450 | * @cmd: The command to send | |
451 | * | |
452 | * Safe to use from interrupt context | |
453 | */ | |
e3f879bf SB |
454 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
455 | struct nvme_command *cmd) | |
b60503ba | 456 | { |
a4aea562 MB |
457 | u16 tail = nvmeq->sq_tail; |
458 | ||
8ffaadf7 JD |
459 | if (nvmeq->sq_cmds_io) |
460 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
461 | else | |
462 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
463 | ||
b60503ba MW |
464 | if (++tail == nvmeq->q_depth) |
465 | tail = 0; | |
7547881d | 466 | writel(tail, nvmeq->q_db); |
b60503ba | 467 | nvmeq->sq_tail = tail; |
b60503ba MW |
468 | } |
469 | ||
e3f879bf | 470 | static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
a4aea562 MB |
471 | { |
472 | unsigned long flags; | |
a4aea562 | 473 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
e3f879bf | 474 | __nvme_submit_cmd(nvmeq, cmd); |
a4aea562 | 475 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); |
a4aea562 MB |
476 | } |
477 | ||
eca18b23 | 478 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 479 | { |
eca18b23 | 480 | return ((void *)iod) + iod->offset; |
e025344c SMM |
481 | } |
482 | ||
ac3dd5bd JA |
483 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
484 | unsigned nseg, unsigned long private) | |
eca18b23 | 485 | { |
ac3dd5bd JA |
486 | iod->private = private; |
487 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
488 | iod->npages = -1; | |
489 | iod->length = nbytes; | |
490 | iod->nents = 0; | |
eca18b23 | 491 | } |
b60503ba | 492 | |
eca18b23 | 493 | static struct nvme_iod * |
ac3dd5bd JA |
494 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
495 | unsigned long priv, gfp_t gfp) | |
b60503ba | 496 | { |
eca18b23 | 497 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 498 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
499 | sizeof(struct scatterlist) * nseg, gfp); |
500 | ||
ac3dd5bd JA |
501 | if (iod) |
502 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
503 | |
504 | return iod; | |
b60503ba MW |
505 | } |
506 | ||
ac3dd5bd JA |
507 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
508 | gfp_t gfp) | |
509 | { | |
510 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
511 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
512 | struct nvme_iod *iod; |
513 | ||
514 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
515 | size <= NVME_INT_BYTES(dev)) { | |
516 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
517 | ||
518 | iod = cmd->iod; | |
ac3dd5bd | 519 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 520 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
521 | return iod; |
522 | } | |
523 | ||
524 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
525 | (unsigned long) rq, gfp); | |
526 | } | |
527 | ||
d29ec824 | 528 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 529 | { |
1d090624 | 530 | const int last_prp = dev->page_size / 8 - 1; |
eca18b23 MW |
531 | int i; |
532 | __le64 **list = iod_list(iod); | |
533 | dma_addr_t prp_dma = iod->first_dma; | |
534 | ||
535 | if (iod->npages == 0) | |
536 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
537 | for (i = 0; i < iod->npages; i++) { | |
538 | __le64 *prp_list = list[i]; | |
539 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
540 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
541 | prp_dma = next_prp_dma; | |
542 | } | |
ac3dd5bd JA |
543 | |
544 | if (iod_should_kfree(iod)) | |
545 | kfree(iod); | |
b60503ba MW |
546 | } |
547 | ||
b4ff9c8d KB |
548 | static int nvme_error_status(u16 status) |
549 | { | |
550 | switch (status & 0x7ff) { | |
551 | case NVME_SC_SUCCESS: | |
552 | return 0; | |
553 | case NVME_SC_CAP_EXCEEDED: | |
554 | return -ENOSPC; | |
555 | default: | |
556 | return -EIO; | |
557 | } | |
558 | } | |
559 | ||
52b68d7e | 560 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
561 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
562 | { | |
563 | if (be32_to_cpu(pi->ref_tag) == v) | |
564 | pi->ref_tag = cpu_to_be32(p); | |
565 | } | |
566 | ||
567 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
568 | { | |
569 | if (be32_to_cpu(pi->ref_tag) == p) | |
570 | pi->ref_tag = cpu_to_be32(v); | |
571 | } | |
572 | ||
573 | /** | |
574 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
575 | * | |
576 | * The virtual start sector is the one that was originally submitted by the | |
577 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
578 | * start sector may be different. Remap protection information to match the | |
579 | * physical LBA on writes, and back to the original seed on reads. | |
580 | * | |
581 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
582 | */ | |
583 | static void nvme_dif_remap(struct request *req, | |
584 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
585 | { | |
586 | struct nvme_ns *ns = req->rq_disk->private_data; | |
587 | struct bio_integrity_payload *bip; | |
588 | struct t10_pi_tuple *pi; | |
589 | void *p, *pmap; | |
590 | u32 i, nlb, ts, phys, virt; | |
591 | ||
592 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
593 | return; | |
594 | ||
595 | bip = bio_integrity(req->bio); | |
596 | if (!bip) | |
597 | return; | |
598 | ||
599 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
600 | |
601 | p = pmap; | |
602 | virt = bip_get_seed(bip); | |
603 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
604 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 605 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
606 | |
607 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
608 | pi = (struct t10_pi_tuple *)p; | |
609 | dif_swap(phys, virt, pi); | |
610 | p += ts; | |
611 | } | |
612 | kunmap_atomic(pmap); | |
613 | } | |
614 | ||
52b68d7e KB |
615 | static void nvme_init_integrity(struct nvme_ns *ns) |
616 | { | |
617 | struct blk_integrity integrity; | |
618 | ||
619 | switch (ns->pi_type) { | |
620 | case NVME_NS_DPS_PI_TYPE3: | |
0f8087ec | 621 | integrity.profile = &t10_pi_type3_crc; |
52b68d7e KB |
622 | break; |
623 | case NVME_NS_DPS_PI_TYPE1: | |
624 | case NVME_NS_DPS_PI_TYPE2: | |
0f8087ec | 625 | integrity.profile = &t10_pi_type1_crc; |
52b68d7e KB |
626 | break; |
627 | default: | |
4125a09b | 628 | integrity.profile = NULL; |
52b68d7e KB |
629 | break; |
630 | } | |
631 | integrity.tuple_size = ns->ms; | |
632 | blk_integrity_register(ns->disk, &integrity); | |
633 | blk_queue_max_integrity_segments(ns->queue, 1); | |
634 | } | |
635 | #else /* CONFIG_BLK_DEV_INTEGRITY */ | |
636 | static void nvme_dif_remap(struct request *req, | |
637 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
638 | { | |
639 | } | |
640 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
641 | { | |
642 | } | |
643 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
644 | { | |
645 | } | |
646 | static void nvme_init_integrity(struct nvme_ns *ns) | |
647 | { | |
648 | } | |
649 | #endif | |
650 | ||
a4aea562 | 651 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
652 | struct nvme_completion *cqe) |
653 | { | |
eca18b23 | 654 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 655 | struct request *req = iod_get_private(iod); |
a4aea562 | 656 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
b60503ba | 657 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
0dfc70c3 | 658 | bool requeue = false; |
81c04b94 | 659 | int error = 0; |
b60503ba | 660 | |
edd10d33 | 661 | if (unlikely(status)) { |
a4aea562 MB |
662 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
663 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
664 | unsigned long flags; |
665 | ||
0dfc70c3 | 666 | requeue = true; |
a4aea562 | 667 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
668 | spin_lock_irqsave(req->q->queue_lock, flags); |
669 | if (!blk_queue_stopped(req->q)) | |
670 | blk_mq_kick_requeue_list(req->q); | |
671 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
0dfc70c3 | 672 | goto release_iod; |
edd10d33 | 673 | } |
f4829a9b | 674 | |
d29ec824 | 675 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
17188bb4 | 676 | if (cmd_rq->ctx == CMD_CTX_CANCELLED) |
81c04b94 CH |
677 | error = -EINTR; |
678 | else | |
679 | error = status; | |
d29ec824 | 680 | } else { |
81c04b94 | 681 | error = nvme_error_status(status); |
d29ec824 | 682 | } |
f4829a9b CH |
683 | } |
684 | ||
a0a931d6 KB |
685 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
686 | u32 result = le32_to_cpup(&cqe->result); | |
687 | req->special = (void *)(uintptr_t)result; | |
688 | } | |
a4aea562 MB |
689 | |
690 | if (cmd_rq->aborted) | |
e75ec752 | 691 | dev_warn(nvmeq->dev->dev, |
a4aea562 | 692 | "completing aborted command with status:%04x\n", |
81c04b94 | 693 | error); |
a4aea562 | 694 | |
0dfc70c3 | 695 | release_iod: |
e1e5e564 | 696 | if (iod->nents) { |
e75ec752 | 697 | dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents, |
a4aea562 | 698 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
e1e5e564 KB |
699 | if (blk_integrity_rq(req)) { |
700 | if (!rq_data_dir(req)) | |
701 | nvme_dif_remap(req, nvme_dif_complete); | |
e75ec752 | 702 | dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1, |
e1e5e564 KB |
703 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
704 | } | |
705 | } | |
edd10d33 | 706 | nvme_free_iod(nvmeq->dev, iod); |
3291fa57 | 707 | |
0dfc70c3 KB |
708 | if (likely(!requeue)) |
709 | blk_mq_complete_request(req, error); | |
b60503ba MW |
710 | } |
711 | ||
69d2b571 CH |
712 | static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
713 | int total_len) | |
ff22b54f | 714 | { |
99802a7a | 715 | struct dma_pool *pool; |
eca18b23 MW |
716 | int length = total_len; |
717 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
718 | int dma_len = sg_dma_len(sg); |
719 | u64 dma_addr = sg_dma_address(sg); | |
f137e0f1 MI |
720 | u32 page_size = dev->page_size; |
721 | int offset = dma_addr & (page_size - 1); | |
e025344c | 722 | __le64 *prp_list; |
eca18b23 | 723 | __le64 **list = iod_list(iod); |
e025344c | 724 | dma_addr_t prp_dma; |
eca18b23 | 725 | int nprps, i; |
ff22b54f | 726 | |
1d090624 | 727 | length -= (page_size - offset); |
ff22b54f | 728 | if (length <= 0) |
69d2b571 | 729 | return true; |
ff22b54f | 730 | |
1d090624 | 731 | dma_len -= (page_size - offset); |
ff22b54f | 732 | if (dma_len) { |
1d090624 | 733 | dma_addr += (page_size - offset); |
ff22b54f MW |
734 | } else { |
735 | sg = sg_next(sg); | |
736 | dma_addr = sg_dma_address(sg); | |
737 | dma_len = sg_dma_len(sg); | |
738 | } | |
739 | ||
1d090624 | 740 | if (length <= page_size) { |
edd10d33 | 741 | iod->first_dma = dma_addr; |
69d2b571 | 742 | return true; |
e025344c SMM |
743 | } |
744 | ||
1d090624 | 745 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
746 | if (nprps <= (256 / 8)) { |
747 | pool = dev->prp_small_pool; | |
eca18b23 | 748 | iod->npages = 0; |
99802a7a MW |
749 | } else { |
750 | pool = dev->prp_page_pool; | |
eca18b23 | 751 | iod->npages = 1; |
99802a7a MW |
752 | } |
753 | ||
69d2b571 | 754 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 755 | if (!prp_list) { |
edd10d33 | 756 | iod->first_dma = dma_addr; |
eca18b23 | 757 | iod->npages = -1; |
69d2b571 | 758 | return false; |
b77954cb | 759 | } |
eca18b23 MW |
760 | list[0] = prp_list; |
761 | iod->first_dma = prp_dma; | |
e025344c SMM |
762 | i = 0; |
763 | for (;;) { | |
1d090624 | 764 | if (i == page_size >> 3) { |
e025344c | 765 | __le64 *old_prp_list = prp_list; |
69d2b571 | 766 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 767 | if (!prp_list) |
69d2b571 | 768 | return false; |
eca18b23 | 769 | list[iod->npages++] = prp_list; |
7523d834 MW |
770 | prp_list[0] = old_prp_list[i - 1]; |
771 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
772 | i = 1; | |
e025344c SMM |
773 | } |
774 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
775 | dma_len -= page_size; |
776 | dma_addr += page_size; | |
777 | length -= page_size; | |
e025344c SMM |
778 | if (length <= 0) |
779 | break; | |
780 | if (dma_len > 0) | |
781 | continue; | |
782 | BUG_ON(dma_len < 0); | |
783 | sg = sg_next(sg); | |
784 | dma_addr = sg_dma_address(sg); | |
785 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
786 | } |
787 | ||
69d2b571 | 788 | return true; |
ff22b54f MW |
789 | } |
790 | ||
d29ec824 CH |
791 | static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req, |
792 | struct nvme_iod *iod) | |
793 | { | |
498c4394 | 794 | struct nvme_command cmnd; |
d29ec824 | 795 | |
498c4394 JD |
796 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); |
797 | cmnd.rw.command_id = req->tag; | |
d29ec824 | 798 | if (req->nr_phys_segments) { |
498c4394 JD |
799 | cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
800 | cmnd.rw.prp2 = cpu_to_le64(iod->first_dma); | |
d29ec824 CH |
801 | } |
802 | ||
498c4394 | 803 | __nvme_submit_cmd(nvmeq, &cmnd); |
d29ec824 CH |
804 | } |
805 | ||
a4aea562 MB |
806 | /* |
807 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
808 | * worth having a special pool for these or additional cases to handle freeing | |
809 | * the iod. | |
810 | */ | |
811 | static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
812 | struct request *req, struct nvme_iod *iod) | |
0e5e4f0e | 813 | { |
edd10d33 KB |
814 | struct nvme_dsm_range *range = |
815 | (struct nvme_dsm_range *)iod_list(iod)[0]; | |
498c4394 | 816 | struct nvme_command cmnd; |
0e5e4f0e | 817 | |
0e5e4f0e | 818 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
819 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
820 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 821 | |
498c4394 JD |
822 | memset(&cmnd, 0, sizeof(cmnd)); |
823 | cmnd.dsm.opcode = nvme_cmd_dsm; | |
824 | cmnd.dsm.command_id = req->tag; | |
825 | cmnd.dsm.nsid = cpu_to_le32(ns->ns_id); | |
826 | cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma); | |
827 | cmnd.dsm.nr = 0; | |
828 | cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
0e5e4f0e | 829 | |
498c4394 | 830 | __nvme_submit_cmd(nvmeq, &cmnd); |
0e5e4f0e KB |
831 | } |
832 | ||
a4aea562 | 833 | static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
00df5cb4 MW |
834 | int cmdid) |
835 | { | |
498c4394 | 836 | struct nvme_command cmnd; |
00df5cb4 | 837 | |
498c4394 JD |
838 | memset(&cmnd, 0, sizeof(cmnd)); |
839 | cmnd.common.opcode = nvme_cmd_flush; | |
840 | cmnd.common.command_id = cmdid; | |
841 | cmnd.common.nsid = cpu_to_le32(ns->ns_id); | |
00df5cb4 | 842 | |
498c4394 | 843 | __nvme_submit_cmd(nvmeq, &cmnd); |
00df5cb4 MW |
844 | } |
845 | ||
a4aea562 MB |
846 | static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
847 | struct nvme_ns *ns) | |
b60503ba | 848 | { |
ac3dd5bd | 849 | struct request *req = iod_get_private(iod); |
498c4394 | 850 | struct nvme_command cmnd; |
a4aea562 MB |
851 | u16 control = 0; |
852 | u32 dsmgmt = 0; | |
00df5cb4 | 853 | |
a4aea562 | 854 | if (req->cmd_flags & REQ_FUA) |
b60503ba | 855 | control |= NVME_RW_FUA; |
a4aea562 | 856 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) |
b60503ba MW |
857 | control |= NVME_RW_LR; |
858 | ||
a4aea562 | 859 | if (req->cmd_flags & REQ_RAHEAD) |
b60503ba MW |
860 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; |
861 | ||
498c4394 JD |
862 | memset(&cmnd, 0, sizeof(cmnd)); |
863 | cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); | |
864 | cmnd.rw.command_id = req->tag; | |
865 | cmnd.rw.nsid = cpu_to_le32(ns->ns_id); | |
866 | cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
867 | cmnd.rw.prp2 = cpu_to_le64(iod->first_dma); | |
868 | cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
869 | cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
b60503ba | 870 | |
e19b127f | 871 | if (ns->ms) { |
e1e5e564 KB |
872 | switch (ns->pi_type) { |
873 | case NVME_NS_DPS_PI_TYPE3: | |
874 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
875 | break; | |
876 | case NVME_NS_DPS_PI_TYPE1: | |
877 | case NVME_NS_DPS_PI_TYPE2: | |
878 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
879 | NVME_RW_PRINFO_PRCHK_REF; | |
498c4394 | 880 | cmnd.rw.reftag = cpu_to_le32( |
e1e5e564 KB |
881 | nvme_block_nr(ns, blk_rq_pos(req))); |
882 | break; | |
883 | } | |
e19b127f AP |
884 | if (blk_integrity_rq(req)) |
885 | cmnd.rw.metadata = | |
886 | cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
887 | else | |
888 | control |= NVME_RW_PRINFO_PRACT; | |
889 | } | |
e1e5e564 | 890 | |
498c4394 JD |
891 | cmnd.rw.control = cpu_to_le16(control); |
892 | cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 893 | |
498c4394 | 894 | __nvme_submit_cmd(nvmeq, &cmnd); |
b60503ba | 895 | |
1974b1ae | 896 | return 0; |
edd10d33 KB |
897 | } |
898 | ||
d29ec824 CH |
899 | /* |
900 | * NOTE: ns is NULL when called on the admin queue. | |
901 | */ | |
a4aea562 MB |
902 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
903 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 904 | { |
a4aea562 MB |
905 | struct nvme_ns *ns = hctx->queue->queuedata; |
906 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 907 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
908 | struct request *req = bd->rq; |
909 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 910 | struct nvme_iod *iod; |
a4aea562 | 911 | enum dma_data_direction dma_dir; |
edd10d33 | 912 | |
e1e5e564 KB |
913 | /* |
914 | * If formated with metadata, require the block layer provide a buffer | |
915 | * unless this namespace is formated such that the metadata can be | |
916 | * stripped/generated by the controller with PRACT=1. | |
917 | */ | |
d29ec824 | 918 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
919 | if (!(ns->pi_type && ns->ms == 8) && |
920 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
f4829a9b | 921 | blk_mq_complete_request(req, -EFAULT); |
e1e5e564 KB |
922 | return BLK_MQ_RQ_QUEUE_OK; |
923 | } | |
924 | } | |
925 | ||
d29ec824 | 926 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 927 | if (!iod) |
fe54303e | 928 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 929 | |
a4aea562 | 930 | if (req->cmd_flags & REQ_DISCARD) { |
edd10d33 KB |
931 | void *range; |
932 | /* | |
933 | * We reuse the small pool to allocate the 16-byte range here | |
934 | * as it is not worth having a special pool for these or | |
935 | * additional cases to handle freeing the iod. | |
936 | */ | |
d29ec824 | 937 | range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC, |
edd10d33 | 938 | &iod->first_dma); |
a4aea562 | 939 | if (!range) |
fe54303e | 940 | goto retry_cmd; |
edd10d33 KB |
941 | iod_list(iod)[0] = (__le64 *)range; |
942 | iod->npages = 0; | |
ac3dd5bd | 943 | } else if (req->nr_phys_segments) { |
a4aea562 MB |
944 | dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; |
945 | ||
ac3dd5bd | 946 | sg_init_table(iod->sg, req->nr_phys_segments); |
a4aea562 | 947 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
fe54303e JA |
948 | if (!iod->nents) |
949 | goto error_cmd; | |
a4aea562 MB |
950 | |
951 | if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir)) | |
fe54303e | 952 | goto retry_cmd; |
a4aea562 | 953 | |
69d2b571 | 954 | if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) { |
d29ec824 | 955 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); |
fe54303e JA |
956 | goto retry_cmd; |
957 | } | |
e1e5e564 | 958 | if (blk_integrity_rq(req)) { |
bf508e91 CH |
959 | if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) { |
960 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, | |
961 | dma_dir); | |
e1e5e564 | 962 | goto error_cmd; |
bf508e91 | 963 | } |
e1e5e564 KB |
964 | |
965 | sg_init_table(iod->meta_sg, 1); | |
966 | if (blk_rq_map_integrity_sg( | |
bf508e91 CH |
967 | req->q, req->bio, iod->meta_sg) != 1) { |
968 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, | |
969 | dma_dir); | |
e1e5e564 | 970 | goto error_cmd; |
bf508e91 | 971 | } |
e1e5e564 KB |
972 | |
973 | if (rq_data_dir(req)) | |
974 | nvme_dif_remap(req, nvme_dif_prep); | |
975 | ||
bf508e91 CH |
976 | if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) { |
977 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, | |
978 | dma_dir); | |
e1e5e564 | 979 | goto error_cmd; |
bf508e91 | 980 | } |
e1e5e564 | 981 | } |
edd10d33 | 982 | } |
1974b1ae | 983 | |
9af8785a | 984 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 | 985 | spin_lock_irq(&nvmeq->q_lock); |
d29ec824 CH |
986 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
987 | nvme_submit_priv(nvmeq, req, iod); | |
988 | else if (req->cmd_flags & REQ_DISCARD) | |
a4aea562 MB |
989 | nvme_submit_discard(nvmeq, ns, req, iod); |
990 | else if (req->cmd_flags & REQ_FLUSH) | |
991 | nvme_submit_flush(nvmeq, ns, req->tag); | |
992 | else | |
993 | nvme_submit_iod(nvmeq, iod, ns); | |
994 | ||
995 | nvme_process_cq(nvmeq); | |
996 | spin_unlock_irq(&nvmeq->q_lock); | |
997 | return BLK_MQ_RQ_QUEUE_OK; | |
998 | ||
fe54303e | 999 | error_cmd: |
d29ec824 | 1000 | nvme_free_iod(dev, iod); |
fe54303e JA |
1001 | return BLK_MQ_RQ_QUEUE_ERROR; |
1002 | retry_cmd: | |
d29ec824 | 1003 | nvme_free_iod(dev, iod); |
fe54303e | 1004 | return BLK_MQ_RQ_QUEUE_BUSY; |
b60503ba MW |
1005 | } |
1006 | ||
a0fa9647 | 1007 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 1008 | { |
82123460 | 1009 | u16 head, phase; |
b60503ba | 1010 | |
b60503ba | 1011 | head = nvmeq->cq_head; |
82123460 | 1012 | phase = nvmeq->cq_phase; |
b60503ba MW |
1013 | |
1014 | for (;;) { | |
c2f5b650 MW |
1015 | void *ctx; |
1016 | nvme_completion_fn fn; | |
b60503ba | 1017 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 1018 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
1019 | break; |
1020 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
1021 | if (++head == nvmeq->q_depth) { | |
1022 | head = 0; | |
82123460 | 1023 | phase = !phase; |
b60503ba | 1024 | } |
a0fa9647 JA |
1025 | if (tag && *tag == cqe.command_id) |
1026 | *tag = -1; | |
a4aea562 | 1027 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 1028 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
1029 | } |
1030 | ||
1031 | /* If the controller ignores the cq head doorbell and continuously | |
1032 | * writes to the queue, it is theoretically possible to wrap around | |
1033 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
1034 | * requires that 0.1% of your interrupts are handled, so this isn't | |
1035 | * a big problem. | |
1036 | */ | |
82123460 | 1037 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 1038 | return; |
b60503ba | 1039 | |
604e8c8d KB |
1040 | if (likely(nvmeq->cq_vector >= 0)) |
1041 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 1042 | nvmeq->cq_head = head; |
82123460 | 1043 | nvmeq->cq_phase = phase; |
b60503ba | 1044 | |
e9539f47 | 1045 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
1046 | } |
1047 | ||
1048 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
1049 | { | |
1050 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
1051 | } |
1052 | ||
1053 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
1054 | { |
1055 | irqreturn_t result; | |
1056 | struct nvme_queue *nvmeq = data; | |
1057 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
1058 | nvme_process_cq(nvmeq); |
1059 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
1060 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
1061 | spin_unlock(&nvmeq->q_lock); |
1062 | return result; | |
1063 | } | |
1064 | ||
1065 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
1066 | { | |
1067 | struct nvme_queue *nvmeq = data; | |
1068 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
1069 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
1070 | return IRQ_NONE; | |
1071 | return IRQ_WAKE_THREAD; | |
1072 | } | |
1073 | ||
a0fa9647 JA |
1074 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
1075 | { | |
1076 | struct nvme_queue *nvmeq = hctx->driver_data; | |
1077 | ||
1078 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
1079 | nvmeq->cq_phase) { | |
1080 | spin_lock_irq(&nvmeq->q_lock); | |
1081 | __nvme_process_cq(nvmeq, &tag); | |
1082 | spin_unlock_irq(&nvmeq->q_lock); | |
1083 | ||
1084 | if (tag == -1) | |
1085 | return 1; | |
1086 | } | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
a4aea562 MB |
1091 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
1092 | { | |
1093 | struct nvme_queue *nvmeq = dev->queues[0]; | |
1094 | struct nvme_command c; | |
1095 | struct nvme_cmd_info *cmd_info; | |
1096 | struct request *req; | |
1097 | ||
1c63dc66 | 1098 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 1099 | BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); |
9f173b33 DC |
1100 | if (IS_ERR(req)) |
1101 | return PTR_ERR(req); | |
a4aea562 | 1102 | |
c917dfe5 | 1103 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 | 1104 | cmd_info = blk_mq_rq_to_pdu(req); |
1efccc9d | 1105 | nvme_set_info(cmd_info, NULL, async_req_completion); |
a4aea562 MB |
1106 | |
1107 | memset(&c, 0, sizeof(c)); | |
1108 | c.common.opcode = nvme_admin_async_event; | |
1109 | c.common.command_id = req->tag; | |
1110 | ||
42483228 | 1111 | blk_mq_free_request(req); |
e3f879bf SB |
1112 | __nvme_submit_cmd(nvmeq, &c); |
1113 | return 0; | |
a4aea562 MB |
1114 | } |
1115 | ||
1116 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
1117 | struct nvme_command *cmd, |
1118 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
1119 | { | |
a4aea562 MB |
1120 | struct nvme_queue *nvmeq = dev->queues[0]; |
1121 | struct request *req; | |
1122 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1123 | |
1c63dc66 | 1124 | req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); |
9f173b33 DC |
1125 | if (IS_ERR(req)) |
1126 | return PTR_ERR(req); | |
a4aea562 MB |
1127 | |
1128 | req->timeout = timeout; | |
1129 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1130 | cmdinfo->req = req; | |
1131 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1132 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1133 | |
1134 | cmd->common.command_id = req->tag; | |
1135 | ||
e3f879bf SB |
1136 | nvme_submit_cmd(nvmeq, cmd); |
1137 | return 0; | |
4d115420 KB |
1138 | } |
1139 | ||
b60503ba MW |
1140 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1141 | { | |
b60503ba MW |
1142 | struct nvme_command c; |
1143 | ||
1144 | memset(&c, 0, sizeof(c)); | |
1145 | c.delete_queue.opcode = opcode; | |
1146 | c.delete_queue.qid = cpu_to_le16(id); | |
1147 | ||
1c63dc66 | 1148 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1149 | } |
1150 | ||
1151 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1152 | struct nvme_queue *nvmeq) | |
1153 | { | |
b60503ba MW |
1154 | struct nvme_command c; |
1155 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1156 | ||
d29ec824 CH |
1157 | /* |
1158 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1159 | * is attached to the request. | |
1160 | */ | |
b60503ba MW |
1161 | memset(&c, 0, sizeof(c)); |
1162 | c.create_cq.opcode = nvme_admin_create_cq; | |
1163 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1164 | c.create_cq.cqid = cpu_to_le16(qid); | |
1165 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1166 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1167 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1168 | ||
1c63dc66 | 1169 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1170 | } |
1171 | ||
1172 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1173 | struct nvme_queue *nvmeq) | |
1174 | { | |
b60503ba MW |
1175 | struct nvme_command c; |
1176 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1177 | ||
d29ec824 CH |
1178 | /* |
1179 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1180 | * is attached to the request. | |
1181 | */ | |
b60503ba MW |
1182 | memset(&c, 0, sizeof(c)); |
1183 | c.create_sq.opcode = nvme_admin_create_sq; | |
1184 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1185 | c.create_sq.sqid = cpu_to_le16(qid); | |
1186 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1187 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1188 | c.create_sq.cqid = cpu_to_le16(qid); | |
1189 | ||
1c63dc66 | 1190 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1191 | } |
1192 | ||
1193 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1194 | { | |
1195 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1196 | } | |
1197 | ||
1198 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1199 | { | |
1200 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1201 | } | |
1202 | ||
c30341dc | 1203 | /** |
a4aea562 | 1204 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1205 | * |
1206 | * Schedule controller reset if the command was already aborted once before and | |
1207 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1208 | */ | |
a4aea562 | 1209 | static void nvme_abort_req(struct request *req) |
c30341dc | 1210 | { |
a4aea562 MB |
1211 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1212 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1213 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1214 | struct request *abort_req; |
1215 | struct nvme_cmd_info *abort_cmd; | |
1216 | struct nvme_command cmd; | |
c30341dc | 1217 | |
a4aea562 | 1218 | if (!nvmeq->qid || cmd_rq->aborted) { |
90667892 CH |
1219 | spin_lock(&dev_list_lock); |
1220 | if (!__nvme_reset(dev)) { | |
1221 | dev_warn(dev->dev, | |
1222 | "I/O %d QID %d timeout, reset controller\n", | |
1223 | req->tag, nvmeq->qid); | |
1224 | } | |
1225 | spin_unlock(&dev_list_lock); | |
c30341dc KB |
1226 | return; |
1227 | } | |
1228 | ||
1c63dc66 | 1229 | if (!dev->ctrl.abort_limit) |
c30341dc KB |
1230 | return; |
1231 | ||
1c63dc66 | 1232 | abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, |
6f3b0e8b | 1233 | BLK_MQ_REQ_NOWAIT); |
9f173b33 | 1234 | if (IS_ERR(abort_req)) |
c30341dc KB |
1235 | return; |
1236 | ||
a4aea562 MB |
1237 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1238 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1239 | ||
c30341dc KB |
1240 | memset(&cmd, 0, sizeof(cmd)); |
1241 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1242 | cmd.abort.cid = req->tag; |
c30341dc | 1243 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1244 | cmd.abort.command_id = abort_req->tag; |
c30341dc | 1245 | |
1c63dc66 | 1246 | --dev->ctrl.abort_limit; |
a4aea562 | 1247 | cmd_rq->aborted = 1; |
c30341dc | 1248 | |
a4aea562 | 1249 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1250 | nvmeq->qid); |
e3f879bf | 1251 | nvme_submit_cmd(dev->queues[0], &cmd); |
c30341dc KB |
1252 | } |
1253 | ||
42483228 | 1254 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1255 | { |
a4aea562 MB |
1256 | struct nvme_queue *nvmeq = data; |
1257 | void *ctx; | |
1258 | nvme_completion_fn fn; | |
1259 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1260 | struct nvme_completion cqe; |
1261 | ||
1262 | if (!blk_mq_request_started(req)) | |
1263 | return; | |
a09115b2 | 1264 | |
a4aea562 | 1265 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1266 | |
a4aea562 MB |
1267 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1268 | return; | |
1269 | ||
cef6a948 KB |
1270 | if (blk_queue_dying(req->q)) |
1271 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1272 | else | |
1273 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1274 | ||
1275 | ||
a4aea562 MB |
1276 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1277 | req->tag, nvmeq->qid); | |
1278 | ctx = cancel_cmd_info(cmd, &fn); | |
1279 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1280 | } |
1281 | ||
a4aea562 | 1282 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1283 | { |
a4aea562 MB |
1284 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1285 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1286 | ||
1287 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1288 | nvmeq->qid); | |
7a509a6b | 1289 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1290 | nvme_abort_req(req); |
7a509a6b | 1291 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1292 | |
07836e65 KB |
1293 | /* |
1294 | * The aborted req will be completed on receiving the abort req. | |
1295 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1296 | * as the device then is in a faulty state. | |
1297 | */ | |
1298 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1299 | } |
22404274 | 1300 | |
a4aea562 MB |
1301 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1302 | { | |
9e866774 MW |
1303 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1304 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1305 | if (nvmeq->sq_cmds) |
1306 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1307 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1308 | kfree(nvmeq); | |
1309 | } | |
1310 | ||
a1a5ef99 | 1311 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1312 | { |
1313 | int i; | |
1314 | ||
a1a5ef99 | 1315 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1316 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1317 | dev->queue_count--; |
a4aea562 | 1318 | dev->queues[i] = NULL; |
f435c282 | 1319 | nvme_free_queue(nvmeq); |
121c7ad4 | 1320 | } |
22404274 KB |
1321 | } |
1322 | ||
4d115420 KB |
1323 | /** |
1324 | * nvme_suspend_queue - put queue into suspended state | |
1325 | * @nvmeq - queue to suspend | |
4d115420 KB |
1326 | */ |
1327 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1328 | { |
2b25d981 | 1329 | int vector; |
b60503ba | 1330 | |
a09115b2 | 1331 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1332 | if (nvmeq->cq_vector == -1) { |
1333 | spin_unlock_irq(&nvmeq->q_lock); | |
1334 | return 1; | |
1335 | } | |
1336 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1337 | nvmeq->dev->online_queues--; |
2b25d981 | 1338 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1339 | spin_unlock_irq(&nvmeq->q_lock); |
1340 | ||
1c63dc66 CH |
1341 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1342 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1343 | |
aba2080f MW |
1344 | irq_set_affinity_hint(vector, NULL); |
1345 | free_irq(vector, nvmeq); | |
b60503ba | 1346 | |
4d115420 KB |
1347 | return 0; |
1348 | } | |
b60503ba | 1349 | |
4d115420 KB |
1350 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1351 | { | |
22404274 | 1352 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1353 | if (nvmeq->tags && *nvmeq->tags) |
1354 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1355 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1356 | } |
1357 | ||
4d115420 KB |
1358 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1359 | { | |
a4aea562 | 1360 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1361 | |
1362 | if (!nvmeq) | |
1363 | return; | |
1364 | if (nvme_suspend_queue(nvmeq)) | |
1365 | return; | |
1366 | ||
0e53d180 KB |
1367 | /* Don't tell the adapter to delete the admin queue. |
1368 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1369 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1370 | adapter_delete_sq(dev, qid); |
1371 | adapter_delete_cq(dev, qid); | |
1372 | } | |
07836e65 KB |
1373 | |
1374 | spin_lock_irq(&nvmeq->q_lock); | |
1375 | nvme_process_cq(nvmeq); | |
1376 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1377 | } |
1378 | ||
8ffaadf7 JD |
1379 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1380 | int entry_size) | |
1381 | { | |
1382 | int q_depth = dev->q_depth; | |
1383 | unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size); | |
1384 | ||
1385 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 JD |
1386 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
1387 | mem_per_q = round_down(mem_per_q, dev->page_size); | |
1388 | q_depth = div_u64(mem_per_q, entry_size); | |
8ffaadf7 JD |
1389 | |
1390 | /* | |
1391 | * Ensure the reduced q_depth is above some threshold where it | |
1392 | * would be better to map queues in system memory with the | |
1393 | * original depth | |
1394 | */ | |
1395 | if (q_depth < 64) | |
1396 | return -ENOMEM; | |
1397 | } | |
1398 | ||
1399 | return q_depth; | |
1400 | } | |
1401 | ||
1402 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1403 | int qid, int depth) | |
1404 | { | |
1405 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
1406 | unsigned offset = (qid - 1) * | |
1407 | roundup(SQ_SIZE(depth), dev->page_size); | |
1408 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; | |
1409 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1410 | } else { | |
1411 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1412 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1413 | if (!nvmeq->sq_cmds) | |
1414 | return -ENOMEM; | |
1415 | } | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
b60503ba | 1420 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1421 | int depth) |
b60503ba | 1422 | { |
a4aea562 | 1423 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1424 | if (!nvmeq) |
1425 | return NULL; | |
1426 | ||
e75ec752 | 1427 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1428 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1429 | if (!nvmeq->cqes) |
1430 | goto free_nvmeq; | |
b60503ba | 1431 | |
8ffaadf7 | 1432 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1433 | goto free_cqdma; |
1434 | ||
e75ec752 | 1435 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1436 | nvmeq->dev = dev; |
3193f07b | 1437 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1438 | dev->ctrl.instance, qid); |
b60503ba MW |
1439 | spin_lock_init(&nvmeq->q_lock); |
1440 | nvmeq->cq_head = 0; | |
82123460 | 1441 | nvmeq->cq_phase = 1; |
b80d5ccc | 1442 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1443 | nvmeq->q_depth = depth; |
c30341dc | 1444 | nvmeq->qid = qid; |
758dd7fd | 1445 | nvmeq->cq_vector = -1; |
a4aea562 | 1446 | dev->queues[qid] = nvmeq; |
b60503ba | 1447 | |
36a7e993 JD |
1448 | /* make sure queue descriptor is set before queue count, for kthread */ |
1449 | mb(); | |
1450 | dev->queue_count++; | |
1451 | ||
b60503ba MW |
1452 | return nvmeq; |
1453 | ||
1454 | free_cqdma: | |
e75ec752 | 1455 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1456 | nvmeq->cq_dma_addr); |
1457 | free_nvmeq: | |
1458 | kfree(nvmeq); | |
1459 | return NULL; | |
1460 | } | |
1461 | ||
3001082c MW |
1462 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1463 | const char *name) | |
1464 | { | |
58ffacb5 MW |
1465 | if (use_threaded_interrupts) |
1466 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1467 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1468 | name, nvmeq); |
3001082c | 1469 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1470 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1471 | } |
1472 | ||
22404274 | 1473 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1474 | { |
22404274 | 1475 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1476 | |
7be50e93 | 1477 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1478 | nvmeq->sq_tail = 0; |
1479 | nvmeq->cq_head = 0; | |
1480 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1481 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1482 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1483 | dev->online_queues++; |
7be50e93 | 1484 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1485 | } |
1486 | ||
1487 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1488 | { | |
1489 | struct nvme_dev *dev = nvmeq->dev; | |
1490 | int result; | |
3f85d50b | 1491 | |
2b25d981 | 1492 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1493 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1494 | if (result < 0) | |
22404274 | 1495 | return result; |
b60503ba MW |
1496 | |
1497 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1498 | if (result < 0) | |
1499 | goto release_cq; | |
1500 | ||
3193f07b | 1501 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1502 | if (result < 0) |
1503 | goto release_sq; | |
1504 | ||
22404274 | 1505 | nvme_init_queue(nvmeq, qid); |
22404274 | 1506 | return result; |
b60503ba MW |
1507 | |
1508 | release_sq: | |
1509 | adapter_delete_sq(dev, qid); | |
1510 | release_cq: | |
1511 | adapter_delete_cq(dev, qid); | |
22404274 | 1512 | return result; |
b60503ba MW |
1513 | } |
1514 | ||
ba47e386 MW |
1515 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1516 | { | |
1517 | unsigned long timeout; | |
1518 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1519 | ||
1520 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1521 | ||
7a67cbea | 1522 | while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_RDY) != bit) { |
ba47e386 MW |
1523 | msleep(100); |
1524 | if (fatal_signal_pending(current)) | |
1525 | return -EINTR; | |
1526 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1527 | dev_err(dev->dev, |
27e8166c MW |
1528 | "Device not ready; aborting %s\n", enabled ? |
1529 | "initialisation" : "reset"); | |
ba47e386 MW |
1530 | return -ENODEV; |
1531 | } | |
1532 | } | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | /* | |
1538 | * If the device has been passed off to us in an enabled state, just clear | |
1539 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1540 | * bits', but doing so may cause the device to complete commands to the | |
1541 | * admin queue ... and we don't know what memory that might be pointing at! | |
1542 | */ | |
1543 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1544 | { | |
01079522 DM |
1545 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1546 | dev->ctrl_config &= ~NVME_CC_ENABLE; | |
7a67cbea | 1547 | writel(dev->ctrl_config, dev->bar + NVME_REG_CC); |
44af146a | 1548 | |
ba47e386 MW |
1549 | return nvme_wait_ready(dev, cap, false); |
1550 | } | |
1551 | ||
1552 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1553 | { | |
01079522 DM |
1554 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1555 | dev->ctrl_config |= NVME_CC_ENABLE; | |
7a67cbea | 1556 | writel(dev->ctrl_config, dev->bar + NVME_REG_CC); |
01079522 | 1557 | |
ba47e386 MW |
1558 | return nvme_wait_ready(dev, cap, true); |
1559 | } | |
1560 | ||
1894d8f1 KB |
1561 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1562 | { | |
1563 | unsigned long timeout; | |
1894d8f1 | 1564 | |
01079522 DM |
1565 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1566 | dev->ctrl_config |= NVME_CC_SHN_NORMAL; | |
1567 | ||
7a67cbea | 1568 | writel(dev->ctrl_config, dev->bar + NVME_REG_CC); |
1894d8f1 | 1569 | |
2484f407 | 1570 | timeout = SHUTDOWN_TIMEOUT + jiffies; |
7a67cbea | 1571 | while ((readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_SHST_MASK) != |
1894d8f1 KB |
1572 | NVME_CSTS_SHST_CMPLT) { |
1573 | msleep(100); | |
1574 | if (fatal_signal_pending(current)) | |
1575 | return -EINTR; | |
1576 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1577 | dev_err(dev->dev, |
1894d8f1 KB |
1578 | "Device shutdown incomplete; abort shutdown\n"); |
1579 | return -ENODEV; | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
a4aea562 | 1586 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1587 | .queue_rq = nvme_queue_rq, |
a4aea562 MB |
1588 | .map_queue = blk_mq_map_queue, |
1589 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1590 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1591 | .init_request = nvme_admin_init_request, |
1592 | .timeout = nvme_timeout, | |
1593 | }; | |
1594 | ||
1595 | static struct blk_mq_ops nvme_mq_ops = { | |
1596 | .queue_rq = nvme_queue_rq, | |
1597 | .map_queue = blk_mq_map_queue, | |
1598 | .init_hctx = nvme_init_hctx, | |
1599 | .init_request = nvme_init_request, | |
1600 | .timeout = nvme_timeout, | |
a0fa9647 | 1601 | .poll = nvme_poll, |
a4aea562 MB |
1602 | }; |
1603 | ||
ea191d2f KB |
1604 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1605 | { | |
1c63dc66 CH |
1606 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1607 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1608 | blk_mq_free_tag_set(&dev->admin_tagset); |
1609 | } | |
1610 | } | |
1611 | ||
a4aea562 MB |
1612 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1613 | { | |
1c63dc66 | 1614 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1615 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1616 | dev->admin_tagset.nr_hw_queues = 1; | |
1617 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1efccc9d | 1618 | dev->admin_tagset.reserved_tags = 1; |
a4aea562 | 1619 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1620 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1621 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1622 | dev->admin_tagset.driver_data = dev; |
1623 | ||
1624 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1625 | return -ENOMEM; | |
1626 | ||
1c63dc66 CH |
1627 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1628 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1629 | blk_mq_free_tag_set(&dev->admin_tagset); |
1630 | return -ENOMEM; | |
1631 | } | |
1c63dc66 | 1632 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1633 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1634 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1635 | return -ENODEV; |
1636 | } | |
0fb59cbc | 1637 | } else |
1c63dc66 | 1638 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1639 | |
1640 | return 0; | |
1641 | } | |
1642 | ||
8d85fce7 | 1643 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1644 | { |
ba47e386 | 1645 | int result; |
b60503ba | 1646 | u32 aqa; |
7a67cbea | 1647 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba | 1648 | struct nvme_queue *nvmeq; |
c5c9f25b NA |
1649 | /* |
1650 | * default to a 4K page size, with the intention to update this | |
1651 | * path in the future to accomodate architectures with differing | |
1652 | * kernel and IO page sizes. | |
1653 | */ | |
1654 | unsigned page_shift = 12; | |
1d090624 | 1655 | unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12; |
1d090624 KB |
1656 | |
1657 | if (page_shift < dev_page_min) { | |
e75ec752 | 1658 | dev_err(dev->dev, |
1d090624 KB |
1659 | "Minimum device page size (%u) too large for " |
1660 | "host (%u)\n", 1 << dev_page_min, | |
1661 | 1 << page_shift); | |
1662 | return -ENODEV; | |
1663 | } | |
b60503ba | 1664 | |
7a67cbea | 1665 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1666 | NVME_CAP_NSSRC(cap) : 0; |
1667 | ||
7a67cbea CH |
1668 | if (dev->subsystem && |
1669 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1670 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1671 | |
ba47e386 MW |
1672 | result = nvme_disable_ctrl(dev, cap); |
1673 | if (result < 0) | |
1674 | return result; | |
b60503ba | 1675 | |
a4aea562 | 1676 | nvmeq = dev->queues[0]; |
cd638946 | 1677 | if (!nvmeq) { |
2b25d981 | 1678 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1679 | if (!nvmeq) |
1680 | return -ENOMEM; | |
cd638946 | 1681 | } |
b60503ba MW |
1682 | |
1683 | aqa = nvmeq->q_depth - 1; | |
1684 | aqa |= aqa << 16; | |
1685 | ||
1d090624 KB |
1686 | dev->page_size = 1 << page_shift; |
1687 | ||
01079522 | 1688 | dev->ctrl_config = NVME_CC_CSS_NVM; |
1d090624 | 1689 | dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT; |
b60503ba | 1690 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; |
7f53f9d2 | 1691 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba | 1692 | |
7a67cbea CH |
1693 | writel(aqa, dev->bar + NVME_REG_AQA); |
1694 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1695 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1696 | |
ba47e386 | 1697 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1698 | if (result) |
a4aea562 MB |
1699 | goto free_nvmeq; |
1700 | ||
2b25d981 | 1701 | nvmeq->cq_vector = 0; |
3193f07b | 1702 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1703 | if (result) { |
1704 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1705 | goto free_nvmeq; |
758dd7fd | 1706 | } |
025c557a | 1707 | |
b60503ba | 1708 | return result; |
a4aea562 | 1709 | |
a4aea562 MB |
1710 | free_nvmeq: |
1711 | nvme_free_queues(dev, 0); | |
1712 | return result; | |
b60503ba MW |
1713 | } |
1714 | ||
a53295b6 MW |
1715 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1716 | { | |
1c63dc66 | 1717 | struct nvme_dev *dev = to_nvme_dev(ns->ctrl); |
a53295b6 MW |
1718 | struct nvme_user_io io; |
1719 | struct nvme_command c; | |
d29ec824 | 1720 | unsigned length, meta_len; |
a67a9513 | 1721 | int status, write; |
a67a9513 KB |
1722 | dma_addr_t meta_dma = 0; |
1723 | void *meta = NULL; | |
fec558b5 | 1724 | void __user *metadata; |
a53295b6 MW |
1725 | |
1726 | if (copy_from_user(&io, uio, sizeof(io))) | |
1727 | return -EFAULT; | |
6c7d4945 MW |
1728 | |
1729 | switch (io.opcode) { | |
1730 | case nvme_cmd_write: | |
1731 | case nvme_cmd_read: | |
6bbf1acd | 1732 | case nvme_cmd_compare: |
6413214c | 1733 | break; |
6c7d4945 | 1734 | default: |
6bbf1acd | 1735 | return -EINVAL; |
6c7d4945 MW |
1736 | } |
1737 | ||
d29ec824 CH |
1738 | length = (io.nblocks + 1) << ns->lba_shift; |
1739 | meta_len = (io.nblocks + 1) * ns->ms; | |
835da3f9 | 1740 | metadata = (void __user *)(uintptr_t)io.metadata; |
d29ec824 | 1741 | write = io.opcode & 1; |
a53295b6 | 1742 | |
71feb364 KB |
1743 | if (ns->ext) { |
1744 | length += meta_len; | |
1745 | meta_len = 0; | |
a67a9513 KB |
1746 | } |
1747 | if (meta_len) { | |
d29ec824 CH |
1748 | if (((io.metadata & 3) || !io.metadata) && !ns->ext) |
1749 | return -EINVAL; | |
1750 | ||
e75ec752 | 1751 | meta = dma_alloc_coherent(dev->dev, meta_len, |
a67a9513 | 1752 | &meta_dma, GFP_KERNEL); |
fec558b5 | 1753 | |
a67a9513 KB |
1754 | if (!meta) { |
1755 | status = -ENOMEM; | |
1756 | goto unmap; | |
1757 | } | |
1758 | if (write) { | |
fec558b5 | 1759 | if (copy_from_user(meta, metadata, meta_len)) { |
a67a9513 KB |
1760 | status = -EFAULT; |
1761 | goto unmap; | |
1762 | } | |
1763 | } | |
1764 | } | |
1765 | ||
a53295b6 MW |
1766 | memset(&c, 0, sizeof(c)); |
1767 | c.rw.opcode = io.opcode; | |
1768 | c.rw.flags = io.flags; | |
6c7d4945 | 1769 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1770 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1771 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1772 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1773 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1774 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1775 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1776 | c.rw.appmask = cpu_to_le16(io.appmask); | |
a67a9513 | 1777 | c.rw.metadata = cpu_to_le64(meta_dma); |
d29ec824 CH |
1778 | |
1779 | status = __nvme_submit_sync_cmd(ns->queue, &c, NULL, | |
835da3f9 | 1780 | (void __user *)(uintptr_t)io.addr, length, NULL, 0); |
f410c680 | 1781 | unmap: |
a67a9513 KB |
1782 | if (meta) { |
1783 | if (status == NVME_SC_SUCCESS && !write) { | |
fec558b5 | 1784 | if (copy_to_user(metadata, meta, meta_len)) |
a67a9513 KB |
1785 | status = -EFAULT; |
1786 | } | |
e75ec752 | 1787 | dma_free_coherent(dev->dev, meta_len, meta, meta_dma); |
f410c680 | 1788 | } |
a53295b6 MW |
1789 | return status; |
1790 | } | |
1791 | ||
1c63dc66 | 1792 | static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns, |
a4aea562 | 1793 | struct nvme_passthru_cmd __user *ucmd) |
6ee44cdc | 1794 | { |
7963e521 | 1795 | struct nvme_passthru_cmd cmd; |
6ee44cdc | 1796 | struct nvme_command c; |
d29ec824 CH |
1797 | unsigned timeout = 0; |
1798 | int status; | |
6ee44cdc | 1799 | |
6bbf1acd MW |
1800 | if (!capable(CAP_SYS_ADMIN)) |
1801 | return -EACCES; | |
1802 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1803 | return -EFAULT; |
6ee44cdc MW |
1804 | |
1805 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1806 | c.common.opcode = cmd.opcode; |
1807 | c.common.flags = cmd.flags; | |
1808 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1809 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1810 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1811 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1812 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1813 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1814 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1815 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1816 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1817 | ||
d29ec824 CH |
1818 | if (cmd.timeout_ms) |
1819 | timeout = msecs_to_jiffies(cmd.timeout_ms); | |
eca18b23 | 1820 | |
1c63dc66 | 1821 | status = __nvme_submit_sync_cmd(ns ? ns->queue : ctrl->admin_q, &c, |
835da3f9 | 1822 | NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len, |
d29ec824 CH |
1823 | &cmd.result, timeout); |
1824 | if (status >= 0) { | |
1825 | if (put_user(cmd.result, &ucmd->result)) | |
1826 | return -EFAULT; | |
6bbf1acd | 1827 | } |
f4f117f6 | 1828 | |
6ee44cdc MW |
1829 | return status; |
1830 | } | |
1831 | ||
81f03fed JD |
1832 | static int nvme_subsys_reset(struct nvme_dev *dev) |
1833 | { | |
1834 | if (!dev->subsystem) | |
1835 | return -ENOTTY; | |
1836 | ||
7a67cbea | 1837 | writel(0x4E564D65, dev->bar + NVME_REG_NSSR); /* "NVMe" */ |
81f03fed JD |
1838 | return 0; |
1839 | } | |
1840 | ||
b60503ba MW |
1841 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1842 | unsigned long arg) | |
1843 | { | |
1844 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1845 | ||
1846 | switch (cmd) { | |
6bbf1acd | 1847 | case NVME_IOCTL_ID: |
c3bfe717 | 1848 | force_successful_syscall_return(); |
6bbf1acd MW |
1849 | return ns->ns_id; |
1850 | case NVME_IOCTL_ADMIN_CMD: | |
1c63dc66 | 1851 | return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg); |
7963e521 | 1852 | case NVME_IOCTL_IO_CMD: |
1c63dc66 | 1853 | return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg); |
a53295b6 MW |
1854 | case NVME_IOCTL_SUBMIT_IO: |
1855 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1856 | case SG_GET_VERSION_NUM: |
1857 | return nvme_sg_get_version_num((void __user *)arg); | |
1858 | case SG_IO: | |
1859 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1860 | default: |
1861 | return -ENOTTY; | |
1862 | } | |
1863 | } | |
1864 | ||
320a3827 KB |
1865 | #ifdef CONFIG_COMPAT |
1866 | static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode, | |
1867 | unsigned int cmd, unsigned long arg) | |
1868 | { | |
320a3827 KB |
1869 | switch (cmd) { |
1870 | case SG_IO: | |
e179729a | 1871 | return -ENOIOCTLCMD; |
320a3827 KB |
1872 | } |
1873 | return nvme_ioctl(bdev, mode, cmd, arg); | |
1874 | } | |
1875 | #else | |
1876 | #define nvme_compat_ioctl NULL | |
1877 | #endif | |
1878 | ||
5105aa55 | 1879 | static void nvme_free_dev(struct kref *kref); |
188c3568 KB |
1880 | static void nvme_free_ns(struct kref *kref) |
1881 | { | |
1882 | struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref); | |
1c63dc66 | 1883 | struct nvme_dev *dev = to_nvme_dev(ns->ctrl); |
188c3568 | 1884 | |
ca064085 MB |
1885 | if (ns->type == NVME_NS_LIGHTNVM) |
1886 | nvme_nvm_unregister(ns->queue, ns->disk->disk_name); | |
1887 | ||
188c3568 KB |
1888 | spin_lock(&dev_list_lock); |
1889 | ns->disk->private_data = NULL; | |
1890 | spin_unlock(&dev_list_lock); | |
1891 | ||
1c63dc66 | 1892 | kref_put(&dev->kref, nvme_free_dev); |
188c3568 KB |
1893 | put_disk(ns->disk); |
1894 | kfree(ns); | |
1895 | } | |
1896 | ||
9ac27090 KB |
1897 | static int nvme_open(struct block_device *bdev, fmode_t mode) |
1898 | { | |
9e60352c KB |
1899 | int ret = 0; |
1900 | struct nvme_ns *ns; | |
9ac27090 | 1901 | |
9e60352c KB |
1902 | spin_lock(&dev_list_lock); |
1903 | ns = bdev->bd_disk->private_data; | |
1904 | if (!ns) | |
1905 | ret = -ENXIO; | |
188c3568 | 1906 | else if (!kref_get_unless_zero(&ns->kref)) |
9e60352c KB |
1907 | ret = -ENXIO; |
1908 | spin_unlock(&dev_list_lock); | |
1909 | ||
1910 | return ret; | |
9ac27090 KB |
1911 | } |
1912 | ||
9ac27090 KB |
1913 | static void nvme_release(struct gendisk *disk, fmode_t mode) |
1914 | { | |
1915 | struct nvme_ns *ns = disk->private_data; | |
188c3568 | 1916 | kref_put(&ns->kref, nvme_free_ns); |
9ac27090 KB |
1917 | } |
1918 | ||
4cc09e2d KB |
1919 | static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo) |
1920 | { | |
1921 | /* some standard values */ | |
1922 | geo->heads = 1 << 6; | |
1923 | geo->sectors = 1 << 5; | |
1924 | geo->cylinders = get_capacity(bd->bd_disk) >> 11; | |
1925 | return 0; | |
1926 | } | |
1927 | ||
e1e5e564 KB |
1928 | static void nvme_config_discard(struct nvme_ns *ns) |
1929 | { | |
1930 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1931 | ns->queue->limits.discard_zeroes_data = 0; | |
1932 | ns->queue->limits.discard_alignment = logical_block_size; | |
1933 | ns->queue->limits.discard_granularity = logical_block_size; | |
2bb4cd5c | 1934 | blk_queue_max_discard_sectors(ns->queue, 0xffffffff); |
e1e5e564 KB |
1935 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); |
1936 | } | |
1937 | ||
1b9dbf7f KB |
1938 | static int nvme_revalidate_disk(struct gendisk *disk) |
1939 | { | |
1940 | struct nvme_ns *ns = disk->private_data; | |
1c63dc66 | 1941 | struct nvme_dev *dev = to_nvme_dev(ns->ctrl); |
1b9dbf7f | 1942 | struct nvme_id_ns *id; |
a67a9513 KB |
1943 | u8 lbaf, pi_type; |
1944 | u16 old_ms; | |
e1e5e564 | 1945 | unsigned short bs; |
1b9dbf7f | 1946 | |
1c63dc66 | 1947 | if (nvme_identify_ns(&dev->ctrl, ns->ns_id, &id)) { |
a5768aa8 | 1948 | dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__, |
1c63dc66 | 1949 | dev->ctrl.instance, ns->ns_id); |
a5768aa8 | 1950 | return -ENODEV; |
1b9dbf7f | 1951 | } |
a5768aa8 KB |
1952 | if (id->ncap == 0) { |
1953 | kfree(id); | |
1954 | return -ENODEV; | |
e1e5e564 | 1955 | } |
1b9dbf7f | 1956 | |
ca064085 MB |
1957 | if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) { |
1958 | if (nvme_nvm_register(ns->queue, disk->disk_name)) { | |
1959 | dev_warn(dev->dev, | |
1960 | "%s: LightNVM init failure\n", __func__); | |
1961 | kfree(id); | |
1962 | return -ENODEV; | |
1963 | } | |
1964 | ns->type = NVME_NS_LIGHTNVM; | |
1965 | } | |
1966 | ||
e1e5e564 KB |
1967 | old_ms = ns->ms; |
1968 | lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK; | |
1b9dbf7f | 1969 | ns->lba_shift = id->lbaf[lbaf].ds; |
e1e5e564 | 1970 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
a67a9513 | 1971 | ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT); |
e1e5e564 KB |
1972 | |
1973 | /* | |
1974 | * If identify namespace failed, use default 512 byte block size so | |
1975 | * block layer can use before failing read/write for 0 capacity. | |
1976 | */ | |
1977 | if (ns->lba_shift == 0) | |
1978 | ns->lba_shift = 9; | |
1979 | bs = 1 << ns->lba_shift; | |
1980 | ||
1981 | /* XXX: PI implementation requires metadata equal t10 pi tuple size */ | |
1982 | pi_type = ns->ms == sizeof(struct t10_pi_tuple) ? | |
1983 | id->dps & NVME_NS_DPS_PI_MASK : 0; | |
1984 | ||
4cfc766e | 1985 | blk_mq_freeze_queue(disk->queue); |
52b68d7e KB |
1986 | if (blk_get_integrity(disk) && (ns->pi_type != pi_type || |
1987 | ns->ms != old_ms || | |
e1e5e564 | 1988 | bs != queue_logical_block_size(disk->queue) || |
a67a9513 | 1989 | (ns->ms && ns->ext))) |
e1e5e564 KB |
1990 | blk_integrity_unregister(disk); |
1991 | ||
1992 | ns->pi_type = pi_type; | |
1993 | blk_queue_logical_block_size(ns->queue, bs); | |
1994 | ||
25520d55 | 1995 | if (ns->ms && !ns->ext) |
e1e5e564 KB |
1996 | nvme_init_integrity(ns); |
1997 | ||
ca064085 MB |
1998 | if ((ns->ms && !(ns->ms == 8 && ns->pi_type) && |
1999 | !blk_get_integrity(disk)) || | |
2000 | ns->type == NVME_NS_LIGHTNVM) | |
e1e5e564 KB |
2001 | set_capacity(disk, 0); |
2002 | else | |
2003 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
2004 | ||
1c63dc66 | 2005 | if (dev->ctrl.oncs & NVME_CTRL_ONCS_DSM) |
e1e5e564 | 2006 | nvme_config_discard(ns); |
4cfc766e | 2007 | blk_mq_unfreeze_queue(disk->queue); |
1b9dbf7f | 2008 | |
d29ec824 | 2009 | kfree(id); |
1b9dbf7f KB |
2010 | return 0; |
2011 | } | |
2012 | ||
1d277a63 KB |
2013 | static char nvme_pr_type(enum pr_type type) |
2014 | { | |
2015 | switch (type) { | |
2016 | case PR_WRITE_EXCLUSIVE: | |
2017 | return 1; | |
2018 | case PR_EXCLUSIVE_ACCESS: | |
2019 | return 2; | |
2020 | case PR_WRITE_EXCLUSIVE_REG_ONLY: | |
2021 | return 3; | |
2022 | case PR_EXCLUSIVE_ACCESS_REG_ONLY: | |
2023 | return 4; | |
2024 | case PR_WRITE_EXCLUSIVE_ALL_REGS: | |
2025 | return 5; | |
2026 | case PR_EXCLUSIVE_ACCESS_ALL_REGS: | |
2027 | return 6; | |
2028 | default: | |
2029 | return 0; | |
2030 | } | |
2031 | }; | |
2032 | ||
2033 | static int nvme_pr_command(struct block_device *bdev, u32 cdw10, | |
2034 | u64 key, u64 sa_key, u8 op) | |
2035 | { | |
2036 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
2037 | struct nvme_command c; | |
2038 | u8 data[16] = { 0, }; | |
2039 | ||
2040 | put_unaligned_le64(key, &data[0]); | |
2041 | put_unaligned_le64(sa_key, &data[8]); | |
2042 | ||
2043 | memset(&c, 0, sizeof(c)); | |
2044 | c.common.opcode = op; | |
a6dd1020 CH |
2045 | c.common.nsid = cpu_to_le32(ns->ns_id); |
2046 | c.common.cdw10[0] = cpu_to_le32(cdw10); | |
1d277a63 KB |
2047 | |
2048 | return nvme_submit_sync_cmd(ns->queue, &c, data, 16); | |
2049 | } | |
2050 | ||
2051 | static int nvme_pr_register(struct block_device *bdev, u64 old, | |
2052 | u64 new, unsigned flags) | |
2053 | { | |
2054 | u32 cdw10; | |
2055 | ||
2056 | if (flags & ~PR_FL_IGNORE_KEY) | |
2057 | return -EOPNOTSUPP; | |
2058 | ||
2059 | cdw10 = old ? 2 : 0; | |
2060 | cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0; | |
2061 | cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */ | |
2062 | return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register); | |
2063 | } | |
2064 | ||
2065 | static int nvme_pr_reserve(struct block_device *bdev, u64 key, | |
2066 | enum pr_type type, unsigned flags) | |
2067 | { | |
2068 | u32 cdw10; | |
2069 | ||
2070 | if (flags & ~PR_FL_IGNORE_KEY) | |
2071 | return -EOPNOTSUPP; | |
2072 | ||
2073 | cdw10 = nvme_pr_type(type) << 8; | |
2074 | cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0); | |
2075 | return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire); | |
2076 | } | |
2077 | ||
2078 | static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new, | |
2079 | enum pr_type type, bool abort) | |
2080 | { | |
2081 | u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1; | |
2082 | return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire); | |
2083 | } | |
2084 | ||
2085 | static int nvme_pr_clear(struct block_device *bdev, u64 key) | |
2086 | { | |
73fcf4e2 | 2087 | u32 cdw10 = 1 | (key ? 1 << 3 : 0); |
1d277a63 KB |
2088 | return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register); |
2089 | } | |
2090 | ||
2091 | static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type) | |
2092 | { | |
2093 | u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0; | |
2094 | return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release); | |
2095 | } | |
2096 | ||
2097 | static const struct pr_ops nvme_pr_ops = { | |
2098 | .pr_register = nvme_pr_register, | |
2099 | .pr_reserve = nvme_pr_reserve, | |
2100 | .pr_release = nvme_pr_release, | |
2101 | .pr_preempt = nvme_pr_preempt, | |
2102 | .pr_clear = nvme_pr_clear, | |
2103 | }; | |
2104 | ||
b60503ba MW |
2105 | static const struct block_device_operations nvme_fops = { |
2106 | .owner = THIS_MODULE, | |
2107 | .ioctl = nvme_ioctl, | |
320a3827 | 2108 | .compat_ioctl = nvme_compat_ioctl, |
9ac27090 KB |
2109 | .open = nvme_open, |
2110 | .release = nvme_release, | |
4cc09e2d | 2111 | .getgeo = nvme_getgeo, |
1b9dbf7f | 2112 | .revalidate_disk= nvme_revalidate_disk, |
1d277a63 | 2113 | .pr_ops = &nvme_pr_ops, |
b60503ba MW |
2114 | }; |
2115 | ||
1fa6aead MW |
2116 | static int nvme_kthread(void *data) |
2117 | { | |
d4b4ff8e | 2118 | struct nvme_dev *dev, *next; |
1fa6aead MW |
2119 | |
2120 | while (!kthread_should_stop()) { | |
564a232c | 2121 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 2122 | spin_lock(&dev_list_lock); |
d4b4ff8e | 2123 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 2124 | int i; |
7a67cbea | 2125 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 KB |
2126 | |
2127 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || | |
2128 | csts & NVME_CSTS_CFS) { | |
90667892 CH |
2129 | if (!__nvme_reset(dev)) { |
2130 | dev_warn(dev->dev, | |
2131 | "Failed status: %x, reset controller\n", | |
7a67cbea | 2132 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 2133 | } |
d4b4ff8e KB |
2134 | continue; |
2135 | } | |
1fa6aead | 2136 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 2137 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
2138 | if (!nvmeq) |
2139 | continue; | |
1fa6aead | 2140 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 2141 | nvme_process_cq(nvmeq); |
6fccf938 | 2142 | |
1c63dc66 | 2143 | while (i == 0 && dev->ctrl.event_limit > 0) { |
a4aea562 | 2144 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 | 2145 | break; |
1c63dc66 | 2146 | dev->ctrl.event_limit--; |
6fccf938 | 2147 | } |
1fa6aead MW |
2148 | spin_unlock_irq(&nvmeq->q_lock); |
2149 | } | |
2150 | } | |
2151 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 2152 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
2153 | } |
2154 | return 0; | |
2155 | } | |
2156 | ||
e1e5e564 | 2157 | static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid) |
b60503ba MW |
2158 | { |
2159 | struct nvme_ns *ns; | |
2160 | struct gendisk *disk; | |
e75ec752 | 2161 | int node = dev_to_node(dev->dev); |
b60503ba | 2162 | |
a4aea562 | 2163 | ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); |
b60503ba | 2164 | if (!ns) |
e1e5e564 KB |
2165 | return; |
2166 | ||
a4aea562 | 2167 | ns->queue = blk_mq_init_queue(&dev->tagset); |
9f173b33 | 2168 | if (IS_ERR(ns->queue)) |
b60503ba | 2169 | goto out_free_ns; |
4eeb9215 MW |
2170 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); |
2171 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
1c63dc66 | 2172 | ns->ctrl = &dev->ctrl; |
b60503ba MW |
2173 | ns->queue->queuedata = ns; |
2174 | ||
a4aea562 | 2175 | disk = alloc_disk_node(0, node); |
b60503ba MW |
2176 | if (!disk) |
2177 | goto out_free_queue; | |
a4aea562 | 2178 | |
188c3568 | 2179 | kref_init(&ns->kref); |
5aff9382 | 2180 | ns->ns_id = nsid; |
b60503ba | 2181 | ns->disk = disk; |
e1e5e564 KB |
2182 | ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */ |
2183 | list_add_tail(&ns->list, &dev->namespaces); | |
2184 | ||
e9ef4636 | 2185 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
e824410f | 2186 | if (dev->max_hw_sectors) { |
8fc23e03 | 2187 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); |
e824410f | 2188 | blk_queue_max_segments(ns->queue, |
6824c5ef | 2189 | (dev->max_hw_sectors / (dev->page_size >> 9)) + 1); |
e824410f | 2190 | } |
a4aea562 MB |
2191 | if (dev->stripe_size) |
2192 | blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9); | |
1c63dc66 | 2193 | if (dev->ctrl.vwc & NVME_CTRL_VWC_PRESENT) |
a7d2ce28 | 2194 | blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA); |
03100aad | 2195 | blk_queue_virt_boundary(ns->queue, dev->page_size - 1); |
b60503ba MW |
2196 | |
2197 | disk->major = nvme_major; | |
469071a3 | 2198 | disk->first_minor = 0; |
b60503ba MW |
2199 | disk->fops = &nvme_fops; |
2200 | disk->private_data = ns; | |
2201 | disk->queue = ns->queue; | |
b3fffdef | 2202 | disk->driverfs_dev = dev->device; |
469071a3 | 2203 | disk->flags = GENHD_FL_EXT_DEVT; |
1c63dc66 | 2204 | sprintf(disk->disk_name, "nvme%dn%d", dev->ctrl.instance, nsid); |
b60503ba | 2205 | |
e1e5e564 KB |
2206 | /* |
2207 | * Initialize capacity to 0 until we establish the namespace format and | |
2208 | * setup integrity extentions if necessary. The revalidate_disk after | |
2209 | * add_disk allows the driver to register with integrity if the format | |
2210 | * requires it. | |
2211 | */ | |
2212 | set_capacity(disk, 0); | |
a5768aa8 KB |
2213 | if (nvme_revalidate_disk(ns->disk)) |
2214 | goto out_free_disk; | |
2215 | ||
5105aa55 | 2216 | kref_get(&dev->kref); |
ca064085 MB |
2217 | if (ns->type != NVME_NS_LIGHTNVM) { |
2218 | add_disk(ns->disk); | |
2219 | if (ns->ms) { | |
2220 | struct block_device *bd = bdget_disk(ns->disk, 0); | |
2221 | if (!bd) | |
2222 | return; | |
2223 | if (blkdev_get(bd, FMODE_READ, NULL)) { | |
2224 | bdput(bd); | |
2225 | return; | |
2226 | } | |
2227 | blkdev_reread_part(bd); | |
2228 | blkdev_put(bd, FMODE_READ); | |
7bee6074 | 2229 | } |
7bee6074 | 2230 | } |
e1e5e564 | 2231 | return; |
a5768aa8 KB |
2232 | out_free_disk: |
2233 | kfree(disk); | |
2234 | list_del(&ns->list); | |
b60503ba MW |
2235 | out_free_queue: |
2236 | blk_cleanup_queue(ns->queue); | |
2237 | out_free_ns: | |
2238 | kfree(ns); | |
b60503ba MW |
2239 | } |
2240 | ||
2659e57b CH |
2241 | /* |
2242 | * Create I/O queues. Failing to create an I/O queue is not an issue, | |
2243 | * we can continue with less than the desired amount of queues, and | |
2244 | * even a controller without I/O queues an still be used to issue | |
2245 | * admin commands. This might be useful to upgrade a buggy firmware | |
2246 | * for example. | |
2247 | */ | |
42f61420 KB |
2248 | static void nvme_create_io_queues(struct nvme_dev *dev) |
2249 | { | |
a4aea562 | 2250 | unsigned i; |
42f61420 | 2251 | |
a4aea562 | 2252 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 2253 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
2254 | break; |
2255 | ||
a4aea562 | 2256 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2659e57b CH |
2257 | if (nvme_create_queue(dev->queues[i], i)) { |
2258 | nvme_free_queues(dev, i); | |
42f61420 | 2259 | break; |
2659e57b | 2260 | } |
42f61420 KB |
2261 | } |
2262 | ||
b3b06812 | 2263 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
2264 | { |
2265 | int status; | |
2266 | u32 result; | |
b3b06812 | 2267 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 2268 | |
1c63dc66 | 2269 | status = nvme_set_features(&dev->ctrl, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 2270 | &result); |
27e8166c MW |
2271 | if (status < 0) |
2272 | return status; | |
2273 | if (status > 0) { | |
e75ec752 | 2274 | dev_err(dev->dev, "Could not set queue count (%d)\n", status); |
badc34d4 | 2275 | return 0; |
27e8166c | 2276 | } |
b60503ba MW |
2277 | return min(result & 0xffff, result >> 16) + 1; |
2278 | } | |
2279 | ||
8ffaadf7 JD |
2280 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
2281 | { | |
2282 | u64 szu, size, offset; | |
2283 | u32 cmbloc; | |
2284 | resource_size_t bar_size; | |
2285 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
2286 | void __iomem *cmb; | |
2287 | dma_addr_t dma_addr; | |
2288 | ||
2289 | if (!use_cmb_sqes) | |
2290 | return NULL; | |
2291 | ||
7a67cbea | 2292 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
2293 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
2294 | return NULL; | |
2295 | ||
7a67cbea | 2296 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
2297 | |
2298 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
2299 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
2300 | offset = szu * NVME_CMB_OFST(cmbloc); | |
2301 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
2302 | ||
2303 | if (offset > bar_size) | |
2304 | return NULL; | |
2305 | ||
2306 | /* | |
2307 | * Controllers may support a CMB size larger than their BAR, | |
2308 | * for example, due to being behind a bridge. Reduce the CMB to | |
2309 | * the reported size of the BAR | |
2310 | */ | |
2311 | if (size > bar_size - offset) | |
2312 | size = bar_size - offset; | |
2313 | ||
2314 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
2315 | cmb = ioremap_wc(dma_addr, size); | |
2316 | if (!cmb) | |
2317 | return NULL; | |
2318 | ||
2319 | dev->cmb_dma_addr = dma_addr; | |
2320 | dev->cmb_size = size; | |
2321 | return cmb; | |
2322 | } | |
2323 | ||
2324 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
2325 | { | |
2326 | if (dev->cmb) { | |
2327 | iounmap(dev->cmb); | |
2328 | dev->cmb = NULL; | |
2329 | } | |
2330 | } | |
2331 | ||
9d713c2b KB |
2332 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
2333 | { | |
b80d5ccc | 2334 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
2335 | } |
2336 | ||
8d85fce7 | 2337 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2338 | { |
a4aea562 | 2339 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 2340 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 2341 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 2342 | |
42f61420 | 2343 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 2344 | result = set_queue_count(dev, nr_io_queues); |
badc34d4 | 2345 | if (result <= 0) |
1b23484b | 2346 | return result; |
b348b7d5 MW |
2347 | if (result < nr_io_queues) |
2348 | nr_io_queues = result; | |
b60503ba | 2349 | |
8ffaadf7 JD |
2350 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
2351 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
2352 | sizeof(struct nvme_command)); | |
2353 | if (result > 0) | |
2354 | dev->q_depth = result; | |
2355 | else | |
2356 | nvme_release_cmb(dev); | |
2357 | } | |
2358 | ||
9d713c2b KB |
2359 | size = db_bar_size(dev, nr_io_queues); |
2360 | if (size > 8192) { | |
f1938f6e | 2361 | iounmap(dev->bar); |
9d713c2b KB |
2362 | do { |
2363 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
2364 | if (dev->bar) | |
2365 | break; | |
2366 | if (!--nr_io_queues) | |
2367 | return -ENOMEM; | |
2368 | size = db_bar_size(dev, nr_io_queues); | |
2369 | } while (1); | |
7a67cbea | 2370 | dev->dbs = dev->bar + 4096; |
5a92e700 | 2371 | adminq->q_db = dev->dbs; |
f1938f6e MW |
2372 | } |
2373 | ||
9d713c2b | 2374 | /* Deregister the admin queue's interrupt */ |
3193f07b | 2375 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 2376 | |
e32efbfc JA |
2377 | /* |
2378 | * If we enable msix early due to not intx, disable it again before | |
2379 | * setting up the full range we need. | |
2380 | */ | |
2381 | if (!pdev->irq) | |
2382 | pci_disable_msix(pdev); | |
2383 | ||
be577fab | 2384 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 2385 | dev->entry[i].entry = i; |
be577fab AG |
2386 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
2387 | if (vecs < 0) { | |
2388 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
2389 | if (vecs < 0) { | |
2390 | vecs = 1; | |
2391 | } else { | |
2392 | for (i = 0; i < vecs; i++) | |
2393 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
2394 | } |
2395 | } | |
2396 | ||
063a8096 MW |
2397 | /* |
2398 | * Should investigate if there's a performance win from allocating | |
2399 | * more queues than interrupt vectors; it might allow the submission | |
2400 | * path to scale better, even if the receive path is limited by the | |
2401 | * number of interrupts. | |
2402 | */ | |
2403 | nr_io_queues = vecs; | |
42f61420 | 2404 | dev->max_qid = nr_io_queues; |
063a8096 | 2405 | |
3193f07b | 2406 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
2407 | if (result) { |
2408 | adminq->cq_vector = -1; | |
22404274 | 2409 | goto free_queues; |
758dd7fd | 2410 | } |
1b23484b | 2411 | |
cd638946 | 2412 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 2413 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 2414 | nvme_create_io_queues(dev); |
9ecdc946 | 2415 | |
22404274 | 2416 | return 0; |
b60503ba | 2417 | |
22404274 | 2418 | free_queues: |
a1a5ef99 | 2419 | nvme_free_queues(dev, 1); |
22404274 | 2420 | return result; |
b60503ba MW |
2421 | } |
2422 | ||
a5768aa8 KB |
2423 | static int ns_cmp(void *priv, struct list_head *a, struct list_head *b) |
2424 | { | |
2425 | struct nvme_ns *nsa = container_of(a, struct nvme_ns, list); | |
2426 | struct nvme_ns *nsb = container_of(b, struct nvme_ns, list); | |
2427 | ||
2428 | return nsa->ns_id - nsb->ns_id; | |
2429 | } | |
2430 | ||
2431 | static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid) | |
2432 | { | |
2433 | struct nvme_ns *ns; | |
2434 | ||
2435 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2436 | if (ns->ns_id == nsid) | |
2437 | return ns; | |
2438 | if (ns->ns_id > nsid) | |
2439 | break; | |
2440 | } | |
2441 | return NULL; | |
2442 | } | |
2443 | ||
2444 | static inline bool nvme_io_incapable(struct nvme_dev *dev) | |
2445 | { | |
7a67cbea CH |
2446 | return (!dev->bar || |
2447 | readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_CFS || | |
2448 | dev->online_queues < 2); | |
a5768aa8 KB |
2449 | } |
2450 | ||
2451 | static void nvme_ns_remove(struct nvme_ns *ns) | |
2452 | { | |
1c63dc66 CH |
2453 | bool kill = nvme_io_incapable(to_nvme_dev(ns->ctrl)) && |
2454 | !blk_queue_dying(ns->queue); | |
a5768aa8 KB |
2455 | |
2456 | if (kill) | |
2457 | blk_set_queue_dying(ns->queue); | |
9609b994 | 2458 | if (ns->disk->flags & GENHD_FL_UP) |
a5768aa8 | 2459 | del_gendisk(ns->disk); |
a5768aa8 KB |
2460 | if (kill || !blk_queue_dying(ns->queue)) { |
2461 | blk_mq_abort_requeue_list(ns->queue); | |
2462 | blk_cleanup_queue(ns->queue); | |
5105aa55 KB |
2463 | } |
2464 | list_del_init(&ns->list); | |
2465 | kref_put(&ns->kref, nvme_free_ns); | |
a5768aa8 KB |
2466 | } |
2467 | ||
2468 | static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn) | |
2469 | { | |
2470 | struct nvme_ns *ns, *next; | |
2471 | unsigned i; | |
2472 | ||
2473 | for (i = 1; i <= nn; i++) { | |
2474 | ns = nvme_find_ns(dev, i); | |
2475 | if (ns) { | |
5105aa55 | 2476 | if (revalidate_disk(ns->disk)) |
a5768aa8 | 2477 | nvme_ns_remove(ns); |
a5768aa8 KB |
2478 | } else |
2479 | nvme_alloc_ns(dev, i); | |
2480 | } | |
2481 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
5105aa55 | 2482 | if (ns->ns_id > nn) |
a5768aa8 | 2483 | nvme_ns_remove(ns); |
a5768aa8 KB |
2484 | } |
2485 | list_sort(NULL, &dev->namespaces, ns_cmp); | |
2486 | } | |
2487 | ||
bda4e0fb KB |
2488 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
2489 | { | |
2490 | struct nvme_queue *nvmeq; | |
2491 | int i; | |
2492 | ||
2493 | for (i = 0; i < dev->online_queues; i++) { | |
2494 | nvmeq = dev->queues[i]; | |
2495 | ||
2496 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
2497 | continue; | |
2498 | ||
2499 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
2500 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
2501 | } | |
2502 | } | |
2503 | ||
a5768aa8 KB |
2504 | static void nvme_dev_scan(struct work_struct *work) |
2505 | { | |
2506 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
2507 | struct nvme_id_ctrl *ctrl; | |
2508 | ||
2509 | if (!dev->tagset.tags) | |
2510 | return; | |
1c63dc66 | 2511 | if (nvme_identify_ctrl(&dev->ctrl, &ctrl)) |
a5768aa8 KB |
2512 | return; |
2513 | nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn)); | |
2514 | kfree(ctrl); | |
bda4e0fb | 2515 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
2516 | } |
2517 | ||
422ef0c7 MW |
2518 | /* |
2519 | * Return: error value if an error occurred setting up the queues or calling | |
2520 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2521 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2522 | * failures should be reported. | |
2523 | */ | |
8d85fce7 | 2524 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2525 | { |
e75ec752 | 2526 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
c3bfe717 | 2527 | int res; |
51814232 | 2528 | struct nvme_id_ctrl *ctrl; |
7a67cbea | 2529 | int shift = NVME_CAP_MPSMIN(lo_hi_readq(dev->bar + NVME_REG_CAP)) + 12; |
b60503ba | 2530 | |
1c63dc66 | 2531 | res = nvme_identify_ctrl(&dev->ctrl, &ctrl); |
b60503ba | 2532 | if (res) { |
e75ec752 | 2533 | dev_err(dev->dev, "Identify Controller failed (%d)\n", res); |
e1e5e564 | 2534 | return -EIO; |
b60503ba MW |
2535 | } |
2536 | ||
1c63dc66 CH |
2537 | dev->ctrl.oncs = le16_to_cpup(&ctrl->oncs); |
2538 | dev->ctrl.abort_limit = ctrl->acl + 1; | |
2539 | dev->ctrl.vwc = ctrl->vwc; | |
2540 | memcpy(dev->ctrl.serial, ctrl->sn, sizeof(ctrl->sn)); | |
2541 | memcpy(dev->ctrl.model, ctrl->mn, sizeof(ctrl->mn)); | |
2542 | memcpy(dev->ctrl.firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 2543 | if (ctrl->mdts) |
8fc23e03 | 2544 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
b12363d0 S |
2545 | else |
2546 | dev->max_hw_sectors = UINT_MAX; | |
68608c26 | 2547 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL) && |
a4aea562 MB |
2548 | (pdev->device == 0x0953) && ctrl->vs[3]) { |
2549 | unsigned int max_hw_sectors; | |
2550 | ||
159b67d7 | 2551 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); |
a4aea562 MB |
2552 | max_hw_sectors = dev->stripe_size >> (shift - 9); |
2553 | if (dev->max_hw_sectors) { | |
2554 | dev->max_hw_sectors = min(max_hw_sectors, | |
2555 | dev->max_hw_sectors); | |
2556 | } else | |
2557 | dev->max_hw_sectors = max_hw_sectors; | |
2558 | } | |
d29ec824 | 2559 | kfree(ctrl); |
a4aea562 | 2560 | |
ffe7704d KB |
2561 | if (!dev->tagset.tags) { |
2562 | dev->tagset.ops = &nvme_mq_ops; | |
2563 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2564 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
2565 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
2566 | dev->tagset.queue_depth = | |
a4aea562 | 2567 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
2568 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
2569 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
2570 | dev->tagset.driver_data = dev; | |
b60503ba | 2571 | |
ffe7704d KB |
2572 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
2573 | return 0; | |
2574 | } | |
a5768aa8 | 2575 | schedule_work(&dev->scan_work); |
e1e5e564 | 2576 | return 0; |
b60503ba MW |
2577 | } |
2578 | ||
0877cb0d KB |
2579 | static int nvme_dev_map(struct nvme_dev *dev) |
2580 | { | |
42f61420 | 2581 | u64 cap; |
0877cb0d | 2582 | int bars, result = -ENOMEM; |
e75ec752 | 2583 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
2584 | |
2585 | if (pci_enable_device_mem(pdev)) | |
2586 | return result; | |
2587 | ||
2588 | dev->entry[0].vector = pdev->irq; | |
2589 | pci_set_master(pdev); | |
2590 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
2591 | if (!bars) |
2592 | goto disable_pci; | |
2593 | ||
0877cb0d KB |
2594 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
2595 | goto disable_pci; | |
2596 | ||
e75ec752 CH |
2597 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
2598 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 2599 | goto disable; |
0877cb0d | 2600 | |
0877cb0d KB |
2601 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2602 | if (!dev->bar) | |
2603 | goto disable; | |
e32efbfc | 2604 | |
7a67cbea | 2605 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
2606 | result = -ENODEV; |
2607 | goto unmap; | |
2608 | } | |
e32efbfc JA |
2609 | |
2610 | /* | |
2611 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
2612 | * MSIX vec for setup. We'll adjust this later. | |
2613 | */ | |
2614 | if (!pdev->irq) { | |
2615 | result = pci_enable_msix(pdev, dev->entry, 1); | |
2616 | if (result < 0) | |
2617 | goto unmap; | |
2618 | } | |
2619 | ||
7a67cbea CH |
2620 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
2621 | ||
42f61420 KB |
2622 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
2623 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
2624 | dev->dbs = dev->bar + 4096; |
2625 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 2626 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d KB |
2627 | |
2628 | return 0; | |
2629 | ||
0e53d180 KB |
2630 | unmap: |
2631 | iounmap(dev->bar); | |
2632 | dev->bar = NULL; | |
0877cb0d KB |
2633 | disable: |
2634 | pci_release_regions(pdev); | |
2635 | disable_pci: | |
2636 | pci_disable_device(pdev); | |
2637 | return result; | |
2638 | } | |
2639 | ||
2640 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
2641 | { | |
e75ec752 CH |
2642 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2643 | ||
2644 | if (pdev->msi_enabled) | |
2645 | pci_disable_msi(pdev); | |
2646 | else if (pdev->msix_enabled) | |
2647 | pci_disable_msix(pdev); | |
0877cb0d KB |
2648 | |
2649 | if (dev->bar) { | |
2650 | iounmap(dev->bar); | |
2651 | dev->bar = NULL; | |
e75ec752 | 2652 | pci_release_regions(pdev); |
0877cb0d KB |
2653 | } |
2654 | ||
e75ec752 CH |
2655 | if (pci_is_enabled(pdev)) |
2656 | pci_disable_device(pdev); | |
0877cb0d KB |
2657 | } |
2658 | ||
4d115420 KB |
2659 | struct nvme_delq_ctx { |
2660 | struct task_struct *waiter; | |
2661 | struct kthread_worker *worker; | |
2662 | atomic_t refcount; | |
2663 | }; | |
2664 | ||
2665 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
2666 | { | |
2667 | dq->waiter = current; | |
2668 | mb(); | |
2669 | ||
2670 | for (;;) { | |
2671 | set_current_state(TASK_KILLABLE); | |
2672 | if (!atomic_read(&dq->refcount)) | |
2673 | break; | |
2674 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
2675 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
2676 | /* |
2677 | * Disable the controller first since we can't trust it | |
2678 | * at this point, but leave the admin queue enabled | |
2679 | * until all queue deletion requests are flushed. | |
2680 | * FIXME: This may take a while if there are more h/w | |
2681 | * queues than admin tags. | |
2682 | */ | |
4d115420 | 2683 | set_current_state(TASK_RUNNING); |
7a67cbea CH |
2684 | nvme_disable_ctrl(dev, |
2685 | lo_hi_readq(dev->bar + NVME_REG_CAP)); | |
0fb59cbc | 2686 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 2687 | flush_kthread_worker(dq->worker); |
0fb59cbc | 2688 | nvme_disable_queue(dev, 0); |
4d115420 KB |
2689 | return; |
2690 | } | |
2691 | } | |
2692 | set_current_state(TASK_RUNNING); | |
2693 | } | |
2694 | ||
2695 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
2696 | { | |
2697 | atomic_dec(&dq->refcount); | |
2698 | if (dq->waiter) | |
2699 | wake_up_process(dq->waiter); | |
2700 | } | |
2701 | ||
2702 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
2703 | { | |
2704 | atomic_inc(&dq->refcount); | |
2705 | return dq; | |
2706 | } | |
2707 | ||
2708 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
2709 | { | |
2710 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 2711 | nvme_put_dq(dq); |
604e8c8d KB |
2712 | |
2713 | spin_lock_irq(&nvmeq->q_lock); | |
2714 | nvme_process_cq(nvmeq); | |
2715 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
2716 | } |
2717 | ||
2718 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
2719 | kthread_work_func_t fn) | |
2720 | { | |
2721 | struct nvme_command c; | |
2722 | ||
2723 | memset(&c, 0, sizeof(c)); | |
2724 | c.delete_queue.opcode = opcode; | |
2725 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
2726 | ||
2727 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
2728 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
2729 | ADMIN_TIMEOUT); | |
4d115420 KB |
2730 | } |
2731 | ||
2732 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
2733 | { | |
2734 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2735 | cmdinfo.work); | |
2736 | nvme_del_queue_end(nvmeq); | |
2737 | } | |
2738 | ||
2739 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
2740 | { | |
2741 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
2742 | nvme_del_cq_work_handler); | |
2743 | } | |
2744 | ||
2745 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
2746 | { | |
2747 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2748 | cmdinfo.work); | |
2749 | int status = nvmeq->cmdinfo.status; | |
2750 | ||
2751 | if (!status) | |
2752 | status = nvme_delete_cq(nvmeq); | |
2753 | if (status) | |
2754 | nvme_del_queue_end(nvmeq); | |
2755 | } | |
2756 | ||
2757 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
2758 | { | |
2759 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
2760 | nvme_del_sq_work_handler); | |
2761 | } | |
2762 | ||
2763 | static void nvme_del_queue_start(struct kthread_work *work) | |
2764 | { | |
2765 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2766 | cmdinfo.work); | |
4d115420 KB |
2767 | if (nvme_delete_sq(nvmeq)) |
2768 | nvme_del_queue_end(nvmeq); | |
2769 | } | |
2770 | ||
2771 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
2772 | { | |
2773 | int i; | |
2774 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
2775 | struct nvme_delq_ctx dq; | |
2776 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 2777 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
2778 | |
2779 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 2780 | dev_err(dev->dev, |
4d115420 KB |
2781 | "Failed to create queue del task\n"); |
2782 | for (i = dev->queue_count - 1; i > 0; i--) | |
2783 | nvme_disable_queue(dev, i); | |
2784 | return; | |
2785 | } | |
2786 | ||
2787 | dq.waiter = NULL; | |
2788 | atomic_set(&dq.refcount, 0); | |
2789 | dq.worker = &worker; | |
2790 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 2791 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
2792 | |
2793 | if (nvme_suspend_queue(nvmeq)) | |
2794 | continue; | |
2795 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2796 | nvmeq->cmdinfo.worker = dq.worker; | |
2797 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2798 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2799 | } | |
2800 | nvme_wait_dq(&dq, dev); | |
2801 | kthread_stop(kworker_task); | |
2802 | } | |
2803 | ||
b9afca3e DM |
2804 | /* |
2805 | * Remove the node from the device list and check | |
2806 | * for whether or not we need to stop the nvme_thread. | |
2807 | */ | |
2808 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2809 | { | |
2810 | struct task_struct *tmp = NULL; | |
2811 | ||
2812 | spin_lock(&dev_list_lock); | |
2813 | list_del_init(&dev->node); | |
2814 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2815 | tmp = nvme_thread; | |
2816 | nvme_thread = NULL; | |
2817 | } | |
2818 | spin_unlock(&dev_list_lock); | |
2819 | ||
2820 | if (tmp) | |
2821 | kthread_stop(tmp); | |
2822 | } | |
2823 | ||
c9d3bf88 KB |
2824 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2825 | { | |
2826 | struct nvme_ns *ns; | |
2827 | ||
2828 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2829 | blk_mq_freeze_queue_start(ns->queue); | |
2830 | ||
cddcd72b | 2831 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 2832 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 2833 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
2834 | |
2835 | blk_mq_cancel_requeue_work(ns->queue); | |
2836 | blk_mq_stop_hw_queues(ns->queue); | |
2837 | } | |
2838 | } | |
2839 | ||
2840 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2841 | { | |
2842 | struct nvme_ns *ns; | |
2843 | ||
2844 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2845 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); | |
2846 | blk_mq_unfreeze_queue(ns->queue); | |
2847 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2848 | blk_mq_kick_requeue_list(ns->queue); | |
2849 | } | |
2850 | } | |
2851 | ||
f0b50732 | 2852 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2853 | { |
22404274 | 2854 | int i; |
7c1b2450 | 2855 | u32 csts = -1; |
22404274 | 2856 | |
b9afca3e | 2857 | nvme_dev_list_remove(dev); |
1fa6aead | 2858 | |
c9d3bf88 KB |
2859 | if (dev->bar) { |
2860 | nvme_freeze_queues(dev); | |
7a67cbea | 2861 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 2862 | } |
7c1b2450 | 2863 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2864 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2865 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2866 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2867 | } |
2868 | } else { | |
2869 | nvme_disable_io_queues(dev); | |
1894d8f1 | 2870 | nvme_shutdown_ctrl(dev); |
4d115420 KB |
2871 | nvme_disable_queue(dev, 0); |
2872 | } | |
f0b50732 | 2873 | nvme_dev_unmap(dev); |
07836e65 KB |
2874 | |
2875 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2876 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2877 | } |
2878 | ||
2879 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2880 | { | |
5105aa55 | 2881 | struct nvme_ns *ns, *next; |
f0b50732 | 2882 | |
5105aa55 | 2883 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) |
a5768aa8 | 2884 | nvme_ns_remove(ns); |
b60503ba MW |
2885 | } |
2886 | ||
091b6092 MW |
2887 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2888 | { | |
e75ec752 | 2889 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2890 | PAGE_SIZE, PAGE_SIZE, 0); |
2891 | if (!dev->prp_page_pool) | |
2892 | return -ENOMEM; | |
2893 | ||
99802a7a | 2894 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2895 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2896 | 256, 256, 0); |
2897 | if (!dev->prp_small_pool) { | |
2898 | dma_pool_destroy(dev->prp_page_pool); | |
2899 | return -ENOMEM; | |
2900 | } | |
091b6092 MW |
2901 | return 0; |
2902 | } | |
2903 | ||
2904 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2905 | { | |
2906 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2907 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2908 | } |
2909 | ||
cd58ad7d QSA |
2910 | static DEFINE_IDA(nvme_instance_ida); |
2911 | ||
2912 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2913 | { |
cd58ad7d QSA |
2914 | int instance, error; |
2915 | ||
2916 | do { | |
2917 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2918 | return -ENODEV; | |
2919 | ||
2920 | spin_lock(&dev_list_lock); | |
2921 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2922 | spin_unlock(&dev_list_lock); | |
2923 | } while (error == -EAGAIN); | |
2924 | ||
2925 | if (error) | |
2926 | return -ENODEV; | |
2927 | ||
1c63dc66 | 2928 | dev->ctrl.instance = instance; |
cd58ad7d | 2929 | return 0; |
b60503ba MW |
2930 | } |
2931 | ||
2932 | static void nvme_release_instance(struct nvme_dev *dev) | |
2933 | { | |
cd58ad7d | 2934 | spin_lock(&dev_list_lock); |
1c63dc66 | 2935 | ida_remove(&nvme_instance_ida, dev->ctrl.instance); |
cd58ad7d | 2936 | spin_unlock(&dev_list_lock); |
b60503ba MW |
2937 | } |
2938 | ||
5e82e952 KB |
2939 | static void nvme_free_dev(struct kref *kref) |
2940 | { | |
2941 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
9ac27090 | 2942 | |
e75ec752 | 2943 | put_device(dev->dev); |
b3fffdef | 2944 | put_device(dev->device); |
285dffc9 | 2945 | nvme_release_instance(dev); |
4af0e21c KB |
2946 | if (dev->tagset.tags) |
2947 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2948 | if (dev->ctrl.admin_q) |
2949 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
2950 | kfree(dev->queues); |
2951 | kfree(dev->entry); | |
2952 | kfree(dev); | |
2953 | } | |
2954 | ||
2955 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2956 | { | |
b3fffdef KB |
2957 | struct nvme_dev *dev; |
2958 | int instance = iminor(inode); | |
2959 | int ret = -ENODEV; | |
2960 | ||
2961 | spin_lock(&dev_list_lock); | |
2962 | list_for_each_entry(dev, &dev_list, node) { | |
1c63dc66 CH |
2963 | if (dev->ctrl.instance == instance) { |
2964 | if (!dev->ctrl.admin_q) { | |
2e1d8448 KB |
2965 | ret = -EWOULDBLOCK; |
2966 | break; | |
2967 | } | |
b3fffdef KB |
2968 | if (!kref_get_unless_zero(&dev->kref)) |
2969 | break; | |
2970 | f->private_data = dev; | |
2971 | ret = 0; | |
2972 | break; | |
2973 | } | |
2974 | } | |
2975 | spin_unlock(&dev_list_lock); | |
2976 | ||
2977 | return ret; | |
5e82e952 KB |
2978 | } |
2979 | ||
2980 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2981 | { | |
2982 | struct nvme_dev *dev = f->private_data; | |
2983 | kref_put(&dev->kref, nvme_free_dev); | |
2984 | return 0; | |
2985 | } | |
2986 | ||
2987 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2988 | { | |
2989 | struct nvme_dev *dev = f->private_data; | |
a4aea562 MB |
2990 | struct nvme_ns *ns; |
2991 | ||
5e82e952 KB |
2992 | switch (cmd) { |
2993 | case NVME_IOCTL_ADMIN_CMD: | |
1c63dc66 | 2994 | return nvme_user_cmd(&dev->ctrl, NULL, (void __user *)arg); |
7963e521 | 2995 | case NVME_IOCTL_IO_CMD: |
a4aea562 MB |
2996 | if (list_empty(&dev->namespaces)) |
2997 | return -ENOTTY; | |
2998 | ns = list_first_entry(&dev->namespaces, struct nvme_ns, list); | |
1c63dc66 | 2999 | return nvme_user_cmd(&dev->ctrl, ns, (void __user *)arg); |
4cc06521 KB |
3000 | case NVME_IOCTL_RESET: |
3001 | dev_warn(dev->dev, "resetting controller\n"); | |
3002 | return nvme_reset(dev); | |
81f03fed JD |
3003 | case NVME_IOCTL_SUBSYS_RESET: |
3004 | return nvme_subsys_reset(dev); | |
5e82e952 KB |
3005 | default: |
3006 | return -ENOTTY; | |
3007 | } | |
3008 | } | |
3009 | ||
3010 | static const struct file_operations nvme_dev_fops = { | |
3011 | .owner = THIS_MODULE, | |
3012 | .open = nvme_dev_open, | |
3013 | .release = nvme_dev_release, | |
3014 | .unlocked_ioctl = nvme_dev_ioctl, | |
3015 | .compat_ioctl = nvme_dev_ioctl, | |
3016 | }; | |
3017 | ||
3cf519b5 | 3018 | static void nvme_probe_work(struct work_struct *work) |
f0b50732 | 3019 | { |
3cf519b5 | 3020 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); |
b9afca3e | 3021 | bool start_thread = false; |
3cf519b5 | 3022 | int result; |
f0b50732 KB |
3023 | |
3024 | result = nvme_dev_map(dev); | |
3025 | if (result) | |
3cf519b5 | 3026 | goto out; |
f0b50732 KB |
3027 | |
3028 | result = nvme_configure_admin_queue(dev); | |
3029 | if (result) | |
3030 | goto unmap; | |
3031 | ||
3032 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
3033 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
3034 | start_thread = true; | |
3035 | nvme_thread = NULL; | |
3036 | } | |
f0b50732 KB |
3037 | list_add(&dev->node, &dev_list); |
3038 | spin_unlock(&dev_list_lock); | |
3039 | ||
b9afca3e DM |
3040 | if (start_thread) { |
3041 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 3042 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
3043 | } else |
3044 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
3045 | ||
3046 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
3047 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
3048 | goto disable; | |
3049 | } | |
a4aea562 MB |
3050 | |
3051 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
3052 | result = nvme_alloc_admin_tags(dev); |
3053 | if (result) | |
3054 | goto disable; | |
b9afca3e | 3055 | |
f0b50732 | 3056 | result = nvme_setup_io_queues(dev); |
badc34d4 | 3057 | if (result) |
0fb59cbc | 3058 | goto free_tags; |
f0b50732 | 3059 | |
1c63dc66 | 3060 | dev->ctrl.event_limit = 1; |
3cf519b5 | 3061 | |
2659e57b CH |
3062 | /* |
3063 | * Keep the controller around but remove all namespaces if we don't have | |
3064 | * any working I/O queue. | |
3065 | */ | |
3cf519b5 CH |
3066 | if (dev->online_queues < 2) { |
3067 | dev_warn(dev->dev, "IO queues not created\n"); | |
3cf519b5 CH |
3068 | nvme_dev_remove(dev); |
3069 | } else { | |
3070 | nvme_unfreeze_queues(dev); | |
3071 | nvme_dev_add(dev); | |
3072 | } | |
3073 | ||
3074 | return; | |
f0b50732 | 3075 | |
0fb59cbc KB |
3076 | free_tags: |
3077 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
3078 | blk_put_queue(dev->ctrl.admin_q); |
3079 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 3080 | dev->queues[0]->tags = NULL; |
f0b50732 | 3081 | disable: |
a1a5ef99 | 3082 | nvme_disable_queue(dev, 0); |
b9afca3e | 3083 | nvme_dev_list_remove(dev); |
f0b50732 KB |
3084 | unmap: |
3085 | nvme_dev_unmap(dev); | |
3cf519b5 CH |
3086 | out: |
3087 | if (!work_busy(&dev->reset_work)) | |
3088 | nvme_dead_ctrl(dev); | |
f0b50732 KB |
3089 | } |
3090 | ||
9a6b9458 KB |
3091 | static int nvme_remove_dead_ctrl(void *arg) |
3092 | { | |
3093 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
e75ec752 | 3094 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
3095 | |
3096 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 3097 | pci_stop_and_remove_bus_device_locked(pdev); |
9a6b9458 KB |
3098 | kref_put(&dev->kref, nvme_free_dev); |
3099 | return 0; | |
3100 | } | |
3101 | ||
de3eff2b KB |
3102 | static void nvme_dead_ctrl(struct nvme_dev *dev) |
3103 | { | |
3104 | dev_warn(dev->dev, "Device failed to resume\n"); | |
3105 | kref_get(&dev->kref); | |
3106 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", | |
1c63dc66 | 3107 | dev->ctrl.instance))) { |
de3eff2b KB |
3108 | dev_err(dev->dev, |
3109 | "Failed to start controller remove task\n"); | |
3110 | kref_put(&dev->kref, nvme_free_dev); | |
3111 | } | |
3112 | } | |
3113 | ||
77b50d9e | 3114 | static void nvme_reset_work(struct work_struct *ws) |
9a6b9458 | 3115 | { |
77b50d9e | 3116 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
ffe7704d KB |
3117 | bool in_probe = work_busy(&dev->probe_work); |
3118 | ||
9a6b9458 | 3119 | nvme_dev_shutdown(dev); |
ffe7704d KB |
3120 | |
3121 | /* Synchronize with device probe so that work will see failure status | |
3122 | * and exit gracefully without trying to schedule another reset */ | |
3123 | flush_work(&dev->probe_work); | |
3124 | ||
3125 | /* Fail this device if reset occured during probe to avoid | |
3126 | * infinite initialization loops. */ | |
3127 | if (in_probe) { | |
de3eff2b | 3128 | nvme_dead_ctrl(dev); |
ffe7704d | 3129 | return; |
9a6b9458 | 3130 | } |
ffe7704d KB |
3131 | /* Schedule device resume asynchronously so the reset work is available |
3132 | * to cleanup errors that may occur during reinitialization */ | |
3133 | schedule_work(&dev->probe_work); | |
9a6b9458 KB |
3134 | } |
3135 | ||
90667892 | 3136 | static int __nvme_reset(struct nvme_dev *dev) |
9ca97374 | 3137 | { |
90667892 CH |
3138 | if (work_pending(&dev->reset_work)) |
3139 | return -EBUSY; | |
3140 | list_del_init(&dev->node); | |
3141 | queue_work(nvme_workq, &dev->reset_work); | |
3142 | return 0; | |
9ca97374 TH |
3143 | } |
3144 | ||
4cc06521 KB |
3145 | static int nvme_reset(struct nvme_dev *dev) |
3146 | { | |
90667892 | 3147 | int ret; |
4cc06521 | 3148 | |
1c63dc66 | 3149 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
3150 | return -ENODEV; |
3151 | ||
3152 | spin_lock(&dev_list_lock); | |
90667892 | 3153 | ret = __nvme_reset(dev); |
4cc06521 KB |
3154 | spin_unlock(&dev_list_lock); |
3155 | ||
3156 | if (!ret) { | |
3157 | flush_work(&dev->reset_work); | |
ffe7704d | 3158 | flush_work(&dev->probe_work); |
4cc06521 KB |
3159 | return 0; |
3160 | } | |
3161 | ||
3162 | return ret; | |
3163 | } | |
3164 | ||
3165 | static ssize_t nvme_sysfs_reset(struct device *dev, | |
3166 | struct device_attribute *attr, const char *buf, | |
3167 | size_t count) | |
3168 | { | |
3169 | struct nvme_dev *ndev = dev_get_drvdata(dev); | |
3170 | int ret; | |
3171 | ||
3172 | ret = nvme_reset(ndev); | |
3173 | if (ret < 0) | |
3174 | return ret; | |
3175 | ||
3176 | return count; | |
3177 | } | |
3178 | static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset); | |
3179 | ||
1c63dc66 CH |
3180 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
3181 | { | |
3182 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
3183 | return 0; | |
3184 | } | |
3185 | ||
3186 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { | |
3187 | .reg_read32 = nvme_pci_reg_read32, | |
3188 | }; | |
3189 | ||
8d85fce7 | 3190 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 3191 | { |
a4aea562 | 3192 | int node, result = -ENOMEM; |
b60503ba MW |
3193 | struct nvme_dev *dev; |
3194 | ||
a4aea562 MB |
3195 | node = dev_to_node(&pdev->dev); |
3196 | if (node == NUMA_NO_NODE) | |
3197 | set_dev_node(&pdev->dev, 0); | |
3198 | ||
3199 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
3200 | if (!dev) |
3201 | return -ENOMEM; | |
a4aea562 MB |
3202 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
3203 | GFP_KERNEL, node); | |
b60503ba MW |
3204 | if (!dev->entry) |
3205 | goto free; | |
a4aea562 MB |
3206 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
3207 | GFP_KERNEL, node); | |
b60503ba MW |
3208 | if (!dev->queues) |
3209 | goto free; | |
3210 | ||
3211 | INIT_LIST_HEAD(&dev->namespaces); | |
77b50d9e | 3212 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
e75ec752 | 3213 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 3214 | pci_set_drvdata(pdev, dev); |
1c63dc66 CH |
3215 | |
3216 | dev->ctrl.ops = &nvme_pci_ctrl_ops; | |
3217 | dev->ctrl.dev = dev->dev; | |
3218 | ||
cd58ad7d QSA |
3219 | result = nvme_set_instance(dev); |
3220 | if (result) | |
a96d4f5c | 3221 | goto put_pci; |
b60503ba | 3222 | |
091b6092 MW |
3223 | result = nvme_setup_prp_pools(dev); |
3224 | if (result) | |
0877cb0d | 3225 | goto release; |
091b6092 | 3226 | |
fb35e914 | 3227 | kref_init(&dev->kref); |
b3fffdef | 3228 | dev->device = device_create(nvme_class, &pdev->dev, |
1c63dc66 CH |
3229 | MKDEV(nvme_char_major, dev->ctrl.instance), |
3230 | dev, "nvme%d", dev->ctrl.instance); | |
b3fffdef KB |
3231 | if (IS_ERR(dev->device)) { |
3232 | result = PTR_ERR(dev->device); | |
2e1d8448 | 3233 | goto release_pools; |
b3fffdef KB |
3234 | } |
3235 | get_device(dev->device); | |
4cc06521 KB |
3236 | dev_set_drvdata(dev->device, dev); |
3237 | ||
3238 | result = device_create_file(dev->device, &dev_attr_reset_controller); | |
3239 | if (result) | |
3240 | goto put_dev; | |
740216fc | 3241 | |
e6e96d73 | 3242 | INIT_LIST_HEAD(&dev->node); |
a5768aa8 | 3243 | INIT_WORK(&dev->scan_work, nvme_dev_scan); |
3cf519b5 | 3244 | INIT_WORK(&dev->probe_work, nvme_probe_work); |
2e1d8448 | 3245 | schedule_work(&dev->probe_work); |
b60503ba MW |
3246 | return 0; |
3247 | ||
4cc06521 | 3248 | put_dev: |
1c63dc66 | 3249 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance)); |
4cc06521 | 3250 | put_device(dev->device); |
0877cb0d | 3251 | release_pools: |
091b6092 | 3252 | nvme_release_prp_pools(dev); |
0877cb0d KB |
3253 | release: |
3254 | nvme_release_instance(dev); | |
a96d4f5c | 3255 | put_pci: |
e75ec752 | 3256 | put_device(dev->dev); |
b60503ba MW |
3257 | free: |
3258 | kfree(dev->queues); | |
3259 | kfree(dev->entry); | |
3260 | kfree(dev); | |
3261 | return result; | |
3262 | } | |
3263 | ||
f0d54a54 KB |
3264 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
3265 | { | |
a6739479 | 3266 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 3267 | |
a6739479 KB |
3268 | if (prepare) |
3269 | nvme_dev_shutdown(dev); | |
3270 | else | |
0a7385ad | 3271 | schedule_work(&dev->probe_work); |
f0d54a54 KB |
3272 | } |
3273 | ||
09ece142 KB |
3274 | static void nvme_shutdown(struct pci_dev *pdev) |
3275 | { | |
3276 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3277 | nvme_dev_shutdown(dev); | |
3278 | } | |
3279 | ||
8d85fce7 | 3280 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3281 | { |
3282 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
3283 | |
3284 | spin_lock(&dev_list_lock); | |
3285 | list_del_init(&dev->node); | |
3286 | spin_unlock(&dev_list_lock); | |
3287 | ||
3288 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 3289 | flush_work(&dev->probe_work); |
9a6b9458 | 3290 | flush_work(&dev->reset_work); |
a5768aa8 | 3291 | flush_work(&dev->scan_work); |
4cc06521 | 3292 | device_remove_file(dev->device, &dev_attr_reset_controller); |
c9d3bf88 | 3293 | nvme_dev_remove(dev); |
3399a3f7 | 3294 | nvme_dev_shutdown(dev); |
a4aea562 | 3295 | nvme_dev_remove_admin(dev); |
1c63dc66 | 3296 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->ctrl.instance)); |
a1a5ef99 | 3297 | nvme_free_queues(dev, 0); |
8ffaadf7 | 3298 | nvme_release_cmb(dev); |
9a6b9458 | 3299 | nvme_release_prp_pools(dev); |
5e82e952 | 3300 | kref_put(&dev->kref, nvme_free_dev); |
b60503ba MW |
3301 | } |
3302 | ||
3303 | /* These functions are yet to be implemented */ | |
3304 | #define nvme_error_detected NULL | |
3305 | #define nvme_dump_registers NULL | |
3306 | #define nvme_link_reset NULL | |
3307 | #define nvme_slot_reset NULL | |
3308 | #define nvme_error_resume NULL | |
cd638946 | 3309 | |
671a6018 | 3310 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3311 | static int nvme_suspend(struct device *dev) |
3312 | { | |
3313 | struct pci_dev *pdev = to_pci_dev(dev); | |
3314 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
3315 | ||
3316 | nvme_dev_shutdown(ndev); | |
3317 | return 0; | |
3318 | } | |
3319 | ||
3320 | static int nvme_resume(struct device *dev) | |
3321 | { | |
3322 | struct pci_dev *pdev = to_pci_dev(dev); | |
3323 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3324 | |
0a7385ad | 3325 | schedule_work(&ndev->probe_work); |
9a6b9458 | 3326 | return 0; |
cd638946 | 3327 | } |
671a6018 | 3328 | #endif |
cd638946 KB |
3329 | |
3330 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 3331 | |
1d352035 | 3332 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
3333 | .error_detected = nvme_error_detected, |
3334 | .mmio_enabled = nvme_dump_registers, | |
3335 | .link_reset = nvme_link_reset, | |
3336 | .slot_reset = nvme_slot_reset, | |
3337 | .resume = nvme_error_resume, | |
f0d54a54 | 3338 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
3339 | }; |
3340 | ||
3341 | /* Move to pci_ids.h later */ | |
3342 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
3343 | ||
6eb0d698 | 3344 | static const struct pci_device_id nvme_id_table[] = { |
b60503ba | 3345 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 3346 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
3347 | { 0, } |
3348 | }; | |
3349 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3350 | ||
3351 | static struct pci_driver nvme_driver = { | |
3352 | .name = "nvme", | |
3353 | .id_table = nvme_id_table, | |
3354 | .probe = nvme_probe, | |
8d85fce7 | 3355 | .remove = nvme_remove, |
09ece142 | 3356 | .shutdown = nvme_shutdown, |
cd638946 KB |
3357 | .driver = { |
3358 | .pm = &nvme_dev_pm_ops, | |
3359 | }, | |
b60503ba MW |
3360 | .err_handler = &nvme_err_handler, |
3361 | }; | |
3362 | ||
3363 | static int __init nvme_init(void) | |
3364 | { | |
0ac13140 | 3365 | int result; |
1fa6aead | 3366 | |
b9afca3e | 3367 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 3368 | |
9a6b9458 KB |
3369 | nvme_workq = create_singlethread_workqueue("nvme"); |
3370 | if (!nvme_workq) | |
b9afca3e | 3371 | return -ENOMEM; |
9a6b9458 | 3372 | |
5c42ea16 KB |
3373 | result = register_blkdev(nvme_major, "nvme"); |
3374 | if (result < 0) | |
9a6b9458 | 3375 | goto kill_workq; |
5c42ea16 | 3376 | else if (result > 0) |
0ac13140 | 3377 | nvme_major = result; |
b60503ba | 3378 | |
b3fffdef KB |
3379 | result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme", |
3380 | &nvme_dev_fops); | |
3381 | if (result < 0) | |
3382 | goto unregister_blkdev; | |
3383 | else if (result > 0) | |
3384 | nvme_char_major = result; | |
3385 | ||
3386 | nvme_class = class_create(THIS_MODULE, "nvme"); | |
c727040b AK |
3387 | if (IS_ERR(nvme_class)) { |
3388 | result = PTR_ERR(nvme_class); | |
b3fffdef | 3389 | goto unregister_chrdev; |
c727040b | 3390 | } |
b3fffdef | 3391 | |
f3db22fe KB |
3392 | result = pci_register_driver(&nvme_driver); |
3393 | if (result) | |
b3fffdef | 3394 | goto destroy_class; |
1fa6aead | 3395 | return 0; |
b60503ba | 3396 | |
b3fffdef KB |
3397 | destroy_class: |
3398 | class_destroy(nvme_class); | |
3399 | unregister_chrdev: | |
3400 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
1fa6aead | 3401 | unregister_blkdev: |
b60503ba | 3402 | unregister_blkdev(nvme_major, "nvme"); |
9a6b9458 KB |
3403 | kill_workq: |
3404 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
3405 | return result; |
3406 | } | |
3407 | ||
3408 | static void __exit nvme_exit(void) | |
3409 | { | |
3410 | pci_unregister_driver(&nvme_driver); | |
3411 | unregister_blkdev(nvme_major, "nvme"); | |
9a6b9458 | 3412 | destroy_workqueue(nvme_workq); |
b3fffdef KB |
3413 | class_destroy(nvme_class); |
3414 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
b9afca3e | 3415 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 3416 | _nvme_check_size(); |
b60503ba MW |
3417 | } |
3418 | ||
3419 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3420 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3421 | MODULE_VERSION("1.0"); |
b60503ba MW |
3422 | module_init(nvme_init); |
3423 | module_exit(nvme_exit); |