Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
8de05535 | 15 | #include <linux/bitops.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
42f61420 | 18 | #include <linux/cpu.h> |
fd63e9ce | 19 | #include <linux/delay.h> |
b60503ba MW |
20 | #include <linux/errno.h> |
21 | #include <linux/fs.h> | |
22 | #include <linux/genhd.h> | |
4cc09e2d | 23 | #include <linux/hdreg.h> |
5aff9382 | 24 | #include <linux/idr.h> |
b60503ba MW |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
1fa6aead | 29 | #include <linux/kthread.h> |
b60503ba MW |
30 | #include <linux/kernel.h> |
31 | #include <linux/mm.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
77bf25ea | 34 | #include <linux/mutex.h> |
b60503ba | 35 | #include <linux/pci.h> |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
b60503ba | 41 | #include <linux/types.h> |
2f8e2c87 | 42 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 43 | #include <asm/unaligned.h> |
797a796a | 44 | |
f11bb3e2 CH |
45 | #include "nvme.h" |
46 | ||
9d43cf64 | 47 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 48 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
49 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
50 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
adf68f21 CH |
51 | |
52 | /* | |
53 | * We handle AEN commands ourselves and don't even let the | |
54 | * block layer know about them. | |
55 | */ | |
56 | #define NVME_NR_AEN_COMMANDS 1 | |
57 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
9d43cf64 | 58 | |
21d34711 | 59 | unsigned char admin_timeout = 60; |
9d43cf64 KB |
60 | module_param(admin_timeout, byte, 0644); |
61 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 62 | |
bd67608a MW |
63 | unsigned char nvme_io_timeout = 30; |
64 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 65 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 66 | |
5fd4ce1b | 67 | unsigned char shutdown_timeout = 5; |
2484f407 DM |
68 | module_param(shutdown_timeout, byte, 0644); |
69 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
70 | ||
58ffacb5 MW |
71 | static int use_threaded_interrupts; |
72 | module_param(use_threaded_interrupts, int, 0); | |
73 | ||
8ffaadf7 JD |
74 | static bool use_cmb_sqes = true; |
75 | module_param(use_cmb_sqes, bool, 0644); | |
76 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
77 | ||
1fa6aead MW |
78 | static LIST_HEAD(dev_list); |
79 | static struct task_struct *nvme_thread; | |
9a6b9458 | 80 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 81 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 82 | |
1c63dc66 CH |
83 | struct nvme_dev; |
84 | struct nvme_queue; | |
85 | ||
4cc06521 | 86 | static int nvme_reset(struct nvme_dev *dev); |
a0fa9647 | 87 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
5c8809e6 | 88 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev); |
e1569a16 | 89 | static void nvme_dev_shutdown(struct nvme_dev *dev); |
d4b4ff8e | 90 | |
4d115420 KB |
91 | struct async_cmd_info { |
92 | struct kthread_work work; | |
93 | struct kthread_worker *worker; | |
4d115420 KB |
94 | int status; |
95 | void *ctx; | |
96 | }; | |
1fa6aead | 97 | |
1c63dc66 CH |
98 | /* |
99 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
100 | */ | |
101 | struct nvme_dev { | |
102 | struct list_head node; | |
103 | struct nvme_queue **queues; | |
104 | struct blk_mq_tag_set tagset; | |
105 | struct blk_mq_tag_set admin_tagset; | |
106 | u32 __iomem *dbs; | |
107 | struct device *dev; | |
108 | struct dma_pool *prp_page_pool; | |
109 | struct dma_pool *prp_small_pool; | |
110 | unsigned queue_count; | |
111 | unsigned online_queues; | |
112 | unsigned max_qid; | |
113 | int q_depth; | |
114 | u32 db_stride; | |
1c63dc66 CH |
115 | struct msix_entry *entry; |
116 | void __iomem *bar; | |
1c63dc66 | 117 | struct work_struct reset_work; |
1c63dc66 | 118 | struct work_struct scan_work; |
5c8809e6 | 119 | struct work_struct remove_work; |
77bf25ea | 120 | struct mutex shutdown_lock; |
1c63dc66 | 121 | bool subsystem; |
1c63dc66 CH |
122 | void __iomem *cmb; |
123 | dma_addr_t cmb_dma_addr; | |
124 | u64 cmb_size; | |
125 | u32 cmbsz; | |
fd634f41 CH |
126 | unsigned long flags; |
127 | #define NVME_CTRL_RESETTING 0 | |
1c63dc66 CH |
128 | |
129 | struct nvme_ctrl ctrl; | |
130 | }; | |
131 | ||
132 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) | |
133 | { | |
134 | return container_of(ctrl, struct nvme_dev, ctrl); | |
135 | } | |
136 | ||
b60503ba MW |
137 | /* |
138 | * An NVM Express queue. Each device has at least two (one for admin | |
139 | * commands and one for I/O commands). | |
140 | */ | |
141 | struct nvme_queue { | |
142 | struct device *q_dmadev; | |
091b6092 | 143 | struct nvme_dev *dev; |
3193f07b | 144 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
145 | spinlock_t q_lock; |
146 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 147 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 148 | volatile struct nvme_completion *cqes; |
42483228 | 149 | struct blk_mq_tags **tags; |
b60503ba MW |
150 | dma_addr_t sq_dma_addr; |
151 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
152 | u32 __iomem *q_db; |
153 | u16 q_depth; | |
6222d172 | 154 | s16 cq_vector; |
b60503ba MW |
155 | u16 sq_head; |
156 | u16 sq_tail; | |
157 | u16 cq_head; | |
c30341dc | 158 | u16 qid; |
e9539f47 MW |
159 | u8 cq_phase; |
160 | u8 cqe_seen; | |
4d115420 | 161 | struct async_cmd_info cmdinfo; |
b60503ba MW |
162 | }; |
163 | ||
71bd150c CH |
164 | /* |
165 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
166 | * entries. You can't see it in this data structure because C doesn't let | |
167 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
168 | * allocated to store the PRP list. | |
169 | */ | |
170 | struct nvme_iod { | |
171 | unsigned long private; /* For the use of the submitter of the I/O */ | |
172 | int npages; /* In the PRP list. 0 means small pool in use */ | |
173 | int offset; /* Of PRP list */ | |
174 | int nents; /* Used in scatterlist */ | |
175 | int length; /* Of data, in bytes */ | |
176 | dma_addr_t first_dma; | |
bf684057 | 177 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
71bd150c CH |
178 | struct scatterlist sg[0]; |
179 | }; | |
180 | ||
b60503ba MW |
181 | /* |
182 | * Check we didin't inadvertently grow the command struct | |
183 | */ | |
184 | static inline void _nvme_check_size(void) | |
185 | { | |
186 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
187 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
188 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
189 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
190 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 191 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 192 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
193 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
194 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
195 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
196 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 197 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
198 | } |
199 | ||
e85248e5 | 200 | struct nvme_cmd_info { |
c30341dc | 201 | int aborted; |
a4aea562 | 202 | struct nvme_queue *nvmeq; |
aae239e1 CH |
203 | struct nvme_iod *iod; |
204 | struct nvme_iod __iod; | |
e85248e5 MW |
205 | }; |
206 | ||
ac3dd5bd JA |
207 | /* |
208 | * Max size of iod being embedded in the request payload | |
209 | */ | |
210 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 211 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
fda631ff | 212 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
213 | |
214 | /* | |
215 | * Will slightly overestimate the number of pages needed. This is OK | |
216 | * as it only leads to a small amount of wasted memory for the lifetime of | |
217 | * the I/O. | |
218 | */ | |
219 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
220 | { | |
5fd4ce1b CH |
221 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
222 | dev->ctrl.page_size); | |
ac3dd5bd JA |
223 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
224 | } | |
225 | ||
226 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
227 | { | |
228 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
229 | ||
230 | ret += sizeof(struct nvme_iod); | |
231 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
232 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
233 | ||
234 | return ret; | |
235 | } | |
236 | ||
a4aea562 MB |
237 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
238 | unsigned int hctx_idx) | |
e85248e5 | 239 | { |
a4aea562 MB |
240 | struct nvme_dev *dev = data; |
241 | struct nvme_queue *nvmeq = dev->queues[0]; | |
242 | ||
42483228 KB |
243 | WARN_ON(hctx_idx != 0); |
244 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
245 | WARN_ON(nvmeq->tags); | |
246 | ||
a4aea562 | 247 | hctx->driver_data = nvmeq; |
42483228 | 248 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 249 | return 0; |
e85248e5 MW |
250 | } |
251 | ||
4af0e21c KB |
252 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
253 | { | |
254 | struct nvme_queue *nvmeq = hctx->driver_data; | |
255 | ||
256 | nvmeq->tags = NULL; | |
257 | } | |
258 | ||
a4aea562 MB |
259 | static int nvme_admin_init_request(void *data, struct request *req, |
260 | unsigned int hctx_idx, unsigned int rq_idx, | |
261 | unsigned int numa_node) | |
22404274 | 262 | { |
a4aea562 MB |
263 | struct nvme_dev *dev = data; |
264 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
265 | struct nvme_queue *nvmeq = dev->queues[0]; | |
266 | ||
267 | BUG_ON(!nvmeq); | |
268 | cmd->nvmeq = nvmeq; | |
269 | return 0; | |
22404274 KB |
270 | } |
271 | ||
a4aea562 MB |
272 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
273 | unsigned int hctx_idx) | |
b60503ba | 274 | { |
a4aea562 | 275 | struct nvme_dev *dev = data; |
42483228 | 276 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 277 | |
42483228 KB |
278 | if (!nvmeq->tags) |
279 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 280 | |
42483228 | 281 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
282 | hctx->driver_data = nvmeq; |
283 | return 0; | |
b60503ba MW |
284 | } |
285 | ||
a4aea562 MB |
286 | static int nvme_init_request(void *data, struct request *req, |
287 | unsigned int hctx_idx, unsigned int rq_idx, | |
288 | unsigned int numa_node) | |
b60503ba | 289 | { |
a4aea562 MB |
290 | struct nvme_dev *dev = data; |
291 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
292 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
293 | ||
294 | BUG_ON(!nvmeq); | |
295 | cmd->nvmeq = nvmeq; | |
296 | return 0; | |
297 | } | |
298 | ||
ac3dd5bd JA |
299 | static void *iod_get_private(struct nvme_iod *iod) |
300 | { | |
301 | return (void *) (iod->private & ~0x1UL); | |
302 | } | |
303 | ||
304 | /* | |
305 | * If bit 0 is set, the iod is embedded in the request payload. | |
306 | */ | |
307 | static bool iod_should_kfree(struct nvme_iod *iod) | |
308 | { | |
fda631ff | 309 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
310 | } |
311 | ||
adf68f21 CH |
312 | static void nvme_complete_async_event(struct nvme_dev *dev, |
313 | struct nvme_completion *cqe) | |
3c0cf138 | 314 | { |
adf68f21 CH |
315 | u16 status = le16_to_cpu(cqe->status) >> 1; |
316 | u32 result = le32_to_cpu(cqe->result); | |
a4aea562 MB |
317 | |
318 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
adf68f21 | 319 | ++dev->ctrl.event_limit; |
a5768aa8 KB |
320 | if (status != NVME_SC_SUCCESS) |
321 | return; | |
322 | ||
323 | switch (result & 0xff07) { | |
324 | case NVME_AER_NOTICE_NS_CHANGED: | |
adf68f21 CH |
325 | dev_info(dev->dev, "rescanning\n"); |
326 | queue_work(nvme_workq, &dev->scan_work); | |
a5768aa8 | 327 | default: |
adf68f21 | 328 | dev_warn(dev->dev, "async event result %08x\n", result); |
a5768aa8 | 329 | } |
b60503ba MW |
330 | } |
331 | ||
b60503ba | 332 | /** |
adf68f21 | 333 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
334 | * @nvmeq: The queue to use |
335 | * @cmd: The command to send | |
336 | * | |
337 | * Safe to use from interrupt context | |
338 | */ | |
e3f879bf SB |
339 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
340 | struct nvme_command *cmd) | |
b60503ba | 341 | { |
a4aea562 MB |
342 | u16 tail = nvmeq->sq_tail; |
343 | ||
8ffaadf7 JD |
344 | if (nvmeq->sq_cmds_io) |
345 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
346 | else | |
347 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
348 | ||
b60503ba MW |
349 | if (++tail == nvmeq->q_depth) |
350 | tail = 0; | |
7547881d | 351 | writel(tail, nvmeq->q_db); |
b60503ba | 352 | nvmeq->sq_tail = tail; |
b60503ba MW |
353 | } |
354 | ||
eca18b23 | 355 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 356 | { |
eca18b23 | 357 | return ((void *)iod) + iod->offset; |
e025344c SMM |
358 | } |
359 | ||
ac3dd5bd JA |
360 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
361 | unsigned nseg, unsigned long private) | |
eca18b23 | 362 | { |
ac3dd5bd JA |
363 | iod->private = private; |
364 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
365 | iod->npages = -1; | |
366 | iod->length = nbytes; | |
367 | iod->nents = 0; | |
eca18b23 | 368 | } |
b60503ba | 369 | |
eca18b23 | 370 | static struct nvme_iod * |
ac3dd5bd JA |
371 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
372 | unsigned long priv, gfp_t gfp) | |
b60503ba | 373 | { |
eca18b23 | 374 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 375 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
376 | sizeof(struct scatterlist) * nseg, gfp); |
377 | ||
ac3dd5bd JA |
378 | if (iod) |
379 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
380 | |
381 | return iod; | |
b60503ba MW |
382 | } |
383 | ||
ac3dd5bd JA |
384 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
385 | gfp_t gfp) | |
386 | { | |
387 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
388 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
389 | struct nvme_iod *iod; |
390 | ||
391 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
392 | size <= NVME_INT_BYTES(dev)) { | |
393 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
394 | ||
aae239e1 | 395 | iod = &cmd->__iod; |
ac3dd5bd | 396 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 397 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
398 | return iod; |
399 | } | |
400 | ||
401 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
402 | (unsigned long) rq, gfp); | |
403 | } | |
404 | ||
d29ec824 | 405 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 406 | { |
5fd4ce1b | 407 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 MW |
408 | int i; |
409 | __le64 **list = iod_list(iod); | |
410 | dma_addr_t prp_dma = iod->first_dma; | |
411 | ||
412 | if (iod->npages == 0) | |
413 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
414 | for (i = 0; i < iod->npages; i++) { | |
415 | __le64 *prp_list = list[i]; | |
416 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
417 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
418 | prp_dma = next_prp_dma; | |
419 | } | |
ac3dd5bd JA |
420 | |
421 | if (iod_should_kfree(iod)) | |
422 | kfree(iod); | |
b60503ba MW |
423 | } |
424 | ||
52b68d7e | 425 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
426 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
427 | { | |
428 | if (be32_to_cpu(pi->ref_tag) == v) | |
429 | pi->ref_tag = cpu_to_be32(p); | |
430 | } | |
431 | ||
432 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
433 | { | |
434 | if (be32_to_cpu(pi->ref_tag) == p) | |
435 | pi->ref_tag = cpu_to_be32(v); | |
436 | } | |
437 | ||
438 | /** | |
439 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
440 | * | |
441 | * The virtual start sector is the one that was originally submitted by the | |
442 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
443 | * start sector may be different. Remap protection information to match the | |
444 | * physical LBA on writes, and back to the original seed on reads. | |
445 | * | |
446 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
447 | */ | |
448 | static void nvme_dif_remap(struct request *req, | |
449 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
450 | { | |
451 | struct nvme_ns *ns = req->rq_disk->private_data; | |
452 | struct bio_integrity_payload *bip; | |
453 | struct t10_pi_tuple *pi; | |
454 | void *p, *pmap; | |
455 | u32 i, nlb, ts, phys, virt; | |
456 | ||
457 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
458 | return; | |
459 | ||
460 | bip = bio_integrity(req->bio); | |
461 | if (!bip) | |
462 | return; | |
463 | ||
464 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
465 | |
466 | p = pmap; | |
467 | virt = bip_get_seed(bip); | |
468 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
469 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 470 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
471 | |
472 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
473 | pi = (struct t10_pi_tuple *)p; | |
474 | dif_swap(phys, virt, pi); | |
475 | p += ts; | |
476 | } | |
477 | kunmap_atomic(pmap); | |
478 | } | |
52b68d7e KB |
479 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
480 | static void nvme_dif_remap(struct request *req, | |
481 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
482 | { | |
483 | } | |
484 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
485 | { | |
486 | } | |
487 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
488 | { | |
489 | } | |
52b68d7e KB |
490 | #endif |
491 | ||
69d2b571 CH |
492 | static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
493 | int total_len) | |
ff22b54f | 494 | { |
99802a7a | 495 | struct dma_pool *pool; |
eca18b23 MW |
496 | int length = total_len; |
497 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
498 | int dma_len = sg_dma_len(sg); |
499 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 500 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 501 | int offset = dma_addr & (page_size - 1); |
e025344c | 502 | __le64 *prp_list; |
eca18b23 | 503 | __le64 **list = iod_list(iod); |
e025344c | 504 | dma_addr_t prp_dma; |
eca18b23 | 505 | int nprps, i; |
ff22b54f | 506 | |
1d090624 | 507 | length -= (page_size - offset); |
ff22b54f | 508 | if (length <= 0) |
69d2b571 | 509 | return true; |
ff22b54f | 510 | |
1d090624 | 511 | dma_len -= (page_size - offset); |
ff22b54f | 512 | if (dma_len) { |
1d090624 | 513 | dma_addr += (page_size - offset); |
ff22b54f MW |
514 | } else { |
515 | sg = sg_next(sg); | |
516 | dma_addr = sg_dma_address(sg); | |
517 | dma_len = sg_dma_len(sg); | |
518 | } | |
519 | ||
1d090624 | 520 | if (length <= page_size) { |
edd10d33 | 521 | iod->first_dma = dma_addr; |
69d2b571 | 522 | return true; |
e025344c SMM |
523 | } |
524 | ||
1d090624 | 525 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
526 | if (nprps <= (256 / 8)) { |
527 | pool = dev->prp_small_pool; | |
eca18b23 | 528 | iod->npages = 0; |
99802a7a MW |
529 | } else { |
530 | pool = dev->prp_page_pool; | |
eca18b23 | 531 | iod->npages = 1; |
99802a7a MW |
532 | } |
533 | ||
69d2b571 | 534 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 535 | if (!prp_list) { |
edd10d33 | 536 | iod->first_dma = dma_addr; |
eca18b23 | 537 | iod->npages = -1; |
69d2b571 | 538 | return false; |
b77954cb | 539 | } |
eca18b23 MW |
540 | list[0] = prp_list; |
541 | iod->first_dma = prp_dma; | |
e025344c SMM |
542 | i = 0; |
543 | for (;;) { | |
1d090624 | 544 | if (i == page_size >> 3) { |
e025344c | 545 | __le64 *old_prp_list = prp_list; |
69d2b571 | 546 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 547 | if (!prp_list) |
69d2b571 | 548 | return false; |
eca18b23 | 549 | list[iod->npages++] = prp_list; |
7523d834 MW |
550 | prp_list[0] = old_prp_list[i - 1]; |
551 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
552 | i = 1; | |
e025344c SMM |
553 | } |
554 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
555 | dma_len -= page_size; |
556 | dma_addr += page_size; | |
557 | length -= page_size; | |
e025344c SMM |
558 | if (length <= 0) |
559 | break; | |
560 | if (dma_len > 0) | |
561 | continue; | |
562 | BUG_ON(dma_len < 0); | |
563 | sg = sg_next(sg); | |
564 | dma_addr = sg_dma_address(sg); | |
565 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
566 | } |
567 | ||
69d2b571 | 568 | return true; |
ff22b54f MW |
569 | } |
570 | ||
ba1ca37e CH |
571 | static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, |
572 | struct nvme_command *cmnd) | |
d29ec824 | 573 | { |
ba1ca37e CH |
574 | struct request *req = iod_get_private(iod); |
575 | struct request_queue *q = req->q; | |
576 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
577 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
578 | int ret = BLK_MQ_RQ_QUEUE_ERROR; | |
579 | ||
580 | sg_init_table(iod->sg, req->nr_phys_segments); | |
581 | iod->nents = blk_rq_map_sg(q, req, iod->sg); | |
582 | if (!iod->nents) | |
583 | goto out; | |
584 | ||
585 | ret = BLK_MQ_RQ_QUEUE_BUSY; | |
586 | if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) | |
587 | goto out; | |
588 | ||
589 | if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) | |
590 | goto out_unmap; | |
591 | ||
592 | ret = BLK_MQ_RQ_QUEUE_ERROR; | |
593 | if (blk_integrity_rq(req)) { | |
594 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
595 | goto out_unmap; | |
596 | ||
bf684057 CH |
597 | sg_init_table(&iod->meta_sg, 1); |
598 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 599 | goto out_unmap; |
d29ec824 | 600 | |
ba1ca37e CH |
601 | if (rq_data_dir(req)) |
602 | nvme_dif_remap(req, nvme_dif_prep); | |
603 | ||
bf684057 | 604 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 605 | goto out_unmap; |
d29ec824 CH |
606 | } |
607 | ||
ba1ca37e CH |
608 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
609 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
610 | if (blk_integrity_rq(req)) | |
bf684057 | 611 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
ba1ca37e CH |
612 | return BLK_MQ_RQ_QUEUE_OK; |
613 | ||
614 | out_unmap: | |
615 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
616 | out: | |
617 | return ret; | |
d29ec824 CH |
618 | } |
619 | ||
d4f6c3ab CH |
620 | static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) |
621 | { | |
622 | struct request *req = iod_get_private(iod); | |
623 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
624 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
625 | ||
626 | if (iod->nents) { | |
627 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
628 | if (blk_integrity_rq(req)) { | |
629 | if (!rq_data_dir(req)) | |
630 | nvme_dif_remap(req, nvme_dif_complete); | |
bf684057 | 631 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
d4f6c3ab CH |
632 | } |
633 | } | |
634 | ||
635 | nvme_free_iod(dev, iod); | |
636 | } | |
637 | ||
a4aea562 MB |
638 | /* |
639 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
640 | * worth having a special pool for these or additional cases to handle freeing | |
641 | * the iod. | |
642 | */ | |
ba1ca37e CH |
643 | static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
644 | struct nvme_iod *iod, struct nvme_command *cmnd) | |
0e5e4f0e | 645 | { |
ba1ca37e CH |
646 | struct request *req = iod_get_private(iod); |
647 | struct nvme_dsm_range *range; | |
648 | ||
649 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
650 | &iod->first_dma); | |
651 | if (!range) | |
652 | return BLK_MQ_RQ_QUEUE_BUSY; | |
653 | iod_list(iod)[0] = (__le64 *)range; | |
654 | iod->npages = 0; | |
0e5e4f0e | 655 | |
0e5e4f0e | 656 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
657 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
658 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e | 659 | |
ba1ca37e CH |
660 | memset(cmnd, 0, sizeof(*cmnd)); |
661 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
662 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
663 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
664 | cmnd->dsm.nr = 0; | |
665 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
666 | return BLK_MQ_RQ_QUEUE_OK; | |
0e5e4f0e KB |
667 | } |
668 | ||
d29ec824 CH |
669 | /* |
670 | * NOTE: ns is NULL when called on the admin queue. | |
671 | */ | |
a4aea562 MB |
672 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
673 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 674 | { |
a4aea562 MB |
675 | struct nvme_ns *ns = hctx->queue->queuedata; |
676 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 677 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
678 | struct request *req = bd->rq; |
679 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 680 | struct nvme_iod *iod; |
ba1ca37e CH |
681 | struct nvme_command cmnd; |
682 | int ret = BLK_MQ_RQ_QUEUE_OK; | |
edd10d33 | 683 | |
e1e5e564 KB |
684 | /* |
685 | * If formated with metadata, require the block layer provide a buffer | |
686 | * unless this namespace is formated such that the metadata can be | |
687 | * stripped/generated by the controller with PRACT=1. | |
688 | */ | |
d29ec824 | 689 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
690 | if (!(ns->pi_type && ns->ms == 8) && |
691 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
eee417b0 | 692 | blk_mq_end_request(req, -EFAULT); |
e1e5e564 KB |
693 | return BLK_MQ_RQ_QUEUE_OK; |
694 | } | |
695 | } | |
696 | ||
d29ec824 | 697 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 698 | if (!iod) |
fe54303e | 699 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 700 | |
a4aea562 | 701 | if (req->cmd_flags & REQ_DISCARD) { |
ba1ca37e CH |
702 | ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); |
703 | } else { | |
704 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
705 | memcpy(&cmnd, req->cmd, sizeof(cmnd)); | |
706 | else if (req->cmd_flags & REQ_FLUSH) | |
707 | nvme_setup_flush(ns, &cmnd); | |
708 | else | |
709 | nvme_setup_rw(ns, req, &cmnd); | |
a4aea562 | 710 | |
ba1ca37e CH |
711 | if (req->nr_phys_segments) |
712 | ret = nvme_map_data(dev, iod, &cmnd); | |
edd10d33 | 713 | } |
1974b1ae | 714 | |
ba1ca37e CH |
715 | if (ret) |
716 | goto out; | |
717 | ||
aae239e1 CH |
718 | cmd->iod = iod; |
719 | cmd->aborted = 0; | |
ba1ca37e | 720 | cmnd.common.command_id = req->tag; |
aae239e1 | 721 | blk_mq_start_request(req); |
a4aea562 | 722 | |
ba1ca37e CH |
723 | spin_lock_irq(&nvmeq->q_lock); |
724 | __nvme_submit_cmd(nvmeq, &cmnd); | |
a4aea562 MB |
725 | nvme_process_cq(nvmeq); |
726 | spin_unlock_irq(&nvmeq->q_lock); | |
727 | return BLK_MQ_RQ_QUEUE_OK; | |
ba1ca37e | 728 | out: |
d29ec824 | 729 | nvme_free_iod(dev, iod); |
ba1ca37e | 730 | return ret; |
b60503ba MW |
731 | } |
732 | ||
eee417b0 CH |
733 | static void nvme_complete_rq(struct request *req) |
734 | { | |
735 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
736 | struct nvme_dev *dev = cmd->nvmeq->dev; | |
737 | int error = 0; | |
738 | ||
739 | nvme_unmap_data(dev, cmd->iod); | |
740 | ||
741 | if (unlikely(req->errors)) { | |
742 | if (nvme_req_needs_retry(req, req->errors)) { | |
743 | nvme_requeue_req(req); | |
744 | return; | |
745 | } | |
746 | ||
747 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) | |
748 | error = req->errors; | |
749 | else | |
750 | error = nvme_error_status(req->errors); | |
751 | } | |
752 | ||
753 | if (unlikely(cmd->aborted)) { | |
754 | dev_warn(dev->dev, | |
755 | "completing aborted command with status: %04x\n", | |
756 | req->errors); | |
757 | } | |
758 | ||
759 | blk_mq_end_request(req, error); | |
760 | } | |
761 | ||
a0fa9647 | 762 | static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) |
b60503ba | 763 | { |
82123460 | 764 | u16 head, phase; |
b60503ba | 765 | |
b60503ba | 766 | head = nvmeq->cq_head; |
82123460 | 767 | phase = nvmeq->cq_phase; |
b60503ba MW |
768 | |
769 | for (;;) { | |
b60503ba | 770 | struct nvme_completion cqe = nvmeq->cqes[head]; |
adf68f21 | 771 | u16 status = le16_to_cpu(cqe.status); |
eee417b0 | 772 | struct request *req; |
adf68f21 CH |
773 | |
774 | if ((status & 1) != phase) | |
b60503ba MW |
775 | break; |
776 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
777 | if (++head == nvmeq->q_depth) { | |
778 | head = 0; | |
82123460 | 779 | phase = !phase; |
b60503ba | 780 | } |
adf68f21 | 781 | |
a0fa9647 JA |
782 | if (tag && *tag == cqe.command_id) |
783 | *tag = -1; | |
adf68f21 | 784 | |
aae239e1 CH |
785 | if (unlikely(cqe.command_id >= nvmeq->q_depth)) { |
786 | dev_warn(nvmeq->q_dmadev, | |
787 | "invalid id %d completed on queue %d\n", | |
788 | cqe.command_id, le16_to_cpu(cqe.sq_id)); | |
789 | continue; | |
790 | } | |
791 | ||
adf68f21 CH |
792 | /* |
793 | * AEN requests are special as they don't time out and can | |
794 | * survive any kind of queue freeze and often don't respond to | |
795 | * aborts. We don't even bother to allocate a struct request | |
796 | * for them but rather special case them here. | |
797 | */ | |
798 | if (unlikely(nvmeq->qid == 0 && | |
799 | cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
800 | nvme_complete_async_event(nvmeq->dev, &cqe); | |
801 | continue; | |
802 | } | |
803 | ||
eee417b0 CH |
804 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); |
805 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { | |
806 | u32 result = le32_to_cpu(cqe.result); | |
807 | req->special = (void *)(uintptr_t)result; | |
808 | } | |
809 | blk_mq_complete_request(req, status >> 1); | |
810 | ||
b60503ba MW |
811 | } |
812 | ||
813 | /* If the controller ignores the cq head doorbell and continuously | |
814 | * writes to the queue, it is theoretically possible to wrap around | |
815 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
816 | * requires that 0.1% of your interrupts are handled, so this isn't | |
817 | * a big problem. | |
818 | */ | |
82123460 | 819 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
a0fa9647 | 820 | return; |
b60503ba | 821 | |
604e8c8d KB |
822 | if (likely(nvmeq->cq_vector >= 0)) |
823 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
b60503ba | 824 | nvmeq->cq_head = head; |
82123460 | 825 | nvmeq->cq_phase = phase; |
b60503ba | 826 | |
e9539f47 | 827 | nvmeq->cqe_seen = 1; |
a0fa9647 JA |
828 | } |
829 | ||
830 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
831 | { | |
832 | __nvme_process_cq(nvmeq, NULL); | |
b60503ba MW |
833 | } |
834 | ||
835 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
836 | { |
837 | irqreturn_t result; | |
838 | struct nvme_queue *nvmeq = data; | |
839 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
840 | nvme_process_cq(nvmeq); |
841 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
842 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
843 | spin_unlock(&nvmeq->q_lock); |
844 | return result; | |
845 | } | |
846 | ||
847 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
848 | { | |
849 | struct nvme_queue *nvmeq = data; | |
850 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
851 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
852 | return IRQ_NONE; | |
853 | return IRQ_WAKE_THREAD; | |
854 | } | |
855 | ||
a0fa9647 JA |
856 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
857 | { | |
858 | struct nvme_queue *nvmeq = hctx->driver_data; | |
859 | ||
860 | if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == | |
861 | nvmeq->cq_phase) { | |
862 | spin_lock_irq(&nvmeq->q_lock); | |
863 | __nvme_process_cq(nvmeq, &tag); | |
864 | spin_unlock_irq(&nvmeq->q_lock); | |
865 | ||
866 | if (tag == -1) | |
867 | return 1; | |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
adf68f21 | 873 | static void nvme_submit_async_event(struct nvme_dev *dev) |
a4aea562 | 874 | { |
a4aea562 | 875 | struct nvme_command c; |
a4aea562 MB |
876 | |
877 | memset(&c, 0, sizeof(c)); | |
878 | c.common.opcode = nvme_admin_async_event; | |
adf68f21 | 879 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit; |
a4aea562 | 880 | |
adf68f21 | 881 | __nvme_submit_cmd(dev->queues[0], &c); |
a4aea562 MB |
882 | } |
883 | ||
d8f32166 | 884 | static void async_cmd_info_endio(struct request *req, int error) |
4d115420 | 885 | { |
d8f32166 | 886 | struct async_cmd_info *cmdinfo = req->end_io_data; |
a4aea562 | 887 | |
d8f32166 CH |
888 | cmdinfo->status = req->errors; |
889 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
890 | blk_mq_free_request(req); | |
4d115420 KB |
891 | } |
892 | ||
b60503ba MW |
893 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
894 | { | |
b60503ba MW |
895 | struct nvme_command c; |
896 | ||
897 | memset(&c, 0, sizeof(c)); | |
898 | c.delete_queue.opcode = opcode; | |
899 | c.delete_queue.qid = cpu_to_le16(id); | |
900 | ||
1c63dc66 | 901 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
902 | } |
903 | ||
904 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
905 | struct nvme_queue *nvmeq) | |
906 | { | |
b60503ba MW |
907 | struct nvme_command c; |
908 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
909 | ||
d29ec824 CH |
910 | /* |
911 | * Note: we (ab)use the fact the the prp fields survive if no data | |
912 | * is attached to the request. | |
913 | */ | |
b60503ba MW |
914 | memset(&c, 0, sizeof(c)); |
915 | c.create_cq.opcode = nvme_admin_create_cq; | |
916 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
917 | c.create_cq.cqid = cpu_to_le16(qid); | |
918 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
919 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
920 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
921 | ||
1c63dc66 | 922 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
923 | } |
924 | ||
925 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
926 | struct nvme_queue *nvmeq) | |
927 | { | |
b60503ba MW |
928 | struct nvme_command c; |
929 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
930 | ||
d29ec824 CH |
931 | /* |
932 | * Note: we (ab)use the fact the the prp fields survive if no data | |
933 | * is attached to the request. | |
934 | */ | |
b60503ba MW |
935 | memset(&c, 0, sizeof(c)); |
936 | c.create_sq.opcode = nvme_admin_create_sq; | |
937 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
938 | c.create_sq.sqid = cpu_to_le16(qid); | |
939 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
940 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
941 | c.create_sq.cqid = cpu_to_le16(qid); | |
942 | ||
1c63dc66 | 943 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
944 | } |
945 | ||
946 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
947 | { | |
948 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
949 | } | |
950 | ||
951 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
952 | { | |
953 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
954 | } | |
955 | ||
e7a2a87d CH |
956 | static void abort_endio(struct request *req, int error) |
957 | { | |
958 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
959 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
960 | u32 result = (u32)(uintptr_t)req->special; | |
961 | u16 status = req->errors; | |
962 | ||
963 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); | |
964 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); | |
965 | ||
966 | blk_mq_free_request(req); | |
967 | } | |
968 | ||
31c7c7d2 | 969 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 970 | { |
a4aea562 MB |
971 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
972 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 973 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 974 | struct request *abort_req; |
a4aea562 | 975 | struct nvme_command cmd; |
c30341dc | 976 | |
31c7c7d2 | 977 | /* |
fd634f41 CH |
978 | * Shutdown immediately if controller times out while starting. The |
979 | * reset work will see the pci device disabled when it gets the forced | |
980 | * cancellation error. All outstanding requests are completed on | |
981 | * shutdown, so we return BLK_EH_HANDLED. | |
982 | */ | |
983 | if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) { | |
984 | dev_warn(dev->dev, | |
985 | "I/O %d QID %d timeout, disable controller\n", | |
986 | req->tag, nvmeq->qid); | |
987 | nvme_dev_shutdown(dev); | |
988 | req->errors = NVME_SC_CANCELLED; | |
989 | return BLK_EH_HANDLED; | |
990 | } | |
991 | ||
992 | /* | |
993 | * Shutdown the controller immediately and schedule a reset if the | |
994 | * command was already aborted once before and still hasn't been | |
995 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 996 | */ |
a4aea562 | 997 | if (!nvmeq->qid || cmd_rq->aborted) { |
e1569a16 KB |
998 | dev_warn(dev->dev, |
999 | "I/O %d QID %d timeout, reset controller\n", | |
1000 | req->tag, nvmeq->qid); | |
1001 | nvme_dev_shutdown(dev); | |
1002 | queue_work(nvme_workq, &dev->reset_work); | |
1003 | ||
1004 | /* | |
1005 | * Mark the request as handled, since the inline shutdown | |
1006 | * forces all outstanding requests to complete. | |
1007 | */ | |
1008 | req->errors = NVME_SC_CANCELLED; | |
1009 | return BLK_EH_HANDLED; | |
c30341dc KB |
1010 | } |
1011 | ||
e7a2a87d | 1012 | cmd_rq->aborted = 1; |
c30341dc | 1013 | |
e7a2a87d | 1014 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1015 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1016 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1017 | } |
c30341dc KB |
1018 | |
1019 | memset(&cmd, 0, sizeof(cmd)); | |
1020 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1021 | cmd.abort.cid = req->tag; |
c30341dc | 1022 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1023 | |
31c7c7d2 CH |
1024 | dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n", |
1025 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1026 | |
1027 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
1028 | BLK_MQ_REQ_NOWAIT); | |
1029 | if (IS_ERR(abort_req)) { | |
1030 | atomic_inc(&dev->ctrl.abort_limit); | |
1031 | return BLK_EH_RESET_TIMER; | |
1032 | } | |
1033 | ||
1034 | abort_req->timeout = ADMIN_TIMEOUT; | |
1035 | abort_req->end_io_data = NULL; | |
1036 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
31c7c7d2 CH |
1037 | |
1038 | /* | |
1039 | * The aborted req will be completed on receiving the abort req. | |
1040 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1041 | * as the device then is in a faulty state. | |
1042 | */ | |
1043 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1044 | } |
1045 | ||
42483228 | 1046 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1047 | { |
a4aea562 | 1048 | struct nvme_queue *nvmeq = data; |
aae239e1 | 1049 | int status; |
cef6a948 KB |
1050 | |
1051 | if (!blk_mq_request_started(req)) | |
1052 | return; | |
a09115b2 | 1053 | |
aae239e1 CH |
1054 | dev_warn(nvmeq->q_dmadev, |
1055 | "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid); | |
a4aea562 | 1056 | |
aae239e1 | 1057 | status = NVME_SC_CANCELLED; |
cef6a948 | 1058 | if (blk_queue_dying(req->q)) |
aae239e1 CH |
1059 | status |= NVME_SC_DNR; |
1060 | blk_mq_complete_request(req, status); | |
a09115b2 MW |
1061 | } |
1062 | ||
a4aea562 MB |
1063 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1064 | { | |
9e866774 MW |
1065 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1066 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1067 | if (nvmeq->sq_cmds) |
1068 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1069 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1070 | kfree(nvmeq); | |
1071 | } | |
1072 | ||
a1a5ef99 | 1073 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1074 | { |
1075 | int i; | |
1076 | ||
a1a5ef99 | 1077 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1078 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1079 | dev->queue_count--; |
a4aea562 | 1080 | dev->queues[i] = NULL; |
f435c282 | 1081 | nvme_free_queue(nvmeq); |
121c7ad4 | 1082 | } |
22404274 KB |
1083 | } |
1084 | ||
4d115420 KB |
1085 | /** |
1086 | * nvme_suspend_queue - put queue into suspended state | |
1087 | * @nvmeq - queue to suspend | |
4d115420 KB |
1088 | */ |
1089 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1090 | { |
2b25d981 | 1091 | int vector; |
b60503ba | 1092 | |
a09115b2 | 1093 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1094 | if (nvmeq->cq_vector == -1) { |
1095 | spin_unlock_irq(&nvmeq->q_lock); | |
1096 | return 1; | |
1097 | } | |
1098 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1099 | nvmeq->dev->online_queues--; |
2b25d981 | 1100 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1101 | spin_unlock_irq(&nvmeq->q_lock); |
1102 | ||
1c63dc66 CH |
1103 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
1104 | blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); | |
6df3dbc8 | 1105 | |
aba2080f MW |
1106 | irq_set_affinity_hint(vector, NULL); |
1107 | free_irq(vector, nvmeq); | |
b60503ba | 1108 | |
4d115420 KB |
1109 | return 0; |
1110 | } | |
b60503ba | 1111 | |
4d115420 KB |
1112 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1113 | { | |
22404274 | 1114 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1115 | if (nvmeq->tags && *nvmeq->tags) |
1116 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1117 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1118 | } |
1119 | ||
4d115420 KB |
1120 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1121 | { | |
a4aea562 | 1122 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1123 | |
1124 | if (!nvmeq) | |
1125 | return; | |
1126 | if (nvme_suspend_queue(nvmeq)) | |
1127 | return; | |
1128 | ||
0e53d180 KB |
1129 | /* Don't tell the adapter to delete the admin queue. |
1130 | * Don't tell a removed adapter to delete IO queues. */ | |
7a67cbea | 1131 | if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { |
b60503ba MW |
1132 | adapter_delete_sq(dev, qid); |
1133 | adapter_delete_cq(dev, qid); | |
1134 | } | |
07836e65 KB |
1135 | |
1136 | spin_lock_irq(&nvmeq->q_lock); | |
1137 | nvme_process_cq(nvmeq); | |
1138 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1139 | } |
1140 | ||
8ffaadf7 JD |
1141 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1142 | int entry_size) | |
1143 | { | |
1144 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1145 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1146 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1147 | |
1148 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1149 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1150 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1151 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1152 | |
1153 | /* | |
1154 | * Ensure the reduced q_depth is above some threshold where it | |
1155 | * would be better to map queues in system memory with the | |
1156 | * original depth | |
1157 | */ | |
1158 | if (q_depth < 64) | |
1159 | return -ENOMEM; | |
1160 | } | |
1161 | ||
1162 | return q_depth; | |
1163 | } | |
1164 | ||
1165 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1166 | int qid, int depth) | |
1167 | { | |
1168 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1169 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1170 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1171 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1172 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1173 | } else { | |
1174 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1175 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1176 | if (!nvmeq->sq_cmds) | |
1177 | return -ENOMEM; | |
1178 | } | |
1179 | ||
1180 | return 0; | |
1181 | } | |
1182 | ||
b60503ba | 1183 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
2b25d981 | 1184 | int depth) |
b60503ba | 1185 | { |
a4aea562 | 1186 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1187 | if (!nvmeq) |
1188 | return NULL; | |
1189 | ||
e75ec752 | 1190 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1191 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1192 | if (!nvmeq->cqes) |
1193 | goto free_nvmeq; | |
b60503ba | 1194 | |
8ffaadf7 | 1195 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1196 | goto free_cqdma; |
1197 | ||
e75ec752 | 1198 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1199 | nvmeq->dev = dev; |
3193f07b | 1200 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1c63dc66 | 1201 | dev->ctrl.instance, qid); |
b60503ba MW |
1202 | spin_lock_init(&nvmeq->q_lock); |
1203 | nvmeq->cq_head = 0; | |
82123460 | 1204 | nvmeq->cq_phase = 1; |
b80d5ccc | 1205 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1206 | nvmeq->q_depth = depth; |
c30341dc | 1207 | nvmeq->qid = qid; |
758dd7fd | 1208 | nvmeq->cq_vector = -1; |
a4aea562 | 1209 | dev->queues[qid] = nvmeq; |
b60503ba | 1210 | |
36a7e993 JD |
1211 | /* make sure queue descriptor is set before queue count, for kthread */ |
1212 | mb(); | |
1213 | dev->queue_count++; | |
1214 | ||
b60503ba MW |
1215 | return nvmeq; |
1216 | ||
1217 | free_cqdma: | |
e75ec752 | 1218 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1219 | nvmeq->cq_dma_addr); |
1220 | free_nvmeq: | |
1221 | kfree(nvmeq); | |
1222 | return NULL; | |
1223 | } | |
1224 | ||
3001082c MW |
1225 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1226 | const char *name) | |
1227 | { | |
58ffacb5 MW |
1228 | if (use_threaded_interrupts) |
1229 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1230 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1231 | name, nvmeq); |
3001082c | 1232 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1233 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1234 | } |
1235 | ||
22404274 | 1236 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1237 | { |
22404274 | 1238 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1239 | |
7be50e93 | 1240 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1241 | nvmeq->sq_tail = 0; |
1242 | nvmeq->cq_head = 0; | |
1243 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1244 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1245 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1246 | dev->online_queues++; |
7be50e93 | 1247 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1248 | } |
1249 | ||
1250 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1251 | { | |
1252 | struct nvme_dev *dev = nvmeq->dev; | |
1253 | int result; | |
3f85d50b | 1254 | |
2b25d981 | 1255 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1256 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1257 | if (result < 0) | |
22404274 | 1258 | return result; |
b60503ba MW |
1259 | |
1260 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1261 | if (result < 0) | |
1262 | goto release_cq; | |
1263 | ||
3193f07b | 1264 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1265 | if (result < 0) |
1266 | goto release_sq; | |
1267 | ||
22404274 | 1268 | nvme_init_queue(nvmeq, qid); |
22404274 | 1269 | return result; |
b60503ba MW |
1270 | |
1271 | release_sq: | |
1272 | adapter_delete_sq(dev, qid); | |
1273 | release_cq: | |
1274 | adapter_delete_cq(dev, qid); | |
22404274 | 1275 | return result; |
b60503ba MW |
1276 | } |
1277 | ||
a4aea562 | 1278 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1279 | .queue_rq = nvme_queue_rq, |
eee417b0 | 1280 | .complete = nvme_complete_rq, |
a4aea562 MB |
1281 | .map_queue = blk_mq_map_queue, |
1282 | .init_hctx = nvme_admin_init_hctx, | |
4af0e21c | 1283 | .exit_hctx = nvme_admin_exit_hctx, |
a4aea562 MB |
1284 | .init_request = nvme_admin_init_request, |
1285 | .timeout = nvme_timeout, | |
1286 | }; | |
1287 | ||
1288 | static struct blk_mq_ops nvme_mq_ops = { | |
1289 | .queue_rq = nvme_queue_rq, | |
eee417b0 | 1290 | .complete = nvme_complete_rq, |
a4aea562 MB |
1291 | .map_queue = blk_mq_map_queue, |
1292 | .init_hctx = nvme_init_hctx, | |
1293 | .init_request = nvme_init_request, | |
1294 | .timeout = nvme_timeout, | |
a0fa9647 | 1295 | .poll = nvme_poll, |
a4aea562 MB |
1296 | }; |
1297 | ||
ea191d2f KB |
1298 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1299 | { | |
1c63dc66 CH |
1300 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
1301 | blk_cleanup_queue(dev->ctrl.admin_q); | |
ea191d2f KB |
1302 | blk_mq_free_tag_set(&dev->admin_tagset); |
1303 | } | |
1304 | } | |
1305 | ||
a4aea562 MB |
1306 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1307 | { | |
1c63dc66 | 1308 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1309 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1310 | dev->admin_tagset.nr_hw_queues = 1; | |
adf68f21 | 1311 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH; |
a4aea562 | 1312 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1313 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1314 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1315 | dev->admin_tagset.driver_data = dev; |
1316 | ||
1317 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1318 | return -ENOMEM; | |
1319 | ||
1c63dc66 CH |
1320 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1321 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1322 | blk_mq_free_tag_set(&dev->admin_tagset); |
1323 | return -ENOMEM; | |
1324 | } | |
1c63dc66 | 1325 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1326 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1327 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1328 | return -ENODEV; |
1329 | } | |
0fb59cbc | 1330 | } else |
1c63dc66 | 1331 | blk_mq_unfreeze_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1332 | |
1333 | return 0; | |
1334 | } | |
1335 | ||
8d85fce7 | 1336 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1337 | { |
ba47e386 | 1338 | int result; |
b60503ba | 1339 | u32 aqa; |
7a67cbea | 1340 | u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
b60503ba MW |
1341 | struct nvme_queue *nvmeq; |
1342 | ||
7a67cbea | 1343 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? |
dfbac8c7 KB |
1344 | NVME_CAP_NSSRC(cap) : 0; |
1345 | ||
7a67cbea CH |
1346 | if (dev->subsystem && |
1347 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1348 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1349 | |
5fd4ce1b | 1350 | result = nvme_disable_ctrl(&dev->ctrl, cap); |
ba47e386 MW |
1351 | if (result < 0) |
1352 | return result; | |
b60503ba | 1353 | |
a4aea562 | 1354 | nvmeq = dev->queues[0]; |
cd638946 | 1355 | if (!nvmeq) { |
2b25d981 | 1356 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1357 | if (!nvmeq) |
1358 | return -ENOMEM; | |
cd638946 | 1359 | } |
b60503ba MW |
1360 | |
1361 | aqa = nvmeq->q_depth - 1; | |
1362 | aqa |= aqa << 16; | |
1363 | ||
7a67cbea CH |
1364 | writel(aqa, dev->bar + NVME_REG_AQA); |
1365 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1366 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1367 | |
5fd4ce1b | 1368 | result = nvme_enable_ctrl(&dev->ctrl, cap); |
025c557a | 1369 | if (result) |
a4aea562 MB |
1370 | goto free_nvmeq; |
1371 | ||
2b25d981 | 1372 | nvmeq->cq_vector = 0; |
3193f07b | 1373 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
758dd7fd JD |
1374 | if (result) { |
1375 | nvmeq->cq_vector = -1; | |
0fb59cbc | 1376 | goto free_nvmeq; |
758dd7fd | 1377 | } |
025c557a | 1378 | |
b60503ba | 1379 | return result; |
a4aea562 | 1380 | |
a4aea562 MB |
1381 | free_nvmeq: |
1382 | nvme_free_queues(dev, 0); | |
1383 | return result; | |
b60503ba MW |
1384 | } |
1385 | ||
1fa6aead MW |
1386 | static int nvme_kthread(void *data) |
1387 | { | |
d4b4ff8e | 1388 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1389 | |
1390 | while (!kthread_should_stop()) { | |
564a232c | 1391 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1392 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1393 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1394 | int i; |
7a67cbea | 1395 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
dfbac8c7 | 1396 | |
846cc05f CH |
1397 | /* |
1398 | * Skip controllers currently under reset. | |
1399 | */ | |
1400 | if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work)) | |
1401 | continue; | |
1402 | ||
dfbac8c7 KB |
1403 | if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || |
1404 | csts & NVME_CSTS_CFS) { | |
846cc05f | 1405 | if (queue_work(nvme_workq, &dev->reset_work)) { |
90667892 CH |
1406 | dev_warn(dev->dev, |
1407 | "Failed status: %x, reset controller\n", | |
7a67cbea | 1408 | readl(dev->bar + NVME_REG_CSTS)); |
90667892 | 1409 | } |
d4b4ff8e KB |
1410 | continue; |
1411 | } | |
1fa6aead | 1412 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 1413 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
1414 | if (!nvmeq) |
1415 | continue; | |
1fa6aead | 1416 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1417 | nvme_process_cq(nvmeq); |
6fccf938 | 1418 | |
adf68f21 CH |
1419 | while (i == 0 && dev->ctrl.event_limit > 0) |
1420 | nvme_submit_async_event(dev); | |
1fa6aead MW |
1421 | spin_unlock_irq(&nvmeq->q_lock); |
1422 | } | |
1423 | } | |
1424 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1425 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1426 | } |
1427 | return 0; | |
1428 | } | |
1429 | ||
749941f2 | 1430 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1431 | { |
a4aea562 | 1432 | unsigned i; |
749941f2 | 1433 | int ret = 0; |
42f61420 | 1434 | |
749941f2 CH |
1435 | for (i = dev->queue_count; i <= dev->max_qid; i++) { |
1436 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) { | |
1437 | ret = -ENOMEM; | |
42f61420 | 1438 | break; |
749941f2 CH |
1439 | } |
1440 | } | |
42f61420 | 1441 | |
749941f2 CH |
1442 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { |
1443 | ret = nvme_create_queue(dev->queues[i], i); | |
1444 | if (ret) { | |
2659e57b | 1445 | nvme_free_queues(dev, i); |
42f61420 | 1446 | break; |
2659e57b | 1447 | } |
749941f2 CH |
1448 | } |
1449 | ||
1450 | /* | |
1451 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1452 | * than the desired aount of queues, and even a controller without | |
1453 | * I/O queues an still be used to issue admin commands. This might | |
1454 | * be useful to upgrade a buggy firmware for example. | |
1455 | */ | |
1456 | return ret >= 0 ? 0 : ret; | |
42f61420 KB |
1457 | } |
1458 | ||
8ffaadf7 JD |
1459 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1460 | { | |
1461 | u64 szu, size, offset; | |
1462 | u32 cmbloc; | |
1463 | resource_size_t bar_size; | |
1464 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1465 | void __iomem *cmb; | |
1466 | dma_addr_t dma_addr; | |
1467 | ||
1468 | if (!use_cmb_sqes) | |
1469 | return NULL; | |
1470 | ||
7a67cbea | 1471 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1472 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1473 | return NULL; | |
1474 | ||
7a67cbea | 1475 | cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 JD |
1476 | |
1477 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1478 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
1479 | offset = szu * NVME_CMB_OFST(cmbloc); | |
1480 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); | |
1481 | ||
1482 | if (offset > bar_size) | |
1483 | return NULL; | |
1484 | ||
1485 | /* | |
1486 | * Controllers may support a CMB size larger than their BAR, | |
1487 | * for example, due to being behind a bridge. Reduce the CMB to | |
1488 | * the reported size of the BAR | |
1489 | */ | |
1490 | if (size > bar_size - offset) | |
1491 | size = bar_size - offset; | |
1492 | ||
1493 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; | |
1494 | cmb = ioremap_wc(dma_addr, size); | |
1495 | if (!cmb) | |
1496 | return NULL; | |
1497 | ||
1498 | dev->cmb_dma_addr = dma_addr; | |
1499 | dev->cmb_size = size; | |
1500 | return cmb; | |
1501 | } | |
1502 | ||
1503 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1504 | { | |
1505 | if (dev->cmb) { | |
1506 | iounmap(dev->cmb); | |
1507 | dev->cmb = NULL; | |
1508 | } | |
1509 | } | |
1510 | ||
9d713c2b KB |
1511 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1512 | { | |
b80d5ccc | 1513 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
1514 | } |
1515 | ||
8d85fce7 | 1516 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1517 | { |
a4aea562 | 1518 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1519 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 1520 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 1521 | |
42f61420 | 1522 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1523 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1524 | if (result < 0) | |
1b23484b | 1525 | return result; |
9a0be7ab CH |
1526 | |
1527 | /* | |
1528 | * Degraded controllers might return an error when setting the queue | |
1529 | * count. We still want to be able to bring them online and offer | |
1530 | * access to the admin queue, as that might be only way to fix them up. | |
1531 | */ | |
1532 | if (result > 0) { | |
1533 | dev_err(dev->dev, "Could not set queue count (%d)\n", result); | |
1534 | nr_io_queues = 0; | |
1535 | result = 0; | |
1536 | } | |
b60503ba | 1537 | |
8ffaadf7 JD |
1538 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1539 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1540 | sizeof(struct nvme_command)); | |
1541 | if (result > 0) | |
1542 | dev->q_depth = result; | |
1543 | else | |
1544 | nvme_release_cmb(dev); | |
1545 | } | |
1546 | ||
9d713c2b KB |
1547 | size = db_bar_size(dev, nr_io_queues); |
1548 | if (size > 8192) { | |
f1938f6e | 1549 | iounmap(dev->bar); |
9d713c2b KB |
1550 | do { |
1551 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1552 | if (dev->bar) | |
1553 | break; | |
1554 | if (!--nr_io_queues) | |
1555 | return -ENOMEM; | |
1556 | size = db_bar_size(dev, nr_io_queues); | |
1557 | } while (1); | |
7a67cbea | 1558 | dev->dbs = dev->bar + 4096; |
5a92e700 | 1559 | adminq->q_db = dev->dbs; |
f1938f6e MW |
1560 | } |
1561 | ||
9d713c2b | 1562 | /* Deregister the admin queue's interrupt */ |
3193f07b | 1563 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 1564 | |
e32efbfc JA |
1565 | /* |
1566 | * If we enable msix early due to not intx, disable it again before | |
1567 | * setting up the full range we need. | |
1568 | */ | |
1569 | if (!pdev->irq) | |
1570 | pci_disable_msix(pdev); | |
1571 | ||
be577fab | 1572 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 1573 | dev->entry[i].entry = i; |
be577fab AG |
1574 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
1575 | if (vecs < 0) { | |
1576 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
1577 | if (vecs < 0) { | |
1578 | vecs = 1; | |
1579 | } else { | |
1580 | for (i = 0; i < vecs; i++) | |
1581 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
1582 | } |
1583 | } | |
1584 | ||
063a8096 MW |
1585 | /* |
1586 | * Should investigate if there's a performance win from allocating | |
1587 | * more queues than interrupt vectors; it might allow the submission | |
1588 | * path to scale better, even if the receive path is limited by the | |
1589 | * number of interrupts. | |
1590 | */ | |
1591 | nr_io_queues = vecs; | |
42f61420 | 1592 | dev->max_qid = nr_io_queues; |
063a8096 | 1593 | |
3193f07b | 1594 | result = queue_request_irq(dev, adminq, adminq->irqname); |
758dd7fd JD |
1595 | if (result) { |
1596 | adminq->cq_vector = -1; | |
22404274 | 1597 | goto free_queues; |
758dd7fd | 1598 | } |
1b23484b | 1599 | |
cd638946 | 1600 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 1601 | nvme_free_queues(dev, nr_io_queues + 1); |
749941f2 | 1602 | return nvme_create_io_queues(dev); |
b60503ba | 1603 | |
22404274 | 1604 | free_queues: |
a1a5ef99 | 1605 | nvme_free_queues(dev, 1); |
22404274 | 1606 | return result; |
b60503ba MW |
1607 | } |
1608 | ||
bda4e0fb KB |
1609 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
1610 | { | |
1611 | struct nvme_queue *nvmeq; | |
1612 | int i; | |
1613 | ||
1614 | for (i = 0; i < dev->online_queues; i++) { | |
1615 | nvmeq = dev->queues[i]; | |
1616 | ||
1617 | if (!nvmeq->tags || !(*nvmeq->tags)) | |
1618 | continue; | |
1619 | ||
1620 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1621 | blk_mq_tags_cpumask(*nvmeq->tags)); | |
1622 | } | |
1623 | } | |
1624 | ||
a5768aa8 KB |
1625 | static void nvme_dev_scan(struct work_struct *work) |
1626 | { | |
1627 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
a5768aa8 KB |
1628 | |
1629 | if (!dev->tagset.tags) | |
1630 | return; | |
5bae7f73 | 1631 | nvme_scan_namespaces(&dev->ctrl); |
bda4e0fb | 1632 | nvme_set_irq_hints(dev); |
a5768aa8 KB |
1633 | } |
1634 | ||
422ef0c7 MW |
1635 | /* |
1636 | * Return: error value if an error occurred setting up the queues or calling | |
1637 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1638 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1639 | * failures should be reported. | |
1640 | */ | |
8d85fce7 | 1641 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1642 | { |
5bae7f73 | 1643 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1644 | dev->tagset.ops = &nvme_mq_ops; |
1645 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1646 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1647 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1648 | dev->tagset.queue_depth = | |
a4aea562 | 1649 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1650 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1651 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1652 | dev->tagset.driver_data = dev; | |
b60503ba | 1653 | |
ffe7704d KB |
1654 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1655 | return 0; | |
5bae7f73 | 1656 | dev->ctrl.tagset = &dev->tagset; |
ffe7704d | 1657 | } |
92f7a162 | 1658 | queue_work(nvme_workq, &dev->scan_work); |
e1e5e564 | 1659 | return 0; |
b60503ba MW |
1660 | } |
1661 | ||
0877cb0d KB |
1662 | static int nvme_dev_map(struct nvme_dev *dev) |
1663 | { | |
42f61420 | 1664 | u64 cap; |
0877cb0d | 1665 | int bars, result = -ENOMEM; |
e75ec752 | 1666 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1667 | |
1668 | if (pci_enable_device_mem(pdev)) | |
1669 | return result; | |
1670 | ||
1671 | dev->entry[0].vector = pdev->irq; | |
1672 | pci_set_master(pdev); | |
1673 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
1674 | if (!bars) |
1675 | goto disable_pci; | |
1676 | ||
0877cb0d KB |
1677 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
1678 | goto disable_pci; | |
1679 | ||
e75ec752 CH |
1680 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1681 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1682 | goto disable; |
0877cb0d | 1683 | |
0877cb0d KB |
1684 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1685 | if (!dev->bar) | |
1686 | goto disable; | |
e32efbfc | 1687 | |
7a67cbea | 1688 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 KB |
1689 | result = -ENODEV; |
1690 | goto unmap; | |
1691 | } | |
e32efbfc JA |
1692 | |
1693 | /* | |
1694 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
1695 | * MSIX vec for setup. We'll adjust this later. | |
1696 | */ | |
1697 | if (!pdev->irq) { | |
1698 | result = pci_enable_msix(pdev, dev->entry, 1); | |
1699 | if (result < 0) | |
1700 | goto unmap; | |
1701 | } | |
1702 | ||
7a67cbea CH |
1703 | cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
1704 | ||
42f61420 KB |
1705 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); |
1706 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
7a67cbea CH |
1707 | dev->dbs = dev->bar + 4096; |
1708 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) | |
8ffaadf7 | 1709 | dev->cmb = nvme_map_cmb(dev); |
0877cb0d KB |
1710 | |
1711 | return 0; | |
1712 | ||
0e53d180 KB |
1713 | unmap: |
1714 | iounmap(dev->bar); | |
1715 | dev->bar = NULL; | |
0877cb0d KB |
1716 | disable: |
1717 | pci_release_regions(pdev); | |
1718 | disable_pci: | |
1719 | pci_disable_device(pdev); | |
1720 | return result; | |
1721 | } | |
1722 | ||
1723 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
1724 | { | |
e75ec752 CH |
1725 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1726 | ||
1727 | if (pdev->msi_enabled) | |
1728 | pci_disable_msi(pdev); | |
1729 | else if (pdev->msix_enabled) | |
1730 | pci_disable_msix(pdev); | |
0877cb0d KB |
1731 | |
1732 | if (dev->bar) { | |
1733 | iounmap(dev->bar); | |
1734 | dev->bar = NULL; | |
e75ec752 | 1735 | pci_release_regions(pdev); |
0877cb0d KB |
1736 | } |
1737 | ||
e75ec752 CH |
1738 | if (pci_is_enabled(pdev)) |
1739 | pci_disable_device(pdev); | |
0877cb0d KB |
1740 | } |
1741 | ||
4d115420 KB |
1742 | struct nvme_delq_ctx { |
1743 | struct task_struct *waiter; | |
1744 | struct kthread_worker *worker; | |
1745 | atomic_t refcount; | |
1746 | }; | |
1747 | ||
1748 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
1749 | { | |
1750 | dq->waiter = current; | |
1751 | mb(); | |
1752 | ||
1753 | for (;;) { | |
1754 | set_current_state(TASK_KILLABLE); | |
1755 | if (!atomic_read(&dq->refcount)) | |
1756 | break; | |
1757 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
1758 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
1759 | /* |
1760 | * Disable the controller first since we can't trust it | |
1761 | * at this point, but leave the admin queue enabled | |
1762 | * until all queue deletion requests are flushed. | |
1763 | * FIXME: This may take a while if there are more h/w | |
1764 | * queues than admin tags. | |
1765 | */ | |
4d115420 | 1766 | set_current_state(TASK_RUNNING); |
5fd4ce1b | 1767 | nvme_disable_ctrl(&dev->ctrl, |
7a67cbea | 1768 | lo_hi_readq(dev->bar + NVME_REG_CAP)); |
0fb59cbc | 1769 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 1770 | flush_kthread_worker(dq->worker); |
0fb59cbc | 1771 | nvme_disable_queue(dev, 0); |
4d115420 KB |
1772 | return; |
1773 | } | |
1774 | } | |
1775 | set_current_state(TASK_RUNNING); | |
1776 | } | |
1777 | ||
1778 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
1779 | { | |
1780 | atomic_dec(&dq->refcount); | |
1781 | if (dq->waiter) | |
1782 | wake_up_process(dq->waiter); | |
1783 | } | |
1784 | ||
1785 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
1786 | { | |
1787 | atomic_inc(&dq->refcount); | |
1788 | return dq; | |
1789 | } | |
1790 | ||
1791 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
1792 | { | |
1793 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 | 1794 | nvme_put_dq(dq); |
604e8c8d KB |
1795 | |
1796 | spin_lock_irq(&nvmeq->q_lock); | |
1797 | nvme_process_cq(nvmeq); | |
1798 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 KB |
1799 | } |
1800 | ||
1801 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
1802 | kthread_work_func_t fn) | |
1803 | { | |
d8f32166 | 1804 | struct request *req; |
4d115420 KB |
1805 | struct nvme_command c; |
1806 | ||
1807 | memset(&c, 0, sizeof(c)); | |
1808 | c.delete_queue.opcode = opcode; | |
1809 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
1810 | ||
1811 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
d8f32166 CH |
1812 | |
1813 | req = nvme_alloc_request(nvmeq->dev->ctrl.admin_q, &c, 0); | |
1814 | if (IS_ERR(req)) | |
1815 | return PTR_ERR(req); | |
1816 | ||
1817 | req->timeout = ADMIN_TIMEOUT; | |
1818 | req->end_io_data = &nvmeq->cmdinfo; | |
1819 | blk_execute_rq_nowait(req->q, NULL, req, 0, async_cmd_info_endio); | |
1820 | return 0; | |
4d115420 KB |
1821 | } |
1822 | ||
1823 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
1824 | { | |
1825 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1826 | cmdinfo.work); | |
1827 | nvme_del_queue_end(nvmeq); | |
1828 | } | |
1829 | ||
1830 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
1831 | { | |
1832 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
1833 | nvme_del_cq_work_handler); | |
1834 | } | |
1835 | ||
1836 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
1837 | { | |
1838 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1839 | cmdinfo.work); | |
1840 | int status = nvmeq->cmdinfo.status; | |
1841 | ||
1842 | if (!status) | |
1843 | status = nvme_delete_cq(nvmeq); | |
1844 | if (status) | |
1845 | nvme_del_queue_end(nvmeq); | |
1846 | } | |
1847 | ||
1848 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
1849 | { | |
1850 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
1851 | nvme_del_sq_work_handler); | |
1852 | } | |
1853 | ||
1854 | static void nvme_del_queue_start(struct kthread_work *work) | |
1855 | { | |
1856 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
1857 | cmdinfo.work); | |
4d115420 KB |
1858 | if (nvme_delete_sq(nvmeq)) |
1859 | nvme_del_queue_end(nvmeq); | |
1860 | } | |
1861 | ||
1862 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
1863 | { | |
1864 | int i; | |
1865 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
1866 | struct nvme_delq_ctx dq; | |
1867 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
1c63dc66 | 1868 | &worker, "nvme%d", dev->ctrl.instance); |
4d115420 KB |
1869 | |
1870 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 1871 | dev_err(dev->dev, |
4d115420 KB |
1872 | "Failed to create queue del task\n"); |
1873 | for (i = dev->queue_count - 1; i > 0; i--) | |
1874 | nvme_disable_queue(dev, i); | |
1875 | return; | |
1876 | } | |
1877 | ||
1878 | dq.waiter = NULL; | |
1879 | atomic_set(&dq.refcount, 0); | |
1880 | dq.worker = &worker; | |
1881 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 1882 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
1883 | |
1884 | if (nvme_suspend_queue(nvmeq)) | |
1885 | continue; | |
1886 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
1887 | nvmeq->cmdinfo.worker = dq.worker; | |
1888 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
1889 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
1890 | } | |
1891 | nvme_wait_dq(&dq, dev); | |
1892 | kthread_stop(kworker_task); | |
1893 | } | |
1894 | ||
7385014c CH |
1895 | static int nvme_dev_list_add(struct nvme_dev *dev) |
1896 | { | |
1897 | bool start_thread = false; | |
1898 | ||
1899 | spin_lock(&dev_list_lock); | |
1900 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { | |
1901 | start_thread = true; | |
1902 | nvme_thread = NULL; | |
1903 | } | |
1904 | list_add(&dev->node, &dev_list); | |
1905 | spin_unlock(&dev_list_lock); | |
1906 | ||
1907 | if (start_thread) { | |
1908 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1909 | wake_up_all(&nvme_kthread_wait); | |
1910 | } else | |
1911 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
1912 | ||
1913 | if (IS_ERR_OR_NULL(nvme_thread)) | |
1914 | return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
b9afca3e DM |
1919 | /* |
1920 | * Remove the node from the device list and check | |
1921 | * for whether or not we need to stop the nvme_thread. | |
1922 | */ | |
1923 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
1924 | { | |
1925 | struct task_struct *tmp = NULL; | |
1926 | ||
1927 | spin_lock(&dev_list_lock); | |
1928 | list_del_init(&dev->node); | |
1929 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
1930 | tmp = nvme_thread; | |
1931 | nvme_thread = NULL; | |
1932 | } | |
1933 | spin_unlock(&dev_list_lock); | |
1934 | ||
1935 | if (tmp) | |
1936 | kthread_stop(tmp); | |
1937 | } | |
1938 | ||
c9d3bf88 KB |
1939 | static void nvme_freeze_queues(struct nvme_dev *dev) |
1940 | { | |
1941 | struct nvme_ns *ns; | |
1942 | ||
5bae7f73 | 1943 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
1944 | blk_mq_freeze_queue_start(ns->queue); |
1945 | ||
cddcd72b | 1946 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 1947 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 1948 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
1949 | |
1950 | blk_mq_cancel_requeue_work(ns->queue); | |
1951 | blk_mq_stop_hw_queues(ns->queue); | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
1956 | { | |
1957 | struct nvme_ns *ns; | |
1958 | ||
5bae7f73 | 1959 | list_for_each_entry(ns, &dev->ctrl.namespaces, list) { |
c9d3bf88 KB |
1960 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); |
1961 | blk_mq_unfreeze_queue(ns->queue); | |
1962 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
1963 | blk_mq_kick_requeue_list(ns->queue); | |
1964 | } | |
1965 | } | |
1966 | ||
f0b50732 | 1967 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 1968 | { |
22404274 | 1969 | int i; |
7c1b2450 | 1970 | u32 csts = -1; |
22404274 | 1971 | |
b9afca3e | 1972 | nvme_dev_list_remove(dev); |
1fa6aead | 1973 | |
77bf25ea | 1974 | mutex_lock(&dev->shutdown_lock); |
c9d3bf88 KB |
1975 | if (dev->bar) { |
1976 | nvme_freeze_queues(dev); | |
7a67cbea | 1977 | csts = readl(dev->bar + NVME_REG_CSTS); |
c9d3bf88 | 1978 | } |
7c1b2450 | 1979 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 1980 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 1981 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 1982 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
1983 | } |
1984 | } else { | |
1985 | nvme_disable_io_queues(dev); | |
5fd4ce1b | 1986 | nvme_shutdown_ctrl(&dev->ctrl); |
4d115420 KB |
1987 | nvme_disable_queue(dev, 0); |
1988 | } | |
f0b50732 | 1989 | nvme_dev_unmap(dev); |
07836e65 KB |
1990 | |
1991 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1992 | nvme_clear_queue(dev->queues[i]); | |
77bf25ea | 1993 | mutex_unlock(&dev->shutdown_lock); |
f0b50732 KB |
1994 | } |
1995 | ||
091b6092 MW |
1996 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1997 | { | |
e75ec752 | 1998 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
1999 | PAGE_SIZE, PAGE_SIZE, 0); |
2000 | if (!dev->prp_page_pool) | |
2001 | return -ENOMEM; | |
2002 | ||
99802a7a | 2003 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2004 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2005 | 256, 256, 0); |
2006 | if (!dev->prp_small_pool) { | |
2007 | dma_pool_destroy(dev->prp_page_pool); | |
2008 | return -ENOMEM; | |
2009 | } | |
091b6092 MW |
2010 | return 0; |
2011 | } | |
2012 | ||
2013 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2014 | { | |
2015 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2016 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2017 | } |
2018 | ||
1673f1f0 | 2019 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2020 | { |
1673f1f0 | 2021 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2022 | |
e75ec752 | 2023 | put_device(dev->dev); |
4af0e21c KB |
2024 | if (dev->tagset.tags) |
2025 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2026 | if (dev->ctrl.admin_q) |
2027 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 KB |
2028 | kfree(dev->queues); |
2029 | kfree(dev->entry); | |
2030 | kfree(dev); | |
2031 | } | |
2032 | ||
fd634f41 | 2033 | static void nvme_reset_work(struct work_struct *work) |
f0b50732 | 2034 | { |
fd634f41 | 2035 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); |
3cf519b5 | 2036 | int result; |
f0b50732 | 2037 | |
fd634f41 CH |
2038 | if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags))) |
2039 | goto out; | |
2040 | ||
2041 | /* | |
2042 | * If we're called to reset a live controller first shut it down before | |
2043 | * moving on. | |
2044 | */ | |
2045 | if (dev->bar) | |
2046 | nvme_dev_shutdown(dev); | |
2047 | ||
2048 | set_bit(NVME_CTRL_RESETTING, &dev->flags); | |
2049 | ||
f0b50732 KB |
2050 | result = nvme_dev_map(dev); |
2051 | if (result) | |
3cf519b5 | 2052 | goto out; |
f0b50732 KB |
2053 | |
2054 | result = nvme_configure_admin_queue(dev); | |
2055 | if (result) | |
2056 | goto unmap; | |
2057 | ||
a4aea562 | 2058 | nvme_init_queue(dev->queues[0], 0); |
0fb59cbc KB |
2059 | result = nvme_alloc_admin_tags(dev); |
2060 | if (result) | |
2061 | goto disable; | |
b9afca3e | 2062 | |
ce4541f4 CH |
2063 | result = nvme_init_identify(&dev->ctrl); |
2064 | if (result) | |
2065 | goto free_tags; | |
2066 | ||
f0b50732 | 2067 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2068 | if (result) |
0fb59cbc | 2069 | goto free_tags; |
f0b50732 | 2070 | |
adf68f21 | 2071 | dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS; |
3cf519b5 | 2072 | |
7385014c CH |
2073 | result = nvme_dev_list_add(dev); |
2074 | if (result) | |
2075 | goto remove; | |
2076 | ||
2659e57b CH |
2077 | /* |
2078 | * Keep the controller around but remove all namespaces if we don't have | |
2079 | * any working I/O queue. | |
2080 | */ | |
3cf519b5 CH |
2081 | if (dev->online_queues < 2) { |
2082 | dev_warn(dev->dev, "IO queues not created\n"); | |
5bae7f73 | 2083 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 CH |
2084 | } else { |
2085 | nvme_unfreeze_queues(dev); | |
2086 | nvme_dev_add(dev); | |
2087 | } | |
2088 | ||
fd634f41 | 2089 | clear_bit(NVME_CTRL_RESETTING, &dev->flags); |
3cf519b5 | 2090 | return; |
f0b50732 | 2091 | |
7385014c CH |
2092 | remove: |
2093 | nvme_dev_list_remove(dev); | |
0fb59cbc KB |
2094 | free_tags: |
2095 | nvme_dev_remove_admin(dev); | |
1c63dc66 CH |
2096 | blk_put_queue(dev->ctrl.admin_q); |
2097 | dev->ctrl.admin_q = NULL; | |
4af0e21c | 2098 | dev->queues[0]->tags = NULL; |
f0b50732 | 2099 | disable: |
a1a5ef99 | 2100 | nvme_disable_queue(dev, 0); |
f0b50732 KB |
2101 | unmap: |
2102 | nvme_dev_unmap(dev); | |
3cf519b5 | 2103 | out: |
5c8809e6 | 2104 | nvme_remove_dead_ctrl(dev); |
f0b50732 KB |
2105 | } |
2106 | ||
5c8809e6 | 2107 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2108 | { |
5c8809e6 | 2109 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2110 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2111 | |
2112 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2113 | pci_stop_and_remove_bus_device_locked(pdev); |
1673f1f0 | 2114 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2115 | } |
2116 | ||
5c8809e6 | 2117 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
de3eff2b | 2118 | { |
5c8809e6 | 2119 | dev_warn(dev->dev, "Removing after probe failure\n"); |
1673f1f0 | 2120 | kref_get(&dev->ctrl.kref); |
5c8809e6 | 2121 | if (!schedule_work(&dev->remove_work)) |
1673f1f0 | 2122 | nvme_put_ctrl(&dev->ctrl); |
de3eff2b KB |
2123 | } |
2124 | ||
4cc06521 KB |
2125 | static int nvme_reset(struct nvme_dev *dev) |
2126 | { | |
1c63dc66 | 2127 | if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) |
4cc06521 KB |
2128 | return -ENODEV; |
2129 | ||
846cc05f CH |
2130 | if (!queue_work(nvme_workq, &dev->reset_work)) |
2131 | return -EBUSY; | |
4cc06521 | 2132 | |
846cc05f | 2133 | flush_work(&dev->reset_work); |
846cc05f | 2134 | return 0; |
4cc06521 KB |
2135 | } |
2136 | ||
1c63dc66 CH |
2137 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
2138 | { | |
2139 | *val = readl(to_nvme_dev(ctrl)->bar + off); | |
2140 | return 0; | |
2141 | } | |
2142 | ||
5fd4ce1b CH |
2143 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
2144 | { | |
2145 | writel(val, to_nvme_dev(ctrl)->bar + off); | |
2146 | return 0; | |
2147 | } | |
2148 | ||
7fd8930f CH |
2149 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2150 | { | |
2151 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2152 | return 0; | |
2153 | } | |
2154 | ||
5bae7f73 CH |
2155 | static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) |
2156 | { | |
2157 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2158 | ||
2159 | return !dev->bar || dev->online_queues < 2; | |
2160 | } | |
2161 | ||
f3ca80fc CH |
2162 | static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) |
2163 | { | |
2164 | return nvme_reset(to_nvme_dev(ctrl)); | |
2165 | } | |
2166 | ||
1c63dc66 CH |
2167 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
2168 | .reg_read32 = nvme_pci_reg_read32, | |
5fd4ce1b | 2169 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2170 | .reg_read64 = nvme_pci_reg_read64, |
5bae7f73 | 2171 | .io_incapable = nvme_pci_io_incapable, |
f3ca80fc | 2172 | .reset_ctrl = nvme_pci_reset_ctrl, |
1673f1f0 | 2173 | .free_ctrl = nvme_pci_free_ctrl, |
1c63dc66 CH |
2174 | }; |
2175 | ||
8d85fce7 | 2176 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2177 | { |
a4aea562 | 2178 | int node, result = -ENOMEM; |
b60503ba MW |
2179 | struct nvme_dev *dev; |
2180 | ||
a4aea562 MB |
2181 | node = dev_to_node(&pdev->dev); |
2182 | if (node == NUMA_NO_NODE) | |
2183 | set_dev_node(&pdev->dev, 0); | |
2184 | ||
2185 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2186 | if (!dev) |
2187 | return -ENOMEM; | |
a4aea562 MB |
2188 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2189 | GFP_KERNEL, node); | |
b60503ba MW |
2190 | if (!dev->entry) |
2191 | goto free; | |
a4aea562 MB |
2192 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2193 | GFP_KERNEL, node); | |
b60503ba MW |
2194 | if (!dev->queues) |
2195 | goto free; | |
2196 | ||
e75ec752 | 2197 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2198 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2199 | |
f3ca80fc CH |
2200 | INIT_LIST_HEAD(&dev->node); |
2201 | INIT_WORK(&dev->scan_work, nvme_dev_scan); | |
f3ca80fc | 2202 | INIT_WORK(&dev->reset_work, nvme_reset_work); |
5c8809e6 | 2203 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2204 | mutex_init(&dev->shutdown_lock); |
1c63dc66 | 2205 | |
f3ca80fc | 2206 | result = nvme_setup_prp_pools(dev); |
cd58ad7d | 2207 | if (result) |
a96d4f5c | 2208 | goto put_pci; |
b60503ba | 2209 | |
f3ca80fc CH |
2210 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
2211 | id->driver_data); | |
091b6092 | 2212 | if (result) |
2e1d8448 | 2213 | goto release_pools; |
740216fc | 2214 | |
92f7a162 | 2215 | queue_work(nvme_workq, &dev->reset_work); |
b60503ba MW |
2216 | return 0; |
2217 | ||
0877cb0d | 2218 | release_pools: |
091b6092 | 2219 | nvme_release_prp_pools(dev); |
a96d4f5c | 2220 | put_pci: |
e75ec752 | 2221 | put_device(dev->dev); |
b60503ba MW |
2222 | free: |
2223 | kfree(dev->queues); | |
2224 | kfree(dev->entry); | |
2225 | kfree(dev); | |
2226 | return result; | |
2227 | } | |
2228 | ||
f0d54a54 KB |
2229 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
2230 | { | |
a6739479 | 2231 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 2232 | |
a6739479 KB |
2233 | if (prepare) |
2234 | nvme_dev_shutdown(dev); | |
2235 | else | |
92f7a162 | 2236 | queue_work(nvme_workq, &dev->reset_work); |
f0d54a54 KB |
2237 | } |
2238 | ||
09ece142 KB |
2239 | static void nvme_shutdown(struct pci_dev *pdev) |
2240 | { | |
2241 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2242 | nvme_dev_shutdown(dev); | |
2243 | } | |
2244 | ||
8d85fce7 | 2245 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2246 | { |
2247 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2248 | |
2249 | spin_lock(&dev_list_lock); | |
2250 | list_del_init(&dev->node); | |
2251 | spin_unlock(&dev_list_lock); | |
2252 | ||
2253 | pci_set_drvdata(pdev, NULL); | |
2254 | flush_work(&dev->reset_work); | |
a5768aa8 | 2255 | flush_work(&dev->scan_work); |
5bae7f73 | 2256 | nvme_remove_namespaces(&dev->ctrl); |
53029b04 | 2257 | nvme_uninit_ctrl(&dev->ctrl); |
3399a3f7 | 2258 | nvme_dev_shutdown(dev); |
a4aea562 | 2259 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2260 | nvme_free_queues(dev, 0); |
8ffaadf7 | 2261 | nvme_release_cmb(dev); |
9a6b9458 | 2262 | nvme_release_prp_pools(dev); |
1673f1f0 | 2263 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2264 | } |
2265 | ||
2266 | /* These functions are yet to be implemented */ | |
2267 | #define nvme_error_detected NULL | |
2268 | #define nvme_dump_registers NULL | |
2269 | #define nvme_link_reset NULL | |
2270 | #define nvme_slot_reset NULL | |
2271 | #define nvme_error_resume NULL | |
cd638946 | 2272 | |
671a6018 | 2273 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2274 | static int nvme_suspend(struct device *dev) |
2275 | { | |
2276 | struct pci_dev *pdev = to_pci_dev(dev); | |
2277 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2278 | ||
2279 | nvme_dev_shutdown(ndev); | |
2280 | return 0; | |
2281 | } | |
2282 | ||
2283 | static int nvme_resume(struct device *dev) | |
2284 | { | |
2285 | struct pci_dev *pdev = to_pci_dev(dev); | |
2286 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2287 | |
92f7a162 | 2288 | queue_work(nvme_workq, &ndev->reset_work); |
9a6b9458 | 2289 | return 0; |
cd638946 | 2290 | } |
671a6018 | 2291 | #endif |
cd638946 KB |
2292 | |
2293 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2294 | |
1d352035 | 2295 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2296 | .error_detected = nvme_error_detected, |
2297 | .mmio_enabled = nvme_dump_registers, | |
2298 | .link_reset = nvme_link_reset, | |
2299 | .slot_reset = nvme_slot_reset, | |
2300 | .resume = nvme_error_resume, | |
f0d54a54 | 2301 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
2302 | }; |
2303 | ||
2304 | /* Move to pci_ids.h later */ | |
2305 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2306 | ||
6eb0d698 | 2307 | static const struct pci_device_id nvme_id_table[] = { |
106198ed CH |
2308 | { PCI_VDEVICE(INTEL, 0x0953), |
2309 | .driver_data = NVME_QUIRK_STRIPE_SIZE, }, | |
540c801c KB |
2310 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2311 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
b60503ba | 2312 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2313 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
b60503ba MW |
2314 | { 0, } |
2315 | }; | |
2316 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2317 | ||
2318 | static struct pci_driver nvme_driver = { | |
2319 | .name = "nvme", | |
2320 | .id_table = nvme_id_table, | |
2321 | .probe = nvme_probe, | |
8d85fce7 | 2322 | .remove = nvme_remove, |
09ece142 | 2323 | .shutdown = nvme_shutdown, |
cd638946 KB |
2324 | .driver = { |
2325 | .pm = &nvme_dev_pm_ops, | |
2326 | }, | |
b60503ba MW |
2327 | .err_handler = &nvme_err_handler, |
2328 | }; | |
2329 | ||
2330 | static int __init nvme_init(void) | |
2331 | { | |
0ac13140 | 2332 | int result; |
1fa6aead | 2333 | |
b9afca3e | 2334 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 2335 | |
92f7a162 | 2336 | nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); |
9a6b9458 | 2337 | if (!nvme_workq) |
b9afca3e | 2338 | return -ENOMEM; |
9a6b9458 | 2339 | |
5bae7f73 | 2340 | result = nvme_core_init(); |
5c42ea16 | 2341 | if (result < 0) |
9a6b9458 | 2342 | goto kill_workq; |
b60503ba | 2343 | |
f3db22fe KB |
2344 | result = pci_register_driver(&nvme_driver); |
2345 | if (result) | |
f3ca80fc | 2346 | goto core_exit; |
1fa6aead | 2347 | return 0; |
b60503ba | 2348 | |
f3ca80fc | 2349 | core_exit: |
5bae7f73 | 2350 | nvme_core_exit(); |
9a6b9458 KB |
2351 | kill_workq: |
2352 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
2353 | return result; |
2354 | } | |
2355 | ||
2356 | static void __exit nvme_exit(void) | |
2357 | { | |
2358 | pci_unregister_driver(&nvme_driver); | |
5bae7f73 | 2359 | nvme_core_exit(); |
9a6b9458 | 2360 | destroy_workqueue(nvme_workq); |
b9afca3e | 2361 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 2362 | _nvme_check_size(); |
b60503ba MW |
2363 | } |
2364 | ||
2365 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2366 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2367 | MODULE_VERSION("1.0"); |
b60503ba MW |
2368 | module_init(nvme_init); |
2369 | module_exit(nvme_exit); |