Commit | Line | Data |
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6b884a8d | 1 | |
5019f0b1 | 2 | #include <linux/device.h> |
6b884a8d GL |
3 | #include <linux/io.h> |
4 | #include <linux/ioport.h> | |
dbbdee94 | 5 | #include <linux/module.h> |
6b884a8d | 6 | #include <linux/of_address.h> |
dbbdee94 | 7 | #include <linux/pci_regs.h> |
41f8bba7 LD |
8 | #include <linux/sizes.h> |
9 | #include <linux/slab.h> | |
dbbdee94 | 10 | #include <linux/string.h> |
6b884a8d | 11 | |
dbbdee94 GL |
12 | /* Max address size we deal with */ |
13 | #define OF_MAX_ADDR_CELLS 4 | |
5d61b165 SW |
14 | #define OF_CHECK_ADDR_COUNT(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) |
15 | #define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && (ns) > 0) | |
dbbdee94 GL |
16 | |
17 | static struct of_bus *of_match_bus(struct device_node *np); | |
0131d897 SAS |
18 | static int __of_address_to_resource(struct device_node *dev, |
19 | const __be32 *addrp, u64 size, unsigned int flags, | |
35f3da32 | 20 | const char *name, struct resource *r); |
dbbdee94 GL |
21 | |
22 | /* Debug utility */ | |
23 | #ifdef DEBUG | |
0131d897 | 24 | static void of_dump_addr(const char *s, const __be32 *addr, int na) |
dbbdee94 GL |
25 | { |
26 | printk(KERN_DEBUG "%s", s); | |
27 | while (na--) | |
154063a9 | 28 | printk(" %08x", be32_to_cpu(*(addr++))); |
dbbdee94 GL |
29 | printk("\n"); |
30 | } | |
31 | #else | |
0131d897 | 32 | static void of_dump_addr(const char *s, const __be32 *addr, int na) { } |
dbbdee94 GL |
33 | #endif |
34 | ||
35 | /* Callbacks for bus specific translators */ | |
36 | struct of_bus { | |
37 | const char *name; | |
38 | const char *addresses; | |
39 | int (*match)(struct device_node *parent); | |
40 | void (*count_cells)(struct device_node *child, | |
41 | int *addrc, int *sizec); | |
47b1e689 | 42 | u64 (*map)(__be32 *addr, const __be32 *range, |
dbbdee94 | 43 | int na, int ns, int pna); |
47b1e689 | 44 | int (*translate)(__be32 *addr, u64 offset, int na); |
0131d897 | 45 | unsigned int (*get_flags)(const __be32 *addr); |
dbbdee94 GL |
46 | }; |
47 | ||
48 | /* | |
49 | * Default translator (generic bus) | |
50 | */ | |
51 | ||
52 | static void of_bus_default_count_cells(struct device_node *dev, | |
53 | int *addrc, int *sizec) | |
54 | { | |
55 | if (addrc) | |
56 | *addrc = of_n_addr_cells(dev); | |
57 | if (sizec) | |
58 | *sizec = of_n_size_cells(dev); | |
59 | } | |
60 | ||
47b1e689 | 61 | static u64 of_bus_default_map(__be32 *addr, const __be32 *range, |
dbbdee94 GL |
62 | int na, int ns, int pna) |
63 | { | |
64 | u64 cp, s, da; | |
65 | ||
66 | cp = of_read_number(range, na); | |
67 | s = of_read_number(range + na + pna, ns); | |
68 | da = of_read_number(addr, na); | |
69 | ||
70 | pr_debug("OF: default map, cp=%llx, s=%llx, da=%llx\n", | |
71 | (unsigned long long)cp, (unsigned long long)s, | |
72 | (unsigned long long)da); | |
73 | ||
74 | if (da < cp || da >= (cp + s)) | |
75 | return OF_BAD_ADDR; | |
76 | return da - cp; | |
77 | } | |
78 | ||
47b1e689 | 79 | static int of_bus_default_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
80 | { |
81 | u64 a = of_read_number(addr, na); | |
82 | memset(addr, 0, na * 4); | |
83 | a += offset; | |
84 | if (na > 1) | |
154063a9 GL |
85 | addr[na - 2] = cpu_to_be32(a >> 32); |
86 | addr[na - 1] = cpu_to_be32(a & 0xffffffffu); | |
dbbdee94 GL |
87 | |
88 | return 0; | |
89 | } | |
90 | ||
0131d897 | 91 | static unsigned int of_bus_default_get_flags(const __be32 *addr) |
dbbdee94 GL |
92 | { |
93 | return IORESOURCE_MEM; | |
94 | } | |
95 | ||
25a31579 | 96 | #ifdef CONFIG_OF_ADDRESS_PCI |
dbbdee94 GL |
97 | /* |
98 | * PCI bus specific translator | |
99 | */ | |
100 | ||
101 | static int of_bus_pci_match(struct device_node *np) | |
102 | { | |
6dd18e46 | 103 | /* |
14e2abb7 | 104 | * "pciex" is PCI Express |
6dd18e46 BH |
105 | * "vci" is for the /chaos bridge on 1st-gen PCI powermacs |
106 | * "ht" is hypertransport | |
107 | */ | |
14e2abb7 KSS |
108 | return !strcmp(np->type, "pci") || !strcmp(np->type, "pciex") || |
109 | !strcmp(np->type, "vci") || !strcmp(np->type, "ht"); | |
dbbdee94 GL |
110 | } |
111 | ||
112 | static void of_bus_pci_count_cells(struct device_node *np, | |
113 | int *addrc, int *sizec) | |
114 | { | |
115 | if (addrc) | |
116 | *addrc = 3; | |
117 | if (sizec) | |
118 | *sizec = 2; | |
119 | } | |
120 | ||
0131d897 | 121 | static unsigned int of_bus_pci_get_flags(const __be32 *addr) |
dbbdee94 GL |
122 | { |
123 | unsigned int flags = 0; | |
0131d897 | 124 | u32 w = be32_to_cpup(addr); |
dbbdee94 GL |
125 | |
126 | switch((w >> 24) & 0x03) { | |
127 | case 0x01: | |
128 | flags |= IORESOURCE_IO; | |
129 | break; | |
130 | case 0x02: /* 32 bits */ | |
131 | case 0x03: /* 64 bits */ | |
132 | flags |= IORESOURCE_MEM; | |
133 | break; | |
134 | } | |
135 | if (w & 0x40000000) | |
136 | flags |= IORESOURCE_PREFETCH; | |
137 | return flags; | |
138 | } | |
139 | ||
47b1e689 | 140 | static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns, |
0131d897 | 141 | int pna) |
dbbdee94 GL |
142 | { |
143 | u64 cp, s, da; | |
144 | unsigned int af, rf; | |
145 | ||
146 | af = of_bus_pci_get_flags(addr); | |
147 | rf = of_bus_pci_get_flags(range); | |
148 | ||
149 | /* Check address type match */ | |
150 | if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO)) | |
151 | return OF_BAD_ADDR; | |
152 | ||
153 | /* Read address values, skipping high cell */ | |
154 | cp = of_read_number(range + 1, na - 1); | |
155 | s = of_read_number(range + na + pna, ns); | |
156 | da = of_read_number(addr + 1, na - 1); | |
157 | ||
158 | pr_debug("OF: PCI map, cp=%llx, s=%llx, da=%llx\n", | |
159 | (unsigned long long)cp, (unsigned long long)s, | |
160 | (unsigned long long)da); | |
161 | ||
162 | if (da < cp || da >= (cp + s)) | |
163 | return OF_BAD_ADDR; | |
164 | return da - cp; | |
165 | } | |
166 | ||
47b1e689 | 167 | static int of_bus_pci_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
168 | { |
169 | return of_bus_default_translate(addr + 1, offset, na - 1); | |
170 | } | |
25a31579 | 171 | #endif /* CONFIG_OF_ADDRESS_PCI */ |
dbbdee94 | 172 | |
25a31579 | 173 | #ifdef CONFIG_PCI |
0131d897 | 174 | const __be32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size, |
dbbdee94 GL |
175 | unsigned int *flags) |
176 | { | |
a9fadeef | 177 | const __be32 *prop; |
dbbdee94 GL |
178 | unsigned int psize; |
179 | struct device_node *parent; | |
180 | struct of_bus *bus; | |
181 | int onesize, i, na, ns; | |
182 | ||
183 | /* Get parent & match bus type */ | |
184 | parent = of_get_parent(dev); | |
185 | if (parent == NULL) | |
186 | return NULL; | |
187 | bus = of_match_bus(parent); | |
188 | if (strcmp(bus->name, "pci")) { | |
189 | of_node_put(parent); | |
190 | return NULL; | |
191 | } | |
192 | bus->count_cells(dev, &na, &ns); | |
193 | of_node_put(parent); | |
5d61b165 | 194 | if (!OF_CHECK_ADDR_COUNT(na)) |
dbbdee94 GL |
195 | return NULL; |
196 | ||
197 | /* Get "reg" or "assigned-addresses" property */ | |
198 | prop = of_get_property(dev, bus->addresses, &psize); | |
199 | if (prop == NULL) | |
200 | return NULL; | |
201 | psize /= 4; | |
202 | ||
203 | onesize = na + ns; | |
154063a9 GL |
204 | for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++) { |
205 | u32 val = be32_to_cpu(prop[0]); | |
206 | if ((val & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0)) { | |
dbbdee94 GL |
207 | if (size) |
208 | *size = of_read_number(prop + na, ns); | |
209 | if (flags) | |
210 | *flags = bus->get_flags(prop); | |
211 | return prop; | |
212 | } | |
154063a9 | 213 | } |
dbbdee94 GL |
214 | return NULL; |
215 | } | |
216 | EXPORT_SYMBOL(of_get_pci_address); | |
217 | ||
218 | int of_pci_address_to_resource(struct device_node *dev, int bar, | |
219 | struct resource *r) | |
220 | { | |
0131d897 | 221 | const __be32 *addrp; |
dbbdee94 GL |
222 | u64 size; |
223 | unsigned int flags; | |
224 | ||
225 | addrp = of_get_pci_address(dev, bar, &size, &flags); | |
226 | if (addrp == NULL) | |
227 | return -EINVAL; | |
35f3da32 | 228 | return __of_address_to_resource(dev, addrp, size, flags, NULL, r); |
dbbdee94 GL |
229 | } |
230 | EXPORT_SYMBOL_GPL(of_pci_address_to_resource); | |
29b635c0 AM |
231 | |
232 | int of_pci_range_parser_init(struct of_pci_range_parser *parser, | |
233 | struct device_node *node) | |
234 | { | |
235 | const int na = 3, ns = 2; | |
236 | int rlen; | |
237 | ||
238 | parser->node = node; | |
239 | parser->pna = of_n_addr_cells(node); | |
240 | parser->np = parser->pna + na + ns; | |
241 | ||
242 | parser->range = of_get_property(node, "ranges", &rlen); | |
243 | if (parser->range == NULL) | |
244 | return -ENOENT; | |
245 | ||
246 | parser->end = parser->range + rlen / sizeof(__be32); | |
247 | ||
248 | return 0; | |
249 | } | |
250 | EXPORT_SYMBOL_GPL(of_pci_range_parser_init); | |
251 | ||
252 | struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, | |
253 | struct of_pci_range *range) | |
254 | { | |
255 | const int na = 3, ns = 2; | |
256 | ||
257 | if (!range) | |
258 | return NULL; | |
259 | ||
260 | if (!parser->range || parser->range + parser->np > parser->end) | |
261 | return NULL; | |
262 | ||
263 | range->pci_space = parser->range[0]; | |
264 | range->flags = of_bus_pci_get_flags(parser->range); | |
265 | range->pci_addr = of_read_number(parser->range + 1, ns); | |
266 | range->cpu_addr = of_translate_address(parser->node, | |
267 | parser->range + na); | |
268 | range->size = of_read_number(parser->range + parser->pna + na, ns); | |
269 | ||
270 | parser->range += parser->np; | |
271 | ||
272 | /* Now consume following elements while they are contiguous */ | |
273 | while (parser->range + parser->np <= parser->end) { | |
274 | u32 flags, pci_space; | |
275 | u64 pci_addr, cpu_addr, size; | |
276 | ||
277 | pci_space = be32_to_cpup(parser->range); | |
278 | flags = of_bus_pci_get_flags(parser->range); | |
279 | pci_addr = of_read_number(parser->range + 1, ns); | |
280 | cpu_addr = of_translate_address(parser->node, | |
281 | parser->range + na); | |
282 | size = of_read_number(parser->range + parser->pna + na, ns); | |
283 | ||
284 | if (flags != range->flags) | |
285 | break; | |
286 | if (pci_addr != range->pci_addr + range->size || | |
287 | cpu_addr != range->cpu_addr + range->size) | |
288 | break; | |
289 | ||
290 | range->size += size; | |
291 | parser->range += parser->np; | |
292 | } | |
293 | ||
294 | return range; | |
295 | } | |
296 | EXPORT_SYMBOL_GPL(of_pci_range_parser_one); | |
297 | ||
83bbde1c LD |
298 | void of_pci_range_to_resource(struct of_pci_range *range, |
299 | struct device_node *np, struct resource *res) | |
300 | { | |
301 | res->flags = range->flags; | |
302 | res->start = range->cpu_addr; | |
303 | res->end = range->cpu_addr + range->size - 1; | |
304 | res->parent = res->child = res->sibling = NULL; | |
305 | res->name = np->full_name; | |
306 | } | |
dbbdee94 GL |
307 | #endif /* CONFIG_PCI */ |
308 | ||
309 | /* | |
310 | * ISA bus specific translator | |
311 | */ | |
312 | ||
313 | static int of_bus_isa_match(struct device_node *np) | |
314 | { | |
315 | return !strcmp(np->name, "isa"); | |
316 | } | |
317 | ||
318 | static void of_bus_isa_count_cells(struct device_node *child, | |
319 | int *addrc, int *sizec) | |
320 | { | |
321 | if (addrc) | |
322 | *addrc = 2; | |
323 | if (sizec) | |
324 | *sizec = 1; | |
325 | } | |
326 | ||
47b1e689 | 327 | static u64 of_bus_isa_map(__be32 *addr, const __be32 *range, int na, int ns, |
0131d897 | 328 | int pna) |
dbbdee94 GL |
329 | { |
330 | u64 cp, s, da; | |
331 | ||
332 | /* Check address type match */ | |
0131d897 | 333 | if ((addr[0] ^ range[0]) & cpu_to_be32(1)) |
dbbdee94 GL |
334 | return OF_BAD_ADDR; |
335 | ||
336 | /* Read address values, skipping high cell */ | |
337 | cp = of_read_number(range + 1, na - 1); | |
338 | s = of_read_number(range + na + pna, ns); | |
339 | da = of_read_number(addr + 1, na - 1); | |
340 | ||
341 | pr_debug("OF: ISA map, cp=%llx, s=%llx, da=%llx\n", | |
342 | (unsigned long long)cp, (unsigned long long)s, | |
343 | (unsigned long long)da); | |
344 | ||
345 | if (da < cp || da >= (cp + s)) | |
346 | return OF_BAD_ADDR; | |
347 | return da - cp; | |
348 | } | |
349 | ||
47b1e689 | 350 | static int of_bus_isa_translate(__be32 *addr, u64 offset, int na) |
dbbdee94 GL |
351 | { |
352 | return of_bus_default_translate(addr + 1, offset, na - 1); | |
353 | } | |
354 | ||
0131d897 | 355 | static unsigned int of_bus_isa_get_flags(const __be32 *addr) |
dbbdee94 GL |
356 | { |
357 | unsigned int flags = 0; | |
0131d897 | 358 | u32 w = be32_to_cpup(addr); |
dbbdee94 GL |
359 | |
360 | if (w & 1) | |
361 | flags |= IORESOURCE_IO; | |
362 | else | |
363 | flags |= IORESOURCE_MEM; | |
364 | return flags; | |
365 | } | |
366 | ||
367 | /* | |
368 | * Array of bus specific translators | |
369 | */ | |
370 | ||
371 | static struct of_bus of_busses[] = { | |
25a31579 | 372 | #ifdef CONFIG_OF_ADDRESS_PCI |
dbbdee94 GL |
373 | /* PCI */ |
374 | { | |
375 | .name = "pci", | |
376 | .addresses = "assigned-addresses", | |
377 | .match = of_bus_pci_match, | |
378 | .count_cells = of_bus_pci_count_cells, | |
379 | .map = of_bus_pci_map, | |
380 | .translate = of_bus_pci_translate, | |
381 | .get_flags = of_bus_pci_get_flags, | |
382 | }, | |
25a31579 | 383 | #endif /* CONFIG_OF_ADDRESS_PCI */ |
dbbdee94 GL |
384 | /* ISA */ |
385 | { | |
386 | .name = "isa", | |
387 | .addresses = "reg", | |
388 | .match = of_bus_isa_match, | |
389 | .count_cells = of_bus_isa_count_cells, | |
390 | .map = of_bus_isa_map, | |
391 | .translate = of_bus_isa_translate, | |
392 | .get_flags = of_bus_isa_get_flags, | |
393 | }, | |
394 | /* Default */ | |
395 | { | |
396 | .name = "default", | |
397 | .addresses = "reg", | |
398 | .match = NULL, | |
399 | .count_cells = of_bus_default_count_cells, | |
400 | .map = of_bus_default_map, | |
401 | .translate = of_bus_default_translate, | |
402 | .get_flags = of_bus_default_get_flags, | |
403 | }, | |
404 | }; | |
405 | ||
406 | static struct of_bus *of_match_bus(struct device_node *np) | |
407 | { | |
408 | int i; | |
409 | ||
410 | for (i = 0; i < ARRAY_SIZE(of_busses); i++) | |
411 | if (!of_busses[i].match || of_busses[i].match(np)) | |
412 | return &of_busses[i]; | |
413 | BUG(); | |
414 | return NULL; | |
415 | } | |
416 | ||
417 | static int of_translate_one(struct device_node *parent, struct of_bus *bus, | |
47b1e689 | 418 | struct of_bus *pbus, __be32 *addr, |
dbbdee94 GL |
419 | int na, int ns, int pna, const char *rprop) |
420 | { | |
0131d897 | 421 | const __be32 *ranges; |
dbbdee94 GL |
422 | unsigned int rlen; |
423 | int rone; | |
424 | u64 offset = OF_BAD_ADDR; | |
425 | ||
426 | /* Normally, an absence of a "ranges" property means we are | |
427 | * crossing a non-translatable boundary, and thus the addresses | |
428 | * below the current not cannot be converted to CPU physical ones. | |
429 | * Unfortunately, while this is very clear in the spec, it's not | |
430 | * what Apple understood, and they do have things like /uni-n or | |
431 | * /ht nodes with no "ranges" property and a lot of perfectly | |
432 | * useable mapped devices below them. Thus we treat the absence of | |
433 | * "ranges" as equivalent to an empty "ranges" property which means | |
434 | * a 1:1 translation at that level. It's up to the caller not to try | |
435 | * to translate addresses that aren't supposed to be translated in | |
436 | * the first place. --BenH. | |
3930f294 GL |
437 | * |
438 | * As far as we know, this damage only exists on Apple machines, so | |
439 | * This code is only enabled on powerpc. --gcl | |
dbbdee94 GL |
440 | */ |
441 | ranges = of_get_property(parent, rprop, &rlen); | |
3930f294 GL |
442 | #if !defined(CONFIG_PPC) |
443 | if (ranges == NULL) { | |
444 | pr_err("OF: no ranges; cannot translate\n"); | |
445 | return 1; | |
446 | } | |
447 | #endif /* !defined(CONFIG_PPC) */ | |
dbbdee94 GL |
448 | if (ranges == NULL || rlen == 0) { |
449 | offset = of_read_number(addr, na); | |
450 | memset(addr, 0, pna * 4); | |
3930f294 | 451 | pr_debug("OF: empty ranges; 1:1 translation\n"); |
dbbdee94 GL |
452 | goto finish; |
453 | } | |
454 | ||
455 | pr_debug("OF: walking ranges...\n"); | |
456 | ||
457 | /* Now walk through the ranges */ | |
458 | rlen /= 4; | |
459 | rone = na + pna + ns; | |
460 | for (; rlen >= rone; rlen -= rone, ranges += rone) { | |
461 | offset = bus->map(addr, ranges, na, ns, pna); | |
462 | if (offset != OF_BAD_ADDR) | |
463 | break; | |
464 | } | |
465 | if (offset == OF_BAD_ADDR) { | |
466 | pr_debug("OF: not found !\n"); | |
467 | return 1; | |
468 | } | |
469 | memcpy(addr, ranges + na, 4 * pna); | |
470 | ||
471 | finish: | |
472 | of_dump_addr("OF: parent translation for:", addr, pna); | |
473 | pr_debug("OF: with offset: %llx\n", (unsigned long long)offset); | |
474 | ||
475 | /* Translate it into parent bus space */ | |
476 | return pbus->translate(addr, offset, pna); | |
477 | } | |
478 | ||
479 | /* | |
480 | * Translate an address from the device-tree into a CPU physical address, | |
481 | * this walks up the tree and applies the various bus mappings on the | |
482 | * way. | |
483 | * | |
484 | * Note: We consider that crossing any level with #size-cells == 0 to mean | |
485 | * that translation is impossible (that is we are not dealing with a value | |
486 | * that can be mapped to a cpu physical address). This is not really specified | |
487 | * that way, but this is traditionally the way IBM at least do things | |
488 | */ | |
47b1e689 KP |
489 | static u64 __of_translate_address(struct device_node *dev, |
490 | const __be32 *in_addr, const char *rprop) | |
dbbdee94 GL |
491 | { |
492 | struct device_node *parent = NULL; | |
493 | struct of_bus *bus, *pbus; | |
47b1e689 | 494 | __be32 addr[OF_MAX_ADDR_CELLS]; |
dbbdee94 GL |
495 | int na, ns, pna, pns; |
496 | u64 result = OF_BAD_ADDR; | |
497 | ||
8804827b | 498 | pr_debug("OF: ** translation for device %s **\n", of_node_full_name(dev)); |
dbbdee94 GL |
499 | |
500 | /* Increase refcount at current level */ | |
501 | of_node_get(dev); | |
502 | ||
503 | /* Get parent & match bus type */ | |
504 | parent = of_get_parent(dev); | |
505 | if (parent == NULL) | |
506 | goto bail; | |
507 | bus = of_match_bus(parent); | |
508 | ||
59f5ca48 | 509 | /* Count address cells & copy address locally */ |
dbbdee94 GL |
510 | bus->count_cells(dev, &na, &ns); |
511 | if (!OF_CHECK_COUNTS(na, ns)) { | |
d9c6866b | 512 | pr_debug("OF: Bad cell count for %s\n", of_node_full_name(dev)); |
dbbdee94 GL |
513 | goto bail; |
514 | } | |
515 | memcpy(addr, in_addr, na * 4); | |
516 | ||
517 | pr_debug("OF: bus is %s (na=%d, ns=%d) on %s\n", | |
8804827b | 518 | bus->name, na, ns, of_node_full_name(parent)); |
dbbdee94 GL |
519 | of_dump_addr("OF: translating address:", addr, na); |
520 | ||
521 | /* Translate */ | |
522 | for (;;) { | |
523 | /* Switch to parent bus */ | |
524 | of_node_put(dev); | |
525 | dev = parent; | |
526 | parent = of_get_parent(dev); | |
527 | ||
528 | /* If root, we have finished */ | |
529 | if (parent == NULL) { | |
530 | pr_debug("OF: reached root node\n"); | |
531 | result = of_read_number(addr, na); | |
532 | break; | |
533 | } | |
534 | ||
535 | /* Get new parent bus and counts */ | |
536 | pbus = of_match_bus(parent); | |
537 | pbus->count_cells(dev, &pna, &pns); | |
538 | if (!OF_CHECK_COUNTS(pna, pns)) { | |
539 | printk(KERN_ERR "prom_parse: Bad cell count for %s\n", | |
0c02c800 | 540 | of_node_full_name(dev)); |
dbbdee94 GL |
541 | break; |
542 | } | |
543 | ||
544 | pr_debug("OF: parent bus is %s (na=%d, ns=%d) on %s\n", | |
0c02c800 | 545 | pbus->name, pna, pns, of_node_full_name(parent)); |
dbbdee94 GL |
546 | |
547 | /* Apply bus translation */ | |
548 | if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop)) | |
549 | break; | |
550 | ||
551 | /* Complete the move up one level */ | |
552 | na = pna; | |
553 | ns = pns; | |
554 | bus = pbus; | |
555 | ||
556 | of_dump_addr("OF: one level translation:", addr, na); | |
557 | } | |
558 | bail: | |
559 | of_node_put(parent); | |
560 | of_node_put(dev); | |
561 | ||
562 | return result; | |
563 | } | |
564 | ||
0131d897 | 565 | u64 of_translate_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 GL |
566 | { |
567 | return __of_translate_address(dev, in_addr, "ranges"); | |
568 | } | |
569 | EXPORT_SYMBOL(of_translate_address); | |
570 | ||
0131d897 | 571 | u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr) |
dbbdee94 GL |
572 | { |
573 | return __of_translate_address(dev, in_addr, "dma-ranges"); | |
574 | } | |
575 | EXPORT_SYMBOL(of_translate_dma_address); | |
576 | ||
0131d897 | 577 | const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, |
dbbdee94 GL |
578 | unsigned int *flags) |
579 | { | |
0131d897 | 580 | const __be32 *prop; |
dbbdee94 GL |
581 | unsigned int psize; |
582 | struct device_node *parent; | |
583 | struct of_bus *bus; | |
584 | int onesize, i, na, ns; | |
585 | ||
586 | /* Get parent & match bus type */ | |
587 | parent = of_get_parent(dev); | |
588 | if (parent == NULL) | |
589 | return NULL; | |
590 | bus = of_match_bus(parent); | |
591 | bus->count_cells(dev, &na, &ns); | |
592 | of_node_put(parent); | |
5d61b165 | 593 | if (!OF_CHECK_ADDR_COUNT(na)) |
dbbdee94 GL |
594 | return NULL; |
595 | ||
596 | /* Get "reg" or "assigned-addresses" property */ | |
597 | prop = of_get_property(dev, bus->addresses, &psize); | |
598 | if (prop == NULL) | |
599 | return NULL; | |
600 | psize /= 4; | |
601 | ||
602 | onesize = na + ns; | |
603 | for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++) | |
604 | if (i == index) { | |
605 | if (size) | |
606 | *size = of_read_number(prop + na, ns); | |
607 | if (flags) | |
608 | *flags = bus->get_flags(prop); | |
609 | return prop; | |
610 | } | |
611 | return NULL; | |
612 | } | |
613 | EXPORT_SYMBOL(of_get_address); | |
614 | ||
41f8bba7 LD |
615 | #ifdef PCI_IOBASE |
616 | struct io_range { | |
617 | struct list_head list; | |
618 | phys_addr_t start; | |
619 | resource_size_t size; | |
620 | }; | |
621 | ||
622 | static LIST_HEAD(io_range_list); | |
623 | static DEFINE_SPINLOCK(io_range_lock); | |
624 | #endif | |
625 | ||
626 | /* | |
627 | * Record the PCI IO range (expressed as CPU physical address + size). | |
628 | * Return a negative value if an error has occured, zero otherwise | |
629 | */ | |
630 | int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size) | |
631 | { | |
632 | int err = 0; | |
633 | ||
634 | #ifdef PCI_IOBASE | |
635 | struct io_range *range; | |
636 | resource_size_t allocated_size = 0; | |
637 | ||
638 | /* check if the range hasn't been previously recorded */ | |
639 | spin_lock(&io_range_lock); | |
640 | list_for_each_entry(range, &io_range_list, list) { | |
641 | if (addr >= range->start && addr + size <= range->start + size) { | |
642 | /* range already registered, bail out */ | |
643 | goto end_register; | |
644 | } | |
645 | allocated_size += range->size; | |
646 | } | |
647 | ||
648 | /* range not registed yet, check for available space */ | |
649 | if (allocated_size + size - 1 > IO_SPACE_LIMIT) { | |
650 | /* if it's too big check if 64K space can be reserved */ | |
651 | if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { | |
652 | err = -E2BIG; | |
653 | goto end_register; | |
654 | } | |
655 | ||
656 | size = SZ_64K; | |
657 | pr_warn("Requested IO range too big, new size set to 64K\n"); | |
658 | } | |
659 | ||
660 | /* add the range to the list */ | |
661 | range = kzalloc(sizeof(*range), GFP_KERNEL); | |
662 | if (!range) { | |
663 | err = -ENOMEM; | |
664 | goto end_register; | |
665 | } | |
666 | ||
667 | range->start = addr; | |
668 | range->size = size; | |
669 | ||
670 | list_add_tail(&range->list, &io_range_list); | |
671 | ||
672 | end_register: | |
673 | spin_unlock(&io_range_lock); | |
674 | #endif | |
675 | ||
676 | return err; | |
677 | } | |
678 | ||
679 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
680 | { | |
681 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
682 | ||
683 | #ifdef PCI_IOBASE | |
684 | struct io_range *range; | |
685 | resource_size_t allocated_size = 0; | |
686 | ||
687 | if (pio > IO_SPACE_LIMIT) | |
688 | return address; | |
689 | ||
690 | spin_lock(&io_range_lock); | |
691 | list_for_each_entry(range, &io_range_list, list) { | |
692 | if (pio >= allocated_size && pio < allocated_size + range->size) { | |
693 | address = range->start + pio - allocated_size; | |
694 | break; | |
695 | } | |
696 | allocated_size += range->size; | |
697 | } | |
698 | spin_unlock(&io_range_lock); | |
699 | #endif | |
700 | ||
701 | return address; | |
702 | } | |
703 | ||
25ff7944 RH |
704 | unsigned long __weak pci_address_to_pio(phys_addr_t address) |
705 | { | |
41f8bba7 LD |
706 | #ifdef PCI_IOBASE |
707 | struct io_range *res; | |
708 | resource_size_t offset = 0; | |
709 | unsigned long addr = -1; | |
710 | ||
711 | spin_lock(&io_range_lock); | |
712 | list_for_each_entry(res, &io_range_list, list) { | |
713 | if (address >= res->start && address < res->start + res->size) { | |
714 | addr = res->start - address + offset; | |
715 | break; | |
716 | } | |
717 | offset += res->size; | |
718 | } | |
719 | spin_unlock(&io_range_lock); | |
720 | ||
721 | return addr; | |
722 | #else | |
25ff7944 RH |
723 | if (address > IO_SPACE_LIMIT) |
724 | return (unsigned long)-1; | |
725 | ||
726 | return (unsigned long) address; | |
41f8bba7 | 727 | #endif |
25ff7944 RH |
728 | } |
729 | ||
0131d897 SAS |
730 | static int __of_address_to_resource(struct device_node *dev, |
731 | const __be32 *addrp, u64 size, unsigned int flags, | |
35f3da32 | 732 | const char *name, struct resource *r) |
1f5bef30 GL |
733 | { |
734 | u64 taddr; | |
735 | ||
736 | if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) | |
737 | return -EINVAL; | |
738 | taddr = of_translate_address(dev, addrp); | |
739 | if (taddr == OF_BAD_ADDR) | |
740 | return -EINVAL; | |
741 | memset(r, 0, sizeof(struct resource)); | |
742 | if (flags & IORESOURCE_IO) { | |
743 | unsigned long port; | |
744 | port = pci_address_to_pio(taddr); | |
745 | if (port == (unsigned long)-1) | |
746 | return -EINVAL; | |
747 | r->start = port; | |
748 | r->end = port + size - 1; | |
749 | } else { | |
750 | r->start = taddr; | |
751 | r->end = taddr + size - 1; | |
752 | } | |
753 | r->flags = flags; | |
35f3da32 BC |
754 | r->name = name ? name : dev->full_name; |
755 | ||
1f5bef30 GL |
756 | return 0; |
757 | } | |
758 | ||
759 | /** | |
760 | * of_address_to_resource - Translate device tree address and return as resource | |
761 | * | |
762 | * Note that if your address is a PIO address, the conversion will fail if | |
763 | * the physical address can't be internally converted to an IO token with | |
764 | * pci_address_to_pio(), that is because it's either called to early or it | |
765 | * can't be matched to any host bridge IO space | |
766 | */ | |
767 | int of_address_to_resource(struct device_node *dev, int index, | |
768 | struct resource *r) | |
769 | { | |
0131d897 | 770 | const __be32 *addrp; |
1f5bef30 GL |
771 | u64 size; |
772 | unsigned int flags; | |
35f3da32 | 773 | const char *name = NULL; |
1f5bef30 GL |
774 | |
775 | addrp = of_get_address(dev, index, &size, &flags); | |
776 | if (addrp == NULL) | |
777 | return -EINVAL; | |
35f3da32 BC |
778 | |
779 | /* Get optional "reg-names" property to add a name to a resource */ | |
780 | of_property_read_string_index(dev, "reg-names", index, &name); | |
781 | ||
782 | return __of_address_to_resource(dev, addrp, size, flags, name, r); | |
1f5bef30 GL |
783 | } |
784 | EXPORT_SYMBOL_GPL(of_address_to_resource); | |
785 | ||
90e33f62 GL |
786 | struct device_node *of_find_matching_node_by_address(struct device_node *from, |
787 | const struct of_device_id *matches, | |
788 | u64 base_address) | |
789 | { | |
790 | struct device_node *dn = of_find_matching_node(from, matches); | |
791 | struct resource res; | |
792 | ||
793 | while (dn) { | |
794 | if (of_address_to_resource(dn, 0, &res)) | |
795 | continue; | |
796 | if (res.start == base_address) | |
797 | return dn; | |
798 | dn = of_find_matching_node(dn, matches); | |
799 | } | |
800 | ||
801 | return NULL; | |
802 | } | |
803 | ||
1f5bef30 | 804 | |
6b884a8d GL |
805 | /** |
806 | * of_iomap - Maps the memory mapped IO for a given device_node | |
807 | * @device: the device whose io range will be mapped | |
808 | * @index: index of the io range | |
809 | * | |
810 | * Returns a pointer to the mapped memory | |
811 | */ | |
812 | void __iomem *of_iomap(struct device_node *np, int index) | |
813 | { | |
814 | struct resource res; | |
815 | ||
816 | if (of_address_to_resource(np, index, &res)) | |
817 | return NULL; | |
818 | ||
28c1b6d6 | 819 | return ioremap(res.start, resource_size(&res)); |
6b884a8d GL |
820 | } |
821 | EXPORT_SYMBOL(of_iomap); | |
18308c94 | 822 | |
efd342fb MB |
823 | /* |
824 | * of_io_request_and_map - Requests a resource and maps the memory mapped IO | |
825 | * for a given device_node | |
826 | * @device: the device whose io range will be mapped | |
827 | * @index: index of the io range | |
828 | * @name: name of the resource | |
829 | * | |
830 | * Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded | |
831 | * error code on failure. Usage example: | |
832 | * | |
833 | * base = of_io_request_and_map(node, 0, "foo"); | |
834 | * if (IS_ERR(base)) | |
835 | * return PTR_ERR(base); | |
836 | */ | |
837 | void __iomem *of_io_request_and_map(struct device_node *np, int index, | |
838 | char *name) | |
839 | { | |
840 | struct resource res; | |
841 | void __iomem *mem; | |
842 | ||
843 | if (of_address_to_resource(np, index, &res)) | |
844 | return IOMEM_ERR_PTR(-EINVAL); | |
845 | ||
846 | if (!request_mem_region(res.start, resource_size(&res), name)) | |
847 | return IOMEM_ERR_PTR(-EBUSY); | |
848 | ||
849 | mem = ioremap(res.start, resource_size(&res)); | |
850 | if (!mem) { | |
851 | release_mem_region(res.start, resource_size(&res)); | |
852 | return IOMEM_ERR_PTR(-ENOMEM); | |
853 | } | |
854 | ||
855 | return mem; | |
856 | } | |
857 | EXPORT_SYMBOL(of_io_request_and_map); | |
858 | ||
18308c94 GS |
859 | /** |
860 | * of_dma_get_range - Get DMA range info | |
861 | * @np: device node to get DMA range info | |
862 | * @dma_addr: pointer to store initial DMA address of DMA range | |
863 | * @paddr: pointer to store initial CPU address of DMA range | |
864 | * @size: pointer to store size of DMA range | |
865 | * | |
866 | * Look in bottom up direction for the first "dma-ranges" property | |
867 | * and parse it. | |
868 | * dma-ranges format: | |
869 | * DMA addr (dma_addr) : naddr cells | |
870 | * CPU addr (phys_addr_t) : pna cells | |
871 | * size : nsize cells | |
872 | * | |
873 | * It returns -ENODEV if "dma-ranges" property was not found | |
874 | * for this device in DT. | |
875 | */ | |
876 | int of_dma_get_range(struct device_node *np, u64 *dma_addr, u64 *paddr, u64 *size) | |
877 | { | |
878 | struct device_node *node = of_node_get(np); | |
879 | const __be32 *ranges = NULL; | |
880 | int len, naddr, nsize, pna; | |
881 | int ret = 0; | |
882 | u64 dmaaddr; | |
883 | ||
884 | if (!node) | |
885 | return -EINVAL; | |
886 | ||
887 | while (1) { | |
888 | naddr = of_n_addr_cells(node); | |
889 | nsize = of_n_size_cells(node); | |
890 | node = of_get_next_parent(node); | |
891 | if (!node) | |
892 | break; | |
893 | ||
894 | ranges = of_get_property(node, "dma-ranges", &len); | |
895 | ||
896 | /* Ignore empty ranges, they imply no translation required */ | |
897 | if (ranges && len > 0) | |
898 | break; | |
899 | ||
900 | /* | |
901 | * At least empty ranges has to be defined for parent node if | |
902 | * DMA is supported | |
903 | */ | |
904 | if (!ranges) | |
905 | break; | |
906 | } | |
907 | ||
908 | if (!ranges) { | |
909 | pr_debug("%s: no dma-ranges found for node(%s)\n", | |
910 | __func__, np->full_name); | |
911 | ret = -ENODEV; | |
912 | goto out; | |
913 | } | |
914 | ||
915 | len /= sizeof(u32); | |
916 | ||
917 | pna = of_n_addr_cells(node); | |
918 | ||
919 | /* dma-ranges format: | |
920 | * DMA addr : naddr cells | |
921 | * CPU addr : pna cells | |
922 | * size : nsize cells | |
923 | */ | |
924 | dmaaddr = of_read_number(ranges, naddr); | |
925 | *paddr = of_translate_dma_address(np, ranges); | |
926 | if (*paddr == OF_BAD_ADDR) { | |
927 | pr_err("%s: translation of DMA address(%pad) to CPU address failed node(%s)\n", | |
928 | __func__, dma_addr, np->full_name); | |
929 | ret = -EINVAL; | |
930 | goto out; | |
931 | } | |
932 | *dma_addr = dmaaddr; | |
933 | ||
934 | *size = of_read_number(ranges + naddr + pna, nsize); | |
935 | ||
936 | pr_debug("dma_addr(%llx) cpu_addr(%llx) size(%llx)\n", | |
937 | *dma_addr, *paddr, *size); | |
938 | ||
939 | out: | |
940 | of_node_put(node); | |
941 | ||
942 | return ret; | |
943 | } | |
944 | EXPORT_SYMBOL_GPL(of_dma_get_range); | |
92ea637e SS |
945 | |
946 | /** | |
947 | * of_dma_is_coherent - Check if device is coherent | |
948 | * @np: device node | |
949 | * | |
950 | * It returns true if "dma-coherent" property was found | |
951 | * for this device in DT. | |
952 | */ | |
953 | bool of_dma_is_coherent(struct device_node *np) | |
954 | { | |
955 | struct device_node *node = of_node_get(np); | |
956 | ||
957 | while (node) { | |
958 | if (of_property_read_bool(node, "dma-coherent")) { | |
959 | of_node_put(node); | |
960 | return true; | |
961 | } | |
962 | node = of_get_next_parent(node); | |
963 | } | |
964 | of_node_put(node); | |
965 | return false; | |
966 | } | |
eb3d3ec5 | 967 | EXPORT_SYMBOL_GPL(of_dma_is_coherent); |