[deliverable/linux.git] / drivers / pci / access.c

#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/wait.h>

#include "pci.h"

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */

static DEFINE_RAW_SPINLOCK(pci_lock);

/*
 *  Wrappers for all PCI configuration access functions.  They just check
 *  alignment, do locking and call the low-level functions pointed to
 *  by pci_dev->ops.
 */

#define PCI_byte_BAD 0
#define PCI_word_BAD (pos & 1)
#define PCI_dword_BAD (pos & 3)

#define PCI_OP_READ(size,type,len) \
int pci_bus_read_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type *value)	\
{									\
	int res;							\
	unsigned long flags;						\
	u32 data = 0;							\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	raw_spin_lock_irqsave(&pci_lock, flags);			\
	res = bus->ops->read(bus, devfn, pos, len, &data);		\
	*value = (type)data;						\
	raw_spin_unlock_irqrestore(&pci_lock, flags);		\
	return res;							\
}

#define PCI_OP_WRITE(size,type,len) \
int pci_bus_write_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type value)	\
{									\
	int res;							\
	unsigned long flags;						\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	raw_spin_lock_irqsave(&pci_lock, flags);			\
	res = bus->ops->write(bus, devfn, pos, len, value);		\
	raw_spin_unlock_irqrestore(&pci_lock, flags);		\
	return res;							\
}

PCI_OP_READ(byte, u8, 1)
PCI_OP_READ(word, u16, 2)
PCI_OP_READ(dword, u32, 4)
PCI_OP_WRITE(byte, u8, 1)
PCI_OP_WRITE(word, u16, 2)
PCI_OP_WRITE(dword, u32, 4)

EXPORT_SYMBOL(pci_bus_read_config_byte);
EXPORT_SYMBOL(pci_bus_read_config_word);
EXPORT_SYMBOL(pci_bus_read_config_dword);
EXPORT_SYMBOL(pci_bus_write_config_byte);
EXPORT_SYMBOL(pci_bus_write_config_word);
EXPORT_SYMBOL(pci_bus_write_config_dword);

/**
 * pci_bus_set_ops - Set raw operations of pci bus
 * @bus:	pci bus struct
 * @ops:	new raw operations
 *
 * Return previous raw operations
 */
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
{
	struct pci_ops *old_ops;
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);
	old_ops = bus->ops;
	bus->ops = ops;
	raw_spin_unlock_irqrestore(&pci_lock, flags);
	return old_ops;
}
EXPORT_SYMBOL(pci_bus_set_ops);

/**
 * pci_read_vpd - Read one entry from Vital Product Data
 * @dev:	pci device struct
 * @pos:	offset in vpd space
 * @count:	number of bytes to read
 * @buf:	pointer to where to store result
 *
 */
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
{
	if (!dev->vpd || !dev->vpd->ops)
		return -ENODEV;
	return dev->vpd->ops->read(dev, pos, count, buf);
}
EXPORT_SYMBOL(pci_read_vpd);

/**
 * pci_write_vpd - Write entry to Vital Product Data
 * @dev:	pci device struct
 * @pos:	offset in vpd space
 * @count:	number of bytes to write
 * @buf:	buffer containing write data
 *
 */
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
{
	if (!dev->vpd || !dev->vpd->ops)
		return -ENODEV;
	return dev->vpd->ops->write(dev, pos, count, buf);
}
EXPORT_SYMBOL(pci_write_vpd);

/*
 * The following routines are to prevent the user from accessing PCI config
 * space when it's unsafe to do so.  Some devices require this during BIST and
 * we're required to prevent it during D-state transitions.
 *
 * We have a bit per device to indicate it's blocked and a global wait queue
 * for callers to sleep on until devices are unblocked.
 */
static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);

static noinline void pci_wait_ucfg(struct pci_dev *dev)
{
	DECLARE_WAITQUEUE(wait, current);

	__add_wait_queue(&pci_ucfg_wait, &wait);
	do {
		set_current_state(TASK_UNINTERRUPTIBLE);
		raw_spin_unlock_irq(&pci_lock);
		schedule();
		raw_spin_lock_irq(&pci_lock);
	} while (dev->block_ucfg_access);
	__remove_wait_queue(&pci_ucfg_wait, &wait);
}

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_READ_CONFIG(size,type)					\
int pci_user_read_config_##size						\
	(struct pci_dev *dev, int pos, type *val)			\
{									\
	int ret = 0;							\
	u32 data = -1;							\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev);	\
	ret = dev->bus->ops->read(dev->bus, dev->devfn,			\
					pos, sizeof(type), &data);	\
	raw_spin_unlock_irq(&pci_lock);				\
	*val = (type)data;						\
	if (ret > 0)							\
		ret = -EINVAL;						\
	return ret;							\
}

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_WRITE_CONFIG(size,type)				\
int pci_user_write_config_##size					\
	(struct pci_dev *dev, int pos, type val)			\
{									\
	int ret = -EIO;							\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev);	\
	ret = dev->bus->ops->write(dev->bus, dev->devfn,		\
					pos, sizeof(type), val);	\
	raw_spin_unlock_irq(&pci_lock);				\
	if (ret > 0)							\
		ret = -EINVAL;						\
	return ret;							\
}

PCI_USER_READ_CONFIG(byte, u8)
PCI_USER_READ_CONFIG(word, u16)
PCI_USER_READ_CONFIG(dword, u32)
PCI_USER_WRITE_CONFIG(byte, u8)
PCI_USER_WRITE_CONFIG(word, u16)
PCI_USER_WRITE_CONFIG(dword, u32)

/* VPD access through PCI 2.2+ VPD capability */

#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)

struct pci_vpd_pci22 {
	struct pci_vpd base;
	struct mutex lock;
	u16	flag;
	bool	busy;
	u8	cap;
};

/*
 * Wait for last operation to complete.
 * This code has to spin since there is no other notification from the PCI
 * hardware. Since the VPD is often implemented by serial attachment to an
 * EEPROM, it may take many milliseconds to complete.
 *
 * Returns 0 on success, negative values indicate error.
 */
static int pci_vpd_pci22_wait(struct pci_dev *dev)
{
	struct pci_vpd_pci22 *vpd =
		container_of(dev->vpd, struct pci_vpd_pci22, base);
	unsigned long timeout = jiffies + HZ/20 + 2;
	u16 status;
	int ret;

	if (!vpd->busy)
		return 0;

	for (;;) {
		ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						&status);
		if (ret < 0)
			return ret;

		if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
			vpd->busy = false;
			return 0;
		}

		if (time_after(jiffies, timeout)) {
			dev_printk(KERN_DEBUG, &dev->dev,
				   "vpd r/w failed.  This is likely a firmware "
				   "bug on this device.  Contact the card "
				   "vendor for a firmware update.");
			return -ETIMEDOUT;
		}
		if (fatal_signal_pending(current))
			return -EINTR;
		if (!cond_resched())
			udelay(10);
	}
}

static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
				  void *arg)
{
	struct pci_vpd_pci22 *vpd =
		container_of(dev->vpd, struct pci_vpd_pci22, base);
	int ret;
	loff_t end = pos + count;
	u8 *buf = arg;

	if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
		return -EINVAL;

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	ret = pci_vpd_pci22_wait(dev);
	if (ret < 0)
		goto out;

	while (pos < end) {
		u32 val;
		unsigned int i, skip;

		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos & ~3);
		if (ret < 0)
			break;
		vpd->busy = true;
		vpd->flag = PCI_VPD_ADDR_F;
		ret = pci_vpd_pci22_wait(dev);
		if (ret < 0)
			break;

		ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
		if (ret < 0)
			break;

		skip = pos & 3;
		for (i = 0;  i < sizeof(u32); i++) {
			if (i >= skip) {
				*buf++ = val;
				if (++pos == end)
					break;
			}
			val >>= 8;
		}
	}
out:
	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
				   const void *arg)
{
	struct pci_vpd_pci22 *vpd =
		container_of(dev->vpd, struct pci_vpd_pci22, base);
	const u8 *buf = arg;
	loff_t end = pos + count;
	int ret = 0;

	if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
		return -EINVAL;

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	ret = pci_vpd_pci22_wait(dev);
	if (ret < 0)
		goto out;

	while (pos < end) {
		u32 val;

		val = *buf++;
		val |= *buf++ << 8;
		val |= *buf++ << 16;
		val |= *buf++ << 24;

		ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
		if (ret < 0)
			break;
		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos | PCI_VPD_ADDR_F);
		if (ret < 0)
			break;

		vpd->busy = true;
		vpd->flag = 0;
		ret = pci_vpd_pci22_wait(dev);
		if (ret < 0)
			break;

		pos += sizeof(u32);
	}
out:
	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

static void pci_vpd_pci22_release(struct pci_dev *dev)
{
	kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
}

static const struct pci_vpd_ops pci_vpd_pci22_ops = {
	.read = pci_vpd_pci22_read,
	.write = pci_vpd_pci22_write,
	.release = pci_vpd_pci22_release,
};

int pci_vpd_pci22_init(struct pci_dev *dev)
{
	struct pci_vpd_pci22 *vpd;
	u8 cap;

	cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
	if (!cap)
		return -ENODEV;
	vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
	if (!vpd)
		return -ENOMEM;

	vpd->base.len = PCI_VPD_PCI22_SIZE;
	vpd->base.ops = &pci_vpd_pci22_ops;
	mutex_init(&vpd->lock);
	vpd->cap = cap;
	vpd->busy = false;
	dev->vpd = &vpd->base;
	return 0;
}

/**
 * pci_vpd_truncate - Set available Vital Product Data size
 * @dev:	pci device struct
 * @size:	available memory in bytes
 *
 * Adjust size of available VPD area.
 */
int pci_vpd_truncate(struct pci_dev *dev, size_t size)
{
	if (!dev->vpd)
		return -EINVAL;

	/* limited by the access method */
	if (size > dev->vpd->len)
		return -EINVAL;

	dev->vpd->len = size;
	if (dev->vpd->attr)
		dev->vpd->attr->size = size;

	return 0;
}
EXPORT_SYMBOL(pci_vpd_truncate);

/**
 * pci_block_user_cfg_access - Block userspace PCI config reads/writes
 * @dev:	pci device struct
 *
 * When user access is blocked, any reads or writes to config space will
 * sleep until access is unblocked again.  We don't allow nesting of
 * block/unblock calls.
 */
void pci_block_user_cfg_access(struct pci_dev *dev)
{
	unsigned long flags;
	int was_blocked;

	raw_spin_lock_irqsave(&pci_lock, flags);
	was_blocked = dev->block_ucfg_access;
	dev->block_ucfg_access = 1;
	raw_spin_unlock_irqrestore(&pci_lock, flags);

	/* If we BUG() inside the pci_lock, we're guaranteed to hose
	 * the machine */
	BUG_ON(was_blocked);
}
EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);

/**
 * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
 * @dev:	pci device struct
 *
 * This function allows userspace PCI config accesses to resume.
 */
void pci_unblock_user_cfg_access(struct pci_dev *dev)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);

	/* This indicates a problem in the caller, but we don't need
	 * to kill them, unlike a double-block above. */
	WARN_ON(!dev->block_ucfg_access);

	dev->block_ucfg_access = 0;
	wake_up_all(&pci_ucfg_wait);
	raw_spin_unlock_irqrestore(&pci_lock, flags);
}
EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
Commit	Line	Data
94e61088	1	#include <linux/delay.h>
1da177e4 LT	2	#include <linux/pci.h>
1da177e4 LT	3	#include <linux/module.h>
f6a57033	4	#include <linux/sched.h>
5a0e3ad6	5	#include <linux/slab.h>
1da177e4	6	#include <linux/ioport.h>
7ea7e98f	7	#include <linux/wait.h>
1da177e4	8
48b19148 AB	9	#include "pci.h"
48b19148 AB	10
1da177e4 LT	11	/*
	12	* This interrupt-safe spinlock protects all accesses to PCI
	13	* configuration space.
	14	*/
	15
511dd98c	16	static DEFINE_RAW_SPINLOCK(pci_lock);
1da177e4 LT	17
	18	/*
	19	* Wrappers for all PCI configuration access functions. They just check
	20	* alignment, do locking and call the low-level functions pointed to
	21	* by pci_dev->ops.
	22	*/
	23
	24	#define PCI_byte_BAD 0
	25	#define PCI_word_BAD (pos & 1)
	26	#define PCI_dword_BAD (pos & 3)
	27
	28	#define PCI_OP_READ(size,type,len) \
	29	int pci_bus_read_config_##size \
	30	(struct pci_bus bus, unsigned int devfn, int pos, type value) \
	31	{ \
	32	int res; \
	33	unsigned long flags; \
	34	u32 data = 0; \
	35	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
511dd98c	36	raw_spin_lock_irqsave(&pci_lock, flags); \
1da177e4 LT	37	res = bus->ops->read(bus, devfn, pos, len, &data); \
1da177e4 LT	38	*value = (type)data; \
511dd98c	39	raw_spin_unlock_irqrestore(&pci_lock, flags); \
1da177e4 LT	40	return res; \
	41	}
	42
	43	#define PCI_OP_WRITE(size,type,len) \
	44	int pci_bus_write_config_##size \
	45	(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
	46	{ \
	47	int res; \
	48	unsigned long flags; \
	49	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
511dd98c	50	raw_spin_lock_irqsave(&pci_lock, flags); \
1da177e4	51	res = bus->ops->write(bus, devfn, pos, len, value); \
511dd98c	52	raw_spin_unlock_irqrestore(&pci_lock, flags); \
1da177e4 LT	53	return res; \
	54	}
	55
	56	PCI_OP_READ(byte, u8, 1)
	57	PCI_OP_READ(word, u16, 2)
	58	PCI_OP_READ(dword, u32, 4)
	59	PCI_OP_WRITE(byte, u8, 1)
	60	PCI_OP_WRITE(word, u16, 2)
	61	PCI_OP_WRITE(dword, u32, 4)
	62
	63	EXPORT_SYMBOL(pci_bus_read_config_byte);
	64	EXPORT_SYMBOL(pci_bus_read_config_word);
	65	EXPORT_SYMBOL(pci_bus_read_config_dword);
	66	EXPORT_SYMBOL(pci_bus_write_config_byte);
	67	EXPORT_SYMBOL(pci_bus_write_config_word);
	68	EXPORT_SYMBOL(pci_bus_write_config_dword);
e04b0ea2	69
a72b46c3 HY	70	/**
	71	* pci_bus_set_ops - Set raw operations of pci bus
	72	* @bus: pci bus struct
	73	* @ops: new raw operations
	74	*
	75	* Return previous raw operations
	76	*/
	77	struct pci_ops pci_bus_set_ops(struct pci_bus bus, struct pci_ops *ops)
	78	{
	79	struct pci_ops *old_ops;
	80	unsigned long flags;
	81
511dd98c	82	raw_spin_lock_irqsave(&pci_lock, flags);
a72b46c3 HY	83	old_ops = bus->ops;
a72b46c3 HY	84	bus->ops = ops;
511dd98c	85	raw_spin_unlock_irqrestore(&pci_lock, flags);
a72b46c3 HY	86	return old_ops;
	87	}
	88	EXPORT_SYMBOL(pci_bus_set_ops);
287d19ce SH	89
	90	/**
	91	* pci_read_vpd - Read one entry from Vital Product Data
	92	* @dev: pci device struct
	93	* @pos: offset in vpd space
	94	* @count: number of bytes to read
	95	* @buf: pointer to where to store result
	96	*
	97	*/
	98	ssize_t pci_read_vpd(struct pci_dev dev, loff_t pos, size_t count, void buf)
	99	{
	100	if (!dev->vpd \|\| !dev->vpd->ops)
	101	return -ENODEV;
	102	return dev->vpd->ops->read(dev, pos, count, buf);
	103	}
	104	EXPORT_SYMBOL(pci_read_vpd);
	105
	106	/**
	107	* pci_write_vpd - Write entry to Vital Product Data
	108	* @dev: pci device struct
	109	* @pos: offset in vpd space
cffb2faf RD	110	* @count: number of bytes to write
cffb2faf RD	111	* @buf: buffer containing write data
287d19ce SH	112	*
	113	*/
	114	ssize_t pci_write_vpd(struct pci_dev dev, loff_t pos, size_t count, const void buf)
	115	{
	116	if (!dev->vpd \|\| !dev->vpd->ops)
	117	return -ENODEV;
	118	return dev->vpd->ops->write(dev, pos, count, buf);
	119	}
	120	EXPORT_SYMBOL(pci_write_vpd);
	121
7ea7e98f MW	122	/*
	123	* The following routines are to prevent the user from accessing PCI config
	124	* space when it's unsafe to do so. Some devices require this during BIST and
	125	* we're required to prevent it during D-state transitions.
	126	*
	127	* We have a bit per device to indicate it's blocked and a global wait queue
	128	* for callers to sleep on until devices are unblocked.
	129	*/
	130	static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
e04b0ea2	131
7ea7e98f MW	132	static noinline void pci_wait_ucfg(struct pci_dev *dev)
	133	{
	134	DECLARE_WAITQUEUE(wait, current);
	135
	136	__add_wait_queue(&pci_ucfg_wait, &wait);
	137	do {
	138	set_current_state(TASK_UNINTERRUPTIBLE);
511dd98c	139	raw_spin_unlock_irq(&pci_lock);
7ea7e98f	140	schedule();
511dd98c	141	raw_spin_lock_irq(&pci_lock);
7ea7e98f MW	142	} while (dev->block_ucfg_access);
7ea7e98f MW	143	__remove_wait_queue(&pci_ucfg_wait, &wait);
e04b0ea2 BK	144	}
e04b0ea2 BK	145
34e32072	146	/* Returns 0 on success, negative values indicate error. */
e04b0ea2 BK	147	#define PCI_USER_READ_CONFIG(size,type) \
	148	int pci_user_read_config_##size \
	149	(struct pci_dev dev, int pos, type val) \
	150	{ \
e04b0ea2 BK	151	int ret = 0; \
e04b0ea2 BK	152	u32 data = -1; \
34e32072 GT	153	if (PCI_##size##_BAD) \
34e32072 GT	154	return -EINVAL; \
511dd98c	155	raw_spin_lock_irq(&pci_lock); \
7ea7e98f MW	156	if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
7ea7e98f MW	157	ret = dev->bus->ops->read(dev->bus, dev->devfn, \
e04b0ea2	158	pos, sizeof(type), &data); \
511dd98c	159	raw_spin_unlock_irq(&pci_lock); \
e04b0ea2	160	*val = (type)data; \
34e32072 GT	161	if (ret > 0) \
34e32072 GT	162	ret = -EINVAL; \
e04b0ea2 BK	163	return ret; \
	164	}
	165
34e32072	166	/* Returns 0 on success, negative values indicate error. */
e04b0ea2 BK	167	#define PCI_USER_WRITE_CONFIG(size,type) \
	168	int pci_user_write_config_##size \
	169	(struct pci_dev *dev, int pos, type val) \
	170	{ \
e04b0ea2	171	int ret = -EIO; \
34e32072 GT	172	if (PCI_##size##_BAD) \
34e32072 GT	173	return -EINVAL; \
511dd98c	174	raw_spin_lock_irq(&pci_lock); \
7ea7e98f MW	175	if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
7ea7e98f MW	176	ret = dev->bus->ops->write(dev->bus, dev->devfn, \
e04b0ea2	177	pos, sizeof(type), val); \
511dd98c	178	raw_spin_unlock_irq(&pci_lock); \
34e32072 GT	179	if (ret > 0) \
34e32072 GT	180	ret = -EINVAL; \
e04b0ea2 BK	181	return ret; \
	182	}
	183
	184	PCI_USER_READ_CONFIG(byte, u8)
	185	PCI_USER_READ_CONFIG(word, u16)
	186	PCI_USER_READ_CONFIG(dword, u32)
	187	PCI_USER_WRITE_CONFIG(byte, u8)
	188	PCI_USER_WRITE_CONFIG(word, u16)
	189	PCI_USER_WRITE_CONFIG(dword, u32)
	190
94e61088 BH	191	/* VPD access through PCI 2.2+ VPD capability */
	192
	193	#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
	194
	195	struct pci_vpd_pci22 {
	196	struct pci_vpd base;
1120f8b8 SH	197	struct mutex lock;
1120f8b8 SH	198	u16 flag;
94e61088	199	bool busy;
1120f8b8	200	u8 cap;
94e61088 BH	201	};
94e61088 BH	202
1120f8b8 SH	203	/*
	204	* Wait for last operation to complete.
	205	* This code has to spin since there is no other notification from the PCI
	206	* hardware. Since the VPD is often implemented by serial attachment to an
	207	* EEPROM, it may take many milliseconds to complete.
34e32072 GT	208	*
34e32072 GT	209	* Returns 0 on success, negative values indicate error.
1120f8b8	210	*/
94e61088 BH	211	static int pci_vpd_pci22_wait(struct pci_dev *dev)
	212	{
	213	struct pci_vpd_pci22 *vpd =
	214	container_of(dev->vpd, struct pci_vpd_pci22, base);
1120f8b8 SH	215	unsigned long timeout = jiffies + HZ/20 + 2;
1120f8b8 SH	216	u16 status;
94e61088 BH	217	int ret;
	218
	219	if (!vpd->busy)
	220	return 0;
	221
94e61088	222	for (;;) {
1120f8b8	223	ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
94e61088	224	&status);
34e32072	225	if (ret < 0)
94e61088	226	return ret;
1120f8b8 SH	227
1120f8b8 SH	228	if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
94e61088 BH	229	vpd->busy = false;
	230	return 0;
	231	}
1120f8b8	232
5030718e PB	233	if (time_after(jiffies, timeout)) {
	234	dev_printk(KERN_DEBUG, &dev->dev,
	235	"vpd r/w failed. This is likely a firmware "
	236	"bug on this device. Contact the card "
	237	"vendor for a firmware update.");
94e61088	238	return -ETIMEDOUT;
5030718e	239	}
1120f8b8 SH	240	if (fatal_signal_pending(current))
	241	return -EINTR;
	242	if (!cond_resched())
	243	udelay(10);
94e61088 BH	244	}
	245	}
	246
287d19ce SH	247	static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
287d19ce SH	248	void *arg)
94e61088 BH	249	{
	250	struct pci_vpd_pci22 *vpd =
	251	container_of(dev->vpd, struct pci_vpd_pci22, base);
287d19ce SH	252	int ret;
	253	loff_t end = pos + count;
	254	u8 *buf = arg;
94e61088	255
287d19ce	256	if (pos < 0 \|\| pos > vpd->base.len \|\| end > vpd->base.len)
94e61088	257	return -EINVAL;
94e61088	258
1120f8b8 SH	259	if (mutex_lock_killable(&vpd->lock))
	260	return -EINTR;
	261
94e61088 BH	262	ret = pci_vpd_pci22_wait(dev);
	263	if (ret < 0)
	264	goto out;
1120f8b8	265
287d19ce SH	266	while (pos < end) {
	267	u32 val;
	268	unsigned int i, skip;
	269
	270	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	271	pos & ~3);
	272	if (ret < 0)
	273	break;
	274	vpd->busy = true;
	275	vpd->flag = PCI_VPD_ADDR_F;
	276	ret = pci_vpd_pci22_wait(dev);
	277	if (ret < 0)
	278	break;
	279
	280	ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
	281	if (ret < 0)
	282	break;
	283
	284	skip = pos & 3;
	285	for (i = 0; i < sizeof(u32); i++) {
	286	if (i >= skip) {
	287	*buf++ = val;
	288	if (++pos == end)
	289	break;
	290	}
	291	val >>= 8;
	292	}
	293	}
94e61088	294	out:
1120f8b8	295	mutex_unlock(&vpd->lock);
287d19ce	296	return ret ? ret : count;
94e61088 BH	297	}
94e61088 BH	298
287d19ce SH	299	static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
287d19ce SH	300	const void *arg)
94e61088 BH	301	{
	302	struct pci_vpd_pci22 *vpd =
	303	container_of(dev->vpd, struct pci_vpd_pci22, base);
287d19ce SH	304	const u8 *buf = arg;
287d19ce SH	305	loff_t end = pos + count;
1120f8b8	306	int ret = 0;
94e61088	307
287d19ce	308	if (pos < 0 \|\| (pos & 3) \|\| (count & 3) \|\| end > vpd->base.len)
94e61088 BH	309	return -EINVAL;
94e61088 BH	310
1120f8b8 SH	311	if (mutex_lock_killable(&vpd->lock))
1120f8b8 SH	312	return -EINTR;
287d19ce	313
94e61088 BH	314	ret = pci_vpd_pci22_wait(dev);
	315	if (ret < 0)
	316	goto out;
287d19ce SH	317
	318	while (pos < end) {
	319	u32 val;
	320
	321	val = *buf++;
	322	val \|= *buf++ << 8;
	323	val \|= *buf++ << 16;
	324	val \|= *buf++ << 24;
	325
	326	ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
	327	if (ret < 0)
	328	break;
	329	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	330	pos \| PCI_VPD_ADDR_F);
	331	if (ret < 0)
	332	break;
	333
	334	vpd->busy = true;
	335	vpd->flag = 0;
	336	ret = pci_vpd_pci22_wait(dev);
d97ecd81 GT	337	if (ret < 0)
d97ecd81 GT	338	break;
287d19ce SH	339
	340	pos += sizeof(u32);
	341	}
94e61088	342	out:
1120f8b8	343	mutex_unlock(&vpd->lock);
287d19ce	344	return ret ? ret : count;
94e61088 BH	345	}
94e61088 BH	346
94e61088 BH	347	static void pci_vpd_pci22_release(struct pci_dev *dev)
	348	{
	349	kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
	350	}
	351
287d19ce	352	static const struct pci_vpd_ops pci_vpd_pci22_ops = {
94e61088 BH	353	.read = pci_vpd_pci22_read,
94e61088 BH	354	.write = pci_vpd_pci22_write,
94e61088 BH	355	.release = pci_vpd_pci22_release,
	356	};
	357
	358	int pci_vpd_pci22_init(struct pci_dev *dev)
	359	{
	360	struct pci_vpd_pci22 *vpd;
	361	u8 cap;
	362
	363	cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
	364	if (!cap)
	365	return -ENODEV;
	366	vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
	367	if (!vpd)
	368	return -ENOMEM;
	369
99cb233d	370	vpd->base.len = PCI_VPD_PCI22_SIZE;
94e61088	371	vpd->base.ops = &pci_vpd_pci22_ops;
1120f8b8	372	mutex_init(&vpd->lock);
94e61088 BH	373	vpd->cap = cap;
	374	vpd->busy = false;
	375	dev->vpd = &vpd->base;
	376	return 0;
	377	}
	378
db567943 SH	379	/**
	380	* pci_vpd_truncate - Set available Vital Product Data size
	381	* @dev: pci device struct
	382	* @size: available memory in bytes
	383	*
	384	* Adjust size of available VPD area.
	385	*/
	386	int pci_vpd_truncate(struct pci_dev *dev, size_t size)
	387	{
	388	if (!dev->vpd)
	389	return -EINVAL;
	390
	391	/* limited by the access method */
	392	if (size > dev->vpd->len)
	393	return -EINVAL;
	394
	395	dev->vpd->len = size;
d407e32e AV	396	if (dev->vpd->attr)
d407e32e AV	397	dev->vpd->attr->size = size;
db567943 SH	398
	399	return 0;
	400	}
	401	EXPORT_SYMBOL(pci_vpd_truncate);
	402
e04b0ea2 BK	403	/**
	404	* pci_block_user_cfg_access - Block userspace PCI config reads/writes
	405	* @dev: pci device struct
	406	*
7ea7e98f MW	407	* When user access is blocked, any reads or writes to config space will
	408	* sleep until access is unblocked again. We don't allow nesting of
	409	* block/unblock calls.
	410	*/
e04b0ea2 BK	411	void pci_block_user_cfg_access(struct pci_dev *dev)
	412	{
	413	unsigned long flags;
7ea7e98f	414	int was_blocked;
e04b0ea2	415
511dd98c	416	raw_spin_lock_irqsave(&pci_lock, flags);
7ea7e98f	417	was_blocked = dev->block_ucfg_access;
e04b0ea2	418	dev->block_ucfg_access = 1;
511dd98c	419	raw_spin_unlock_irqrestore(&pci_lock, flags);
7ea7e98f MW	420
	421	/* If we BUG() inside the pci_lock, we're guaranteed to hose
	422	* the machine */
	423	BUG_ON(was_blocked);
e04b0ea2 BK	424	}
	425	EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
	426
	427	/**
	428	* pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
	429	* @dev: pci device struct
	430	*
	431	* This function allows userspace PCI config accesses to resume.
7ea7e98f	432	*/
e04b0ea2 BK	433	void pci_unblock_user_cfg_access(struct pci_dev *dev)
	434	{
	435	unsigned long flags;
	436
511dd98c	437	raw_spin_lock_irqsave(&pci_lock, flags);
7ea7e98f MW	438
	439	/* This indicates a problem in the caller, but we don't need
	440	* to kill them, unlike a double-block above. */
	441	WARN_ON(!dev->block_ucfg_access);
	442
e04b0ea2	443	dev->block_ucfg_access = 0;
7ea7e98f	444	wake_up_all(&pci_ucfg_wait);
511dd98c	445	raw_spin_unlock_irqrestore(&pci_lock, flags);
e04b0ea2 BK	446	}
e04b0ea2 BK	447	EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);