Commit | Line | Data |
---|---|---|
94e61088 | 1 | #include <linux/delay.h> |
1da177e4 LT |
2 | #include <linux/pci.h> |
3 | #include <linux/module.h> | |
f6a57033 | 4 | #include <linux/sched.h> |
5a0e3ad6 | 5 | #include <linux/slab.h> |
1da177e4 | 6 | #include <linux/ioport.h> |
7ea7e98f | 7 | #include <linux/wait.h> |
1da177e4 | 8 | |
48b19148 AB |
9 | #include "pci.h" |
10 | ||
1da177e4 LT |
11 | /* |
12 | * This interrupt-safe spinlock protects all accesses to PCI | |
13 | * configuration space. | |
14 | */ | |
15 | ||
a2e27787 | 16 | DEFINE_RAW_SPINLOCK(pci_lock); |
1da177e4 LT |
17 | |
18 | /* | |
19 | * Wrappers for all PCI configuration access functions. They just check | |
20 | * alignment, do locking and call the low-level functions pointed to | |
21 | * by pci_dev->ops. | |
22 | */ | |
23 | ||
24 | #define PCI_byte_BAD 0 | |
25 | #define PCI_word_BAD (pos & 1) | |
26 | #define PCI_dword_BAD (pos & 3) | |
27 | ||
ff3ce480 | 28 | #define PCI_OP_READ(size, type, len) \ |
1da177e4 LT |
29 | int pci_bus_read_config_##size \ |
30 | (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ | |
31 | { \ | |
32 | int res; \ | |
33 | unsigned long flags; \ | |
34 | u32 data = 0; \ | |
35 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 36 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 LT |
37 | res = bus->ops->read(bus, devfn, pos, len, &data); \ |
38 | *value = (type)data; \ | |
511dd98c | 39 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
40 | return res; \ |
41 | } | |
42 | ||
ff3ce480 | 43 | #define PCI_OP_WRITE(size, type, len) \ |
1da177e4 LT |
44 | int pci_bus_write_config_##size \ |
45 | (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ | |
46 | { \ | |
47 | int res; \ | |
48 | unsigned long flags; \ | |
49 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 50 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 | 51 | res = bus->ops->write(bus, devfn, pos, len, value); \ |
511dd98c | 52 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
53 | return res; \ |
54 | } | |
55 | ||
56 | PCI_OP_READ(byte, u8, 1) | |
57 | PCI_OP_READ(word, u16, 2) | |
58 | PCI_OP_READ(dword, u32, 4) | |
59 | PCI_OP_WRITE(byte, u8, 1) | |
60 | PCI_OP_WRITE(word, u16, 2) | |
61 | PCI_OP_WRITE(dword, u32, 4) | |
62 | ||
63 | EXPORT_SYMBOL(pci_bus_read_config_byte); | |
64 | EXPORT_SYMBOL(pci_bus_read_config_word); | |
65 | EXPORT_SYMBOL(pci_bus_read_config_dword); | |
66 | EXPORT_SYMBOL(pci_bus_write_config_byte); | |
67 | EXPORT_SYMBOL(pci_bus_write_config_word); | |
68 | EXPORT_SYMBOL(pci_bus_write_config_dword); | |
e04b0ea2 | 69 | |
1f94a94f RH |
70 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
71 | int where, int size, u32 *val) | |
72 | { | |
73 | void __iomem *addr; | |
74 | ||
75 | addr = bus->ops->map_bus(bus, devfn, where); | |
76 | if (!addr) { | |
77 | *val = ~0; | |
78 | return PCIBIOS_DEVICE_NOT_FOUND; | |
79 | } | |
80 | ||
81 | if (size == 1) | |
82 | *val = readb(addr); | |
83 | else if (size == 2) | |
84 | *val = readw(addr); | |
85 | else | |
86 | *val = readl(addr); | |
87 | ||
88 | return PCIBIOS_SUCCESSFUL; | |
89 | } | |
90 | EXPORT_SYMBOL_GPL(pci_generic_config_read); | |
91 | ||
92 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
93 | int where, int size, u32 val) | |
94 | { | |
95 | void __iomem *addr; | |
96 | ||
97 | addr = bus->ops->map_bus(bus, devfn, where); | |
98 | if (!addr) | |
99 | return PCIBIOS_DEVICE_NOT_FOUND; | |
100 | ||
101 | if (size == 1) | |
102 | writeb(val, addr); | |
103 | else if (size == 2) | |
104 | writew(val, addr); | |
105 | else | |
106 | writel(val, addr); | |
107 | ||
108 | return PCIBIOS_SUCCESSFUL; | |
109 | } | |
110 | EXPORT_SYMBOL_GPL(pci_generic_config_write); | |
111 | ||
112 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
113 | int where, int size, u32 *val) | |
114 | { | |
115 | void __iomem *addr; | |
116 | ||
117 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
118 | if (!addr) { | |
119 | *val = ~0; | |
120 | return PCIBIOS_DEVICE_NOT_FOUND; | |
121 | } | |
122 | ||
123 | *val = readl(addr); | |
124 | ||
125 | if (size <= 2) | |
126 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
127 | ||
128 | return PCIBIOS_SUCCESSFUL; | |
129 | } | |
130 | EXPORT_SYMBOL_GPL(pci_generic_config_read32); | |
131 | ||
132 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
133 | int where, int size, u32 val) | |
134 | { | |
135 | void __iomem *addr; | |
136 | u32 mask, tmp; | |
137 | ||
138 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
139 | if (!addr) | |
140 | return PCIBIOS_DEVICE_NOT_FOUND; | |
141 | ||
142 | if (size == 4) { | |
143 | writel(val, addr); | |
144 | return PCIBIOS_SUCCESSFUL; | |
145 | } else { | |
146 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); | |
147 | } | |
148 | ||
149 | tmp = readl(addr) & mask; | |
150 | tmp |= val << ((where & 0x3) * 8); | |
151 | writel(tmp, addr); | |
152 | ||
153 | return PCIBIOS_SUCCESSFUL; | |
154 | } | |
155 | EXPORT_SYMBOL_GPL(pci_generic_config_write32); | |
156 | ||
a72b46c3 HY |
157 | /** |
158 | * pci_bus_set_ops - Set raw operations of pci bus | |
159 | * @bus: pci bus struct | |
160 | * @ops: new raw operations | |
161 | * | |
162 | * Return previous raw operations | |
163 | */ | |
164 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) | |
165 | { | |
166 | struct pci_ops *old_ops; | |
167 | unsigned long flags; | |
168 | ||
511dd98c | 169 | raw_spin_lock_irqsave(&pci_lock, flags); |
a72b46c3 HY |
170 | old_ops = bus->ops; |
171 | bus->ops = ops; | |
511dd98c | 172 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
a72b46c3 HY |
173 | return old_ops; |
174 | } | |
175 | EXPORT_SYMBOL(pci_bus_set_ops); | |
287d19ce SH |
176 | |
177 | /** | |
178 | * pci_read_vpd - Read one entry from Vital Product Data | |
179 | * @dev: pci device struct | |
180 | * @pos: offset in vpd space | |
181 | * @count: number of bytes to read | |
182 | * @buf: pointer to where to store result | |
183 | * | |
184 | */ | |
185 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) | |
186 | { | |
187 | if (!dev->vpd || !dev->vpd->ops) | |
188 | return -ENODEV; | |
189 | return dev->vpd->ops->read(dev, pos, count, buf); | |
190 | } | |
191 | EXPORT_SYMBOL(pci_read_vpd); | |
192 | ||
193 | /** | |
194 | * pci_write_vpd - Write entry to Vital Product Data | |
195 | * @dev: pci device struct | |
196 | * @pos: offset in vpd space | |
cffb2faf RD |
197 | * @count: number of bytes to write |
198 | * @buf: buffer containing write data | |
287d19ce SH |
199 | * |
200 | */ | |
201 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) | |
202 | { | |
203 | if (!dev->vpd || !dev->vpd->ops) | |
204 | return -ENODEV; | |
205 | return dev->vpd->ops->write(dev, pos, count, buf); | |
206 | } | |
207 | EXPORT_SYMBOL(pci_write_vpd); | |
208 | ||
7ea7e98f MW |
209 | /* |
210 | * The following routines are to prevent the user from accessing PCI config | |
211 | * space when it's unsafe to do so. Some devices require this during BIST and | |
212 | * we're required to prevent it during D-state transitions. | |
213 | * | |
214 | * We have a bit per device to indicate it's blocked and a global wait queue | |
215 | * for callers to sleep on until devices are unblocked. | |
216 | */ | |
fb51ccbf | 217 | static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait); |
e04b0ea2 | 218 | |
fb51ccbf | 219 | static noinline void pci_wait_cfg(struct pci_dev *dev) |
7ea7e98f MW |
220 | { |
221 | DECLARE_WAITQUEUE(wait, current); | |
222 | ||
fb51ccbf | 223 | __add_wait_queue(&pci_cfg_wait, &wait); |
7ea7e98f MW |
224 | do { |
225 | set_current_state(TASK_UNINTERRUPTIBLE); | |
511dd98c | 226 | raw_spin_unlock_irq(&pci_lock); |
7ea7e98f | 227 | schedule(); |
511dd98c | 228 | raw_spin_lock_irq(&pci_lock); |
fb51ccbf JK |
229 | } while (dev->block_cfg_access); |
230 | __remove_wait_queue(&pci_cfg_wait, &wait); | |
e04b0ea2 BK |
231 | } |
232 | ||
34e32072 | 233 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 234 | #define PCI_USER_READ_CONFIG(size, type) \ |
e04b0ea2 BK |
235 | int pci_user_read_config_##size \ |
236 | (struct pci_dev *dev, int pos, type *val) \ | |
237 | { \ | |
d97ffe23 | 238 | int ret = PCIBIOS_SUCCESSFUL; \ |
e04b0ea2 | 239 | u32 data = -1; \ |
34e32072 GT |
240 | if (PCI_##size##_BAD) \ |
241 | return -EINVAL; \ | |
511dd98c | 242 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
243 | if (unlikely(dev->block_cfg_access)) \ |
244 | pci_wait_cfg(dev); \ | |
7ea7e98f | 245 | ret = dev->bus->ops->read(dev->bus, dev->devfn, \ |
e04b0ea2 | 246 | pos, sizeof(type), &data); \ |
511dd98c | 247 | raw_spin_unlock_irq(&pci_lock); \ |
e04b0ea2 | 248 | *val = (type)data; \ |
d97ffe23 | 249 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
250 | } \ |
251 | EXPORT_SYMBOL_GPL(pci_user_read_config_##size); | |
e04b0ea2 | 252 | |
34e32072 | 253 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 254 | #define PCI_USER_WRITE_CONFIG(size, type) \ |
e04b0ea2 BK |
255 | int pci_user_write_config_##size \ |
256 | (struct pci_dev *dev, int pos, type val) \ | |
257 | { \ | |
d97ffe23 | 258 | int ret = PCIBIOS_SUCCESSFUL; \ |
34e32072 GT |
259 | if (PCI_##size##_BAD) \ |
260 | return -EINVAL; \ | |
511dd98c | 261 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
262 | if (unlikely(dev->block_cfg_access)) \ |
263 | pci_wait_cfg(dev); \ | |
7ea7e98f | 264 | ret = dev->bus->ops->write(dev->bus, dev->devfn, \ |
e04b0ea2 | 265 | pos, sizeof(type), val); \ |
511dd98c | 266 | raw_spin_unlock_irq(&pci_lock); \ |
d97ffe23 | 267 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
268 | } \ |
269 | EXPORT_SYMBOL_GPL(pci_user_write_config_##size); | |
e04b0ea2 BK |
270 | |
271 | PCI_USER_READ_CONFIG(byte, u8) | |
272 | PCI_USER_READ_CONFIG(word, u16) | |
273 | PCI_USER_READ_CONFIG(dword, u32) | |
274 | PCI_USER_WRITE_CONFIG(byte, u8) | |
275 | PCI_USER_WRITE_CONFIG(word, u16) | |
276 | PCI_USER_WRITE_CONFIG(dword, u32) | |
277 | ||
94e61088 BH |
278 | /* VPD access through PCI 2.2+ VPD capability */ |
279 | ||
280 | #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1) | |
281 | ||
282 | struct pci_vpd_pci22 { | |
283 | struct pci_vpd base; | |
1120f8b8 SH |
284 | struct mutex lock; |
285 | u16 flag; | |
1120f8b8 | 286 | u8 cap; |
c5563887 | 287 | u8 busy:1; |
104daa71 | 288 | u8 valid:1; |
94e61088 BH |
289 | }; |
290 | ||
104daa71 HR |
291 | /** |
292 | * pci_vpd_size - determine actual size of Vital Product Data | |
293 | * @dev: pci device struct | |
294 | * @old_size: current assumed size, also maximum allowed size | |
295 | */ | |
296 | static size_t pci_vpd_pci22_size(struct pci_dev *dev, size_t old_size) | |
297 | { | |
298 | size_t off = 0; | |
299 | unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */ | |
300 | ||
301 | while (off < old_size && | |
302 | pci_read_vpd(dev, off, 1, header) == 1) { | |
303 | unsigned char tag; | |
304 | ||
305 | if (header[0] & PCI_VPD_LRDT) { | |
306 | /* Large Resource Data Type Tag */ | |
307 | tag = pci_vpd_lrdt_tag(header); | |
308 | /* Only read length from known tag items */ | |
309 | if ((tag == PCI_VPD_LTIN_ID_STRING) || | |
310 | (tag == PCI_VPD_LTIN_RO_DATA) || | |
311 | (tag == PCI_VPD_LTIN_RW_DATA)) { | |
312 | if (pci_read_vpd(dev, off+1, 2, | |
313 | &header[1]) != 2) { | |
314 | dev_warn(&dev->dev, | |
315 | "invalid large VPD tag %02x size at offset %zu", | |
316 | tag, off + 1); | |
317 | return 0; | |
318 | } | |
319 | off += PCI_VPD_LRDT_TAG_SIZE + | |
320 | pci_vpd_lrdt_size(header); | |
321 | } | |
322 | } else { | |
323 | /* Short Resource Data Type Tag */ | |
324 | off += PCI_VPD_SRDT_TAG_SIZE + | |
325 | pci_vpd_srdt_size(header); | |
326 | tag = pci_vpd_srdt_tag(header); | |
327 | } | |
328 | ||
329 | if (tag == PCI_VPD_STIN_END) /* End tag descriptor */ | |
330 | return off; | |
331 | ||
332 | if ((tag != PCI_VPD_LTIN_ID_STRING) && | |
333 | (tag != PCI_VPD_LTIN_RO_DATA) && | |
334 | (tag != PCI_VPD_LTIN_RW_DATA)) { | |
335 | dev_warn(&dev->dev, | |
336 | "invalid %s VPD tag %02x at offset %zu", | |
337 | (header[0] & PCI_VPD_LRDT) ? "large" : "short", | |
338 | tag, off); | |
339 | return 0; | |
340 | } | |
341 | } | |
342 | return 0; | |
343 | } | |
344 | ||
1120f8b8 SH |
345 | /* |
346 | * Wait for last operation to complete. | |
347 | * This code has to spin since there is no other notification from the PCI | |
348 | * hardware. Since the VPD is often implemented by serial attachment to an | |
349 | * EEPROM, it may take many milliseconds to complete. | |
34e32072 GT |
350 | * |
351 | * Returns 0 on success, negative values indicate error. | |
1120f8b8 | 352 | */ |
94e61088 BH |
353 | static int pci_vpd_pci22_wait(struct pci_dev *dev) |
354 | { | |
355 | struct pci_vpd_pci22 *vpd = | |
356 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
1120f8b8 SH |
357 | unsigned long timeout = jiffies + HZ/20 + 2; |
358 | u16 status; | |
94e61088 BH |
359 | int ret; |
360 | ||
361 | if (!vpd->busy) | |
362 | return 0; | |
363 | ||
94e61088 | 364 | for (;;) { |
1120f8b8 | 365 | ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
94e61088 | 366 | &status); |
34e32072 | 367 | if (ret < 0) |
94e61088 | 368 | return ret; |
1120f8b8 SH |
369 | |
370 | if ((status & PCI_VPD_ADDR_F) == vpd->flag) { | |
c5563887 | 371 | vpd->busy = 0; |
94e61088 BH |
372 | return 0; |
373 | } | |
1120f8b8 | 374 | |
5030718e | 375 | if (time_after(jiffies, timeout)) { |
227f0647 | 376 | dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); |
94e61088 | 377 | return -ETIMEDOUT; |
5030718e | 378 | } |
1120f8b8 SH |
379 | if (fatal_signal_pending(current)) |
380 | return -EINTR; | |
381 | if (!cond_resched()) | |
382 | udelay(10); | |
94e61088 BH |
383 | } |
384 | } | |
385 | ||
287d19ce SH |
386 | static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count, |
387 | void *arg) | |
94e61088 BH |
388 | { |
389 | struct pci_vpd_pci22 *vpd = | |
390 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
391 | int ret; |
392 | loff_t end = pos + count; | |
393 | u8 *buf = arg; | |
94e61088 | 394 | |
104daa71 | 395 | if (pos < 0) |
94e61088 | 396 | return -EINVAL; |
94e61088 | 397 | |
104daa71 HR |
398 | if (!vpd->valid) { |
399 | vpd->valid = 1; | |
400 | vpd->base.len = pci_vpd_pci22_size(dev, vpd->base.len); | |
401 | } | |
402 | ||
403 | if (vpd->base.len == 0) | |
404 | return -EIO; | |
405 | ||
406 | if (pos >= vpd->base.len) | |
407 | return 0; | |
408 | ||
409 | if (end > vpd->base.len) { | |
410 | end = vpd->base.len; | |
411 | count = end - pos; | |
412 | } | |
413 | ||
1120f8b8 SH |
414 | if (mutex_lock_killable(&vpd->lock)) |
415 | return -EINTR; | |
416 | ||
94e61088 BH |
417 | ret = pci_vpd_pci22_wait(dev); |
418 | if (ret < 0) | |
419 | goto out; | |
1120f8b8 | 420 | |
287d19ce SH |
421 | while (pos < end) { |
422 | u32 val; | |
423 | unsigned int i, skip; | |
424 | ||
425 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
426 | pos & ~3); | |
427 | if (ret < 0) | |
428 | break; | |
c5563887 | 429 | vpd->busy = 1; |
287d19ce SH |
430 | vpd->flag = PCI_VPD_ADDR_F; |
431 | ret = pci_vpd_pci22_wait(dev); | |
432 | if (ret < 0) | |
433 | break; | |
434 | ||
435 | ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); | |
436 | if (ret < 0) | |
437 | break; | |
438 | ||
439 | skip = pos & 3; | |
440 | for (i = 0; i < sizeof(u32); i++) { | |
441 | if (i >= skip) { | |
442 | *buf++ = val; | |
443 | if (++pos == end) | |
444 | break; | |
445 | } | |
446 | val >>= 8; | |
447 | } | |
448 | } | |
94e61088 | 449 | out: |
1120f8b8 | 450 | mutex_unlock(&vpd->lock); |
287d19ce | 451 | return ret ? ret : count; |
94e61088 BH |
452 | } |
453 | ||
287d19ce SH |
454 | static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count, |
455 | const void *arg) | |
94e61088 BH |
456 | { |
457 | struct pci_vpd_pci22 *vpd = | |
458 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
459 | const u8 *buf = arg; |
460 | loff_t end = pos + count; | |
1120f8b8 | 461 | int ret = 0; |
94e61088 | 462 | |
104daa71 HR |
463 | if (pos < 0 || (pos & 3) || (count & 3)) |
464 | return -EINVAL; | |
465 | ||
466 | if (!vpd->valid) { | |
467 | vpd->valid = 1; | |
468 | vpd->base.len = pci_vpd_pci22_size(dev, vpd->base.len); | |
469 | } | |
470 | ||
471 | if (vpd->base.len == 0) | |
472 | return -EIO; | |
473 | ||
474 | if (end > vpd->base.len) | |
94e61088 BH |
475 | return -EINVAL; |
476 | ||
1120f8b8 SH |
477 | if (mutex_lock_killable(&vpd->lock)) |
478 | return -EINTR; | |
287d19ce | 479 | |
94e61088 BH |
480 | ret = pci_vpd_pci22_wait(dev); |
481 | if (ret < 0) | |
482 | goto out; | |
287d19ce SH |
483 | |
484 | while (pos < end) { | |
485 | u32 val; | |
486 | ||
487 | val = *buf++; | |
488 | val |= *buf++ << 8; | |
489 | val |= *buf++ << 16; | |
490 | val |= *buf++ << 24; | |
491 | ||
492 | ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); | |
493 | if (ret < 0) | |
494 | break; | |
495 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
496 | pos | PCI_VPD_ADDR_F); | |
497 | if (ret < 0) | |
498 | break; | |
499 | ||
c5563887 | 500 | vpd->busy = 1; |
287d19ce SH |
501 | vpd->flag = 0; |
502 | ret = pci_vpd_pci22_wait(dev); | |
d97ecd81 GT |
503 | if (ret < 0) |
504 | break; | |
287d19ce SH |
505 | |
506 | pos += sizeof(u32); | |
507 | } | |
94e61088 | 508 | out: |
1120f8b8 | 509 | mutex_unlock(&vpd->lock); |
287d19ce | 510 | return ret ? ret : count; |
94e61088 BH |
511 | } |
512 | ||
94e61088 BH |
513 | static void pci_vpd_pci22_release(struct pci_dev *dev) |
514 | { | |
515 | kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); | |
516 | } | |
517 | ||
287d19ce | 518 | static const struct pci_vpd_ops pci_vpd_pci22_ops = { |
94e61088 BH |
519 | .read = pci_vpd_pci22_read, |
520 | .write = pci_vpd_pci22_write, | |
94e61088 BH |
521 | .release = pci_vpd_pci22_release, |
522 | }; | |
523 | ||
932c435c MR |
524 | static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count, |
525 | void *arg) | |
526 | { | |
9d924075 AW |
527 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
528 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
529 | ssize_t ret; |
530 | ||
531 | if (!tdev) | |
532 | return -ENODEV; | |
533 | ||
534 | ret = pci_read_vpd(tdev, pos, count, arg); | |
535 | pci_dev_put(tdev); | |
536 | return ret; | |
537 | } | |
538 | ||
539 | static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count, | |
540 | const void *arg) | |
541 | { | |
9d924075 AW |
542 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
543 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
544 | ssize_t ret; |
545 | ||
546 | if (!tdev) | |
547 | return -ENODEV; | |
548 | ||
549 | ret = pci_write_vpd(tdev, pos, count, arg); | |
550 | pci_dev_put(tdev); | |
551 | return ret; | |
552 | } | |
553 | ||
554 | static const struct pci_vpd_ops pci_vpd_f0_ops = { | |
555 | .read = pci_vpd_f0_read, | |
556 | .write = pci_vpd_f0_write, | |
557 | .release = pci_vpd_pci22_release, | |
558 | }; | |
559 | ||
94e61088 BH |
560 | int pci_vpd_pci22_init(struct pci_dev *dev) |
561 | { | |
562 | struct pci_vpd_pci22 *vpd; | |
563 | u8 cap; | |
564 | ||
565 | cap = pci_find_capability(dev, PCI_CAP_ID_VPD); | |
566 | if (!cap) | |
567 | return -ENODEV; | |
932c435c | 568 | |
94e61088 BH |
569 | vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); |
570 | if (!vpd) | |
571 | return -ENOMEM; | |
572 | ||
99cb233d | 573 | vpd->base.len = PCI_VPD_PCI22_SIZE; |
932c435c MR |
574 | if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) |
575 | vpd->base.ops = &pci_vpd_f0_ops; | |
576 | else | |
577 | vpd->base.ops = &pci_vpd_pci22_ops; | |
1120f8b8 | 578 | mutex_init(&vpd->lock); |
94e61088 | 579 | vpd->cap = cap; |
c5563887 | 580 | vpd->busy = 0; |
104daa71 | 581 | vpd->valid = 0; |
94e61088 BH |
582 | dev->vpd = &vpd->base; |
583 | return 0; | |
584 | } | |
585 | ||
e04b0ea2 | 586 | /** |
fb51ccbf | 587 | * pci_cfg_access_lock - Lock PCI config reads/writes |
e04b0ea2 BK |
588 | * @dev: pci device struct |
589 | * | |
fb51ccbf JK |
590 | * When access is locked, any userspace reads or writes to config |
591 | * space and concurrent lock requests will sleep until access is | |
592 | * allowed via pci_cfg_access_unlocked again. | |
7ea7e98f | 593 | */ |
fb51ccbf JK |
594 | void pci_cfg_access_lock(struct pci_dev *dev) |
595 | { | |
596 | might_sleep(); | |
597 | ||
598 | raw_spin_lock_irq(&pci_lock); | |
599 | if (dev->block_cfg_access) | |
600 | pci_wait_cfg(dev); | |
601 | dev->block_cfg_access = 1; | |
602 | raw_spin_unlock_irq(&pci_lock); | |
603 | } | |
604 | EXPORT_SYMBOL_GPL(pci_cfg_access_lock); | |
605 | ||
606 | /** | |
607 | * pci_cfg_access_trylock - try to lock PCI config reads/writes | |
608 | * @dev: pci device struct | |
609 | * | |
610 | * Same as pci_cfg_access_lock, but will return 0 if access is | |
611 | * already locked, 1 otherwise. This function can be used from | |
612 | * atomic contexts. | |
613 | */ | |
614 | bool pci_cfg_access_trylock(struct pci_dev *dev) | |
e04b0ea2 BK |
615 | { |
616 | unsigned long flags; | |
fb51ccbf | 617 | bool locked = true; |
e04b0ea2 | 618 | |
511dd98c | 619 | raw_spin_lock_irqsave(&pci_lock, flags); |
fb51ccbf JK |
620 | if (dev->block_cfg_access) |
621 | locked = false; | |
622 | else | |
623 | dev->block_cfg_access = 1; | |
511dd98c | 624 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
7ea7e98f | 625 | |
fb51ccbf | 626 | return locked; |
e04b0ea2 | 627 | } |
fb51ccbf | 628 | EXPORT_SYMBOL_GPL(pci_cfg_access_trylock); |
e04b0ea2 BK |
629 | |
630 | /** | |
fb51ccbf | 631 | * pci_cfg_access_unlock - Unlock PCI config reads/writes |
e04b0ea2 BK |
632 | * @dev: pci device struct |
633 | * | |
fb51ccbf | 634 | * This function allows PCI config accesses to resume. |
7ea7e98f | 635 | */ |
fb51ccbf | 636 | void pci_cfg_access_unlock(struct pci_dev *dev) |
e04b0ea2 BK |
637 | { |
638 | unsigned long flags; | |
639 | ||
511dd98c | 640 | raw_spin_lock_irqsave(&pci_lock, flags); |
7ea7e98f MW |
641 | |
642 | /* This indicates a problem in the caller, but we don't need | |
643 | * to kill them, unlike a double-block above. */ | |
fb51ccbf | 644 | WARN_ON(!dev->block_cfg_access); |
7ea7e98f | 645 | |
fb51ccbf JK |
646 | dev->block_cfg_access = 0; |
647 | wake_up_all(&pci_cfg_wait); | |
511dd98c | 648 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
e04b0ea2 | 649 | } |
fb51ccbf | 650 | EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); |
8c0d3a02 JL |
651 | |
652 | static inline int pcie_cap_version(const struct pci_dev *dev) | |
653 | { | |
1c531d82 | 654 | return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; |
8c0d3a02 JL |
655 | } |
656 | ||
ffb4d602 BH |
657 | static bool pcie_downstream_port(const struct pci_dev *dev) |
658 | { | |
659 | int type = pci_pcie_type(dev); | |
660 | ||
661 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
662 | type == PCI_EXP_TYPE_DOWNSTREAM; | |
663 | } | |
664 | ||
7a1562d4 | 665 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
8c0d3a02 JL |
666 | { |
667 | int type = pci_pcie_type(dev); | |
668 | ||
c8b303d0 | 669 | return type == PCI_EXP_TYPE_ENDPOINT || |
d3694d4f BH |
670 | type == PCI_EXP_TYPE_LEG_END || |
671 | type == PCI_EXP_TYPE_ROOT_PORT || | |
672 | type == PCI_EXP_TYPE_UPSTREAM || | |
673 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
674 | type == PCI_EXP_TYPE_PCI_BRIDGE || | |
675 | type == PCI_EXP_TYPE_PCIE_BRIDGE; | |
8c0d3a02 JL |
676 | } |
677 | ||
678 | static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) | |
679 | { | |
ffb4d602 | 680 | return pcie_downstream_port(dev) && |
6d3a1741 | 681 | pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; |
8c0d3a02 JL |
682 | } |
683 | ||
684 | static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) | |
685 | { | |
686 | int type = pci_pcie_type(dev); | |
687 | ||
c8b303d0 | 688 | return type == PCI_EXP_TYPE_ROOT_PORT || |
8c0d3a02 JL |
689 | type == PCI_EXP_TYPE_RC_EC; |
690 | } | |
691 | ||
692 | static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) | |
693 | { | |
694 | if (!pci_is_pcie(dev)) | |
695 | return false; | |
696 | ||
697 | switch (pos) { | |
969daa34 | 698 | case PCI_EXP_FLAGS: |
8c0d3a02 JL |
699 | return true; |
700 | case PCI_EXP_DEVCAP: | |
701 | case PCI_EXP_DEVCTL: | |
702 | case PCI_EXP_DEVSTA: | |
fed24515 | 703 | return true; |
8c0d3a02 JL |
704 | case PCI_EXP_LNKCAP: |
705 | case PCI_EXP_LNKCTL: | |
706 | case PCI_EXP_LNKSTA: | |
707 | return pcie_cap_has_lnkctl(dev); | |
708 | case PCI_EXP_SLTCAP: | |
709 | case PCI_EXP_SLTCTL: | |
710 | case PCI_EXP_SLTSTA: | |
711 | return pcie_cap_has_sltctl(dev); | |
712 | case PCI_EXP_RTCTL: | |
713 | case PCI_EXP_RTCAP: | |
714 | case PCI_EXP_RTSTA: | |
715 | return pcie_cap_has_rtctl(dev); | |
716 | case PCI_EXP_DEVCAP2: | |
717 | case PCI_EXP_DEVCTL2: | |
718 | case PCI_EXP_LNKCAP2: | |
719 | case PCI_EXP_LNKCTL2: | |
720 | case PCI_EXP_LNKSTA2: | |
721 | return pcie_cap_version(dev) > 1; | |
722 | default: | |
723 | return false; | |
724 | } | |
725 | } | |
726 | ||
727 | /* | |
728 | * Note that these accessor functions are only for the "PCI Express | |
729 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the | |
730 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) | |
731 | */ | |
732 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) | |
733 | { | |
734 | int ret; | |
735 | ||
736 | *val = 0; | |
737 | if (pos & 1) | |
738 | return -EINVAL; | |
739 | ||
740 | if (pcie_capability_reg_implemented(dev, pos)) { | |
741 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
742 | /* | |
743 | * Reset *val to 0 if pci_read_config_word() fails, it may | |
744 | * have been written as 0xFFFF if hardware error happens | |
745 | * during pci_read_config_word(). | |
746 | */ | |
747 | if (ret) | |
748 | *val = 0; | |
749 | return ret; | |
750 | } | |
751 | ||
752 | /* | |
753 | * For Functions that do not implement the Slot Capabilities, | |
754 | * Slot Status, and Slot Control registers, these spaces must | |
755 | * be hardwired to 0b, with the exception of the Presence Detect | |
756 | * State bit in the Slot Status register of Downstream Ports, | |
757 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) | |
758 | */ | |
ffb4d602 BH |
759 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
760 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 761 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
762 | |
763 | return 0; | |
764 | } | |
765 | EXPORT_SYMBOL(pcie_capability_read_word); | |
766 | ||
767 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) | |
768 | { | |
769 | int ret; | |
770 | ||
771 | *val = 0; | |
772 | if (pos & 3) | |
773 | return -EINVAL; | |
774 | ||
775 | if (pcie_capability_reg_implemented(dev, pos)) { | |
776 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
777 | /* | |
778 | * Reset *val to 0 if pci_read_config_dword() fails, it may | |
779 | * have been written as 0xFFFFFFFF if hardware error happens | |
780 | * during pci_read_config_dword(). | |
781 | */ | |
782 | if (ret) | |
783 | *val = 0; | |
784 | return ret; | |
785 | } | |
786 | ||
ffb4d602 BH |
787 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
788 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 789 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
790 | |
791 | return 0; | |
792 | } | |
793 | EXPORT_SYMBOL(pcie_capability_read_dword); | |
794 | ||
795 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) | |
796 | { | |
797 | if (pos & 1) | |
798 | return -EINVAL; | |
799 | ||
800 | if (!pcie_capability_reg_implemented(dev, pos)) | |
801 | return 0; | |
802 | ||
803 | return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
804 | } | |
805 | EXPORT_SYMBOL(pcie_capability_write_word); | |
806 | ||
807 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) | |
808 | { | |
809 | if (pos & 3) | |
810 | return -EINVAL; | |
811 | ||
812 | if (!pcie_capability_reg_implemented(dev, pos)) | |
813 | return 0; | |
814 | ||
815 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
816 | } | |
817 | EXPORT_SYMBOL(pcie_capability_write_dword); | |
818 | ||
819 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
820 | u16 clear, u16 set) | |
821 | { | |
822 | int ret; | |
823 | u16 val; | |
824 | ||
825 | ret = pcie_capability_read_word(dev, pos, &val); | |
826 | if (!ret) { | |
827 | val &= ~clear; | |
828 | val |= set; | |
829 | ret = pcie_capability_write_word(dev, pos, val); | |
830 | } | |
831 | ||
832 | return ret; | |
833 | } | |
834 | EXPORT_SYMBOL(pcie_capability_clear_and_set_word); | |
835 | ||
836 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
837 | u32 clear, u32 set) | |
838 | { | |
839 | int ret; | |
840 | u32 val; | |
841 | ||
842 | ret = pcie_capability_read_dword(dev, pos, &val); | |
843 | if (!ret) { | |
844 | val &= ~clear; | |
845 | val |= set; | |
846 | ret = pcie_capability_write_dword(dev, pos, val); | |
847 | } | |
848 | ||
849 | return ret; | |
850 | } | |
851 | EXPORT_SYMBOL(pcie_capability_clear_and_set_dword); |