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db3c33c6 JR |
1 | /* |
2 | * drivers/pci/ats.c | |
3 | * | |
4 | * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> | |
c320b976 | 5 | * Copyright (C) 2011 Advanced Micro Devices, |
db3c33c6 JR |
6 | * |
7 | * PCI Express I/O Virtualization (IOV) support. | |
8 | * Address Translation Service 1.0 | |
c320b976 | 9 | * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com> |
086ac11f | 10 | * PASID support added by Joerg Roedel <joerg.roedel@amd.com> |
db3c33c6 JR |
11 | */ |
12 | ||
13 | #include <linux/pci-ats.h> | |
14 | #include <linux/pci.h> | |
15 | ||
16 | #include "pci.h" | |
17 | ||
18 | static int ats_alloc_one(struct pci_dev *dev, int ps) | |
19 | { | |
20 | int pos; | |
21 | u16 cap; | |
22 | struct pci_ats *ats; | |
23 | ||
24 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS); | |
25 | if (!pos) | |
26 | return -ENODEV; | |
27 | ||
28 | ats = kzalloc(sizeof(*ats), GFP_KERNEL); | |
29 | if (!ats) | |
30 | return -ENOMEM; | |
31 | ||
32 | ats->pos = pos; | |
33 | ats->stu = ps; | |
34 | pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap); | |
35 | ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : | |
36 | PCI_ATS_MAX_QDEP; | |
37 | dev->ats = ats; | |
38 | ||
39 | return 0; | |
40 | } | |
41 | ||
42 | static void ats_free_one(struct pci_dev *dev) | |
43 | { | |
44 | kfree(dev->ats); | |
45 | dev->ats = NULL; | |
46 | } | |
47 | ||
48 | /** | |
49 | * pci_enable_ats - enable the ATS capability | |
50 | * @dev: the PCI device | |
51 | * @ps: the IOMMU page shift | |
52 | * | |
53 | * Returns 0 on success, or negative on failure. | |
54 | */ | |
55 | int pci_enable_ats(struct pci_dev *dev, int ps) | |
56 | { | |
57 | int rc; | |
58 | u16 ctrl; | |
59 | ||
60 | BUG_ON(dev->ats && dev->ats->is_enabled); | |
61 | ||
62 | if (ps < PCI_ATS_MIN_STU) | |
63 | return -EINVAL; | |
64 | ||
65 | if (dev->is_physfn || dev->is_virtfn) { | |
66 | struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn; | |
67 | ||
68 | mutex_lock(&pdev->sriov->lock); | |
69 | if (pdev->ats) | |
70 | rc = pdev->ats->stu == ps ? 0 : -EINVAL; | |
71 | else | |
72 | rc = ats_alloc_one(pdev, ps); | |
73 | ||
74 | if (!rc) | |
75 | pdev->ats->ref_cnt++; | |
76 | mutex_unlock(&pdev->sriov->lock); | |
77 | if (rc) | |
78 | return rc; | |
79 | } | |
80 | ||
81 | if (!dev->is_physfn) { | |
82 | rc = ats_alloc_one(dev, ps); | |
83 | if (rc) | |
84 | return rc; | |
85 | } | |
86 | ||
87 | ctrl = PCI_ATS_CTRL_ENABLE; | |
88 | if (!dev->is_virtfn) | |
89 | ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU); | |
90 | pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl); | |
91 | ||
92 | dev->ats->is_enabled = 1; | |
93 | ||
94 | return 0; | |
95 | } | |
d4c0636c | 96 | EXPORT_SYMBOL_GPL(pci_enable_ats); |
db3c33c6 JR |
97 | |
98 | /** | |
99 | * pci_disable_ats - disable the ATS capability | |
100 | * @dev: the PCI device | |
101 | */ | |
102 | void pci_disable_ats(struct pci_dev *dev) | |
103 | { | |
104 | u16 ctrl; | |
105 | ||
106 | BUG_ON(!dev->ats || !dev->ats->is_enabled); | |
107 | ||
108 | pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl); | |
109 | ctrl &= ~PCI_ATS_CTRL_ENABLE; | |
110 | pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl); | |
111 | ||
112 | dev->ats->is_enabled = 0; | |
113 | ||
114 | if (dev->is_physfn || dev->is_virtfn) { | |
115 | struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn; | |
116 | ||
117 | mutex_lock(&pdev->sriov->lock); | |
118 | pdev->ats->ref_cnt--; | |
119 | if (!pdev->ats->ref_cnt) | |
120 | ats_free_one(pdev); | |
121 | mutex_unlock(&pdev->sriov->lock); | |
122 | } | |
123 | ||
124 | if (!dev->is_physfn) | |
125 | ats_free_one(dev); | |
126 | } | |
d4c0636c | 127 | EXPORT_SYMBOL_GPL(pci_disable_ats); |
db3c33c6 JR |
128 | |
129 | /** | |
130 | * pci_ats_queue_depth - query the ATS Invalidate Queue Depth | |
131 | * @dev: the PCI device | |
132 | * | |
133 | * Returns the queue depth on success, or negative on failure. | |
134 | * | |
135 | * The ATS spec uses 0 in the Invalidate Queue Depth field to | |
136 | * indicate that the function can accept 32 Invalidate Request. | |
137 | * But here we use the `real' values (i.e. 1~32) for the Queue | |
138 | * Depth; and 0 indicates the function shares the Queue with | |
139 | * other functions (doesn't exclusively own a Queue). | |
140 | */ | |
141 | int pci_ats_queue_depth(struct pci_dev *dev) | |
142 | { | |
143 | int pos; | |
144 | u16 cap; | |
145 | ||
146 | if (dev->is_virtfn) | |
147 | return 0; | |
148 | ||
149 | if (dev->ats) | |
150 | return dev->ats->qdep; | |
151 | ||
152 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS); | |
153 | if (!pos) | |
154 | return -ENODEV; | |
155 | ||
156 | pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap); | |
157 | ||
158 | return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : | |
159 | PCI_ATS_MAX_QDEP; | |
160 | } | |
d4c0636c | 161 | EXPORT_SYMBOL_GPL(pci_ats_queue_depth); |
c320b976 JR |
162 | |
163 | #ifdef CONFIG_PCI_PRI | |
164 | /** | |
165 | * pci_enable_pri - Enable PRI capability | |
166 | * @ pdev: PCI device structure | |
167 | * | |
168 | * Returns 0 on success, negative value on error | |
169 | */ | |
170 | int pci_enable_pri(struct pci_dev *pdev, u32 reqs) | |
171 | { | |
172 | u16 control, status; | |
173 | u32 max_requests; | |
174 | int pos; | |
175 | ||
176 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
177 | if (!pos) | |
178 | return -EINVAL; | |
179 | ||
180 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
181 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF, &status); | |
182 | if ((control & PCI_PRI_ENABLE) || !(status & PCI_PRI_STATUS_STOPPED)) | |
183 | return -EBUSY; | |
184 | ||
185 | pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ_OFF, &max_requests); | |
186 | reqs = min(max_requests, reqs); | |
187 | pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ_OFF, reqs); | |
188 | ||
189 | control |= PCI_PRI_ENABLE; | |
190 | pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control); | |
191 | ||
192 | return 0; | |
193 | } | |
194 | EXPORT_SYMBOL_GPL(pci_enable_pri); | |
195 | ||
196 | /** | |
197 | * pci_disable_pri - Disable PRI capability | |
198 | * @pdev: PCI device structure | |
199 | * | |
200 | * Only clears the enabled-bit, regardless of its former value | |
201 | */ | |
202 | void pci_disable_pri(struct pci_dev *pdev) | |
203 | { | |
204 | u16 control; | |
205 | int pos; | |
206 | ||
207 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
208 | if (!pos) | |
209 | return; | |
210 | ||
211 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
212 | control &= ~PCI_PRI_ENABLE; | |
213 | pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control); | |
214 | } | |
215 | EXPORT_SYMBOL_GPL(pci_disable_pri); | |
216 | ||
217 | /** | |
218 | * pci_pri_enabled - Checks if PRI capability is enabled | |
219 | * @pdev: PCI device structure | |
220 | * | |
221 | * Returns true if PRI is enabled on the device, false otherwise | |
222 | */ | |
223 | bool pci_pri_enabled(struct pci_dev *pdev) | |
224 | { | |
225 | u16 control; | |
226 | int pos; | |
227 | ||
228 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
229 | if (!pos) | |
230 | return false; | |
231 | ||
232 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
233 | ||
234 | return (control & PCI_PRI_ENABLE) ? true : false; | |
235 | } | |
236 | EXPORT_SYMBOL_GPL(pci_pri_enabled); | |
237 | ||
238 | /** | |
239 | * pci_reset_pri - Resets device's PRI state | |
240 | * @pdev: PCI device structure | |
241 | * | |
242 | * The PRI capability must be disabled before this function is called. | |
243 | * Returns 0 on success, negative value on error. | |
244 | */ | |
245 | int pci_reset_pri(struct pci_dev *pdev) | |
246 | { | |
247 | u16 control; | |
248 | int pos; | |
249 | ||
250 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
251 | if (!pos) | |
252 | return -EINVAL; | |
253 | ||
254 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
255 | if (control & PCI_PRI_ENABLE) | |
256 | return -EBUSY; | |
257 | ||
258 | control |= PCI_PRI_RESET; | |
259 | ||
260 | pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | EXPORT_SYMBOL_GPL(pci_reset_pri); | |
265 | ||
266 | /** | |
267 | * pci_pri_stopped - Checks whether the PRI capability is stopped | |
268 | * @pdev: PCI device structure | |
269 | * | |
270 | * Returns true if the PRI capability on the device is disabled and the | |
271 | * device has no outstanding PRI requests, false otherwise. The device | |
272 | * indicates this via the STOPPED bit in the status register of the | |
273 | * capability. | |
274 | * The device internal state can be cleared by resetting the PRI state | |
275 | * with pci_reset_pri(). This can force the capability into the STOPPED | |
276 | * state. | |
277 | */ | |
278 | bool pci_pri_stopped(struct pci_dev *pdev) | |
279 | { | |
280 | u16 control, status; | |
281 | int pos; | |
282 | ||
283 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
284 | if (!pos) | |
285 | return true; | |
286 | ||
287 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
288 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF, &status); | |
289 | ||
290 | if (control & PCI_PRI_ENABLE) | |
291 | return false; | |
292 | ||
293 | return (status & PCI_PRI_STATUS_STOPPED) ? true : false; | |
294 | } | |
295 | EXPORT_SYMBOL_GPL(pci_pri_stopped); | |
296 | ||
297 | /** | |
298 | * pci_pri_status - Request PRI status of a device | |
299 | * @pdev: PCI device structure | |
300 | * | |
301 | * Returns negative value on failure, status on success. The status can | |
302 | * be checked against status-bits. Supported bits are currently: | |
303 | * PCI_PRI_STATUS_RF: Response failure | |
304 | * PCI_PRI_STATUS_UPRGI: Unexpected Page Request Group Index | |
305 | * PCI_PRI_STATUS_STOPPED: PRI has stopped | |
306 | */ | |
307 | int pci_pri_status(struct pci_dev *pdev) | |
308 | { | |
309 | u16 status, control; | |
310 | int pos; | |
311 | ||
312 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
313 | if (!pos) | |
314 | return -EINVAL; | |
315 | ||
316 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
317 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF, &status); | |
318 | ||
319 | /* Stopped bit is undefined when enable == 1, so clear it */ | |
320 | if (control & PCI_PRI_ENABLE) | |
321 | status &= ~PCI_PRI_STATUS_STOPPED; | |
322 | ||
323 | return status; | |
324 | } | |
325 | EXPORT_SYMBOL_GPL(pci_pri_status); | |
326 | #endif /* CONFIG_PCI_PRI */ | |
086ac11f JR |
327 | |
328 | #ifdef CONFIG_PCI_PASID | |
329 | /** | |
330 | * pci_enable_pasid - Enable the PASID capability | |
331 | * @pdev: PCI device structure | |
332 | * @features: Features to enable | |
333 | * | |
334 | * Returns 0 on success, negative value on error. This function checks | |
335 | * whether the features are actually supported by the device and returns | |
336 | * an error if not. | |
337 | */ | |
338 | int pci_enable_pasid(struct pci_dev *pdev, int features) | |
339 | { | |
340 | u16 control, supported; | |
341 | int pos; | |
342 | ||
343 | pos = pci_find_ext_capability(pdev, PCI_PASID_CAP); | |
344 | if (!pos) | |
345 | return -EINVAL; | |
346 | ||
347 | pci_read_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, &control); | |
348 | pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported); | |
349 | ||
350 | if (!(supported & PCI_PASID_ENABLE)) | |
351 | return -EINVAL; | |
352 | ||
353 | supported &= PCI_PASID_EXEC | PCI_PASID_PRIV; | |
354 | ||
355 | /* User wants to enable anything unsupported? */ | |
356 | if ((supported & features) != features) | |
357 | return -EINVAL; | |
358 | ||
359 | control = PCI_PASID_ENABLE | features; | |
360 | ||
361 | pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | EXPORT_SYMBOL_GPL(pci_enable_pasid); | |
366 | ||
367 | /** | |
368 | * pci_disable_pasid - Disable the PASID capability | |
369 | * @pdev: PCI device structure | |
370 | * | |
371 | */ | |
372 | void pci_disable_pasid(struct pci_dev *pdev) | |
373 | { | |
374 | u16 control = 0; | |
375 | int pos; | |
376 | ||
377 | pos = pci_find_ext_capability(pdev, PCI_PASID_CAP); | |
378 | if (!pos) | |
379 | return; | |
380 | ||
381 | pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control); | |
382 | } | |
383 | EXPORT_SYMBOL_GPL(pci_disable_pasid); | |
384 | ||
385 | /** | |
386 | * pci_pasid_features - Check which PASID features are supported | |
387 | * @pdev: PCI device structure | |
388 | * | |
389 | * Returns a negative value when no PASI capability is present. | |
390 | * Otherwise is returns a bitmask with supported features. Current | |
391 | * features reported are: | |
392 | * PCI_PASID_ENABLE - PASID capability can be enabled | |
393 | * PCI_PASID_EXEC - Execute permission supported | |
394 | * PCI_PASID_PRIV - Priviledged mode supported | |
395 | */ | |
396 | int pci_pasid_features(struct pci_dev *pdev) | |
397 | { | |
398 | u16 supported; | |
399 | int pos; | |
400 | ||
401 | pos = pci_find_ext_capability(pdev, PCI_PASID_CAP); | |
402 | if (!pos) | |
403 | return -EINVAL; | |
404 | ||
405 | pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported); | |
406 | ||
407 | supported &= PCI_PASID_ENABLE | PCI_PASID_EXEC | PCI_PASID_PRIV; | |
408 | ||
409 | return supported; | |
410 | } | |
411 | EXPORT_SYMBOL_GPL(pci_pasid_features); | |
412 | ||
413 | #define PASID_NUMBER_SHIFT 8 | |
414 | #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) | |
415 | /** | |
416 | * pci_max_pasid - Get maximum number of PASIDs supported by device | |
417 | * @pdev: PCI device structure | |
418 | * | |
419 | * Returns negative value when PASID capability is not present. | |
420 | * Otherwise it returns the numer of supported PASIDs. | |
421 | */ | |
422 | int pci_max_pasids(struct pci_dev *pdev) | |
423 | { | |
424 | u16 supported; | |
425 | int pos; | |
426 | ||
427 | pos = pci_find_ext_capability(pdev, PCI_PASID_CAP); | |
428 | if (!pos) | |
429 | return -EINVAL; | |
430 | ||
431 | pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported); | |
432 | ||
433 | supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT; | |
434 | ||
435 | return (1 << supported); | |
436 | } | |
437 | EXPORT_SYMBOL_GPL(pci_max_pasids); | |
438 | #endif /* CONFIG_PCI_PASID */ |