Commit | Line | Data |
---|---|---|
db3c33c6 JR |
1 | /* |
2 | * drivers/pci/ats.c | |
3 | * | |
4 | * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> | |
c320b976 | 5 | * Copyright (C) 2011 Advanced Micro Devices, |
db3c33c6 JR |
6 | * |
7 | * PCI Express I/O Virtualization (IOV) support. | |
8 | * Address Translation Service 1.0 | |
c320b976 | 9 | * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com> |
086ac11f | 10 | * PASID support added by Joerg Roedel <joerg.roedel@amd.com> |
db3c33c6 JR |
11 | */ |
12 | ||
363c75db | 13 | #include <linux/export.h> |
db3c33c6 JR |
14 | #include <linux/pci-ats.h> |
15 | #include <linux/pci.h> | |
8c451945 | 16 | #include <linux/slab.h> |
db3c33c6 JR |
17 | |
18 | #include "pci.h" | |
19 | ||
afdd596c | 20 | void pci_ats_init(struct pci_dev *dev) |
db3c33c6 JR |
21 | { |
22 | int pos; | |
23 | u16 cap; | |
db3c33c6 JR |
24 | |
25 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS); | |
26 | if (!pos) | |
edc90fee | 27 | return; |
db3c33c6 | 28 | |
d544d75a BH |
29 | dev->ats_cap = pos; |
30 | pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap); | |
31 | dev->ats_qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : | |
db3c33c6 | 32 | PCI_ATS_MAX_QDEP; |
db3c33c6 JR |
33 | } |
34 | ||
35 | /** | |
36 | * pci_enable_ats - enable the ATS capability | |
37 | * @dev: the PCI device | |
38 | * @ps: the IOMMU page shift | |
39 | * | |
40 | * Returns 0 on success, or negative on failure. | |
41 | */ | |
42 | int pci_enable_ats(struct pci_dev *dev, int ps) | |
43 | { | |
db3c33c6 | 44 | u16 ctrl; |
c39127db | 45 | struct pci_dev *pdev; |
db3c33c6 | 46 | |
d544d75a | 47 | if (!dev->ats_cap) |
edc90fee BH |
48 | return -EINVAL; |
49 | ||
a021f301 BH |
50 | if (WARN_ON(pci_ats_enabled(dev))) |
51 | return -EBUSY; | |
52 | ||
db3c33c6 JR |
53 | if (ps < PCI_ATS_MIN_STU) |
54 | return -EINVAL; | |
55 | ||
edc90fee BH |
56 | /* |
57 | * Note that enabling ATS on a VF fails unless it's already enabled | |
58 | * with the same STU on the PF. | |
59 | */ | |
60 | ctrl = PCI_ATS_CTRL_ENABLE; | |
61 | if (dev->is_virtfn) { | |
c39127db | 62 | pdev = pci_physfn(dev); |
d544d75a | 63 | if (pdev->ats_stu != ps) |
edc90fee | 64 | return -EINVAL; |
db3c33c6 | 65 | |
d544d75a | 66 | atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */ |
edc90fee | 67 | } else { |
d544d75a BH |
68 | dev->ats_stu = ps; |
69 | ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); | |
db3c33c6 | 70 | } |
d544d75a | 71 | pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); |
db3c33c6 | 72 | |
d544d75a | 73 | dev->ats_enabled = 1; |
db3c33c6 JR |
74 | return 0; |
75 | } | |
d4c0636c | 76 | EXPORT_SYMBOL_GPL(pci_enable_ats); |
db3c33c6 JR |
77 | |
78 | /** | |
79 | * pci_disable_ats - disable the ATS capability | |
80 | * @dev: the PCI device | |
81 | */ | |
82 | void pci_disable_ats(struct pci_dev *dev) | |
83 | { | |
c39127db | 84 | struct pci_dev *pdev; |
db3c33c6 JR |
85 | u16 ctrl; |
86 | ||
a021f301 BH |
87 | if (WARN_ON(!pci_ats_enabled(dev))) |
88 | return; | |
db3c33c6 | 89 | |
d544d75a | 90 | if (atomic_read(&dev->ats_ref_cnt)) |
edc90fee BH |
91 | return; /* VFs still enabled */ |
92 | ||
93 | if (dev->is_virtfn) { | |
c39127db | 94 | pdev = pci_physfn(dev); |
d544d75a | 95 | atomic_dec(&pdev->ats_ref_cnt); |
edc90fee BH |
96 | } |
97 | ||
d544d75a | 98 | pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl); |
db3c33c6 | 99 | ctrl &= ~PCI_ATS_CTRL_ENABLE; |
d544d75a | 100 | pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); |
db3c33c6 | 101 | |
d544d75a | 102 | dev->ats_enabled = 0; |
db3c33c6 | 103 | } |
d4c0636c | 104 | EXPORT_SYMBOL_GPL(pci_disable_ats); |
db3c33c6 | 105 | |
1900ca13 HX |
106 | void pci_restore_ats_state(struct pci_dev *dev) |
107 | { | |
108 | u16 ctrl; | |
109 | ||
110 | if (!pci_ats_enabled(dev)) | |
111 | return; | |
1900ca13 HX |
112 | |
113 | ctrl = PCI_ATS_CTRL_ENABLE; | |
114 | if (!dev->is_virtfn) | |
d544d75a BH |
115 | ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); |
116 | pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); | |
1900ca13 HX |
117 | } |
118 | EXPORT_SYMBOL_GPL(pci_restore_ats_state); | |
119 | ||
db3c33c6 JR |
120 | /** |
121 | * pci_ats_queue_depth - query the ATS Invalidate Queue Depth | |
122 | * @dev: the PCI device | |
123 | * | |
124 | * Returns the queue depth on success, or negative on failure. | |
125 | * | |
126 | * The ATS spec uses 0 in the Invalidate Queue Depth field to | |
127 | * indicate that the function can accept 32 Invalidate Request. | |
128 | * But here we use the `real' values (i.e. 1~32) for the Queue | |
129 | * Depth; and 0 indicates the function shares the Queue with | |
130 | * other functions (doesn't exclusively own a Queue). | |
131 | */ | |
132 | int pci_ats_queue_depth(struct pci_dev *dev) | |
133 | { | |
3c765399 BH |
134 | if (!dev->ats_cap) |
135 | return -EINVAL; | |
136 | ||
db3c33c6 JR |
137 | if (dev->is_virtfn) |
138 | return 0; | |
139 | ||
3c765399 | 140 | return dev->ats_qdep; |
db3c33c6 | 141 | } |
d4c0636c | 142 | EXPORT_SYMBOL_GPL(pci_ats_queue_depth); |
c320b976 JR |
143 | |
144 | #ifdef CONFIG_PCI_PRI | |
145 | /** | |
146 | * pci_enable_pri - Enable PRI capability | |
147 | * @ pdev: PCI device structure | |
148 | * | |
149 | * Returns 0 on success, negative value on error | |
150 | */ | |
151 | int pci_enable_pri(struct pci_dev *pdev, u32 reqs) | |
152 | { | |
153 | u16 control, status; | |
154 | u32 max_requests; | |
155 | int pos; | |
156 | ||
69166fbf | 157 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c320b976 JR |
158 | if (!pos) |
159 | return -EINVAL; | |
160 | ||
91f57d5e AW |
161 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
162 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); | |
163 | if ((control & PCI_PRI_CTRL_ENABLE) || | |
164 | !(status & PCI_PRI_STATUS_STOPPED)) | |
c320b976 JR |
165 | return -EBUSY; |
166 | ||
91f57d5e | 167 | pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests); |
c320b976 | 168 | reqs = min(max_requests, reqs); |
91f57d5e | 169 | pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs); |
c320b976 | 170 | |
91f57d5e AW |
171 | control |= PCI_PRI_CTRL_ENABLE; |
172 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
c320b976 JR |
173 | |
174 | return 0; | |
175 | } | |
176 | EXPORT_SYMBOL_GPL(pci_enable_pri); | |
177 | ||
178 | /** | |
179 | * pci_disable_pri - Disable PRI capability | |
180 | * @pdev: PCI device structure | |
181 | * | |
182 | * Only clears the enabled-bit, regardless of its former value | |
183 | */ | |
184 | void pci_disable_pri(struct pci_dev *pdev) | |
185 | { | |
186 | u16 control; | |
187 | int pos; | |
188 | ||
69166fbf | 189 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c320b976 JR |
190 | if (!pos) |
191 | return; | |
192 | ||
91f57d5e AW |
193 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
194 | control &= ~PCI_PRI_CTRL_ENABLE; | |
195 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
c320b976 JR |
196 | } |
197 | EXPORT_SYMBOL_GPL(pci_disable_pri); | |
198 | ||
c320b976 JR |
199 | /** |
200 | * pci_reset_pri - Resets device's PRI state | |
201 | * @pdev: PCI device structure | |
202 | * | |
203 | * The PRI capability must be disabled before this function is called. | |
204 | * Returns 0 on success, negative value on error. | |
205 | */ | |
206 | int pci_reset_pri(struct pci_dev *pdev) | |
207 | { | |
208 | u16 control; | |
209 | int pos; | |
210 | ||
69166fbf | 211 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c320b976 JR |
212 | if (!pos) |
213 | return -EINVAL; | |
214 | ||
91f57d5e AW |
215 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
216 | if (control & PCI_PRI_CTRL_ENABLE) | |
c320b976 JR |
217 | return -EBUSY; |
218 | ||
91f57d5e | 219 | control |= PCI_PRI_CTRL_RESET; |
c320b976 | 220 | |
91f57d5e | 221 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); |
c320b976 JR |
222 | |
223 | return 0; | |
224 | } | |
225 | EXPORT_SYMBOL_GPL(pci_reset_pri); | |
c320b976 | 226 | #endif /* CONFIG_PCI_PRI */ |
086ac11f JR |
227 | |
228 | #ifdef CONFIG_PCI_PASID | |
229 | /** | |
230 | * pci_enable_pasid - Enable the PASID capability | |
231 | * @pdev: PCI device structure | |
232 | * @features: Features to enable | |
233 | * | |
234 | * Returns 0 on success, negative value on error. This function checks | |
235 | * whether the features are actually supported by the device and returns | |
236 | * an error if not. | |
237 | */ | |
238 | int pci_enable_pasid(struct pci_dev *pdev, int features) | |
239 | { | |
240 | u16 control, supported; | |
241 | int pos; | |
242 | ||
69166fbf | 243 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
244 | if (!pos) |
245 | return -EINVAL; | |
246 | ||
91f57d5e AW |
247 | pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control); |
248 | pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported); | |
086ac11f | 249 | |
91f57d5e | 250 | if (control & PCI_PASID_CTRL_ENABLE) |
086ac11f JR |
251 | return -EINVAL; |
252 | ||
91f57d5e | 253 | supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV; |
086ac11f JR |
254 | |
255 | /* User wants to enable anything unsupported? */ | |
256 | if ((supported & features) != features) | |
257 | return -EINVAL; | |
258 | ||
91f57d5e | 259 | control = PCI_PASID_CTRL_ENABLE | features; |
086ac11f | 260 | |
91f57d5e | 261 | pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); |
086ac11f JR |
262 | |
263 | return 0; | |
264 | } | |
265 | EXPORT_SYMBOL_GPL(pci_enable_pasid); | |
266 | ||
267 | /** | |
268 | * pci_disable_pasid - Disable the PASID capability | |
269 | * @pdev: PCI device structure | |
270 | * | |
271 | */ | |
272 | void pci_disable_pasid(struct pci_dev *pdev) | |
273 | { | |
274 | u16 control = 0; | |
275 | int pos; | |
276 | ||
69166fbf | 277 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
278 | if (!pos) |
279 | return; | |
280 | ||
91f57d5e | 281 | pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); |
086ac11f JR |
282 | } |
283 | EXPORT_SYMBOL_GPL(pci_disable_pasid); | |
284 | ||
285 | /** | |
286 | * pci_pasid_features - Check which PASID features are supported | |
287 | * @pdev: PCI device structure | |
288 | * | |
289 | * Returns a negative value when no PASI capability is present. | |
290 | * Otherwise is returns a bitmask with supported features. Current | |
291 | * features reported are: | |
91f57d5e | 292 | * PCI_PASID_CAP_EXEC - Execute permission supported |
f7625980 | 293 | * PCI_PASID_CAP_PRIV - Privileged mode supported |
086ac11f JR |
294 | */ |
295 | int pci_pasid_features(struct pci_dev *pdev) | |
296 | { | |
297 | u16 supported; | |
298 | int pos; | |
299 | ||
69166fbf | 300 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
301 | if (!pos) |
302 | return -EINVAL; | |
303 | ||
91f57d5e | 304 | pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported); |
086ac11f | 305 | |
91f57d5e | 306 | supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV; |
086ac11f JR |
307 | |
308 | return supported; | |
309 | } | |
310 | EXPORT_SYMBOL_GPL(pci_pasid_features); | |
311 | ||
312 | #define PASID_NUMBER_SHIFT 8 | |
313 | #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) | |
314 | /** | |
315 | * pci_max_pasid - Get maximum number of PASIDs supported by device | |
316 | * @pdev: PCI device structure | |
317 | * | |
318 | * Returns negative value when PASID capability is not present. | |
319 | * Otherwise it returns the numer of supported PASIDs. | |
320 | */ | |
321 | int pci_max_pasids(struct pci_dev *pdev) | |
322 | { | |
323 | u16 supported; | |
324 | int pos; | |
325 | ||
69166fbf | 326 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
327 | if (!pos) |
328 | return -EINVAL; | |
329 | ||
91f57d5e | 330 | pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported); |
086ac11f JR |
331 | |
332 | supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT; | |
333 | ||
334 | return (1 << supported); | |
335 | } | |
336 | EXPORT_SYMBOL_GPL(pci_max_pasids); | |
337 | #endif /* CONFIG_PCI_PASID */ |