Commit | Line | Data |
---|---|---|
10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Shaohua Li <shaohua.li@intel.com> | |
20 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
10e5247f | 21 | * |
e61d98d8 | 22 | * This file implements early detection/parsing of Remapping Devices |
10e5247f KA |
23 | * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI |
24 | * tables. | |
e61d98d8 SS |
25 | * |
26 | * These routines are used by both DMA-remapping and Interrupt-remapping | |
10e5247f KA |
27 | */ |
28 | ||
29 | #include <linux/pci.h> | |
30 | #include <linux/dmar.h> | |
fe962e90 | 31 | #include <linux/timer.h> |
093f87d2 | 32 | #include "iova.h" |
f661197e | 33 | #include "intel-iommu.h" |
10e5247f KA |
34 | |
35 | #undef PREFIX | |
36 | #define PREFIX "DMAR:" | |
37 | ||
38 | /* No locks are needed as DMA remapping hardware unit | |
39 | * list is constructed at boot time and hotplug of | |
40 | * these units are not supported by the architecture. | |
41 | */ | |
42 | LIST_HEAD(dmar_drhd_units); | |
10e5247f KA |
43 | |
44 | static struct acpi_table_header * __initdata dmar_tbl; | |
45 | ||
46 | static void __init dmar_register_drhd_unit(struct dmar_drhd_unit *drhd) | |
47 | { | |
48 | /* | |
49 | * add INCLUDE_ALL at the tail, so scan the list will find it at | |
50 | * the very end. | |
51 | */ | |
52 | if (drhd->include_all) | |
53 | list_add_tail(&drhd->list, &dmar_drhd_units); | |
54 | else | |
55 | list_add(&drhd->list, &dmar_drhd_units); | |
56 | } | |
57 | ||
10e5247f KA |
58 | static int __init dmar_parse_one_dev_scope(struct acpi_dmar_device_scope *scope, |
59 | struct pci_dev **dev, u16 segment) | |
60 | { | |
61 | struct pci_bus *bus; | |
62 | struct pci_dev *pdev = NULL; | |
63 | struct acpi_dmar_pci_path *path; | |
64 | int count; | |
65 | ||
66 | bus = pci_find_bus(segment, scope->bus); | |
67 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
68 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
69 | / sizeof(struct acpi_dmar_pci_path); | |
70 | ||
71 | while (count) { | |
72 | if (pdev) | |
73 | pci_dev_put(pdev); | |
74 | /* | |
75 | * Some BIOSes list non-exist devices in DMAR table, just | |
76 | * ignore it | |
77 | */ | |
78 | if (!bus) { | |
79 | printk(KERN_WARNING | |
80 | PREFIX "Device scope bus [%d] not found\n", | |
81 | scope->bus); | |
82 | break; | |
83 | } | |
84 | pdev = pci_get_slot(bus, PCI_DEVFN(path->dev, path->fn)); | |
85 | if (!pdev) { | |
86 | printk(KERN_WARNING PREFIX | |
87 | "Device scope device [%04x:%02x:%02x.%02x] not found\n", | |
88 | segment, bus->number, path->dev, path->fn); | |
89 | break; | |
90 | } | |
91 | path ++; | |
92 | count --; | |
93 | bus = pdev->subordinate; | |
94 | } | |
95 | if (!pdev) { | |
96 | printk(KERN_WARNING PREFIX | |
97 | "Device scope device [%04x:%02x:%02x.%02x] not found\n", | |
98 | segment, scope->bus, path->dev, path->fn); | |
99 | *dev = NULL; | |
100 | return 0; | |
101 | } | |
102 | if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && \ | |
103 | pdev->subordinate) || (scope->entry_type == \ | |
104 | ACPI_DMAR_SCOPE_TYPE_BRIDGE && !pdev->subordinate)) { | |
105 | pci_dev_put(pdev); | |
106 | printk(KERN_WARNING PREFIX | |
107 | "Device scope type does not match for %s\n", | |
108 | pci_name(pdev)); | |
109 | return -EINVAL; | |
110 | } | |
111 | *dev = pdev; | |
112 | return 0; | |
113 | } | |
114 | ||
115 | static int __init dmar_parse_dev_scope(void *start, void *end, int *cnt, | |
116 | struct pci_dev ***devices, u16 segment) | |
117 | { | |
118 | struct acpi_dmar_device_scope *scope; | |
119 | void * tmp = start; | |
120 | int index; | |
121 | int ret; | |
122 | ||
123 | *cnt = 0; | |
124 | while (start < end) { | |
125 | scope = start; | |
126 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || | |
127 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) | |
128 | (*cnt)++; | |
129 | else | |
130 | printk(KERN_WARNING PREFIX | |
131 | "Unsupported device scope\n"); | |
132 | start += scope->length; | |
133 | } | |
134 | if (*cnt == 0) | |
135 | return 0; | |
136 | ||
137 | *devices = kcalloc(*cnt, sizeof(struct pci_dev *), GFP_KERNEL); | |
138 | if (!*devices) | |
139 | return -ENOMEM; | |
140 | ||
141 | start = tmp; | |
142 | index = 0; | |
143 | while (start < end) { | |
144 | scope = start; | |
145 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || | |
146 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) { | |
147 | ret = dmar_parse_one_dev_scope(scope, | |
148 | &(*devices)[index], segment); | |
149 | if (ret) { | |
150 | kfree(*devices); | |
151 | return ret; | |
152 | } | |
153 | index ++; | |
154 | } | |
155 | start += scope->length; | |
156 | } | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | /** | |
162 | * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition | |
163 | * structure which uniquely represent one DMA remapping hardware unit | |
164 | * present in the platform | |
165 | */ | |
166 | static int __init | |
167 | dmar_parse_one_drhd(struct acpi_dmar_header *header) | |
168 | { | |
169 | struct acpi_dmar_hardware_unit *drhd; | |
170 | struct dmar_drhd_unit *dmaru; | |
171 | int ret = 0; | |
10e5247f KA |
172 | |
173 | dmaru = kzalloc(sizeof(*dmaru), GFP_KERNEL); | |
174 | if (!dmaru) | |
175 | return -ENOMEM; | |
176 | ||
1886e8a9 | 177 | dmaru->hdr = header; |
10e5247f KA |
178 | drhd = (struct acpi_dmar_hardware_unit *)header; |
179 | dmaru->reg_base_addr = drhd->address; | |
180 | dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ | |
181 | ||
1886e8a9 SS |
182 | ret = alloc_iommu(dmaru); |
183 | if (ret) { | |
184 | kfree(dmaru); | |
185 | return ret; | |
186 | } | |
187 | dmar_register_drhd_unit(dmaru); | |
188 | return 0; | |
189 | } | |
190 | ||
191 | static int __init | |
192 | dmar_parse_dev(struct dmar_drhd_unit *dmaru) | |
193 | { | |
194 | struct acpi_dmar_hardware_unit *drhd; | |
195 | static int include_all; | |
196 | int ret; | |
197 | ||
198 | drhd = (struct acpi_dmar_hardware_unit *) dmaru->hdr; | |
199 | ||
10e5247f KA |
200 | if (!dmaru->include_all) |
201 | ret = dmar_parse_dev_scope((void *)(drhd + 1), | |
1886e8a9 | 202 | ((void *)drhd) + drhd->header.length, |
10e5247f KA |
203 | &dmaru->devices_cnt, &dmaru->devices, |
204 | drhd->segment); | |
205 | else { | |
206 | /* Only allow one INCLUDE_ALL */ | |
207 | if (include_all) { | |
208 | printk(KERN_WARNING PREFIX "Only one INCLUDE_ALL " | |
209 | "device scope is allowed\n"); | |
210 | ret = -EINVAL; | |
211 | } | |
212 | include_all = 1; | |
213 | } | |
214 | ||
1886e8a9 SS |
215 | if (ret || (dmaru->devices_cnt == 0 && !dmaru->include_all)) { |
216 | list_del(&dmaru->list); | |
10e5247f | 217 | kfree(dmaru); |
1886e8a9 | 218 | } |
10e5247f KA |
219 | return ret; |
220 | } | |
221 | ||
aaa9d1dd SS |
222 | #ifdef CONFIG_DMAR |
223 | LIST_HEAD(dmar_rmrr_units); | |
224 | ||
225 | static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr) | |
226 | { | |
227 | list_add(&rmrr->list, &dmar_rmrr_units); | |
228 | } | |
229 | ||
230 | ||
10e5247f KA |
231 | static int __init |
232 | dmar_parse_one_rmrr(struct acpi_dmar_header *header) | |
233 | { | |
234 | struct acpi_dmar_reserved_memory *rmrr; | |
235 | struct dmar_rmrr_unit *rmrru; | |
10e5247f KA |
236 | |
237 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); | |
238 | if (!rmrru) | |
239 | return -ENOMEM; | |
240 | ||
1886e8a9 | 241 | rmrru->hdr = header; |
10e5247f KA |
242 | rmrr = (struct acpi_dmar_reserved_memory *)header; |
243 | rmrru->base_address = rmrr->base_address; | |
244 | rmrru->end_address = rmrr->end_address; | |
1886e8a9 SS |
245 | |
246 | dmar_register_rmrr_unit(rmrru); | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static int __init | |
251 | rmrr_parse_dev(struct dmar_rmrr_unit *rmrru) | |
252 | { | |
253 | struct acpi_dmar_reserved_memory *rmrr; | |
254 | int ret; | |
255 | ||
256 | rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr; | |
10e5247f | 257 | ret = dmar_parse_dev_scope((void *)(rmrr + 1), |
1886e8a9 | 258 | ((void *)rmrr) + rmrr->header.length, |
10e5247f KA |
259 | &rmrru->devices_cnt, &rmrru->devices, rmrr->segment); |
260 | ||
1886e8a9 SS |
261 | if (ret || (rmrru->devices_cnt == 0)) { |
262 | list_del(&rmrru->list); | |
10e5247f | 263 | kfree(rmrru); |
1886e8a9 | 264 | } |
10e5247f KA |
265 | return ret; |
266 | } | |
aaa9d1dd | 267 | #endif |
10e5247f KA |
268 | |
269 | static void __init | |
270 | dmar_table_print_dmar_entry(struct acpi_dmar_header *header) | |
271 | { | |
272 | struct acpi_dmar_hardware_unit *drhd; | |
273 | struct acpi_dmar_reserved_memory *rmrr; | |
274 | ||
275 | switch (header->type) { | |
276 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
277 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
278 | printk (KERN_INFO PREFIX | |
279 | "DRHD (flags: 0x%08x)base: 0x%016Lx\n", | |
280 | drhd->flags, drhd->address); | |
281 | break; | |
282 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
283 | rmrr = (struct acpi_dmar_reserved_memory *)header; | |
284 | ||
285 | printk (KERN_INFO PREFIX | |
286 | "RMRR base: 0x%016Lx end: 0x%016Lx\n", | |
287 | rmrr->base_address, rmrr->end_address); | |
288 | break; | |
289 | } | |
290 | } | |
291 | ||
aaa9d1dd | 292 | |
10e5247f KA |
293 | /** |
294 | * parse_dmar_table - parses the DMA reporting table | |
295 | */ | |
296 | static int __init | |
297 | parse_dmar_table(void) | |
298 | { | |
299 | struct acpi_table_dmar *dmar; | |
300 | struct acpi_dmar_header *entry_header; | |
301 | int ret = 0; | |
302 | ||
303 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
304 | if (!dmar) | |
305 | return -ENODEV; | |
306 | ||
093f87d2 FY |
307 | if (dmar->width < PAGE_SHIFT_4K - 1) { |
308 | printk(KERN_WARNING PREFIX "Invalid DMAR haw\n"); | |
10e5247f KA |
309 | return -EINVAL; |
310 | } | |
311 | ||
312 | printk (KERN_INFO PREFIX "Host address width %d\n", | |
313 | dmar->width + 1); | |
314 | ||
315 | entry_header = (struct acpi_dmar_header *)(dmar + 1); | |
316 | while (((unsigned long)entry_header) < | |
317 | (((unsigned long)dmar) + dmar_tbl->length)) { | |
318 | dmar_table_print_dmar_entry(entry_header); | |
319 | ||
320 | switch (entry_header->type) { | |
321 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
322 | ret = dmar_parse_one_drhd(entry_header); | |
323 | break; | |
324 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
aaa9d1dd | 325 | #ifdef CONFIG_DMAR |
10e5247f | 326 | ret = dmar_parse_one_rmrr(entry_header); |
aaa9d1dd | 327 | #endif |
10e5247f KA |
328 | break; |
329 | default: | |
330 | printk(KERN_WARNING PREFIX | |
331 | "Unknown DMAR structure type\n"); | |
332 | ret = 0; /* for forward compatibility */ | |
333 | break; | |
334 | } | |
335 | if (ret) | |
336 | break; | |
337 | ||
338 | entry_header = ((void *)entry_header + entry_header->length); | |
339 | } | |
340 | return ret; | |
341 | } | |
342 | ||
e61d98d8 SS |
343 | int dmar_pci_device_match(struct pci_dev *devices[], int cnt, |
344 | struct pci_dev *dev) | |
345 | { | |
346 | int index; | |
347 | ||
348 | while (dev) { | |
349 | for (index = 0; index < cnt; index++) | |
350 | if (dev == devices[index]) | |
351 | return 1; | |
352 | ||
353 | /* Check our parent */ | |
354 | dev = dev->bus->self; | |
355 | } | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | struct dmar_drhd_unit * | |
361 | dmar_find_matched_drhd_unit(struct pci_dev *dev) | |
362 | { | |
363 | struct dmar_drhd_unit *drhd = NULL; | |
364 | ||
365 | list_for_each_entry(drhd, &dmar_drhd_units, list) { | |
366 | if (drhd->include_all || dmar_pci_device_match(drhd->devices, | |
367 | drhd->devices_cnt, dev)) | |
368 | return drhd; | |
369 | } | |
370 | ||
371 | return NULL; | |
372 | } | |
373 | ||
1886e8a9 SS |
374 | int __init dmar_dev_scope_init(void) |
375 | { | |
376 | struct dmar_drhd_unit *drhd; | |
1886e8a9 SS |
377 | int ret = -ENODEV; |
378 | ||
379 | for_each_drhd_unit(drhd) { | |
380 | ret = dmar_parse_dev(drhd); | |
381 | if (ret) | |
382 | return ret; | |
383 | } | |
384 | ||
aaa9d1dd SS |
385 | #ifdef CONFIG_DMAR |
386 | { | |
387 | struct dmar_rmrr_unit *rmrr; | |
388 | for_each_rmrr_units(rmrr) { | |
389 | ret = rmrr_parse_dev(rmrr); | |
390 | if (ret) | |
391 | return ret; | |
392 | } | |
1886e8a9 | 393 | } |
aaa9d1dd | 394 | #endif |
1886e8a9 SS |
395 | |
396 | return ret; | |
397 | } | |
398 | ||
10e5247f KA |
399 | |
400 | int __init dmar_table_init(void) | |
401 | { | |
1886e8a9 | 402 | static int dmar_table_initialized; |
093f87d2 FY |
403 | int ret; |
404 | ||
1886e8a9 SS |
405 | if (dmar_table_initialized) |
406 | return 0; | |
407 | ||
408 | dmar_table_initialized = 1; | |
409 | ||
093f87d2 FY |
410 | ret = parse_dmar_table(); |
411 | if (ret) { | |
1886e8a9 SS |
412 | if (ret != -ENODEV) |
413 | printk(KERN_INFO PREFIX "parse DMAR table failure.\n"); | |
093f87d2 FY |
414 | return ret; |
415 | } | |
416 | ||
10e5247f KA |
417 | if (list_empty(&dmar_drhd_units)) { |
418 | printk(KERN_INFO PREFIX "No DMAR devices found\n"); | |
419 | return -ENODEV; | |
420 | } | |
093f87d2 | 421 | |
aaa9d1dd | 422 | #ifdef CONFIG_DMAR |
2d6b5f85 | 423 | if (list_empty(&dmar_rmrr_units)) |
093f87d2 | 424 | printk(KERN_INFO PREFIX "No RMRR found\n"); |
aaa9d1dd | 425 | #endif |
093f87d2 | 426 | |
ad3ad3f6 SS |
427 | #ifdef CONFIG_INTR_REMAP |
428 | parse_ioapics_under_ir(); | |
429 | #endif | |
10e5247f KA |
430 | return 0; |
431 | } | |
432 | ||
433 | /** | |
434 | * early_dmar_detect - checks to see if the platform supports DMAR devices | |
435 | */ | |
436 | int __init early_dmar_detect(void) | |
437 | { | |
438 | acpi_status status = AE_OK; | |
439 | ||
440 | /* if we could find DMAR table, then there are DMAR devices */ | |
441 | status = acpi_get_table(ACPI_SIG_DMAR, 0, | |
442 | (struct acpi_table_header **)&dmar_tbl); | |
443 | ||
444 | if (ACPI_SUCCESS(status) && !dmar_tbl) { | |
445 | printk (KERN_WARNING PREFIX "Unable to map DMAR\n"); | |
446 | status = AE_NOT_FOUND; | |
447 | } | |
448 | ||
449 | return (ACPI_SUCCESS(status) ? 1 : 0); | |
450 | } | |
e61d98d8 | 451 | |
2ae21010 SS |
452 | void __init detect_intel_iommu(void) |
453 | { | |
454 | int ret; | |
455 | ||
456 | ret = early_dmar_detect(); | |
457 | ||
458 | #ifdef CONFIG_DMAR | |
459 | { | |
460 | if (ret && !no_iommu && !iommu_detected && !swiotlb && | |
461 | !dmar_disabled) | |
462 | iommu_detected = 1; | |
463 | } | |
464 | #endif | |
465 | } | |
466 | ||
467 | ||
1886e8a9 | 468 | int alloc_iommu(struct dmar_drhd_unit *drhd) |
e61d98d8 | 469 | { |
c42d9f32 | 470 | struct intel_iommu *iommu; |
e61d98d8 SS |
471 | int map_size; |
472 | u32 ver; | |
c42d9f32 SS |
473 | static int iommu_allocated = 0; |
474 | ||
475 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); | |
476 | if (!iommu) | |
1886e8a9 | 477 | return -ENOMEM; |
c42d9f32 SS |
478 | |
479 | iommu->seq_id = iommu_allocated++; | |
e61d98d8 SS |
480 | |
481 | iommu->reg = ioremap(drhd->reg_base_addr, PAGE_SIZE_4K); | |
482 | if (!iommu->reg) { | |
483 | printk(KERN_ERR "IOMMU: can't map the region\n"); | |
484 | goto error; | |
485 | } | |
486 | iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); | |
487 | iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); | |
488 | ||
489 | /* the registers might be more than one page */ | |
490 | map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), | |
491 | cap_max_fault_reg_offset(iommu->cap)); | |
492 | map_size = PAGE_ALIGN_4K(map_size); | |
493 | if (map_size > PAGE_SIZE_4K) { | |
494 | iounmap(iommu->reg); | |
495 | iommu->reg = ioremap(drhd->reg_base_addr, map_size); | |
496 | if (!iommu->reg) { | |
497 | printk(KERN_ERR "IOMMU: can't map the region\n"); | |
498 | goto error; | |
499 | } | |
500 | } | |
501 | ||
502 | ver = readl(iommu->reg + DMAR_VER_REG); | |
503 | pr_debug("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n", | |
504 | drhd->reg_base_addr, DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), | |
505 | iommu->cap, iommu->ecap); | |
506 | ||
507 | spin_lock_init(&iommu->register_lock); | |
508 | ||
509 | drhd->iommu = iommu; | |
1886e8a9 | 510 | return 0; |
e61d98d8 SS |
511 | error: |
512 | kfree(iommu); | |
1886e8a9 | 513 | return -1; |
e61d98d8 SS |
514 | } |
515 | ||
516 | void free_iommu(struct intel_iommu *iommu) | |
517 | { | |
518 | if (!iommu) | |
519 | return; | |
520 | ||
521 | #ifdef CONFIG_DMAR | |
522 | free_dmar_iommu(iommu); | |
523 | #endif | |
524 | ||
525 | if (iommu->reg) | |
526 | iounmap(iommu->reg); | |
527 | kfree(iommu); | |
528 | } | |
fe962e90 SS |
529 | |
530 | /* | |
531 | * Reclaim all the submitted descriptors which have completed its work. | |
532 | */ | |
533 | static inline void reclaim_free_desc(struct q_inval *qi) | |
534 | { | |
535 | while (qi->desc_status[qi->free_tail] == QI_DONE) { | |
536 | qi->desc_status[qi->free_tail] = QI_FREE; | |
537 | qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; | |
538 | qi->free_cnt++; | |
539 | } | |
540 | } | |
541 | ||
542 | /* | |
543 | * Submit the queued invalidation descriptor to the remapping | |
544 | * hardware unit and wait for its completion. | |
545 | */ | |
546 | void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu) | |
547 | { | |
548 | struct q_inval *qi = iommu->qi; | |
549 | struct qi_desc *hw, wait_desc; | |
550 | int wait_index, index; | |
551 | unsigned long flags; | |
552 | ||
553 | if (!qi) | |
554 | return; | |
555 | ||
556 | hw = qi->desc; | |
557 | ||
558 | spin_lock(&qi->q_lock); | |
559 | while (qi->free_cnt < 3) { | |
560 | spin_unlock(&qi->q_lock); | |
561 | cpu_relax(); | |
562 | spin_lock(&qi->q_lock); | |
563 | } | |
564 | ||
565 | index = qi->free_head; | |
566 | wait_index = (index + 1) % QI_LENGTH; | |
567 | ||
568 | qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE; | |
569 | ||
570 | hw[index] = *desc; | |
571 | ||
572 | wait_desc.low = QI_IWD_STATUS_DATA(2) | QI_IWD_STATUS_WRITE | QI_IWD_TYPE; | |
573 | wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]); | |
574 | ||
575 | hw[wait_index] = wait_desc; | |
576 | ||
577 | __iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc)); | |
578 | __iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc)); | |
579 | ||
580 | qi->free_head = (qi->free_head + 2) % QI_LENGTH; | |
581 | qi->free_cnt -= 2; | |
582 | ||
583 | spin_lock_irqsave(&iommu->register_lock, flags); | |
584 | /* | |
585 | * update the HW tail register indicating the presence of | |
586 | * new descriptors. | |
587 | */ | |
588 | writel(qi->free_head << 4, iommu->reg + DMAR_IQT_REG); | |
589 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
590 | ||
591 | while (qi->desc_status[wait_index] != QI_DONE) { | |
592 | spin_unlock(&qi->q_lock); | |
593 | cpu_relax(); | |
594 | spin_lock(&qi->q_lock); | |
595 | } | |
596 | ||
597 | qi->desc_status[index] = QI_DONE; | |
598 | ||
599 | reclaim_free_desc(qi); | |
600 | spin_unlock(&qi->q_lock); | |
601 | } | |
602 | ||
603 | /* | |
604 | * Flush the global interrupt entry cache. | |
605 | */ | |
606 | void qi_global_iec(struct intel_iommu *iommu) | |
607 | { | |
608 | struct qi_desc desc; | |
609 | ||
610 | desc.low = QI_IEC_TYPE; | |
611 | desc.high = 0; | |
612 | ||
613 | qi_submit_sync(&desc, iommu); | |
614 | } | |
615 | ||
616 | /* | |
617 | * Enable Queued Invalidation interface. This is a must to support | |
618 | * interrupt-remapping. Also used by DMA-remapping, which replaces | |
619 | * register based IOTLB invalidation. | |
620 | */ | |
621 | int dmar_enable_qi(struct intel_iommu *iommu) | |
622 | { | |
623 | u32 cmd, sts; | |
624 | unsigned long flags; | |
625 | struct q_inval *qi; | |
626 | ||
627 | if (!ecap_qis(iommu->ecap)) | |
628 | return -ENOENT; | |
629 | ||
630 | /* | |
631 | * queued invalidation is already setup and enabled. | |
632 | */ | |
633 | if (iommu->qi) | |
634 | return 0; | |
635 | ||
636 | iommu->qi = kmalloc(sizeof(*qi), GFP_KERNEL); | |
637 | if (!iommu->qi) | |
638 | return -ENOMEM; | |
639 | ||
640 | qi = iommu->qi; | |
641 | ||
642 | qi->desc = (void *)(get_zeroed_page(GFP_KERNEL)); | |
643 | if (!qi->desc) { | |
644 | kfree(qi); | |
645 | iommu->qi = 0; | |
646 | return -ENOMEM; | |
647 | } | |
648 | ||
649 | qi->desc_status = kmalloc(QI_LENGTH * sizeof(int), GFP_KERNEL); | |
650 | if (!qi->desc_status) { | |
651 | free_page((unsigned long) qi->desc); | |
652 | kfree(qi); | |
653 | iommu->qi = 0; | |
654 | return -ENOMEM; | |
655 | } | |
656 | ||
657 | qi->free_head = qi->free_tail = 0; | |
658 | qi->free_cnt = QI_LENGTH; | |
659 | ||
660 | spin_lock_init(&qi->q_lock); | |
661 | ||
662 | spin_lock_irqsave(&iommu->register_lock, flags); | |
663 | /* write zero to the tail reg */ | |
664 | writel(0, iommu->reg + DMAR_IQT_REG); | |
665 | ||
666 | dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc)); | |
667 | ||
668 | cmd = iommu->gcmd | DMA_GCMD_QIE; | |
669 | iommu->gcmd |= DMA_GCMD_QIE; | |
670 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | |
671 | ||
672 | /* Make sure hardware complete it */ | |
673 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); | |
674 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
675 | ||
676 | return 0; | |
677 | } |