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47ff3de9 KVA |
1 | /* |
2 | * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs | |
3 | * | |
4 | * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Authors: Kishon Vijay Abraham I <kishon@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/irq.h> | |
17 | #include <linux/irqdomain.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
78bdcad0 | 20 | #include <linux/of_gpio.h> |
47ff3de9 KVA |
21 | #include <linux/pci.h> |
22 | #include <linux/phy/phy.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/resource.h> | |
26 | #include <linux/types.h> | |
27 | ||
28 | #include "pcie-designware.h" | |
29 | ||
30 | /* PCIe controller wrapper DRA7XX configuration registers */ | |
31 | ||
32 | #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024 | |
33 | #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028 | |
34 | #define ERR_SYS BIT(0) | |
35 | #define ERR_FATAL BIT(1) | |
36 | #define ERR_NONFATAL BIT(2) | |
37 | #define ERR_COR BIT(3) | |
38 | #define ERR_AXI BIT(4) | |
39 | #define ERR_ECRC BIT(5) | |
40 | #define PME_TURN_OFF BIT(8) | |
41 | #define PME_TO_ACK BIT(9) | |
42 | #define PM_PME BIT(10) | |
43 | #define LINK_REQ_RST BIT(11) | |
44 | #define LINK_UP_EVT BIT(12) | |
45 | #define CFG_BME_EVT BIT(13) | |
46 | #define CFG_MSE_EVT BIT(14) | |
47 | #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \ | |
48 | ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \ | |
49 | LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT) | |
50 | ||
51 | #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034 | |
52 | #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038 | |
53 | #define INTA BIT(0) | |
54 | #define INTB BIT(1) | |
55 | #define INTC BIT(2) | |
56 | #define INTD BIT(3) | |
57 | #define MSI BIT(4) | |
58 | #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD) | |
59 | ||
60 | #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104 | |
61 | #define LTSSM_EN 0x1 | |
62 | ||
63 | #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C | |
64 | #define LINK_UP BIT(16) | |
883cc17c | 65 | #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF |
47ff3de9 KVA |
66 | |
67 | struct dra7xx_pcie { | |
68 | void __iomem *base; | |
69 | struct phy **phy; | |
70 | int phy_count; | |
71 | struct device *dev; | |
72 | struct pcie_port pp; | |
73 | }; | |
74 | ||
75 | #define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp) | |
76 | ||
77 | static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) | |
78 | { | |
79 | return readl(pcie->base + offset); | |
80 | } | |
81 | ||
82 | static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, | |
83 | u32 value) | |
84 | { | |
85 | writel(value, pcie->base + offset); | |
86 | } | |
87 | ||
389c7094 KVA |
88 | static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset) |
89 | { | |
90 | return readl(pp->dbi_base + offset); | |
91 | } | |
92 | ||
93 | static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset, | |
94 | u32 value) | |
95 | { | |
96 | writel(value, pp->dbi_base + offset); | |
97 | } | |
98 | ||
47ff3de9 KVA |
99 | static int dra7xx_pcie_link_up(struct pcie_port *pp) |
100 | { | |
101 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); | |
102 | u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); | |
103 | ||
104 | return !!(reg & LINK_UP); | |
105 | } | |
106 | ||
107 | static int dra7xx_pcie_establish_link(struct pcie_port *pp) | |
108 | { | |
47ff3de9 | 109 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); |
6cbb247e BH |
110 | u32 reg; |
111 | unsigned int retries; | |
47ff3de9 KVA |
112 | |
113 | if (dw_pcie_link_up(pp)) { | |
114 | dev_err(pp->dev, "link is already up\n"); | |
115 | return 0; | |
116 | } | |
117 | ||
118 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); | |
119 | reg |= LTSSM_EN; | |
120 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
121 | ||
6cbb247e | 122 | for (retries = 0; retries < 1000; retries++) { |
30fb7ba6 | 123 | if (dw_pcie_link_up(pp)) |
6cbb247e | 124 | return 0; |
47ff3de9 KVA |
125 | usleep_range(10, 20); |
126 | } | |
127 | ||
6cbb247e BH |
128 | dev_err(pp->dev, "link is not up\n"); |
129 | return -EINVAL; | |
47ff3de9 KVA |
130 | } |
131 | ||
132 | static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) | |
133 | { | |
134 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); | |
135 | ||
136 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, | |
137 | ~INTERRUPTS); | |
138 | dra7xx_pcie_writel(dra7xx, | |
139 | PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS); | |
140 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, | |
141 | ~LEG_EP_INTERRUPTS & ~MSI); | |
142 | ||
143 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
144 | dra7xx_pcie_writel(dra7xx, | |
145 | PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI); | |
146 | else | |
147 | dra7xx_pcie_writel(dra7xx, | |
148 | PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, | |
149 | LEG_EP_INTERRUPTS); | |
150 | } | |
151 | ||
152 | static void dra7xx_pcie_host_init(struct pcie_port *pp) | |
153 | { | |
154 | dw_pcie_setup_rc(pp); | |
883cc17c | 155 | |
9cdce1cd ZW |
156 | pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; |
157 | pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; | |
158 | pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR; | |
159 | pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR; | |
883cc17c | 160 | |
47ff3de9 KVA |
161 | dra7xx_pcie_establish_link(pp); |
162 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
163 | dw_pcie_msi_init(pp); | |
164 | dra7xx_pcie_enable_interrupts(pp); | |
165 | } | |
166 | ||
167 | static struct pcie_host_ops dra7xx_pcie_host_ops = { | |
168 | .link_up = dra7xx_pcie_link_up, | |
169 | .host_init = dra7xx_pcie_host_init, | |
170 | }; | |
171 | ||
172 | static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, | |
173 | irq_hw_number_t hwirq) | |
174 | { | |
175 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); | |
176 | irq_set_chip_data(irq, domain->host_data); | |
47ff3de9 KVA |
177 | |
178 | return 0; | |
179 | } | |
180 | ||
181 | static const struct irq_domain_ops intx_domain_ops = { | |
182 | .map = dra7xx_pcie_intx_map, | |
183 | }; | |
184 | ||
185 | static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) | |
186 | { | |
187 | struct device *dev = pp->dev; | |
188 | struct device_node *node = dev->of_node; | |
189 | struct device_node *pcie_intc_node = of_get_next_child(node, NULL); | |
190 | ||
191 | if (!pcie_intc_node) { | |
192 | dev_err(dev, "No PCIe Intc node found\n"); | |
193 | return PTR_ERR(pcie_intc_node); | |
194 | } | |
195 | ||
196 | pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4, | |
197 | &intx_domain_ops, pp); | |
198 | if (!pp->irq_domain) { | |
199 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
200 | return PTR_ERR(pp->irq_domain); | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) | |
207 | { | |
208 | struct pcie_port *pp = arg; | |
209 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); | |
210 | u32 reg; | |
211 | ||
212 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); | |
213 | ||
214 | switch (reg) { | |
215 | case MSI: | |
216 | dw_handle_msi_irq(pp); | |
217 | break; | |
218 | case INTA: | |
219 | case INTB: | |
220 | case INTC: | |
221 | case INTD: | |
222 | generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg))); | |
223 | break; | |
224 | } | |
225 | ||
226 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg); | |
227 | ||
228 | return IRQ_HANDLED; | |
229 | } | |
230 | ||
231 | ||
232 | static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) | |
233 | { | |
234 | struct dra7xx_pcie *dra7xx = arg; | |
235 | u32 reg; | |
236 | ||
237 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); | |
238 | ||
239 | if (reg & ERR_SYS) | |
240 | dev_dbg(dra7xx->dev, "System Error\n"); | |
241 | ||
242 | if (reg & ERR_FATAL) | |
243 | dev_dbg(dra7xx->dev, "Fatal Error\n"); | |
244 | ||
245 | if (reg & ERR_NONFATAL) | |
246 | dev_dbg(dra7xx->dev, "Non Fatal Error\n"); | |
247 | ||
248 | if (reg & ERR_COR) | |
249 | dev_dbg(dra7xx->dev, "Correctable Error\n"); | |
250 | ||
251 | if (reg & ERR_AXI) | |
252 | dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n"); | |
253 | ||
254 | if (reg & ERR_ECRC) | |
255 | dev_dbg(dra7xx->dev, "ECRC Error\n"); | |
256 | ||
257 | if (reg & PME_TURN_OFF) | |
258 | dev_dbg(dra7xx->dev, | |
259 | "Power Management Event Turn-Off message received\n"); | |
260 | ||
261 | if (reg & PME_TO_ACK) | |
262 | dev_dbg(dra7xx->dev, | |
263 | "Power Management Turn-Off Ack message received\n"); | |
264 | ||
265 | if (reg & PM_PME) | |
266 | dev_dbg(dra7xx->dev, | |
267 | "PM Power Management Event message received\n"); | |
268 | ||
269 | if (reg & LINK_REQ_RST) | |
270 | dev_dbg(dra7xx->dev, "Link Request Reset\n"); | |
271 | ||
272 | if (reg & LINK_UP_EVT) | |
273 | dev_dbg(dra7xx->dev, "Link-up state change\n"); | |
274 | ||
275 | if (reg & CFG_BME_EVT) | |
276 | dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n"); | |
277 | ||
278 | if (reg & CFG_MSE_EVT) | |
279 | dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n"); | |
280 | ||
281 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); | |
282 | ||
283 | return IRQ_HANDLED; | |
284 | } | |
285 | ||
e73044a0 JH |
286 | static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, |
287 | struct platform_device *pdev) | |
47ff3de9 KVA |
288 | { |
289 | int ret; | |
290 | struct pcie_port *pp; | |
291 | struct resource *res; | |
292 | struct device *dev = &pdev->dev; | |
293 | ||
294 | pp = &dra7xx->pp; | |
295 | pp->dev = dev; | |
296 | pp->ops = &dra7xx_pcie_host_ops; | |
297 | ||
298 | pp->irq = platform_get_irq(pdev, 1); | |
299 | if (pp->irq < 0) { | |
300 | dev_err(dev, "missing IRQ resource\n"); | |
301 | return -EINVAL; | |
302 | } | |
303 | ||
304 | ret = devm_request_irq(&pdev->dev, pp->irq, | |
305 | dra7xx_pcie_msi_irq_handler, IRQF_SHARED, | |
306 | "dra7-pcie-msi", pp); | |
307 | if (ret) { | |
308 | dev_err(&pdev->dev, "failed to request irq\n"); | |
309 | return ret; | |
310 | } | |
311 | ||
312 | if (!IS_ENABLED(CONFIG_PCI_MSI)) { | |
313 | ret = dra7xx_pcie_init_irq_domain(pp); | |
314 | if (ret < 0) | |
315 | return ret; | |
316 | } | |
317 | ||
318 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics"); | |
319 | pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res)); | |
320 | if (!pp->dbi_base) | |
321 | return -ENOMEM; | |
322 | ||
323 | ret = dw_pcie_host_init(pp); | |
324 | if (ret) { | |
325 | dev_err(dra7xx->dev, "failed to initialize host\n"); | |
326 | return ret; | |
327 | } | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static int __init dra7xx_pcie_probe(struct platform_device *pdev) | |
333 | { | |
334 | u32 reg; | |
335 | int ret; | |
336 | int irq; | |
337 | int i; | |
338 | int phy_count; | |
339 | struct phy **phy; | |
340 | void __iomem *base; | |
341 | struct resource *res; | |
342 | struct dra7xx_pcie *dra7xx; | |
343 | struct device *dev = &pdev->dev; | |
344 | struct device_node *np = dev->of_node; | |
345 | char name[10]; | |
78bdcad0 KVA |
346 | int gpio_sel; |
347 | enum of_gpio_flags flags; | |
348 | unsigned long gpio_flags; | |
47ff3de9 KVA |
349 | |
350 | dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); | |
351 | if (!dra7xx) | |
352 | return -ENOMEM; | |
353 | ||
354 | irq = platform_get_irq(pdev, 0); | |
355 | if (irq < 0) { | |
356 | dev_err(dev, "missing IRQ resource\n"); | |
357 | return -EINVAL; | |
358 | } | |
359 | ||
360 | ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, | |
361 | IRQF_SHARED, "dra7xx-pcie-main", dra7xx); | |
362 | if (ret) { | |
363 | dev_err(dev, "failed to request irq\n"); | |
364 | return ret; | |
365 | } | |
366 | ||
367 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf"); | |
368 | base = devm_ioremap_nocache(dev, res->start, resource_size(res)); | |
369 | if (!base) | |
370 | return -ENOMEM; | |
371 | ||
372 | phy_count = of_property_count_strings(np, "phy-names"); | |
373 | if (phy_count < 0) { | |
374 | dev_err(dev, "unable to find the strings\n"); | |
375 | return phy_count; | |
376 | } | |
377 | ||
378 | phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL); | |
379 | if (!phy) | |
380 | return -ENOMEM; | |
381 | ||
382 | for (i = 0; i < phy_count; i++) { | |
383 | snprintf(name, sizeof(name), "pcie-phy%d", i); | |
384 | phy[i] = devm_phy_get(dev, name); | |
385 | if (IS_ERR(phy[i])) | |
386 | return PTR_ERR(phy[i]); | |
387 | ||
388 | ret = phy_init(phy[i]); | |
389 | if (ret < 0) | |
390 | goto err_phy; | |
391 | ||
392 | ret = phy_power_on(phy[i]); | |
393 | if (ret < 0) { | |
394 | phy_exit(phy[i]); | |
395 | goto err_phy; | |
396 | } | |
397 | } | |
398 | ||
399 | dra7xx->base = base; | |
400 | dra7xx->phy = phy; | |
401 | dra7xx->dev = dev; | |
402 | dra7xx->phy_count = phy_count; | |
403 | ||
404 | pm_runtime_enable(dev); | |
405 | ret = pm_runtime_get_sync(dev); | |
d3f4caa3 | 406 | if (ret < 0) { |
47ff3de9 | 407 | dev_err(dev, "pm_runtime_get_sync failed\n"); |
0e2bdb0e | 408 | goto err_get_sync; |
47ff3de9 KVA |
409 | } |
410 | ||
78bdcad0 KVA |
411 | gpio_sel = of_get_gpio_flags(dev->of_node, 0, &flags); |
412 | if (gpio_is_valid(gpio_sel)) { | |
413 | gpio_flags = (flags & OF_GPIO_ACTIVE_LOW) ? | |
414 | GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH; | |
415 | ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags, | |
416 | "pcie_reset"); | |
417 | if (ret) { | |
418 | dev_err(&pdev->dev, "gpio%d request failed, ret %d\n", | |
419 | gpio_sel, ret); | |
420 | goto err_gpio; | |
421 | } | |
422 | } else if (gpio_sel == -EPROBE_DEFER) { | |
423 | ret = -EPROBE_DEFER; | |
424 | goto err_gpio; | |
47ff3de9 KVA |
425 | } |
426 | ||
427 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); | |
428 | reg &= ~LTSSM_EN; | |
429 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
430 | ||
431 | platform_set_drvdata(pdev, dra7xx); | |
432 | ||
23926c8d | 433 | ret = dra7xx_add_pcie_port(dra7xx, pdev); |
47ff3de9 | 434 | if (ret < 0) |
78bdcad0 | 435 | goto err_gpio; |
47ff3de9 KVA |
436 | |
437 | return 0; | |
438 | ||
78bdcad0 | 439 | err_gpio: |
47ff3de9 | 440 | pm_runtime_put(dev); |
0e2bdb0e KVA |
441 | |
442 | err_get_sync: | |
47ff3de9 KVA |
443 | pm_runtime_disable(dev); |
444 | ||
445 | err_phy: | |
446 | while (--i >= 0) { | |
447 | phy_power_off(phy[i]); | |
448 | phy_exit(phy[i]); | |
449 | } | |
450 | ||
451 | return ret; | |
452 | } | |
453 | ||
454 | static int __exit dra7xx_pcie_remove(struct platform_device *pdev) | |
455 | { | |
456 | struct dra7xx_pcie *dra7xx = platform_get_drvdata(pdev); | |
457 | struct pcie_port *pp = &dra7xx->pp; | |
458 | struct device *dev = &pdev->dev; | |
459 | int count = dra7xx->phy_count; | |
460 | ||
461 | if (pp->irq_domain) | |
462 | irq_domain_remove(pp->irq_domain); | |
463 | pm_runtime_put(dev); | |
464 | pm_runtime_disable(dev); | |
465 | while (count--) { | |
466 | phy_power_off(dra7xx->phy[count]); | |
467 | phy_exit(dra7xx->phy[count]); | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
e52eb445 | 473 | #ifdef CONFIG_PM_SLEEP |
389c7094 KVA |
474 | static int dra7xx_pcie_suspend(struct device *dev) |
475 | { | |
476 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
477 | struct pcie_port *pp = &dra7xx->pp; | |
478 | u32 val; | |
479 | ||
480 | /* clear MSE */ | |
481 | val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); | |
482 | val &= ~PCI_COMMAND_MEMORY; | |
483 | dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int dra7xx_pcie_resume(struct device *dev) | |
489 | { | |
490 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
491 | struct pcie_port *pp = &dra7xx->pp; | |
492 | u32 val; | |
493 | ||
494 | /* set MSE */ | |
495 | val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); | |
496 | val |= PCI_COMMAND_MEMORY; | |
497 | dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
e52eb445 KVA |
502 | static int dra7xx_pcie_suspend_noirq(struct device *dev) |
503 | { | |
504 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
505 | int count = dra7xx->phy_count; | |
506 | ||
507 | while (count--) { | |
508 | phy_power_off(dra7xx->phy[count]); | |
509 | phy_exit(dra7xx->phy[count]); | |
510 | } | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
515 | static int dra7xx_pcie_resume_noirq(struct device *dev) | |
516 | { | |
517 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
518 | int phy_count = dra7xx->phy_count; | |
519 | int ret; | |
520 | int i; | |
521 | ||
522 | for (i = 0; i < phy_count; i++) { | |
523 | ret = phy_init(dra7xx->phy[i]); | |
524 | if (ret < 0) | |
525 | goto err_phy; | |
526 | ||
527 | ret = phy_power_on(dra7xx->phy[i]); | |
528 | if (ret < 0) { | |
529 | phy_exit(dra7xx->phy[i]); | |
530 | goto err_phy; | |
531 | } | |
532 | } | |
533 | ||
534 | return 0; | |
535 | ||
536 | err_phy: | |
537 | while (--i >= 0) { | |
538 | phy_power_off(dra7xx->phy[i]); | |
539 | phy_exit(dra7xx->phy[i]); | |
540 | } | |
541 | ||
542 | return ret; | |
543 | } | |
544 | #endif | |
545 | ||
546 | static const struct dev_pm_ops dra7xx_pcie_pm_ops = { | |
389c7094 | 547 | SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume) |
e52eb445 KVA |
548 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq, |
549 | dra7xx_pcie_resume_noirq) | |
550 | }; | |
551 | ||
47ff3de9 KVA |
552 | static const struct of_device_id of_dra7xx_pcie_match[] = { |
553 | { .compatible = "ti,dra7-pcie", }, | |
554 | {}, | |
555 | }; | |
556 | MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match); | |
557 | ||
558 | static struct platform_driver dra7xx_pcie_driver = { | |
559 | .remove = __exit_p(dra7xx_pcie_remove), | |
560 | .driver = { | |
561 | .name = "dra7-pcie", | |
47ff3de9 | 562 | .of_match_table = of_dra7xx_pcie_match, |
e52eb445 | 563 | .pm = &dra7xx_pcie_pm_ops, |
47ff3de9 KVA |
564 | }, |
565 | }; | |
566 | ||
567 | module_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe); | |
568 | ||
569 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
570 | MODULE_DESCRIPTION("TI PCIe controller driver"); | |
571 | MODULE_LICENSE("GPL v2"); |