[deliverable/linux.git] / drivers / pci / host / pci-imx6.c

/*
 * PCIe host controller driver for Freescale i.MX6 SoCs
 *
 * Copyright (C) 2013 Kosagi
 *		http://www.kosagi.com
 *
 * Author: Sean Cross <xobs@kosagi.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>
#include <linux/interrupt.h>

#include "pcie-designware.h"

#define to_imx6_pcie(x)	container_of(x, struct imx6_pcie, pp)

struct imx6_pcie {
	struct gpio_desc	*reset_gpio;
	struct clk		*pcie_bus;
	struct clk		*pcie_phy;
	struct clk		*pcie;
	struct pcie_port	pp;
	struct regmap		*iomuxc_gpr;
	void __iomem		*mem_base;
};

/* PCIe Root Complex registers (memory-mapped) */
#define PCIE_RC_LCR				0x7c
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1	0x1
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2	0x2
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK	0xf

#define PCIE_RC_LCSR				0x80

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
#define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
#define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)

#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
#define PCIE_PHY_CTRL_WR_LOC 18
#define PCIE_PHY_CTRL_RD_LOC 19

#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
#define PCIE_PHY_STAT_ACK_LOC 16

#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)

/* PHY registers (not memory-mapped) */
#define PCIE_PHY_RX_ASIC_OUT 0x100D
#define PCIE_PHY_RX_ASIC_OUT_VALID	(1 << 0)

#define PHY_RX_OVRD_IN_LO 0x1005
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)

static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
{
	u32 val;
	u32 max_iterations = 10;
	u32 wait_counter = 0;

	do {
		val = readl(dbi_base + PCIE_PHY_STAT);
		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
		wait_counter++;

		if (val == exp_val)
			return 0;

		udelay(1);
	} while (wait_counter < max_iterations);

	return -ETIMEDOUT;
}

static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
{
	u32 val;
	int ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	return pcie_phy_poll_ack(dbi_base, 0);
}

/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
static int pcie_phy_read(void __iomem *dbi_base, int addr, int *data)
{
	u32 val, phy_ctl;
	int ret;

	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	/* assert Read signal */
	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = readl(dbi_base + PCIE_PHY_STAT);
	*data = val & 0xffff;

	/* deassert Read signal */
	writel(0x00, dbi_base + PCIE_PHY_CTRL);

	return pcie_phy_poll_ack(dbi_base, 0);
}

static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
{
	u32 var;
	int ret;

	/* write addr */
	/* cap addr */
	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* capture data */
	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	writel(var, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert cap data */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	/* assert wr signal */
	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack */
	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert wr signal */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	writel(0x0, dbi_base + PCIE_PHY_CTRL);

	return 0;
}

static void imx6_pcie_reset_phy(struct pcie_port *pp)
{
	u32 tmp;

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);

	usleep_range(2000, 3000);

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
}

/*  Added for PCI abort handling */
static int imx6q_pcie_abort_handler(unsigned long addr,
		unsigned int fsr, struct pt_regs *regs)
{
	return 0;
}

static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	u32 val, gpr1, gpr12;

	/*
	 * If the bootloader already enabled the link we need some special
	 * handling to get the core back into a state where it is safe to
	 * touch it for configuration.  As there is no dedicated reset signal
	 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
	 * state before completely disabling LTSSM, which is a prerequisite
	 * for core configuration.
	 *
	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	 * indication that the bootloader activated the link.
	 */
	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);

	if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
	    (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
		val = readl(pp->dbi_base + PCIE_PL_PFLR);
		val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
		val |= PCIE_PL_PFLR_FORCE_LINK;
		writel(val, pp->dbi_base + PCIE_PL_PFLR);

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
				IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	}

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

	return 0;
}

static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	int ret;

	ret = clk_prepare_enable(imx6_pcie->pcie_phy);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_phy clock\n");
		goto err_pcie_phy;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_bus);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_bus clock\n");
		goto err_pcie_bus;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie clock\n");
		goto err_pcie;
	}

	/* power up core phy and enable ref clock */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	/*
	 * the async reset input need ref clock to sync internally,
	 * when the ref clock comes after reset, internal synced
	 * reset time is too short, cannot meet the requirement.
	 * add one ~10us delay here.
	 */
	udelay(10);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

	/* allow the clocks to stabilize */
	usleep_range(200, 500);

	/* Some boards don't have PCIe reset GPIO. */
	if (imx6_pcie->reset_gpio) {
		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0);
		msleep(100);
		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
	}
	return 0;

err_pcie:
	clk_disable_unprepare(imx6_pcie->pcie_bus);
err_pcie_bus:
	clk_disable_unprepare(imx6_pcie->pcie_phy);
err_pcie_phy:
	return ret;

}

static void imx6_pcie_init_phy(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);

	/* configure constant input signal to the pcie ctrl and phy */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
}

static int imx6_pcie_wait_for_link(struct pcie_port *pp)
{
	unsigned int retries;

	for (retries = 0; retries < 200; retries++) {
		if (dw_pcie_link_up(pp))
			return 0;
		usleep_range(100, 1000);
	}

	dev_err(pp->dev, "phy link never came up\n");
	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
		readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
		readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	return -EINVAL;
}

static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
{
	u32 tmp;
	unsigned int retries;

	for (retries = 0; retries < 200; retries++) {
		tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
		/* Test if the speed change finished. */
		if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
			return 0;
		usleep_range(100, 1000);
	}

	dev_err(pp->dev, "Speed change timeout\n");
	return -EINVAL;
}

static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
{
	struct pcie_port *pp = arg;

	return dw_handle_msi_irq(pp);
}

static int imx6_pcie_establish_link(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	u32 tmp;
	int ret;

	/*
	 * Force Gen1 operation when starting the link.  In case the link is
	 * started in Gen2 mode, there is a possibility the devices on the
	 * bus will not be detected at all.  This happens with PCIe switches.
	 */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/* Start LTSSM. */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);

	ret = imx6_pcie_wait_for_link(pp);
	if (ret)
		return ret;

	/* Allow Gen2 mode after the link is up. */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/*
	 * Start Directed Speed Change so the best possible speed both link
	 * partners support can be negotiated.
	 */
	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	tmp |= PORT_LOGIC_SPEED_CHANGE;
	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);

	ret = imx6_pcie_wait_for_speed_change(pp);
	if (ret) {
		dev_err(pp->dev, "Failed to bring link up!\n");
		return ret;
	}

	/* Make sure link training is finished as well! */
	ret = imx6_pcie_wait_for_link(pp);
	if (ret) {
		dev_err(pp->dev, "Failed to bring link up!\n");
		return ret;
	}

	tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
	dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
	return 0;
}

static void imx6_pcie_host_init(struct pcie_port *pp)
{
	imx6_pcie_assert_core_reset(pp);

	imx6_pcie_init_phy(pp);

	imx6_pcie_deassert_core_reset(pp);

	dw_pcie_setup_rc(pp);

	imx6_pcie_establish_link(pp);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
}

static int imx6_pcie_link_up(struct pcie_port *pp)
{
	u32 rc, debug_r0, rx_valid;
	int count = 5;

	/*
	 * Test if the PHY reports that the link is up and also that the LTSSM
	 * training finished. There are three possible states of the link when
	 * this code is called:
	 * 1) The link is DOWN (unlikely)
	 *     The link didn't come up yet for some reason. This usually means
	 *     we have a real problem somewhere. Reset the PHY and exit. This
	 *     state calls for inspection of the DEBUG registers.
	 * 2) The link is UP, but still in LTSSM training
	 *     Wait for the training to finish, which should take a very short
	 *     time. If the training does not finish, we have a problem and we
	 *     need to inspect the DEBUG registers. If the training does finish,
	 *     the link is up and operating correctly.
	 * 3) The link is UP and no longer in LTSSM training
	 *     The link is up and operating correctly.
	 */
	while (1) {
		rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
		if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
			break;
		if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
			return 1;
		if (!count--)
			break;
		dev_dbg(pp->dev, "Link is up, but still in training\n");
		/*
		 * Wait a little bit, then re-check if the link finished
		 * the training.
		 */
		usleep_range(1000, 2000);
	}
	/*
	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	 * to gen2 is stuck
	 */
	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);

	if (rx_valid & PCIE_PHY_RX_ASIC_OUT_VALID)
		return 0;

	if ((debug_r0 & 0x3f) != 0x0d)
		return 0;

	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
	dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);

	imx6_pcie_reset_phy(pp);

	return 0;
}

static struct pcie_host_ops imx6_pcie_host_ops = {
	.link_up = imx6_pcie_link_up,
	.host_init = imx6_pcie_host_init,
};

static int __init imx6_add_pcie_port(struct pcie_port *pp,
			struct platform_device *pdev)
{
	int ret;

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
		if (pp->msi_irq <= 0) {
			dev_err(&pdev->dev, "failed to get MSI irq\n");
			return -ENODEV;
		}

		ret = devm_request_irq(&pdev->dev, pp->msi_irq,
				       imx6_pcie_msi_handler,
				       IRQF_SHARED | IRQF_NO_THREAD,
				       "mx6-pcie-msi", pp);
		if (ret) {
			dev_err(&pdev->dev, "failed to request MSI irq\n");
			return ret;
		}
	}

	pp->root_bus_nr = -1;
	pp->ops = &imx6_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init imx6_pcie_probe(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie;
	struct pcie_port *pp;
	struct resource *dbi_base;
	int ret;

	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	if (!imx6_pcie)
		return -ENOMEM;

	pp = &imx6_pcie->pp;
	pp->dev = &pdev->dev;

	/* Added for PCI abort handling */
	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
		"imprecise external abort");

	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	/* Fetch GPIOs */
	imx6_pcie->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
							GPIOD_OUT_LOW);

	/* Fetch clocks */
	imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
	if (IS_ERR(imx6_pcie->pcie_phy)) {
		dev_err(&pdev->dev,
			"pcie_phy clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_phy);
	}

	imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
	if (IS_ERR(imx6_pcie->pcie_bus)) {
		dev_err(&pdev->dev,
			"pcie_bus clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_bus);
	}

	imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
	if (IS_ERR(imx6_pcie->pcie)) {
		dev_err(&pdev->dev,
			"pcie clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie);
	}

	/* Grab GPR config register range */
	imx6_pcie->iomuxc_gpr =
		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
		return PTR_ERR(imx6_pcie->iomuxc_gpr);
	}

	ret = imx6_add_pcie_port(pp, pdev);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx6_pcie);
	return 0;
}

static void imx6_pcie_shutdown(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);

	/* bring down link, so bootloader gets clean state in case of reboot */
	imx6_pcie_assert_core_reset(&imx6_pcie->pp);
}

static const struct of_device_id imx6_pcie_of_match[] = {
	{ .compatible = "fsl,imx6q-pcie", },
	{},
};
MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

static struct platform_driver imx6_pcie_driver = {
	.driver = {
		.name	= "imx6q-pcie",
		.of_match_table = imx6_pcie_of_match,
	},
	.shutdown = imx6_pcie_shutdown,
};

/* Freescale PCIe driver does not allow module unload */

static int __init imx6_pcie_init(void)
{
	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
}
module_init(imx6_pcie_init);

MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bb38919e SC	1	/*
	2	* PCIe host controller driver for Freescale i.MX6 SoCs
	3	*
	4	* Copyright (C) 2013 Kosagi
	5	* http://www.kosagi.com
	6	*
	7	* Author: Sean Cross <xobs@kosagi.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/gpio.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	20	#include <linux/module.h>
	21	#include <linux/of_gpio.h>
	22	#include <linux/pci.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/resource.h>
	26	#include <linux/signal.h>
	27	#include <linux/types.h>
d1dc9749	28	#include <linux/interrupt.h>
bb38919e SC	29
	30	#include "pcie-designware.h"
	31
	32	#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
	33
	34	struct imx6_pcie {
5c5fb40d	35	struct gpio_desc *reset_gpio;
57526136 LS	36	struct clk *pcie_bus;
	37	struct clk *pcie_phy;
	38	struct clk *pcie;
bb38919e SC	39	struct pcie_port pp;
	40	struct regmap *iomuxc_gpr;
	41	void __iomem *mem_base;
	42	};
	43
fa33a6d8 MV	44	/* PCIe Root Complex registers (memory-mapped) */
	45	#define PCIE_RC_LCR 0x7c
	46	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
	47	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
	48	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
	49
2393f79c BH	50	#define PCIE_RC_LCSR 0x80
2393f79c BH	51
bb38919e SC	52	/* PCIe Port Logic registers (memory-mapped) */
bb38919e SC	53	#define PL_OFFSET 0x700
3e3e406e LS	54	#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
	55	#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
	56	#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
bb38919e SC	57	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
bb38919e SC	58	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
7f9f40c0 MV	59	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
7f9f40c0 MV	60	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
bb38919e SC	61
	62	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
	63	#define PCIE_PHY_CTRL_DATA_LOC 0
	64	#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
	65	#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
	66	#define PCIE_PHY_CTRL_WR_LOC 18
	67	#define PCIE_PHY_CTRL_RD_LOC 19
	68
	69	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
	70	#define PCIE_PHY_STAT_ACK_LOC 16
	71
fa33a6d8 MV	72	#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
	73	#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
	74
bb38919e SC	75	/* PHY registers (not memory-mapped) */
bb38919e SC	76	#define PCIE_PHY_RX_ASIC_OUT 0x100D
111feb7f	77	#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
bb38919e SC	78
	79	#define PHY_RX_OVRD_IN_LO 0x1005
	80	#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
	81	#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
	82
	83	static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
	84	{
	85	u32 val;
	86	u32 max_iterations = 10;
	87	u32 wait_counter = 0;
	88
	89	do {
	90	val = readl(dbi_base + PCIE_PHY_STAT);
	91	val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
	92	wait_counter++;
	93
	94	if (val == exp_val)
	95	return 0;
	96
	97	udelay(1);
	98	} while (wait_counter < max_iterations);
	99
	100	return -ETIMEDOUT;
	101	}
	102
	103	static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
	104	{
	105	u32 val;
	106	int ret;
	107
	108	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	109	writel(val, dbi_base + PCIE_PHY_CTRL);
	110
	111	val \|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	112	writel(val, dbi_base + PCIE_PHY_CTRL);
	113
	114	ret = pcie_phy_poll_ack(dbi_base, 1);
	115	if (ret)
	116	return ret;
	117
	118	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	119	writel(val, dbi_base + PCIE_PHY_CTRL);
	120
8d1ceb52	121	return pcie_phy_poll_ack(dbi_base, 0);
bb38919e SC	122	}
	123
	124	/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
ff3ce480	125	static int pcie_phy_read(void __iomem dbi_base, int addr, int data)
bb38919e SC	126	{
	127	u32 val, phy_ctl;
	128	int ret;
	129
	130	ret = pcie_phy_wait_ack(dbi_base, addr);
	131	if (ret)
	132	return ret;
	133
	134	/* assert Read signal */
	135	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	136	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
	137
	138	ret = pcie_phy_poll_ack(dbi_base, 1);
	139	if (ret)
	140	return ret;
	141
	142	val = readl(dbi_base + PCIE_PHY_STAT);
	143	*data = val & 0xffff;
	144
	145	/* deassert Read signal */
	146	writel(0x00, dbi_base + PCIE_PHY_CTRL);
	147
8d1ceb52	148	return pcie_phy_poll_ack(dbi_base, 0);
bb38919e SC	149	}
	150
	151	static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
	152	{
	153	u32 var;
	154	int ret;
	155
	156	/* write addr */
	157	/* cap addr */
	158	ret = pcie_phy_wait_ack(dbi_base, addr);
	159	if (ret)
	160	return ret;
	161
	162	var = data << PCIE_PHY_CTRL_DATA_LOC;
	163	writel(var, dbi_base + PCIE_PHY_CTRL);
	164
	165	/* capture data */
	166	var \|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	167	writel(var, dbi_base + PCIE_PHY_CTRL);
	168
	169	ret = pcie_phy_poll_ack(dbi_base, 1);
	170	if (ret)
	171	return ret;
	172
	173	/* deassert cap data */
	174	var = data << PCIE_PHY_CTRL_DATA_LOC;
	175	writel(var, dbi_base + PCIE_PHY_CTRL);
	176
	177	/* wait for ack de-assertion */
	178	ret = pcie_phy_poll_ack(dbi_base, 0);
	179	if (ret)
	180	return ret;
	181
	182	/* assert wr signal */
	183	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	184	writel(var, dbi_base + PCIE_PHY_CTRL);
	185
	186	/* wait for ack */
	187	ret = pcie_phy_poll_ack(dbi_base, 1);
	188	if (ret)
	189	return ret;
	190
	191	/* deassert wr signal */
	192	var = data << PCIE_PHY_CTRL_DATA_LOC;
	193	writel(var, dbi_base + PCIE_PHY_CTRL);
	194
	195	/* wait for ack de-assertion */
	196	ret = pcie_phy_poll_ack(dbi_base, 0);
	197	if (ret)
	198	return ret;
	199
	200	writel(0x0, dbi_base + PCIE_PHY_CTRL);
	201
	202	return 0;
	203	}
	204
53eeb48b LS	205	static void imx6_pcie_reset_phy(struct pcie_port *pp)
	206	{
	207	u32 tmp;
	208
	209	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	210	tmp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	211	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	212	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
	213
	214	usleep_range(2000, 3000);
	215
	216	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
	217	tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	218	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	219	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
	220	}
	221
bb38919e SC	222	/* Added for PCI abort handling */
	223	static int imx6q_pcie_abort_handler(unsigned long addr,
	224	unsigned int fsr, struct pt_regs *regs)
	225	{
bb38919e SC	226	return 0;
	227	}
	228
	229	static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
	230	{
	231	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
3e3e406e LS	232	u32 val, gpr1, gpr12;
	233
	234	/*
	235	* If the bootloader already enabled the link we need some special
	236	* handling to get the core back into a state where it is safe to
	237	* touch it for configuration. As there is no dedicated reset signal
	238	* wired up for MX6QDL, we need to manually force LTSSM into "detect"
	239	* state before completely disabling LTSSM, which is a prerequisite
	240	* for core configuration.
	241	*
	242	* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	243	* indication that the bootloader activated the link.
	244	*/
	245	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
	246	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
	247
	248	if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
	249	(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
	250	val = readl(pp->dbi_base + PCIE_PL_PFLR);
	251	val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
	252	val \|= PCIE_PL_PFLR_FORCE_LINK;
	253	writel(val, pp->dbi_base + PCIE_PL_PFLR);
	254
	255	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	256	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	257	}
bb38919e SC	258
	259	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	260	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
bb38919e SC	261	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	262	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
	263
bb38919e SC	264	return 0;
	265	}
	266
	267	static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
	268	{
	269	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	270	int ret;
	271
57526136	272	ret = clk_prepare_enable(imx6_pcie->pcie_phy);
bb38919e	273	if (ret) {
57526136 LS	274	dev_err(pp->dev, "unable to enable pcie_phy clock\n");
57526136 LS	275	goto err_pcie_phy;
bb38919e SC	276	}
bb38919e SC	277
57526136	278	ret = clk_prepare_enable(imx6_pcie->pcie_bus);
bb38919e	279	if (ret) {
57526136 LS	280	dev_err(pp->dev, "unable to enable pcie_bus clock\n");
57526136 LS	281	goto err_pcie_bus;
bb38919e SC	282	}
bb38919e SC	283
57526136	284	ret = clk_prepare_enable(imx6_pcie->pcie);
bb38919e	285	if (ret) {
57526136 LS	286	dev_err(pp->dev, "unable to enable pcie clock\n");
57526136 LS	287	goto err_pcie;
bb38919e SC	288	}
bb38919e SC	289
3fce0e88 TH	290	/* power up core phy and enable ref clock */
	291	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	292	IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
a2fa6f64 RZ	293	/*
	294	* the async reset input need ref clock to sync internally,
	295	* when the ref clock comes after reset, internal synced
	296	* reset time is too short, cannot meet the requirement.
	297	* add one ~10us delay here.
	298	*/
	299	udelay(10);
3fce0e88 TH	300	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	301	IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
	302
a2fa6f64 RZ	303	/* allow the clocks to stabilize */
	304	usleep_range(200, 500);
	305
bc9ef770	306	/* Some boards don't have PCIe reset GPIO. */
5c5fb40d PŠ	307	if (imx6_pcie->reset_gpio) {
5c5fb40d PŠ	308	gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0);
bc9ef770	309	msleep(100);
5c5fb40d	310	gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
bc9ef770	311	}
bb38919e SC	312	return 0;
bb38919e SC	313
57526136 LS	314	err_pcie:
	315	clk_disable_unprepare(imx6_pcie->pcie_bus);
	316	err_pcie_bus:
	317	clk_disable_unprepare(imx6_pcie->pcie_phy);
	318	err_pcie_phy:
bb38919e SC	319	return ret;
	320
	321	}
	322
	323	static void imx6_pcie_init_phy(struct pcie_port *pp)
	324	{
	325	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	326
	327	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	328	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	329
	330	/* configure constant input signal to the pcie ctrl and phy */
	331	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	332	IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	333	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	334	IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
	335
	336	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	337	IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
	338	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	339	IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
	340	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	341	IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
	342	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	343	IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
	344	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	345	IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
	346	}
	347
66a60f93 MV	348	static int imx6_pcie_wait_for_link(struct pcie_port *pp)
66a60f93 MV	349	{
6cbb247e	350	unsigned int retries;
66a60f93	351
6cbb247e BH	352	for (retries = 0; retries < 200; retries++) {
	353	if (dw_pcie_link_up(pp))
	354	return 0;
66a60f93	355	usleep_range(100, 1000);
66a60f93 MV	356	}
66a60f93 MV	357
6cbb247e BH	358	dev_err(pp->dev, "phy link never came up\n");
	359	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	360	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
	361	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	362	return -EINVAL;
66a60f93 MV	363	}
66a60f93 MV	364
a0427464 TK	365	static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
a0427464 TK	366	{
1c7fae18	367	u32 tmp;
a0427464 TK	368	unsigned int retries;
	369
	370	for (retries = 0; retries < 200; retries++) {
	371	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	372	/* Test if the speed change finished. */
	373	if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
	374	return 0;
	375	usleep_range(100, 1000);
	376	}
	377
	378	dev_err(pp->dev, "Speed change timeout\n");
	379	return -EINVAL;
66a60f93 MV	380	}
66a60f93 MV	381
d1dc9749 LS	382	static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
	383	{
	384	struct pcie_port *pp = arg;
	385
	386	return dw_handle_msi_irq(pp);
	387	}
	388
fd5da208	389	static int imx6_pcie_establish_link(struct pcie_port *pp)
bb38919e	390	{
bb38919e	391	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
1c7fae18	392	u32 tmp;
a0427464	393	int ret;
fa33a6d8 MV	394
	395	/*
	396	* Force Gen1 operation when starting the link. In case the link is
	397	* started in Gen2 mode, there is a possibility the devices on the
	398	* bus will not be detected at all. This happens with PCIe switches.
	399	*/
	400	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	401	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	402	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	403	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	404
	405	/* Start LTSSM. */
	406	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	407	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	408
	409	ret = imx6_pcie_wait_for_link(pp);
	410	if (ret)
	411	return ret;
	412
	413	/* Allow Gen2 mode after the link is up. */
	414	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	415	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	416	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	417	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	418
	419	/*
	420	* Start Directed Speed Change so the best possible speed both link
	421	* partners support can be negotiated.
	422	*/
	423	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	424	tmp \|= PORT_LOGIC_SPEED_CHANGE;
	425	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	426
a0427464 TK	427	ret = imx6_pcie_wait_for_speed_change(pp);
	428	if (ret) {
	429	dev_err(pp->dev, "Failed to bring link up!\n");
	430	return ret;
fa33a6d8 MV	431	}
	432
	433	/* Make sure link training is finished as well! */
a0427464	434	ret = imx6_pcie_wait_for_link(pp);
fa33a6d8 MV	435	if (ret) {
fa33a6d8 MV	436	dev_err(pp->dev, "Failed to bring link up!\n");
a0427464	437	return ret;
fa33a6d8 MV	438	}
fa33a6d8 MV	439
2393f79c	440	tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
a0427464 TK	441	dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
a0427464 TK	442	return 0;
fa33a6d8 MV	443	}
	444
	445	static void imx6_pcie_host_init(struct pcie_port *pp)
	446	{
bb38919e SC	447	imx6_pcie_assert_core_reset(pp);
	448
	449	imx6_pcie_init_phy(pp);
	450
	451	imx6_pcie_deassert_core_reset(pp);
	452
	453	dw_pcie_setup_rc(pp);
	454
fd5da208	455	imx6_pcie_establish_link(pp);
d1dc9749 LS	456
	457	if (IS_ENABLED(CONFIG_PCI_MSI))
	458	dw_pcie_msi_init(pp);
bb38919e SC	459	}
	460
	461	static int imx6_pcie_link_up(struct pcie_port *pp)
	462	{
f95d3ae7 MV	463	u32 rc, debug_r0, rx_valid;
f95d3ae7 MV	464	int count = 5;
bb38919e	465
7f9f40c0	466	/*
f95d3ae7 MV	467	* Test if the PHY reports that the link is up and also that the LTSSM
	468	* training finished. There are three possible states of the link when
	469	* this code is called:
	470	* 1) The link is DOWN (unlikely)
	471	* The link didn't come up yet for some reason. This usually means
	472	* we have a real problem somewhere. Reset the PHY and exit. This
	473	* state calls for inspection of the DEBUG registers.
	474	* 2) The link is UP, but still in LTSSM training
	475	* Wait for the training to finish, which should take a very short
	476	* time. If the training does not finish, we have a problem and we
	477	* need to inspect the DEBUG registers. If the training does finish,
	478	* the link is up and operating correctly.
	479	* 3) The link is UP and no longer in LTSSM training
	480	* The link is up and operating correctly.
7f9f40c0	481	*/
f95d3ae7 MV	482	while (1) {
	483	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
	484	if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
	485	break;
	486	if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
	487	return 1;
	488	if (!count--)
	489	break;
	490	dev_dbg(pp->dev, "Link is up, but still in training\n");
	491	/*
	492	* Wait a little bit, then re-check if the link finished
	493	* the training.
	494	*/
	495	usleep_range(1000, 2000);
	496	}
bb38919e SC	497	/*
	498	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	499	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	500	* If (MAC/LTSSM.state == Recovery.RcvrLock)
	501	* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	502	* to gen2 is stuck
	503	*/
	504	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
f95d3ae7	505	debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
bb38919e	506
111feb7f	507	if (rx_valid & PCIE_PHY_RX_ASIC_OUT_VALID)
bb38919e SC	508	return 0;
bb38919e SC	509
f95d3ae7	510	if ((debug_r0 & 0x3f) != 0x0d)
bb38919e SC	511	return 0;
	512
	513	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
f95d3ae7	514	dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
bb38919e	515
982aa234	516	imx6_pcie_reset_phy(pp);
bb38919e SC	517
	518	return 0;
	519	}
	520
	521	static struct pcie_host_ops imx6_pcie_host_ops = {
	522	.link_up = imx6_pcie_link_up,
	523	.host_init = imx6_pcie_host_init,
	524	};
	525
44cb5e94	526	static int __init imx6_add_pcie_port(struct pcie_port *pp,
bb38919e SC	527	struct platform_device *pdev)
	528	{
	529	int ret;
	530
d1dc9749 LS	531	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	532	pp->msi_irq = platform_get_irq_byname(pdev, "msi");
	533	if (pp->msi_irq <= 0) {
	534	dev_err(&pdev->dev, "failed to get MSI irq\n");
	535	return -ENODEV;
	536	}
	537
	538	ret = devm_request_irq(&pdev->dev, pp->msi_irq,
d88a7ef9	539	imx6_pcie_msi_handler,
8ff0ef99 GS	540	IRQF_SHARED \| IRQF_NO_THREAD,
8ff0ef99 GS	541	"mx6-pcie-msi", pp);
d1dc9749 LS	542	if (ret) {
d1dc9749 LS	543	dev_err(&pdev->dev, "failed to request MSI irq\n");
89b2d4f1	544	return ret;
d1dc9749 LS	545	}
	546	}
	547
bb38919e SC	548	pp->root_bus_nr = -1;
	549	pp->ops = &imx6_pcie_host_ops;
	550
bb38919e SC	551	ret = dw_pcie_host_init(pp);
	552	if (ret) {
	553	dev_err(&pdev->dev, "failed to initialize host\n");
	554	return ret;
	555	}
	556
	557	return 0;
	558	}
	559
	560	static int __init imx6_pcie_probe(struct platform_device *pdev)
	561	{
	562	struct imx6_pcie *imx6_pcie;
	563	struct pcie_port *pp;
bb38919e SC	564	struct resource *dbi_base;
	565	int ret;
	566
	567	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	568	if (!imx6_pcie)
	569	return -ENOMEM;
	570
	571	pp = &imx6_pcie->pp;
	572	pp->dev = &pdev->dev;
	573
	574	/* Added for PCI abort handling */
	575	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
	576	"imprecise external abort");
	577
	578	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bb38919e	579	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
b391bf31 FE	580	if (IS_ERR(pp->dbi_base))
b391bf31 FE	581	return PTR_ERR(pp->dbi_base);
bb38919e SC	582
bb38919e SC	583	/* Fetch GPIOs */
5c5fb40d PŠ	584	imx6_pcie->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
5c5fb40d PŠ	585	GPIOD_OUT_LOW);
bb38919e	586
bb38919e	587	/* Fetch clocks */
57526136 LS	588	imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
57526136 LS	589	if (IS_ERR(imx6_pcie->pcie_phy)) {
bb38919e	590	dev_err(&pdev->dev,
57526136 LS	591	"pcie_phy clock source missing or invalid\n");
57526136 LS	592	return PTR_ERR(imx6_pcie->pcie_phy);
bb38919e SC	593	}
bb38919e SC	594
57526136 LS	595	imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
57526136 LS	596	if (IS_ERR(imx6_pcie->pcie_bus)) {
bb38919e	597	dev_err(&pdev->dev,
57526136 LS	598	"pcie_bus clock source missing or invalid\n");
57526136 LS	599	return PTR_ERR(imx6_pcie->pcie_bus);
bb38919e SC	600	}
bb38919e SC	601
57526136 LS	602	imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
57526136 LS	603	if (IS_ERR(imx6_pcie->pcie)) {
bb38919e	604	dev_err(&pdev->dev,
57526136 LS	605	"pcie clock source missing or invalid\n");
57526136 LS	606	return PTR_ERR(imx6_pcie->pcie);
bb38919e SC	607	}
	608
	609	/* Grab GPR config register range */
	610	imx6_pcie->iomuxc_gpr =
	611	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	612	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
	613	dev_err(&pdev->dev, "unable to find iomuxc registers\n");
b391bf31	614	return PTR_ERR(imx6_pcie->iomuxc_gpr);
bb38919e SC	615	}
	616
	617	ret = imx6_add_pcie_port(pp, pdev);
	618	if (ret < 0)
b391bf31	619	return ret;
bb38919e SC	620
	621	platform_set_drvdata(pdev, imx6_pcie);
	622	return 0;
bb38919e SC	623	}
bb38919e SC	624
3e3e406e LS	625	static void imx6_pcie_shutdown(struct platform_device *pdev)
	626	{
	627	struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
	628
	629	/* bring down link, so bootloader gets clean state in case of reboot */
	630	imx6_pcie_assert_core_reset(&imx6_pcie->pp);
	631	}
	632
bb38919e SC	633	static const struct of_device_id imx6_pcie_of_match[] = {
	634	{ .compatible = "fsl,imx6q-pcie", },
	635	{},
	636	};
	637	MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
	638
	639	static struct platform_driver imx6_pcie_driver = {
	640	.driver = {
	641	.name = "imx6q-pcie",
8bcadbe1	642	.of_match_table = imx6_pcie_of_match,
bb38919e	643	},
3e3e406e	644	.shutdown = imx6_pcie_shutdown,
bb38919e SC	645	};
	646
	647	/* Freescale PCIe driver does not allow module unload */
	648
	649	static int __init imx6_pcie_init(void)
	650	{
	651	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
	652	}
61da50da	653	module_init(imx6_pcie_init);
bb38919e SC	654
	655	MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
	656	MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
	657	MODULE_LICENSE("GPL v2");