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bb38919e SC |
1 | /* |
2 | * PCIe host controller driver for Freescale i.MX6 SoCs | |
3 | * | |
4 | * Copyright (C) 2013 Kosagi | |
5 | * http://www.kosagi.com | |
6 | * | |
7 | * Author: Sean Cross <xobs@kosagi.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/mfd/syscon.h> | |
19 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_gpio.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/resource.h> | |
26 | #include <linux/signal.h> | |
27 | #include <linux/types.h> | |
d1dc9749 | 28 | #include <linux/interrupt.h> |
bb38919e SC |
29 | |
30 | #include "pcie-designware.h" | |
31 | ||
32 | #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) | |
33 | ||
34 | struct imx6_pcie { | |
35 | int reset_gpio; | |
57526136 LS |
36 | struct clk *pcie_bus; |
37 | struct clk *pcie_phy; | |
38 | struct clk *pcie; | |
bb38919e SC |
39 | struct pcie_port pp; |
40 | struct regmap *iomuxc_gpr; | |
41 | void __iomem *mem_base; | |
42 | }; | |
43 | ||
fa33a6d8 MV |
44 | /* PCIe Root Complex registers (memory-mapped) */ |
45 | #define PCIE_RC_LCR 0x7c | |
46 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 | |
47 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 | |
48 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf | |
49 | ||
2393f79c BH |
50 | #define PCIE_RC_LCSR 0x80 |
51 | ||
bb38919e SC |
52 | /* PCIe Port Logic registers (memory-mapped) */ |
53 | #define PL_OFFSET 0x700 | |
3e3e406e LS |
54 | #define PCIE_PL_PFLR (PL_OFFSET + 0x08) |
55 | #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) | |
56 | #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) | |
bb38919e SC |
57 | #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) |
58 | #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) | |
7f9f40c0 MV |
59 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) |
60 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) | |
bb38919e SC |
61 | |
62 | #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) | |
63 | #define PCIE_PHY_CTRL_DATA_LOC 0 | |
64 | #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 | |
65 | #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 | |
66 | #define PCIE_PHY_CTRL_WR_LOC 18 | |
67 | #define PCIE_PHY_CTRL_RD_LOC 19 | |
68 | ||
69 | #define PCIE_PHY_STAT (PL_OFFSET + 0x110) | |
70 | #define PCIE_PHY_STAT_ACK_LOC 16 | |
71 | ||
fa33a6d8 MV |
72 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
73 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
74 | ||
bb38919e SC |
75 | /* PHY registers (not memory-mapped) */ |
76 | #define PCIE_PHY_RX_ASIC_OUT 0x100D | |
111feb7f | 77 | #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) |
bb38919e SC |
78 | |
79 | #define PHY_RX_OVRD_IN_LO 0x1005 | |
80 | #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) | |
81 | #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) | |
82 | ||
83 | static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) | |
84 | { | |
85 | u32 val; | |
86 | u32 max_iterations = 10; | |
87 | u32 wait_counter = 0; | |
88 | ||
89 | do { | |
90 | val = readl(dbi_base + PCIE_PHY_STAT); | |
91 | val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; | |
92 | wait_counter++; | |
93 | ||
94 | if (val == exp_val) | |
95 | return 0; | |
96 | ||
97 | udelay(1); | |
98 | } while (wait_counter < max_iterations); | |
99 | ||
100 | return -ETIMEDOUT; | |
101 | } | |
102 | ||
103 | static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) | |
104 | { | |
105 | u32 val; | |
106 | int ret; | |
107 | ||
108 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
109 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
110 | ||
111 | val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); | |
112 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
113 | ||
114 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
115 | if (ret) | |
116 | return ret; | |
117 | ||
118 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
119 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
120 | ||
8d1ceb52 | 121 | return pcie_phy_poll_ack(dbi_base, 0); |
bb38919e SC |
122 | } |
123 | ||
124 | /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ | |
125 | static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) | |
126 | { | |
127 | u32 val, phy_ctl; | |
128 | int ret; | |
129 | ||
130 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
131 | if (ret) | |
132 | return ret; | |
133 | ||
134 | /* assert Read signal */ | |
135 | phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; | |
136 | writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); | |
137 | ||
138 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
139 | if (ret) | |
140 | return ret; | |
141 | ||
142 | val = readl(dbi_base + PCIE_PHY_STAT); | |
143 | *data = val & 0xffff; | |
144 | ||
145 | /* deassert Read signal */ | |
146 | writel(0x00, dbi_base + PCIE_PHY_CTRL); | |
147 | ||
8d1ceb52 | 148 | return pcie_phy_poll_ack(dbi_base, 0); |
bb38919e SC |
149 | } |
150 | ||
151 | static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) | |
152 | { | |
153 | u32 var; | |
154 | int ret; | |
155 | ||
156 | /* write addr */ | |
157 | /* cap addr */ | |
158 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
159 | if (ret) | |
160 | return ret; | |
161 | ||
162 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
163 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
164 | ||
165 | /* capture data */ | |
166 | var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); | |
167 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
168 | ||
169 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
170 | if (ret) | |
171 | return ret; | |
172 | ||
173 | /* deassert cap data */ | |
174 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
175 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
176 | ||
177 | /* wait for ack de-assertion */ | |
178 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
179 | if (ret) | |
180 | return ret; | |
181 | ||
182 | /* assert wr signal */ | |
183 | var = 0x1 << PCIE_PHY_CTRL_WR_LOC; | |
184 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
185 | ||
186 | /* wait for ack */ | |
187 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
188 | if (ret) | |
189 | return ret; | |
190 | ||
191 | /* deassert wr signal */ | |
192 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
193 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
194 | ||
195 | /* wait for ack de-assertion */ | |
196 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
197 | if (ret) | |
198 | return ret; | |
199 | ||
200 | writel(0x0, dbi_base + PCIE_PHY_CTRL); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | /* Added for PCI abort handling */ | |
206 | static int imx6q_pcie_abort_handler(unsigned long addr, | |
207 | unsigned int fsr, struct pt_regs *regs) | |
208 | { | |
bb38919e SC |
209 | return 0; |
210 | } | |
211 | ||
212 | static int imx6_pcie_assert_core_reset(struct pcie_port *pp) | |
213 | { | |
214 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
3e3e406e LS |
215 | u32 val, gpr1, gpr12; |
216 | ||
217 | /* | |
218 | * If the bootloader already enabled the link we need some special | |
219 | * handling to get the core back into a state where it is safe to | |
220 | * touch it for configuration. As there is no dedicated reset signal | |
221 | * wired up for MX6QDL, we need to manually force LTSSM into "detect" | |
222 | * state before completely disabling LTSSM, which is a prerequisite | |
223 | * for core configuration. | |
224 | * | |
225 | * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong | |
226 | * indication that the bootloader activated the link. | |
227 | */ | |
228 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1); | |
229 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12); | |
230 | ||
231 | if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && | |
232 | (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { | |
233 | val = readl(pp->dbi_base + PCIE_PL_PFLR); | |
234 | val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; | |
235 | val |= PCIE_PL_PFLR_FORCE_LINK; | |
236 | writel(val, pp->dbi_base + PCIE_PL_PFLR); | |
237 | ||
238 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
239 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | |
240 | } | |
bb38919e SC |
241 | |
242 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
243 | IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); | |
bb38919e SC |
244 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
245 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); | |
246 | ||
bb38919e SC |
247 | return 0; |
248 | } | |
249 | ||
250 | static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) | |
251 | { | |
252 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
253 | int ret; | |
254 | ||
57526136 | 255 | ret = clk_prepare_enable(imx6_pcie->pcie_phy); |
bb38919e | 256 | if (ret) { |
57526136 LS |
257 | dev_err(pp->dev, "unable to enable pcie_phy clock\n"); |
258 | goto err_pcie_phy; | |
bb38919e SC |
259 | } |
260 | ||
57526136 | 261 | ret = clk_prepare_enable(imx6_pcie->pcie_bus); |
bb38919e | 262 | if (ret) { |
57526136 LS |
263 | dev_err(pp->dev, "unable to enable pcie_bus clock\n"); |
264 | goto err_pcie_bus; | |
bb38919e SC |
265 | } |
266 | ||
57526136 | 267 | ret = clk_prepare_enable(imx6_pcie->pcie); |
bb38919e | 268 | if (ret) { |
57526136 LS |
269 | dev_err(pp->dev, "unable to enable pcie clock\n"); |
270 | goto err_pcie; | |
bb38919e SC |
271 | } |
272 | ||
3fce0e88 TH |
273 | /* power up core phy and enable ref clock */ |
274 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
275 | IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); | |
a2fa6f64 RZ |
276 | /* |
277 | * the async reset input need ref clock to sync internally, | |
278 | * when the ref clock comes after reset, internal synced | |
279 | * reset time is too short, cannot meet the requirement. | |
280 | * add one ~10us delay here. | |
281 | */ | |
282 | udelay(10); | |
3fce0e88 TH |
283 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
284 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); | |
285 | ||
a2fa6f64 RZ |
286 | /* allow the clocks to stabilize */ |
287 | usleep_range(200, 500); | |
288 | ||
bc9ef770 RZ |
289 | /* Some boards don't have PCIe reset GPIO. */ |
290 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { | |
bd534e69 | 291 | gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0); |
bc9ef770 | 292 | msleep(100); |
bd534e69 | 293 | gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1); |
bc9ef770 | 294 | } |
bb38919e SC |
295 | return 0; |
296 | ||
57526136 LS |
297 | err_pcie: |
298 | clk_disable_unprepare(imx6_pcie->pcie_bus); | |
299 | err_pcie_bus: | |
300 | clk_disable_unprepare(imx6_pcie->pcie_phy); | |
301 | err_pcie_phy: | |
bb38919e SC |
302 | return ret; |
303 | ||
304 | } | |
305 | ||
306 | static void imx6_pcie_init_phy(struct pcie_port *pp) | |
307 | { | |
308 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
309 | ||
310 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
311 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | |
312 | ||
313 | /* configure constant input signal to the pcie ctrl and phy */ | |
314 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
315 | IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); | |
316 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
317 | IMX6Q_GPR12_LOS_LEVEL, 9 << 4); | |
318 | ||
319 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
320 | IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0); | |
321 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
322 | IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6); | |
323 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
324 | IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); | |
325 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
326 | IMX6Q_GPR8_TX_SWING_FULL, 127 << 18); | |
327 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
328 | IMX6Q_GPR8_TX_SWING_LOW, 127 << 25); | |
329 | } | |
330 | ||
66a60f93 MV |
331 | static int imx6_pcie_wait_for_link(struct pcie_port *pp) |
332 | { | |
6cbb247e | 333 | unsigned int retries; |
66a60f93 | 334 | |
6cbb247e BH |
335 | for (retries = 0; retries < 200; retries++) { |
336 | if (dw_pcie_link_up(pp)) | |
337 | return 0; | |
66a60f93 | 338 | usleep_range(100, 1000); |
66a60f93 MV |
339 | } |
340 | ||
6cbb247e BH |
341 | dev_err(pp->dev, "phy link never came up\n"); |
342 | dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", | |
343 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), | |
344 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); | |
345 | return -EINVAL; | |
66a60f93 MV |
346 | } |
347 | ||
a0427464 TK |
348 | static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp) |
349 | { | |
1c7fae18 | 350 | u32 tmp; |
a0427464 TK |
351 | unsigned int retries; |
352 | ||
353 | for (retries = 0; retries < 200; retries++) { | |
354 | tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
355 | /* Test if the speed change finished. */ | |
356 | if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) | |
357 | return 0; | |
358 | usleep_range(100, 1000); | |
359 | } | |
360 | ||
361 | dev_err(pp->dev, "Speed change timeout\n"); | |
362 | return -EINVAL; | |
66a60f93 MV |
363 | } |
364 | ||
d1dc9749 LS |
365 | static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg) |
366 | { | |
367 | struct pcie_port *pp = arg; | |
368 | ||
369 | return dw_handle_msi_irq(pp); | |
370 | } | |
371 | ||
fd5da208 | 372 | static int imx6_pcie_establish_link(struct pcie_port *pp) |
bb38919e | 373 | { |
bb38919e | 374 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); |
1c7fae18 | 375 | u32 tmp; |
a0427464 | 376 | int ret; |
fa33a6d8 MV |
377 | |
378 | /* | |
379 | * Force Gen1 operation when starting the link. In case the link is | |
380 | * started in Gen2 mode, there is a possibility the devices on the | |
381 | * bus will not be detected at all. This happens with PCIe switches. | |
382 | */ | |
383 | tmp = readl(pp->dbi_base + PCIE_RC_LCR); | |
384 | tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; | |
385 | tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; | |
386 | writel(tmp, pp->dbi_base + PCIE_RC_LCR); | |
387 | ||
388 | /* Start LTSSM. */ | |
389 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
390 | IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); | |
391 | ||
392 | ret = imx6_pcie_wait_for_link(pp); | |
393 | if (ret) | |
394 | return ret; | |
395 | ||
396 | /* Allow Gen2 mode after the link is up. */ | |
397 | tmp = readl(pp->dbi_base + PCIE_RC_LCR); | |
398 | tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; | |
399 | tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; | |
400 | writel(tmp, pp->dbi_base + PCIE_RC_LCR); | |
401 | ||
402 | /* | |
403 | * Start Directed Speed Change so the best possible speed both link | |
404 | * partners support can be negotiated. | |
405 | */ | |
406 | tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
407 | tmp |= PORT_LOGIC_SPEED_CHANGE; | |
408 | writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
409 | ||
a0427464 TK |
410 | ret = imx6_pcie_wait_for_speed_change(pp); |
411 | if (ret) { | |
412 | dev_err(pp->dev, "Failed to bring link up!\n"); | |
413 | return ret; | |
fa33a6d8 MV |
414 | } |
415 | ||
416 | /* Make sure link training is finished as well! */ | |
a0427464 | 417 | ret = imx6_pcie_wait_for_link(pp); |
fa33a6d8 MV |
418 | if (ret) { |
419 | dev_err(pp->dev, "Failed to bring link up!\n"); | |
a0427464 | 420 | return ret; |
fa33a6d8 MV |
421 | } |
422 | ||
2393f79c | 423 | tmp = readl(pp->dbi_base + PCIE_RC_LCSR); |
a0427464 TK |
424 | dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf); |
425 | return 0; | |
fa33a6d8 MV |
426 | } |
427 | ||
428 | static void imx6_pcie_host_init(struct pcie_port *pp) | |
429 | { | |
bb38919e SC |
430 | imx6_pcie_assert_core_reset(pp); |
431 | ||
432 | imx6_pcie_init_phy(pp); | |
433 | ||
434 | imx6_pcie_deassert_core_reset(pp); | |
435 | ||
436 | dw_pcie_setup_rc(pp); | |
437 | ||
fd5da208 | 438 | imx6_pcie_establish_link(pp); |
d1dc9749 LS |
439 | |
440 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
441 | dw_pcie_msi_init(pp); | |
bb38919e SC |
442 | } |
443 | ||
982aa234 MV |
444 | static void imx6_pcie_reset_phy(struct pcie_port *pp) |
445 | { | |
1c7fae18 | 446 | u32 tmp; |
982aa234 | 447 | |
1c7fae18 BH |
448 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp); |
449 | tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
450 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); | |
451 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp); | |
982aa234 MV |
452 | |
453 | usleep_range(2000, 3000); | |
454 | ||
1c7fae18 BH |
455 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp); |
456 | tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
982aa234 | 457 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); |
1c7fae18 | 458 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp); |
982aa234 MV |
459 | } |
460 | ||
bb38919e SC |
461 | static int imx6_pcie_link_up(struct pcie_port *pp) |
462 | { | |
f95d3ae7 MV |
463 | u32 rc, debug_r0, rx_valid; |
464 | int count = 5; | |
bb38919e | 465 | |
7f9f40c0 | 466 | /* |
f95d3ae7 MV |
467 | * Test if the PHY reports that the link is up and also that the LTSSM |
468 | * training finished. There are three possible states of the link when | |
469 | * this code is called: | |
470 | * 1) The link is DOWN (unlikely) | |
471 | * The link didn't come up yet for some reason. This usually means | |
472 | * we have a real problem somewhere. Reset the PHY and exit. This | |
473 | * state calls for inspection of the DEBUG registers. | |
474 | * 2) The link is UP, but still in LTSSM training | |
475 | * Wait for the training to finish, which should take a very short | |
476 | * time. If the training does not finish, we have a problem and we | |
477 | * need to inspect the DEBUG registers. If the training does finish, | |
478 | * the link is up and operating correctly. | |
479 | * 3) The link is UP and no longer in LTSSM training | |
480 | * The link is up and operating correctly. | |
7f9f40c0 | 481 | */ |
f95d3ae7 MV |
482 | while (1) { |
483 | rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); | |
484 | if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP)) | |
485 | break; | |
486 | if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) | |
487 | return 1; | |
488 | if (!count--) | |
489 | break; | |
490 | dev_dbg(pp->dev, "Link is up, but still in training\n"); | |
491 | /* | |
492 | * Wait a little bit, then re-check if the link finished | |
493 | * the training. | |
494 | */ | |
495 | usleep_range(1000, 2000); | |
496 | } | |
bb38919e SC |
497 | /* |
498 | * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. | |
499 | * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). | |
500 | * If (MAC/LTSSM.state == Recovery.RcvrLock) | |
501 | * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition | |
502 | * to gen2 is stuck | |
503 | */ | |
504 | pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); | |
f95d3ae7 | 505 | debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0); |
bb38919e | 506 | |
111feb7f | 507 | if (rx_valid & PCIE_PHY_RX_ASIC_OUT_VALID) |
bb38919e SC |
508 | return 0; |
509 | ||
f95d3ae7 | 510 | if ((debug_r0 & 0x3f) != 0x0d) |
bb38919e SC |
511 | return 0; |
512 | ||
513 | dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); | |
f95d3ae7 | 514 | dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc); |
bb38919e | 515 | |
982aa234 | 516 | imx6_pcie_reset_phy(pp); |
bb38919e SC |
517 | |
518 | return 0; | |
519 | } | |
520 | ||
521 | static struct pcie_host_ops imx6_pcie_host_ops = { | |
522 | .link_up = imx6_pcie_link_up, | |
523 | .host_init = imx6_pcie_host_init, | |
524 | }; | |
525 | ||
44cb5e94 | 526 | static int __init imx6_add_pcie_port(struct pcie_port *pp, |
bb38919e SC |
527 | struct platform_device *pdev) |
528 | { | |
529 | int ret; | |
530 | ||
d1dc9749 LS |
531 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
532 | pp->msi_irq = platform_get_irq_byname(pdev, "msi"); | |
533 | if (pp->msi_irq <= 0) { | |
534 | dev_err(&pdev->dev, "failed to get MSI irq\n"); | |
535 | return -ENODEV; | |
536 | } | |
537 | ||
538 | ret = devm_request_irq(&pdev->dev, pp->msi_irq, | |
d88a7ef9 JH |
539 | imx6_pcie_msi_handler, |
540 | IRQF_SHARED, "mx6-pcie-msi", pp); | |
d1dc9749 LS |
541 | if (ret) { |
542 | dev_err(&pdev->dev, "failed to request MSI irq\n"); | |
89b2d4f1 | 543 | return ret; |
d1dc9749 LS |
544 | } |
545 | } | |
546 | ||
bb38919e SC |
547 | pp->root_bus_nr = -1; |
548 | pp->ops = &imx6_pcie_host_ops; | |
549 | ||
bb38919e SC |
550 | ret = dw_pcie_host_init(pp); |
551 | if (ret) { | |
552 | dev_err(&pdev->dev, "failed to initialize host\n"); | |
553 | return ret; | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
559 | static int __init imx6_pcie_probe(struct platform_device *pdev) | |
560 | { | |
561 | struct imx6_pcie *imx6_pcie; | |
562 | struct pcie_port *pp; | |
563 | struct device_node *np = pdev->dev.of_node; | |
564 | struct resource *dbi_base; | |
565 | int ret; | |
566 | ||
567 | imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL); | |
568 | if (!imx6_pcie) | |
569 | return -ENOMEM; | |
570 | ||
571 | pp = &imx6_pcie->pp; | |
572 | pp->dev = &pdev->dev; | |
573 | ||
574 | /* Added for PCI abort handling */ | |
575 | hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, | |
576 | "imprecise external abort"); | |
577 | ||
578 | dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
bb38919e | 579 | pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); |
b391bf31 FE |
580 | if (IS_ERR(pp->dbi_base)) |
581 | return PTR_ERR(pp->dbi_base); | |
bb38919e SC |
582 | |
583 | /* Fetch GPIOs */ | |
584 | imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); | |
c28f8a1f MV |
585 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { |
586 | ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio, | |
587 | GPIOF_OUT_INIT_LOW, "PCIe reset"); | |
588 | if (ret) { | |
589 | dev_err(&pdev->dev, "unable to get reset gpio\n"); | |
590 | return ret; | |
591 | } | |
bb38919e SC |
592 | } |
593 | ||
bb38919e | 594 | /* Fetch clocks */ |
57526136 LS |
595 | imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy"); |
596 | if (IS_ERR(imx6_pcie->pcie_phy)) { | |
bb38919e | 597 | dev_err(&pdev->dev, |
57526136 LS |
598 | "pcie_phy clock source missing or invalid\n"); |
599 | return PTR_ERR(imx6_pcie->pcie_phy); | |
bb38919e SC |
600 | } |
601 | ||
57526136 LS |
602 | imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus"); |
603 | if (IS_ERR(imx6_pcie->pcie_bus)) { | |
bb38919e | 604 | dev_err(&pdev->dev, |
57526136 LS |
605 | "pcie_bus clock source missing or invalid\n"); |
606 | return PTR_ERR(imx6_pcie->pcie_bus); | |
bb38919e SC |
607 | } |
608 | ||
57526136 LS |
609 | imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie"); |
610 | if (IS_ERR(imx6_pcie->pcie)) { | |
bb38919e | 611 | dev_err(&pdev->dev, |
57526136 LS |
612 | "pcie clock source missing or invalid\n"); |
613 | return PTR_ERR(imx6_pcie->pcie); | |
bb38919e SC |
614 | } |
615 | ||
616 | /* Grab GPR config register range */ | |
617 | imx6_pcie->iomuxc_gpr = | |
618 | syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | |
619 | if (IS_ERR(imx6_pcie->iomuxc_gpr)) { | |
620 | dev_err(&pdev->dev, "unable to find iomuxc registers\n"); | |
b391bf31 | 621 | return PTR_ERR(imx6_pcie->iomuxc_gpr); |
bb38919e SC |
622 | } |
623 | ||
624 | ret = imx6_add_pcie_port(pp, pdev); | |
625 | if (ret < 0) | |
b391bf31 | 626 | return ret; |
bb38919e SC |
627 | |
628 | platform_set_drvdata(pdev, imx6_pcie); | |
629 | return 0; | |
bb38919e SC |
630 | } |
631 | ||
3e3e406e LS |
632 | static void imx6_pcie_shutdown(struct platform_device *pdev) |
633 | { | |
634 | struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); | |
635 | ||
636 | /* bring down link, so bootloader gets clean state in case of reboot */ | |
637 | imx6_pcie_assert_core_reset(&imx6_pcie->pp); | |
638 | } | |
639 | ||
bb38919e SC |
640 | static const struct of_device_id imx6_pcie_of_match[] = { |
641 | { .compatible = "fsl,imx6q-pcie", }, | |
642 | {}, | |
643 | }; | |
644 | MODULE_DEVICE_TABLE(of, imx6_pcie_of_match); | |
645 | ||
646 | static struct platform_driver imx6_pcie_driver = { | |
647 | .driver = { | |
648 | .name = "imx6q-pcie", | |
8bcadbe1 | 649 | .of_match_table = imx6_pcie_of_match, |
bb38919e | 650 | }, |
3e3e406e | 651 | .shutdown = imx6_pcie_shutdown, |
bb38919e SC |
652 | }; |
653 | ||
654 | /* Freescale PCIe driver does not allow module unload */ | |
655 | ||
656 | static int __init imx6_pcie_init(void) | |
657 | { | |
658 | return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); | |
659 | } | |
61da50da | 660 | module_init(imx6_pcie_init); |
bb38919e SC |
661 | |
662 | MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); | |
663 | MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); | |
664 | MODULE_LICENSE("GPL v2"); |