[deliverable/linux.git] / drivers / pci / host / pci-imx6.c

/*
 * PCIe host controller driver for Freescale i.MX6 SoCs
 *
 * Copyright (C) 2013 Kosagi
 *		http://www.kosagi.com
 *
 * Author: Sean Cross <xobs@kosagi.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>

#include "pcie-designware.h"

#define to_imx6_pcie(x)	container_of(x, struct imx6_pcie, pp)

struct imx6_pcie {
	int			reset_gpio;
	int			power_on_gpio;
	int			wake_up_gpio;
	int			disable_gpio;
	struct clk		*lvds_gate;
	struct clk		*sata_ref_100m;
	struct clk		*pcie_ref_125m;
	struct clk		*pcie_axi;
	struct pcie_port	pp;
	struct regmap		*iomuxc_gpr;
	void __iomem		*mem_base;
};

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)

#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
#define PCIE_PHY_CTRL_WR_LOC 18
#define PCIE_PHY_CTRL_RD_LOC 19

#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
#define PCIE_PHY_STAT_ACK_LOC 16

/* PHY registers (not memory-mapped) */
#define PCIE_PHY_RX_ASIC_OUT 0x100D

#define PHY_RX_OVRD_IN_LO 0x1005
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)

static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
{
	u32 val;
	u32 max_iterations = 10;
	u32 wait_counter = 0;

	do {
		val = readl(dbi_base + PCIE_PHY_STAT);
		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
		wait_counter++;

		if (val == exp_val)
			return 0;

		udelay(1);
	} while (wait_counter < max_iterations);

	return -ETIMEDOUT;
}

static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
{
	u32 val;
	int ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
{
	u32 val, phy_ctl;
	int ret;

	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	/* assert Read signal */
	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = readl(dbi_base + PCIE_PHY_STAT);
	*data = val & 0xffff;

	/* deassert Read signal */
	writel(0x00, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
{
	u32 var;
	int ret;

	/* write addr */
	/* cap addr */
	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* capture data */
	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	writel(var, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert cap data */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	/* assert wr signal */
	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack */
	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert wr signal */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	writel(0x0, dbi_base + PCIE_PHY_CTRL);

	return 0;
}

/*  Added for PCI abort handling */
static int imx6q_pcie_abort_handler(unsigned long addr,
		unsigned int fsr, struct pt_regs *regs)
{
	return 0;
}

static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

	gpio_set_value(imx6_pcie->reset_gpio, 0);
	msleep(100);
	gpio_set_value(imx6_pcie->reset_gpio, 1);

	return 0;
}

static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	int ret;

	if (gpio_is_valid(imx6_pcie->power_on_gpio))
		gpio_set_value(imx6_pcie->power_on_gpio, 1);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

	ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
	if (ret) {
		dev_err(pp->dev, "unable to enable sata_ref_100m\n");
		goto err_sata_ref;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
		goto err_pcie_ref;
	}

	ret = clk_prepare_enable(imx6_pcie->lvds_gate);
	if (ret) {
		dev_err(pp->dev, "unable to enable lvds_gate\n");
		goto err_lvds_gate;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_axi);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_axi\n");
		goto err_pcie_axi;
	}

	/* allow the clocks to stabilize */
	usleep_range(200, 500);

	return 0;

err_pcie_axi:
	clk_disable_unprepare(imx6_pcie->lvds_gate);
err_lvds_gate:
	clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
err_pcie_ref:
	clk_disable_unprepare(imx6_pcie->sata_ref_100m);
err_sata_ref:
	return ret;

}

static void imx6_pcie_init_phy(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);

	/* configure constant input signal to the pcie ctrl and phy */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
}

static void imx6_pcie_host_init(struct pcie_port *pp)
{
	int count = 0;
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	imx6_pcie_assert_core_reset(pp);

	imx6_pcie_init_phy(pp);

	imx6_pcie_deassert_core_reset(pp);

	dw_pcie_setup_rc(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);

	while (!dw_pcie_link_up(pp)) {
		usleep_range(100, 1000);
		count++;
		if (count >= 200) {
			dev_err(pp->dev, "phy link never came up\n");
			dev_dbg(pp->dev,
				"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
				readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
				readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
			break;
		}
	}

	return;
}

static int imx6_pcie_link_up(struct pcie_port *pp)
{
	u32 rc, ltssm, rx_valid, temp;

	/* link is debug bit 36, debug register 1 starts at bit 32 */
	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
	if (rc)
		return -EAGAIN;

	/*
	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	 * to gen2 is stuck
	 */
	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;

	if (rx_valid & 0x01)
		return 0;

	if (ltssm != 0x0d)
		return 0;

	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");

	pcie_phy_read(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, &temp);
	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
		| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, temp);

	usleep_range(2000, 3000);

	pcie_phy_read(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, &temp);
	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
		| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, temp);

	return 0;
}

static struct pcie_host_ops imx6_pcie_host_ops = {
	.link_up = imx6_pcie_link_up,
	.host_init = imx6_pcie_host_init,
};

static int imx6_add_pcie_port(struct pcie_port *pp,
			struct platform_device *pdev)
{
	int ret;

	pp->irq = platform_get_irq(pdev, 0);
	if (!pp->irq) {
		dev_err(&pdev->dev, "failed to get irq\n");
		return -ENODEV;
	}

	pp->root_bus_nr = -1;
	pp->ops = &imx6_pcie_host_ops;

	spin_lock_init(&pp->conf_lock);
	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init imx6_pcie_probe(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie;
	struct pcie_port *pp;
	struct device_node *np = pdev->dev.of_node;
	struct resource *dbi_base;
	int ret;

	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	if (!imx6_pcie)
		return -ENOMEM;

	pp = &imx6_pcie->pp;
	pp->dev = &pdev->dev;

	/* Added for PCI abort handling */
	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
		"imprecise external abort");

	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
	if (IS_ERR(pp->dbi_base)) {
		ret = PTR_ERR(pp->dbi_base);
		goto err;
	}

	/* Fetch GPIOs */
	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
	if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
		dev_err(&pdev->dev, "no reset-gpio defined\n");
		ret = -ENODEV;
	}
	ret = devm_gpio_request_one(&pdev->dev,
				imx6_pcie->reset_gpio,
				GPIOF_OUT_INIT_LOW,
				"PCIe reset");
	if (ret) {
		dev_err(&pdev->dev, "unable to get reset gpio\n");
		goto err;
	}

	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
	if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->power_on_gpio,
					GPIOF_OUT_INIT_LOW,
					"PCIe power enable");
		if (ret) {
			dev_err(&pdev->dev, "unable to get power-on gpio\n");
			goto err;
		}
	}

	imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
	if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->wake_up_gpio,
					GPIOF_IN,
					"PCIe wake up");
		if (ret) {
			dev_err(&pdev->dev, "unable to get wake-up gpio\n");
			goto err;
		}
	}

	imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
	if (gpio_is_valid(imx6_pcie->disable_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->disable_gpio,
					GPIOF_OUT_INIT_HIGH,
					"PCIe disable endpoint");
		if (ret) {
			dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
			goto err;
		}
	}

	/* Fetch clocks */
	imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
	if (IS_ERR(imx6_pcie->lvds_gate)) {
		dev_err(&pdev->dev,
			"lvds_gate clock select missing or invalid\n");
		ret = PTR_ERR(imx6_pcie->lvds_gate);
		goto err;
	}

	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
	if (IS_ERR(imx6_pcie->sata_ref_100m)) {
		dev_err(&pdev->dev,
			"sata_ref_100m clock source missing or invalid\n");
		ret = PTR_ERR(imx6_pcie->sata_ref_100m);
		goto err;
	}

	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
		dev_err(&pdev->dev,
			"pcie_ref_125m clock source missing or invalid\n");
		ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
		goto err;
	}

	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
	if (IS_ERR(imx6_pcie->pcie_axi)) {
		dev_err(&pdev->dev,
			"pcie_axi clock source missing or invalid\n");
		ret = PTR_ERR(imx6_pcie->pcie_axi);
		goto err;
	}

	/* Grab GPR config register range */
	imx6_pcie->iomuxc_gpr =
		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
		ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
		goto err;
	}

	ret = imx6_add_pcie_port(pp, pdev);
	if (ret < 0)
		goto err;

	platform_set_drvdata(pdev, imx6_pcie);
	return 0;

err:
	return ret;
}

static const struct of_device_id imx6_pcie_of_match[] = {
	{ .compatible = "fsl,imx6q-pcie", },
	{},
};
MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

static struct platform_driver imx6_pcie_driver = {
	.driver = {
		.name	= "imx6q-pcie",
		.owner	= THIS_MODULE,
		.of_match_table = imx6_pcie_of_match,
	},
};

/* Freescale PCIe driver does not allow module unload */

static int __init imx6_pcie_init(void)
{
	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
}
fs_initcall(imx6_pcie_init);

MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bb38919e SC	1	/*
	2	* PCIe host controller driver for Freescale i.MX6 SoCs
	3	*
	4	* Copyright (C) 2013 Kosagi
	5	* http://www.kosagi.com
	6	*
	7	* Author: Sean Cross <xobs@kosagi.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/gpio.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	20	#include <linux/module.h>
	21	#include <linux/of_gpio.h>
	22	#include <linux/pci.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/resource.h>
	26	#include <linux/signal.h>
	27	#include <linux/types.h>
	28
	29	#include "pcie-designware.h"
	30
	31	#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
	32
	33	struct imx6_pcie {
	34	int reset_gpio;
	35	int power_on_gpio;
	36	int wake_up_gpio;
	37	int disable_gpio;
	38	struct clk *lvds_gate;
	39	struct clk *sata_ref_100m;
	40	struct clk *pcie_ref_125m;
	41	struct clk *pcie_axi;
	42	struct pcie_port pp;
	43	struct regmap *iomuxc_gpr;
	44	void __iomem *mem_base;
	45	};
	46
	47	/* PCIe Port Logic registers (memory-mapped) */
	48	#define PL_OFFSET 0x700
	49	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
	50	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
	51
	52	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
	53	#define PCIE_PHY_CTRL_DATA_LOC 0
	54	#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
	55	#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
	56	#define PCIE_PHY_CTRL_WR_LOC 18
	57	#define PCIE_PHY_CTRL_RD_LOC 19
	58
	59	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
	60	#define PCIE_PHY_STAT_ACK_LOC 16
	61
	62	/* PHY registers (not memory-mapped) */
	63	#define PCIE_PHY_RX_ASIC_OUT 0x100D
	64
65	#define PHY_RX_OVRD_IN_LO 0x1005
66	#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
67	#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
68
69	static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
70	{
71	u32 val;
72	u32 max_iterations = 10;
73	u32 wait_counter = 0;
74
75	do {
76	val = readl(dbi_base + PCIE_PHY_STAT);
77	val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
78	wait_counter++;
79
80	if (val == exp_val)
81	return 0;
82
83	udelay(1);
84	} while (wait_counter < max_iterations);
85
86	return -ETIMEDOUT;
87	}
88
89	static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
90	{
91	u32 val;
92	int ret;
93
94	val = addr << PCIE_PHY_CTRL_DATA_LOC;
95	writel(val, dbi_base + PCIE_PHY_CTRL);
96
97	val \|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
98	writel(val, dbi_base + PCIE_PHY_CTRL);
99
100	ret = pcie_phy_poll_ack(dbi_base, 1);
101	if (ret)
102	return ret;
103
104	val = addr << PCIE_PHY_CTRL_DATA_LOC;
105	writel(val, dbi_base + PCIE_PHY_CTRL);
106
107	ret = pcie_phy_poll_ack(dbi_base, 0);
108	if (ret)
109	return ret;
110
111	return 0;
112	}
113
114	/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
115	static int pcie_phy_read(void __iomem dbi_base, int addr , int data)
116	{
117	u32 val, phy_ctl;
118	int ret;
119
120	ret = pcie_phy_wait_ack(dbi_base, addr);
121	if (ret)
122	return ret;
123
124	/* assert Read signal */
125	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
126	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
127
128	ret = pcie_phy_poll_ack(dbi_base, 1);
129	if (ret)
130	return ret;
131
132	val = readl(dbi_base + PCIE_PHY_STAT);
133	*data = val & 0xffff;
134
135	/* deassert Read signal */
136	writel(0x00, dbi_base + PCIE_PHY_CTRL);
137
138	ret = pcie_phy_poll_ack(dbi_base, 0);
139	if (ret)
140	return ret;
141
142	return 0;
143	}
144
145	static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
146	{
147	u32 var;
148	int ret;
149
150	/* write addr */
151	/* cap addr */
152	ret = pcie_phy_wait_ack(dbi_base, addr);
153	if (ret)
154	return ret;
155
156	var = data << PCIE_PHY_CTRL_DATA_LOC;
157	writel(var, dbi_base + PCIE_PHY_CTRL);
158
159	/* capture data */
160	var \|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
161	writel(var, dbi_base + PCIE_PHY_CTRL);
162
163	ret = pcie_phy_poll_ack(dbi_base, 1);
164	if (ret)
165	return ret;
166
167	/* deassert cap data */
168	var = data << PCIE_PHY_CTRL_DATA_LOC;
169	writel(var, dbi_base + PCIE_PHY_CTRL);
170
171	/* wait for ack de-assertion */
172	ret = pcie_phy_poll_ack(dbi_base, 0);
173	if (ret)
174	return ret;
175
176	/* assert wr signal */
177	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
178	writel(var, dbi_base + PCIE_PHY_CTRL);
179
180	/* wait for ack */
181	ret = pcie_phy_poll_ack(dbi_base, 1);
182	if (ret)
183	return ret;
184
185	/* deassert wr signal */
186	var = data << PCIE_PHY_CTRL_DATA_LOC;
187	writel(var, dbi_base + PCIE_PHY_CTRL);
188
189	/* wait for ack de-assertion */
190	ret = pcie_phy_poll_ack(dbi_base, 0);
191	if (ret)
192	return ret;
193
194	writel(0x0, dbi_base + PCIE_PHY_CTRL);
195
196	return 0;
197	}
198
199	/* Added for PCI abort handling */
200	static int imx6q_pcie_abort_handler(unsigned long addr,
201	unsigned int fsr, struct pt_regs *regs)
202	{
bb38919e SC	203	return 0;
	204	}
	205
	206	static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
	207	{
	208	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	209
	210	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	211	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	212	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	213	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	214	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	215	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
	216
	217	gpio_set_value(imx6_pcie->reset_gpio, 0);
	218	msleep(100);
	219	gpio_set_value(imx6_pcie->reset_gpio, 1);
	220
	221	return 0;
	222	}
	223
	224	static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
	225	{
	226	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	227	int ret;
	228
	229	if (gpio_is_valid(imx6_pcie->power_on_gpio))
	230	gpio_set_value(imx6_pcie->power_on_gpio, 1);
	231
	232	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	233	IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	234	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	235	IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
	236
	237	ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
	238	if (ret) {
	239	dev_err(pp->dev, "unable to enable sata_ref_100m\n");
	240	goto err_sata_ref;
	241	}
	242
	243	ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
	244	if (ret) {
	245	dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
	246	goto err_pcie_ref;
	247	}
	248
	249	ret = clk_prepare_enable(imx6_pcie->lvds_gate);
	250	if (ret) {
	251	dev_err(pp->dev, "unable to enable lvds_gate\n");
	252	goto err_lvds_gate;
	253	}
	254
	255	ret = clk_prepare_enable(imx6_pcie->pcie_axi);
	256	if (ret) {
	257	dev_err(pp->dev, "unable to enable pcie_axi\n");
	258	goto err_pcie_axi;
	259	}
	260
	261	/* allow the clocks to stabilize */
	262	usleep_range(200, 500);
	263
	264	return 0;
	265
	266	err_pcie_axi:
267	clk_disable_unprepare(imx6_pcie->lvds_gate);
268	err_lvds_gate:
269	clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
270	err_pcie_ref:
271	clk_disable_unprepare(imx6_pcie->sata_ref_100m);
272	err_sata_ref:
273	return ret;
274
275	}
276
277	static void imx6_pcie_init_phy(struct pcie_port *pp)
278	{
279	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
280
281	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
282	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
283
284	/* configure constant input signal to the pcie ctrl and phy */
285	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
286	IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
287	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
288	IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
289
290	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
291	IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
292	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
293	IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
294	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
295	IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
296	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
297	IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
298	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
299	IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
300	}
301
302	static void imx6_pcie_host_init(struct pcie_port *pp)
303	{
304	int count = 0;
305	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
306
307	imx6_pcie_assert_core_reset(pp);
308
309	imx6_pcie_init_phy(pp);
310
311	imx6_pcie_deassert_core_reset(pp);
312
313	dw_pcie_setup_rc(pp);
314
315	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
316	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
317
318	while (!dw_pcie_link_up(pp)) {
319	usleep_range(100, 1000);
320	count++;
017f10e1	321	if (count >= 200) {
bb38919e SC	322	dev_err(pp->dev, "phy link never came up\n");
	323	dev_dbg(pp->dev,
	324	"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	325	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
	326	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	327	break;
	328	}
	329	}
	330
	331	return;
	332	}
	333
	334	static int imx6_pcie_link_up(struct pcie_port *pp)
	335	{
	336	u32 rc, ltssm, rx_valid, temp;
	337
	338	/* link is debug bit 36, debug register 1 starts at bit 32 */
	339	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
	340	if (rc)
	341	return -EAGAIN;
	342
	343	/*
	344	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	345	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	346	* If (MAC/LTSSM.state == Recovery.RcvrLock)
	347	* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	348	* to gen2 is stuck
	349	*/
	350	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	351	ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
	352
	353	if (rx_valid & 0x01)
	354	return 0;
	355
	356	if (ltssm != 0x0d)
	357	return 0;
	358
	359	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
	360
	361	pcie_phy_read(pp->dbi_base,
	362	PHY_RX_OVRD_IN_LO, &temp);
	363	temp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
	364	\| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	365	pcie_phy_write(pp->dbi_base,
	366	PHY_RX_OVRD_IN_LO, temp);
	367
	368	usleep_range(2000, 3000);
	369
	370	pcie_phy_read(pp->dbi_base,
	371	PHY_RX_OVRD_IN_LO, &temp);
	372	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
	373	\| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	374	pcie_phy_write(pp->dbi_base,
	375	PHY_RX_OVRD_IN_LO, temp);
	376
	377	return 0;
	378	}
	379
	380	static struct pcie_host_ops imx6_pcie_host_ops = {
	381	.link_up = imx6_pcie_link_up,
	382	.host_init = imx6_pcie_host_init,
	383	};
	384
	385	static int imx6_add_pcie_port(struct pcie_port *pp,
386	struct platform_device *pdev)
387	{
388	int ret;
389
390	pp->irq = platform_get_irq(pdev, 0);
391	if (!pp->irq) {
392	dev_err(&pdev->dev, "failed to get irq\n");
393	return -ENODEV;
394	}
395
396	pp->root_bus_nr = -1;
397	pp->ops = &imx6_pcie_host_ops;
398
399	spin_lock_init(&pp->conf_lock);
400	ret = dw_pcie_host_init(pp);
401	if (ret) {
402	dev_err(&pdev->dev, "failed to initialize host\n");
403	return ret;
404	}
405
406	return 0;
407	}
408
409	static int __init imx6_pcie_probe(struct platform_device *pdev)
410	{
411	struct imx6_pcie *imx6_pcie;
412	struct pcie_port *pp;
413	struct device_node *np = pdev->dev.of_node;
414	struct resource *dbi_base;
415	int ret;
416
417	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
418	if (!imx6_pcie)
419	return -ENOMEM;
420
421	pp = &imx6_pcie->pp;
422	pp->dev = &pdev->dev;
423
424	/* Added for PCI abort handling */
425	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
426	"imprecise external abort");
427
428	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bb38919e SC	429	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
bb38919e SC	430	if (IS_ERR(pp->dbi_base)) {
bb38919e SC	431	ret = PTR_ERR(pp->dbi_base);
	432	goto err;
	433	}
	434
	435	/* Fetch GPIOs */
	436	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
	437	if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
	438	dev_err(&pdev->dev, "no reset-gpio defined\n");
	439	ret = -ENODEV;
	440	}
	441	ret = devm_gpio_request_one(&pdev->dev,
	442	imx6_pcie->reset_gpio,
	443	GPIOF_OUT_INIT_LOW,
	444	"PCIe reset");
	445	if (ret) {
	446	dev_err(&pdev->dev, "unable to get reset gpio\n");
	447	goto err;
	448	}
	449
	450	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
	451	if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
	452	ret = devm_gpio_request_one(&pdev->dev,
	453	imx6_pcie->power_on_gpio,
	454	GPIOF_OUT_INIT_LOW,
	455	"PCIe power enable");
	456	if (ret) {
	457	dev_err(&pdev->dev, "unable to get power-on gpio\n");
	458	goto err;
	459	}
	460	}
	461
	462	imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
	463	if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
	464	ret = devm_gpio_request_one(&pdev->dev,
	465	imx6_pcie->wake_up_gpio,
	466	GPIOF_IN,
	467	"PCIe wake up");
	468	if (ret) {
	469	dev_err(&pdev->dev, "unable to get wake-up gpio\n");
	470	goto err;
	471	}
	472	}
	473
	474	imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
	475	if (gpio_is_valid(imx6_pcie->disable_gpio)) {
	476	ret = devm_gpio_request_one(&pdev->dev,
	477	imx6_pcie->disable_gpio,
	478	GPIOF_OUT_INIT_HIGH,
	479	"PCIe disable endpoint");
	480	if (ret) {
	481	dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
	482	goto err;
	483	}
	484	}
	485
	486	/* Fetch clocks */
	487	imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
	488	if (IS_ERR(imx6_pcie->lvds_gate)) {
	489	dev_err(&pdev->dev,
	490	"lvds_gate clock select missing or invalid\n");
	491	ret = PTR_ERR(imx6_pcie->lvds_gate);
	492	goto err;
	493	}
	494
495	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
496	if (IS_ERR(imx6_pcie->sata_ref_100m)) {
497	dev_err(&pdev->dev,
498	"sata_ref_100m clock source missing or invalid\n");
499	ret = PTR_ERR(imx6_pcie->sata_ref_100m);
500	goto err;
501	}
502
503	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
504	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
505	dev_err(&pdev->dev,
506	"pcie_ref_125m clock source missing or invalid\n");
507	ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
508	goto err;
509	}
510
511	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
512	if (IS_ERR(imx6_pcie->pcie_axi)) {
513	dev_err(&pdev->dev,
514	"pcie_axi clock source missing or invalid\n");
515	ret = PTR_ERR(imx6_pcie->pcie_axi);
516	goto err;
517	}
518
519	/* Grab GPR config register range */
520	imx6_pcie->iomuxc_gpr =
521	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
522	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
523	dev_err(&pdev->dev, "unable to find iomuxc registers\n");
524	ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
525	goto err;
526	}
527
528	ret = imx6_add_pcie_port(pp, pdev);
529	if (ret < 0)
530	goto err;
531
532	platform_set_drvdata(pdev, imx6_pcie);
533	return 0;
534
535	err:
536	return ret;
537	}
538
539	static const struct of_device_id imx6_pcie_of_match[] = {
540	{ .compatible = "fsl,imx6q-pcie", },
541	{},
542	};
543	MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
544
545	static struct platform_driver imx6_pcie_driver = {
546	.driver = {
547	.name = "imx6q-pcie",
548	.owner = THIS_MODULE,
8bcadbe1	549	.of_match_table = imx6_pcie_of_match,
bb38919e SC	550	},
	551	};
	552
	553	/* Freescale PCIe driver does not allow module unload */
	554
	555	static int __init imx6_pcie_init(void)
	556	{
	557	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
	558	}
f216f57f	559	fs_initcall(imx6_pcie_init);
bb38919e SC	560
	561	MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
	562	MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
	563	MODULE_LICENSE("GPL v2");