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62d0ff83 ML |
1 | /* |
2 | * PCIe host controller driver for Freescale Layerscape SoCs | |
3 | * | |
4 | * Copyright (C) 2014 Freescale Semiconductor. | |
5 | * | |
5192ec7b | 6 | * Author: Minghuan Lian <Minghuan.Lian@freescale.com> |
62d0ff83 ML |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
62d0ff83 ML |
14 | #include <linux/interrupt.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/of_pci.h> | |
17 | #include <linux/of_platform.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/resource.h> | |
23 | #include <linux/mfd/syscon.h> | |
24 | #include <linux/regmap.h> | |
25 | ||
26 | #include "pcie-designware.h" | |
27 | ||
28 | /* PEX1/2 Misc Ports Status Register */ | |
29 | #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) | |
30 | #define LTSSM_STATE_SHIFT 20 | |
31 | #define LTSSM_STATE_MASK 0x3f | |
32 | #define LTSSM_PCIE_L0 0x11 /* L0 state */ | |
33 | ||
5192ec7b ML |
34 | /* PEX Internal Configuration Registers */ |
35 | #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ | |
36 | #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ | |
37 | ||
38 | /* PEX LUT registers */ | |
39 | #define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ | |
62d0ff83 | 40 | |
d6463345 | 41 | struct ls_pcie_drvdata { |
5192ec7b ML |
42 | u32 lut_offset; |
43 | u32 ltssm_shift; | |
d6463345 ML |
44 | struct pcie_host_ops *ops; |
45 | }; | |
46 | ||
62d0ff83 | 47 | struct ls_pcie { |
62d0ff83 | 48 | void __iomem *dbi; |
5192ec7b | 49 | void __iomem *lut; |
62d0ff83 ML |
50 | struct regmap *scfg; |
51 | struct pcie_port pp; | |
d6463345 | 52 | const struct ls_pcie_drvdata *drvdata; |
62d0ff83 | 53 | int index; |
62d0ff83 ML |
54 | }; |
55 | ||
56 | #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) | |
57 | ||
7af4ce35 ML |
58 | static bool ls_pcie_is_bridge(struct ls_pcie *pcie) |
59 | { | |
60 | u32 header_type; | |
61 | ||
62 | header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE); | |
63 | header_type &= 0x7f; | |
64 | ||
65 | return header_type == PCI_HEADER_TYPE_BRIDGE; | |
66 | } | |
67 | ||
5192ec7b ML |
68 | /* Clear multi-function bit */ |
69 | static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) | |
70 | { | |
71 | iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); | |
72 | } | |
73 | ||
74 | /* Fix class value */ | |
75 | static void ls_pcie_fix_class(struct ls_pcie *pcie) | |
76 | { | |
77 | iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); | |
78 | } | |
79 | ||
d6463345 | 80 | static int ls1021_pcie_link_up(struct pcie_port *pp) |
62d0ff83 ML |
81 | { |
82 | u32 state; | |
83 | struct ls_pcie *pcie = to_ls_pcie(pp); | |
84 | ||
d6463345 ML |
85 | if (!pcie->scfg) |
86 | return 0; | |
87 | ||
62d0ff83 ML |
88 | regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); |
89 | state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; | |
90 | ||
91 | if (state < LTSSM_PCIE_L0) | |
92 | return 0; | |
93 | ||
94 | return 1; | |
95 | } | |
96 | ||
d6463345 | 97 | static void ls1021_pcie_host_init(struct pcie_port *pp) |
1d3f9bac BH |
98 | { |
99 | struct ls_pcie *pcie = to_ls_pcie(pp); | |
d6463345 ML |
100 | u32 val, index[2]; |
101 | ||
102 | pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, | |
103 | "fsl,pcie-scfg"); | |
104 | if (IS_ERR(pcie->scfg)) { | |
105 | dev_err(pp->dev, "No syscfg phandle specified\n"); | |
106 | pcie->scfg = NULL; | |
107 | return; | |
108 | } | |
109 | ||
110 | if (of_property_read_u32_array(pp->dev->of_node, | |
111 | "fsl,pcie-scfg", index, 2)) { | |
112 | pcie->scfg = NULL; | |
113 | return; | |
114 | } | |
115 | pcie->index = index[1]; | |
1d3f9bac BH |
116 | |
117 | dw_pcie_setup_rc(pp); | |
1d3f9bac | 118 | |
62d0ff83 ML |
119 | /* |
120 | * LS1021A Workaround for internal TKT228622 | |
121 | * to fix the INTx hang issue | |
122 | */ | |
123 | val = ioread32(pcie->dbi + PCIE_STRFMR1); | |
124 | val &= 0xffff; | |
125 | iowrite32(val, pcie->dbi + PCIE_STRFMR1); | |
126 | } | |
127 | ||
5192ec7b ML |
128 | static int ls_pcie_link_up(struct pcie_port *pp) |
129 | { | |
130 | struct ls_pcie *pcie = to_ls_pcie(pp); | |
131 | u32 state; | |
132 | ||
133 | state = (ioread32(pcie->lut + PCIE_LUT_DBG) >> | |
134 | pcie->drvdata->ltssm_shift) & | |
135 | LTSSM_STATE_MASK; | |
136 | ||
137 | if (state < LTSSM_PCIE_L0) | |
138 | return 0; | |
139 | ||
140 | return 1; | |
141 | } | |
142 | ||
143 | static void ls_pcie_host_init(struct pcie_port *pp) | |
144 | { | |
145 | struct ls_pcie *pcie = to_ls_pcie(pp); | |
146 | ||
147 | iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); | |
148 | ls_pcie_fix_class(pcie); | |
149 | ls_pcie_clear_multifunction(pcie); | |
150 | iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); | |
151 | } | |
152 | ||
bd33b87a ML |
153 | static int ls_pcie_msi_host_init(struct pcie_port *pp, |
154 | struct msi_controller *chip) | |
155 | { | |
156 | struct device_node *msi_node; | |
157 | struct device_node *np = pp->dev->of_node; | |
158 | ||
159 | /* | |
160 | * The MSI domain is set by the generic of_msi_configure(). This | |
161 | * .msi_host_init() function keeps us from doing the default MSI | |
162 | * domain setup in dw_pcie_host_init() and also enforces the | |
163 | * requirement that "msi-parent" exists. | |
164 | */ | |
165 | msi_node = of_parse_phandle(np, "msi-parent", 0); | |
166 | if (!msi_node) { | |
167 | dev_err(pp->dev, "failed to find msi-parent\n"); | |
168 | return -EINVAL; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
d6463345 ML |
174 | static struct pcie_host_ops ls1021_pcie_host_ops = { |
175 | .link_up = ls1021_pcie_link_up, | |
176 | .host_init = ls1021_pcie_host_init, | |
bd33b87a | 177 | .msi_host_init = ls_pcie_msi_host_init, |
d6463345 ML |
178 | }; |
179 | ||
5192ec7b ML |
180 | static struct pcie_host_ops ls_pcie_host_ops = { |
181 | .link_up = ls_pcie_link_up, | |
182 | .host_init = ls_pcie_host_init, | |
bd33b87a | 183 | .msi_host_init = ls_pcie_msi_host_init, |
5192ec7b ML |
184 | }; |
185 | ||
d6463345 ML |
186 | static struct ls_pcie_drvdata ls1021_drvdata = { |
187 | .ops = &ls1021_pcie_host_ops, | |
62d0ff83 ML |
188 | }; |
189 | ||
5192ec7b ML |
190 | static struct ls_pcie_drvdata ls1043_drvdata = { |
191 | .lut_offset = 0x10000, | |
192 | .ltssm_shift = 24, | |
193 | .ops = &ls_pcie_host_ops, | |
194 | }; | |
195 | ||
196 | static struct ls_pcie_drvdata ls2080_drvdata = { | |
197 | .lut_offset = 0x80000, | |
198 | .ltssm_shift = 0, | |
199 | .ops = &ls_pcie_host_ops, | |
200 | }; | |
201 | ||
d6463345 ML |
202 | static const struct of_device_id ls_pcie_of_match[] = { |
203 | { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, | |
5192ec7b ML |
204 | { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, |
205 | { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, | |
d6463345 ML |
206 | { }, |
207 | }; | |
208 | MODULE_DEVICE_TABLE(of, ls_pcie_of_match); | |
209 | ||
a167fb73 ML |
210 | static int __init ls_add_pcie_port(struct pcie_port *pp, |
211 | struct platform_device *pdev) | |
62d0ff83 | 212 | { |
62d0ff83 | 213 | int ret; |
a167fb73 | 214 | struct ls_pcie *pcie = to_ls_pcie(pp); |
62d0ff83 | 215 | |
a167fb73 | 216 | pp->dev = &pdev->dev; |
62d0ff83 | 217 | pp->dbi_base = pcie->dbi; |
d6463345 | 218 | pp->ops = pcie->drvdata->ops; |
62d0ff83 ML |
219 | |
220 | ret = dw_pcie_host_init(pp); | |
221 | if (ret) { | |
222 | dev_err(pp->dev, "failed to initialize host\n"); | |
223 | return ret; | |
224 | } | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | static int __init ls_pcie_probe(struct platform_device *pdev) | |
230 | { | |
d6463345 | 231 | const struct of_device_id *match; |
62d0ff83 ML |
232 | struct ls_pcie *pcie; |
233 | struct resource *dbi_base; | |
62d0ff83 ML |
234 | int ret; |
235 | ||
d6463345 ML |
236 | match = of_match_device(ls_pcie_of_match, &pdev->dev); |
237 | if (!match) | |
238 | return -ENODEV; | |
239 | ||
62d0ff83 ML |
240 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); |
241 | if (!pcie) | |
242 | return -ENOMEM; | |
243 | ||
62d0ff83 | 244 | dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); |
62d0ff83 | 245 | pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); |
e3dc17a5 BH |
246 | if (IS_ERR(pcie->dbi)) { |
247 | dev_err(&pdev->dev, "missing *regs* space\n"); | |
62d0ff83 | 248 | return PTR_ERR(pcie->dbi); |
e3dc17a5 | 249 | } |
62d0ff83 | 250 | |
d6463345 | 251 | pcie->drvdata = match->data; |
5192ec7b | 252 | pcie->lut = pcie->dbi + pcie->drvdata->lut_offset; |
62d0ff83 | 253 | |
7af4ce35 ML |
254 | if (!ls_pcie_is_bridge(pcie)) |
255 | return -ENODEV; | |
256 | ||
a167fb73 | 257 | ret = ls_add_pcie_port(&pcie->pp, pdev); |
62d0ff83 ML |
258 | if (ret < 0) |
259 | return ret; | |
260 | ||
261 | platform_set_drvdata(pdev, pcie); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
62d0ff83 ML |
266 | static struct platform_driver ls_pcie_driver = { |
267 | .driver = { | |
268 | .name = "layerscape-pcie", | |
62d0ff83 ML |
269 | .of_match_table = ls_pcie_of_match, |
270 | }, | |
271 | }; | |
272 | ||
273 | module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe); | |
274 | ||
275 | MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>"); | |
276 | MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver"); | |
277 | MODULE_LICENSE("GPL v2"); |