Commit | Line | Data |
---|---|---|
45361a4f TP |
1 | /* |
2 | * PCIe driver for Marvell Armada 370 and Armada XP SoCs | |
3 | * | |
4 | * This file is licensed under the terms of the GNU General Public | |
5 | * License version 2. This program is licensed "as is" without any | |
6 | * warranty of any kind, whether express or implied. | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/mbus.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/of_address.h> | |
17 | #include <linux/of_pci.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/of_platform.h> | |
20 | ||
21 | /* | |
22 | * PCIe unit register offsets. | |
23 | */ | |
24 | #define PCIE_DEV_ID_OFF 0x0000 | |
25 | #define PCIE_CMD_OFF 0x0004 | |
26 | #define PCIE_DEV_REV_OFF 0x0008 | |
27 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | |
28 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | |
29 | #define PCIE_HEADER_LOG_4_OFF 0x0128 | |
30 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) | |
31 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | |
32 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | |
33 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | |
34 | #define PCIE_WIN5_CTRL_OFF 0x1880 | |
35 | #define PCIE_WIN5_BASE_OFF 0x1884 | |
36 | #define PCIE_WIN5_REMAP_OFF 0x188c | |
37 | #define PCIE_CONF_ADDR_OFF 0x18f8 | |
38 | #define PCIE_CONF_ADDR_EN 0x80000000 | |
39 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) | |
40 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | |
41 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | |
42 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) | |
43 | #define PCIE_CONF_ADDR(bus, devfn, where) \ | |
44 | (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ | |
45 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ | |
46 | PCIE_CONF_ADDR_EN) | |
47 | #define PCIE_CONF_DATA_OFF 0x18fc | |
48 | #define PCIE_MASK_OFF 0x1910 | |
49 | #define PCIE_MASK_ENABLE_INTS 0x0f000000 | |
50 | #define PCIE_CTRL_OFF 0x1a00 | |
51 | #define PCIE_CTRL_X1_MODE 0x0001 | |
52 | #define PCIE_STAT_OFF 0x1a04 | |
53 | #define PCIE_STAT_BUS 0xff00 | |
f4ac9901 | 54 | #define PCIE_STAT_DEV 0x1f0000 |
45361a4f TP |
55 | #define PCIE_STAT_LINK_DOWN BIT(0) |
56 | #define PCIE_DEBUG_CTRL 0x1a60 | |
57 | #define PCIE_DEBUG_SOFT_RESET BIT(20) | |
58 | ||
59 | /* | |
60 | * This product ID is registered by Marvell, and used when the Marvell | |
61 | * SoC is not the root complex, but an endpoint on the PCIe bus. It is | |
62 | * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI | |
63 | * bridge. | |
64 | */ | |
65 | #define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846 | |
66 | ||
67 | /* PCI configuration space of a PCI-to-PCI bridge */ | |
68 | struct mvebu_sw_pci_bridge { | |
69 | u16 vendor; | |
70 | u16 device; | |
71 | u16 command; | |
45361a4f TP |
72 | u16 class; |
73 | u8 interface; | |
74 | u8 revision; | |
75 | u8 bist; | |
76 | u8 header_type; | |
77 | u8 latency_timer; | |
78 | u8 cache_line_size; | |
79 | u32 bar[2]; | |
80 | u8 primary_bus; | |
81 | u8 secondary_bus; | |
82 | u8 subordinate_bus; | |
83 | u8 secondary_latency_timer; | |
84 | u8 iobase; | |
85 | u8 iolimit; | |
86 | u16 secondary_status; | |
87 | u16 membase; | |
88 | u16 memlimit; | |
45361a4f TP |
89 | u16 iobaseupper; |
90 | u16 iolimitupper; | |
91 | u8 cappointer; | |
92 | u8 reserved1; | |
93 | u16 reserved2; | |
94 | u32 romaddr; | |
95 | u8 intline; | |
96 | u8 intpin; | |
97 | u16 bridgectrl; | |
98 | }; | |
99 | ||
100 | struct mvebu_pcie_port; | |
101 | ||
102 | /* Structure representing all PCIe interfaces */ | |
103 | struct mvebu_pcie { | |
104 | struct platform_device *pdev; | |
105 | struct mvebu_pcie_port *ports; | |
106 | struct resource io; | |
107 | struct resource realio; | |
108 | struct resource mem; | |
109 | struct resource busn; | |
110 | int nports; | |
111 | }; | |
112 | ||
113 | /* Structure representing one PCIe interface */ | |
114 | struct mvebu_pcie_port { | |
115 | char *name; | |
116 | void __iomem *base; | |
117 | spinlock_t conf_lock; | |
118 | int haslink; | |
119 | u32 port; | |
120 | u32 lane; | |
121 | int devfn; | |
122 | struct clk *clk; | |
123 | struct mvebu_sw_pci_bridge bridge; | |
124 | struct device_node *dn; | |
125 | struct mvebu_pcie *pcie; | |
126 | phys_addr_t memwin_base; | |
127 | size_t memwin_size; | |
128 | phys_addr_t iowin_base; | |
129 | size_t iowin_size; | |
130 | }; | |
131 | ||
132 | static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) | |
133 | { | |
134 | return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); | |
135 | } | |
136 | ||
137 | static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) | |
138 | { | |
139 | u32 stat; | |
140 | ||
141 | stat = readl(port->base + PCIE_STAT_OFF); | |
142 | stat &= ~PCIE_STAT_BUS; | |
143 | stat |= nr << 8; | |
144 | writel(stat, port->base + PCIE_STAT_OFF); | |
145 | } | |
146 | ||
f4ac9901 TP |
147 | static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) |
148 | { | |
149 | u32 stat; | |
150 | ||
151 | stat = readl(port->base + PCIE_STAT_OFF); | |
152 | stat &= ~PCIE_STAT_DEV; | |
153 | stat |= nr << 16; | |
154 | writel(stat, port->base + PCIE_STAT_OFF); | |
155 | } | |
156 | ||
45361a4f TP |
157 | /* |
158 | * Setup PCIE BARs and Address Decode Wins: | |
159 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | |
160 | * WIN[0-3] -> DRAM bank[0-3] | |
161 | */ | |
162 | static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) | |
163 | { | |
164 | const struct mbus_dram_target_info *dram; | |
165 | u32 size; | |
166 | int i; | |
167 | ||
168 | dram = mv_mbus_dram_info(); | |
169 | ||
170 | /* First, disable and clear BARs and windows. */ | |
171 | for (i = 1; i < 3; i++) { | |
172 | writel(0, port->base + PCIE_BAR_CTRL_OFF(i)); | |
173 | writel(0, port->base + PCIE_BAR_LO_OFF(i)); | |
174 | writel(0, port->base + PCIE_BAR_HI_OFF(i)); | |
175 | } | |
176 | ||
177 | for (i = 0; i < 5; i++) { | |
178 | writel(0, port->base + PCIE_WIN04_CTRL_OFF(i)); | |
179 | writel(0, port->base + PCIE_WIN04_BASE_OFF(i)); | |
180 | writel(0, port->base + PCIE_WIN04_REMAP_OFF(i)); | |
181 | } | |
182 | ||
183 | writel(0, port->base + PCIE_WIN5_CTRL_OFF); | |
184 | writel(0, port->base + PCIE_WIN5_BASE_OFF); | |
185 | writel(0, port->base + PCIE_WIN5_REMAP_OFF); | |
186 | ||
187 | /* Setup windows for DDR banks. Count total DDR size on the fly. */ | |
188 | size = 0; | |
189 | for (i = 0; i < dram->num_cs; i++) { | |
190 | const struct mbus_dram_window *cs = dram->cs + i; | |
191 | ||
192 | writel(cs->base & 0xffff0000, | |
193 | port->base + PCIE_WIN04_BASE_OFF(i)); | |
194 | writel(0, port->base + PCIE_WIN04_REMAP_OFF(i)); | |
195 | writel(((cs->size - 1) & 0xffff0000) | | |
196 | (cs->mbus_attr << 8) | | |
197 | (dram->mbus_dram_target_id << 4) | 1, | |
198 | port->base + PCIE_WIN04_CTRL_OFF(i)); | |
199 | ||
200 | size += cs->size; | |
201 | } | |
202 | ||
203 | /* Round up 'size' to the nearest power of two. */ | |
204 | if ((size & (size - 1)) != 0) | |
205 | size = 1 << fls(size); | |
206 | ||
207 | /* Setup BAR[1] to all DRAM banks. */ | |
208 | writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1)); | |
209 | writel(0, port->base + PCIE_BAR_HI_OFF(1)); | |
210 | writel(((size - 1) & 0xffff0000) | 1, | |
211 | port->base + PCIE_BAR_CTRL_OFF(1)); | |
212 | } | |
213 | ||
214 | static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) | |
215 | { | |
216 | u16 cmd; | |
217 | u32 mask; | |
218 | ||
219 | /* Point PCIe unit MBUS decode windows to DRAM space. */ | |
220 | mvebu_pcie_setup_wins(port); | |
221 | ||
222 | /* Master + slave enable. */ | |
223 | cmd = readw(port->base + PCIE_CMD_OFF); | |
224 | cmd |= PCI_COMMAND_IO; | |
225 | cmd |= PCI_COMMAND_MEMORY; | |
226 | cmd |= PCI_COMMAND_MASTER; | |
227 | writew(cmd, port->base + PCIE_CMD_OFF); | |
228 | ||
229 | /* Enable interrupt lines A-D. */ | |
230 | mask = readl(port->base + PCIE_MASK_OFF); | |
231 | mask |= PCIE_MASK_ENABLE_INTS; | |
232 | writel(mask, port->base + PCIE_MASK_OFF); | |
233 | } | |
234 | ||
235 | static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, | |
236 | struct pci_bus *bus, | |
237 | u32 devfn, int where, int size, u32 *val) | |
238 | { | |
239 | writel(PCIE_CONF_ADDR(bus->number, devfn, where), | |
240 | port->base + PCIE_CONF_ADDR_OFF); | |
241 | ||
242 | *val = readl(port->base + PCIE_CONF_DATA_OFF); | |
243 | ||
244 | if (size == 1) | |
245 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
246 | else if (size == 2) | |
247 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
248 | ||
249 | return PCIBIOS_SUCCESSFUL; | |
250 | } | |
251 | ||
252 | static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, | |
253 | struct pci_bus *bus, | |
254 | u32 devfn, int where, int size, u32 val) | |
255 | { | |
256 | int ret = PCIBIOS_SUCCESSFUL; | |
257 | ||
258 | writel(PCIE_CONF_ADDR(bus->number, devfn, where), | |
259 | port->base + PCIE_CONF_ADDR_OFF); | |
260 | ||
261 | if (size == 4) | |
262 | writel(val, port->base + PCIE_CONF_DATA_OFF); | |
263 | else if (size == 2) | |
264 | writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3)); | |
265 | else if (size == 1) | |
266 | writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3)); | |
267 | else | |
268 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | |
269 | ||
270 | return ret; | |
271 | } | |
272 | ||
273 | static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) | |
274 | { | |
275 | phys_addr_t iobase; | |
276 | ||
277 | /* Are the new iobase/iolimit values invalid? */ | |
278 | if (port->bridge.iolimit < port->bridge.iobase || | |
279 | port->bridge.iolimitupper < port->bridge.iobaseupper) { | |
280 | ||
281 | /* If a window was configured, remove it */ | |
282 | if (port->iowin_base) { | |
283 | mvebu_mbus_del_window(port->iowin_base, | |
284 | port->iowin_size); | |
285 | port->iowin_base = 0; | |
286 | port->iowin_size = 0; | |
287 | } | |
288 | ||
289 | return; | |
290 | } | |
291 | ||
292 | /* | |
293 | * We read the PCI-to-PCI bridge emulated registers, and | |
294 | * calculate the base address and size of the address decoding | |
295 | * window to setup, according to the PCI-to-PCI bridge | |
296 | * specifications. iobase is the bus address, port->iowin_base | |
297 | * is the CPU address. | |
298 | */ | |
299 | iobase = ((port->bridge.iobase & 0xF0) << 8) | | |
300 | (port->bridge.iobaseupper << 16); | |
301 | port->iowin_base = port->pcie->io.start + iobase; | |
302 | port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | | |
303 | (port->bridge.iolimitupper << 16)) - | |
304 | iobase); | |
305 | ||
306 | mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base, | |
307 | port->iowin_size, | |
308 | iobase, | |
309 | MVEBU_MBUS_PCI_IO); | |
310 | ||
311 | pci_ioremap_io(iobase, port->iowin_base); | |
312 | } | |
313 | ||
314 | static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) | |
315 | { | |
316 | /* Are the new membase/memlimit values invalid? */ | |
317 | if (port->bridge.memlimit < port->bridge.membase) { | |
318 | ||
319 | /* If a window was configured, remove it */ | |
320 | if (port->memwin_base) { | |
321 | mvebu_mbus_del_window(port->memwin_base, | |
322 | port->memwin_size); | |
323 | port->memwin_base = 0; | |
324 | port->memwin_size = 0; | |
325 | } | |
326 | ||
327 | return; | |
328 | } | |
329 | ||
330 | /* | |
331 | * We read the PCI-to-PCI bridge emulated registers, and | |
332 | * calculate the base address and size of the address decoding | |
333 | * window to setup, according to the PCI-to-PCI bridge | |
334 | * specifications. | |
335 | */ | |
336 | port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); | |
337 | port->memwin_size = | |
338 | (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - | |
339 | port->memwin_base; | |
340 | ||
341 | mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base, | |
342 | port->memwin_size, | |
343 | MVEBU_MBUS_NO_REMAP, | |
344 | MVEBU_MBUS_PCI_MEM); | |
345 | } | |
346 | ||
347 | /* | |
348 | * Initialize the configuration space of the PCI-to-PCI bridge | |
349 | * associated with the given PCIe interface. | |
350 | */ | |
351 | static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) | |
352 | { | |
353 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
354 | ||
355 | memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); | |
356 | ||
45361a4f TP |
357 | bridge->class = PCI_CLASS_BRIDGE_PCI; |
358 | bridge->vendor = PCI_VENDOR_ID_MARVELL; | |
359 | bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID; | |
360 | bridge->header_type = PCI_HEADER_TYPE_BRIDGE; | |
361 | bridge->cache_line_size = 0x10; | |
362 | ||
363 | /* We support 32 bits I/O addressing */ | |
364 | bridge->iobase = PCI_IO_RANGE_TYPE_32; | |
365 | bridge->iolimit = PCI_IO_RANGE_TYPE_32; | |
366 | } | |
367 | ||
368 | /* | |
369 | * Read the configuration space of the PCI-to-PCI bridge associated to | |
370 | * the given PCIe interface. | |
371 | */ | |
372 | static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, | |
373 | unsigned int where, int size, u32 *value) | |
374 | { | |
375 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
376 | ||
377 | switch (where & ~3) { | |
378 | case PCI_VENDOR_ID: | |
379 | *value = bridge->device << 16 | bridge->vendor; | |
380 | break; | |
381 | ||
382 | case PCI_COMMAND: | |
6eb237c4 | 383 | *value = bridge->command; |
45361a4f TP |
384 | break; |
385 | ||
386 | case PCI_CLASS_REVISION: | |
387 | *value = bridge->class << 16 | bridge->interface << 8 | | |
388 | bridge->revision; | |
389 | break; | |
390 | ||
391 | case PCI_CACHE_LINE_SIZE: | |
392 | *value = bridge->bist << 24 | bridge->header_type << 16 | | |
393 | bridge->latency_timer << 8 | bridge->cache_line_size; | |
394 | break; | |
395 | ||
396 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: | |
397 | *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; | |
398 | break; | |
399 | ||
400 | case PCI_PRIMARY_BUS: | |
401 | *value = (bridge->secondary_latency_timer << 24 | | |
402 | bridge->subordinate_bus << 16 | | |
403 | bridge->secondary_bus << 8 | | |
404 | bridge->primary_bus); | |
405 | break; | |
406 | ||
407 | case PCI_IO_BASE: | |
408 | *value = (bridge->secondary_status << 16 | | |
409 | bridge->iolimit << 8 | | |
410 | bridge->iobase); | |
411 | break; | |
412 | ||
413 | case PCI_MEMORY_BASE: | |
414 | *value = (bridge->memlimit << 16 | bridge->membase); | |
415 | break; | |
416 | ||
417 | case PCI_PREF_MEMORY_BASE: | |
36dd1f3e | 418 | *value = 0; |
45361a4f TP |
419 | break; |
420 | ||
421 | case PCI_IO_BASE_UPPER16: | |
422 | *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); | |
423 | break; | |
424 | ||
425 | case PCI_ROM_ADDRESS1: | |
426 | *value = 0; | |
427 | break; | |
428 | ||
429 | default: | |
430 | *value = 0xffffffff; | |
431 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
432 | } | |
433 | ||
434 | if (size == 2) | |
435 | *value = (*value >> (8 * (where & 3))) & 0xffff; | |
436 | else if (size == 1) | |
437 | *value = (*value >> (8 * (where & 3))) & 0xff; | |
438 | ||
439 | return PCIBIOS_SUCCESSFUL; | |
440 | } | |
441 | ||
442 | /* Write to the PCI-to-PCI bridge configuration space */ | |
443 | static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, | |
444 | unsigned int where, int size, u32 value) | |
445 | { | |
446 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
447 | u32 mask, reg; | |
448 | int err; | |
449 | ||
450 | if (size == 4) | |
451 | mask = 0x0; | |
452 | else if (size == 2) | |
453 | mask = ~(0xffff << ((where & 3) * 8)); | |
454 | else if (size == 1) | |
455 | mask = ~(0xff << ((where & 3) * 8)); | |
456 | else | |
457 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
458 | ||
459 | err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); | |
460 | if (err) | |
461 | return err; | |
462 | ||
463 | value = (reg & mask) | value << ((where & 3) * 8); | |
464 | ||
465 | switch (where & ~3) { | |
466 | case PCI_COMMAND: | |
467 | bridge->command = value & 0xffff; | |
45361a4f TP |
468 | break; |
469 | ||
470 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: | |
471 | bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; | |
472 | break; | |
473 | ||
474 | case PCI_IO_BASE: | |
475 | /* | |
476 | * We also keep bit 1 set, it is a read-only bit that | |
477 | * indicates we support 32 bits addressing for the | |
478 | * I/O | |
479 | */ | |
480 | bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; | |
481 | bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; | |
482 | bridge->secondary_status = value >> 16; | |
483 | mvebu_pcie_handle_iobase_change(port); | |
484 | break; | |
485 | ||
486 | case PCI_MEMORY_BASE: | |
487 | bridge->membase = value & 0xffff; | |
488 | bridge->memlimit = value >> 16; | |
489 | mvebu_pcie_handle_membase_change(port); | |
490 | break; | |
491 | ||
45361a4f TP |
492 | case PCI_IO_BASE_UPPER16: |
493 | bridge->iobaseupper = value & 0xffff; | |
494 | bridge->iolimitupper = value >> 16; | |
495 | mvebu_pcie_handle_iobase_change(port); | |
496 | break; | |
497 | ||
498 | case PCI_PRIMARY_BUS: | |
499 | bridge->primary_bus = value & 0xff; | |
500 | bridge->secondary_bus = (value >> 8) & 0xff; | |
501 | bridge->subordinate_bus = (value >> 16) & 0xff; | |
502 | bridge->secondary_latency_timer = (value >> 24) & 0xff; | |
503 | mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); | |
504 | break; | |
505 | ||
506 | default: | |
507 | break; | |
508 | } | |
509 | ||
510 | return PCIBIOS_SUCCESSFUL; | |
511 | } | |
512 | ||
513 | static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) | |
514 | { | |
515 | return sys->private_data; | |
516 | } | |
517 | ||
518 | static struct mvebu_pcie_port * | |
519 | mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus, | |
520 | int devfn) | |
521 | { | |
522 | int i; | |
523 | ||
524 | for (i = 0; i < pcie->nports; i++) { | |
525 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
526 | if (bus->number == 0 && port->devfn == devfn) | |
527 | return port; | |
528 | if (bus->number != 0 && | |
197fc226 TP |
529 | bus->number >= port->bridge.secondary_bus && |
530 | bus->number <= port->bridge.subordinate_bus) | |
45361a4f TP |
531 | return port; |
532 | } | |
533 | ||
534 | return NULL; | |
535 | } | |
536 | ||
537 | /* PCI configuration space write function */ | |
538 | static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
539 | int where, int size, u32 val) | |
540 | { | |
541 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); | |
542 | struct mvebu_pcie_port *port; | |
543 | unsigned long flags; | |
544 | int ret; | |
545 | ||
546 | port = mvebu_pcie_find_port(pcie, bus, devfn); | |
547 | if (!port) | |
548 | return PCIBIOS_DEVICE_NOT_FOUND; | |
549 | ||
550 | /* Access the emulated PCI-to-PCI bridge */ | |
551 | if (bus->number == 0) | |
552 | return mvebu_sw_pci_bridge_write(port, where, size, val); | |
553 | ||
197fc226 TP |
554 | if (!port->haslink) |
555 | return PCIBIOS_DEVICE_NOT_FOUND; | |
556 | ||
557 | /* | |
558 | * On the secondary bus, we don't want to expose any other | |
559 | * device than the device physically connected in the PCIe | |
560 | * slot, visible in slot 0. In slot 1, there's a special | |
561 | * Marvell device that only makes sense when the Armada is | |
562 | * used as a PCIe endpoint. | |
563 | */ | |
564 | if (bus->number == port->bridge.secondary_bus && | |
565 | PCI_SLOT(devfn) != 0) | |
45361a4f TP |
566 | return PCIBIOS_DEVICE_NOT_FOUND; |
567 | ||
568 | /* Access the real PCIe interface */ | |
569 | spin_lock_irqsave(&port->conf_lock, flags); | |
f4ac9901 | 570 | ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, |
45361a4f TP |
571 | where, size, val); |
572 | spin_unlock_irqrestore(&port->conf_lock, flags); | |
573 | ||
574 | return ret; | |
575 | } | |
576 | ||
577 | /* PCI configuration space read function */ | |
578 | static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
579 | int size, u32 *val) | |
580 | { | |
581 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); | |
582 | struct mvebu_pcie_port *port; | |
583 | unsigned long flags; | |
584 | int ret; | |
585 | ||
586 | port = mvebu_pcie_find_port(pcie, bus, devfn); | |
587 | if (!port) { | |
588 | *val = 0xffffffff; | |
589 | return PCIBIOS_DEVICE_NOT_FOUND; | |
590 | } | |
591 | ||
592 | /* Access the emulated PCI-to-PCI bridge */ | |
593 | if (bus->number == 0) | |
594 | return mvebu_sw_pci_bridge_read(port, where, size, val); | |
595 | ||
197fc226 TP |
596 | if (!port->haslink) { |
597 | *val = 0xffffffff; | |
598 | return PCIBIOS_DEVICE_NOT_FOUND; | |
599 | } | |
600 | ||
601 | /* | |
602 | * On the secondary bus, we don't want to expose any other | |
603 | * device than the device physically connected in the PCIe | |
604 | * slot, visible in slot 0. In slot 1, there's a special | |
605 | * Marvell device that only makes sense when the Armada is | |
606 | * used as a PCIe endpoint. | |
607 | */ | |
608 | if (bus->number == port->bridge.secondary_bus && | |
609 | PCI_SLOT(devfn) != 0) { | |
45361a4f TP |
610 | *val = 0xffffffff; |
611 | return PCIBIOS_DEVICE_NOT_FOUND; | |
612 | } | |
613 | ||
614 | /* Access the real PCIe interface */ | |
615 | spin_lock_irqsave(&port->conf_lock, flags); | |
f4ac9901 | 616 | ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, |
45361a4f TP |
617 | where, size, val); |
618 | spin_unlock_irqrestore(&port->conf_lock, flags); | |
619 | ||
620 | return ret; | |
621 | } | |
622 | ||
623 | static struct pci_ops mvebu_pcie_ops = { | |
624 | .read = mvebu_pcie_rd_conf, | |
625 | .write = mvebu_pcie_wr_conf, | |
626 | }; | |
627 | ||
628 | static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys) | |
629 | { | |
630 | struct mvebu_pcie *pcie = sys_to_pcie(sys); | |
631 | int i; | |
632 | ||
633 | pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset); | |
634 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); | |
635 | pci_add_resource(&sys->resources, &pcie->busn); | |
636 | ||
637 | for (i = 0; i < pcie->nports; i++) { | |
638 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
639 | mvebu_pcie_setup_hw(port); | |
640 | } | |
641 | ||
642 | return 1; | |
643 | } | |
644 | ||
645 | static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
646 | { | |
647 | struct of_irq oirq; | |
648 | int ret; | |
649 | ||
650 | ret = of_irq_map_pci(dev, &oirq); | |
651 | if (ret) | |
652 | return ret; | |
653 | ||
654 | return irq_create_of_mapping(oirq.controller, oirq.specifier, | |
655 | oirq.size); | |
656 | } | |
657 | ||
658 | static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys) | |
659 | { | |
660 | struct mvebu_pcie *pcie = sys_to_pcie(sys); | |
661 | struct pci_bus *bus; | |
662 | ||
663 | bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr, | |
664 | &mvebu_pcie_ops, sys, &sys->resources); | |
665 | if (!bus) | |
666 | return NULL; | |
667 | ||
668 | pci_scan_child_bus(bus); | |
669 | ||
670 | return bus; | |
671 | } | |
672 | ||
673 | resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, | |
674 | const struct resource *res, | |
675 | resource_size_t start, | |
676 | resource_size_t size, | |
677 | resource_size_t align) | |
678 | { | |
679 | if (dev->bus->number != 0) | |
680 | return start; | |
681 | ||
682 | /* | |
683 | * On the PCI-to-PCI bridge side, the I/O windows must have at | |
684 | * least a 64 KB size and be aligned on their size, and the | |
685 | * memory windows must have at least a 1 MB size and be | |
686 | * aligned on their size | |
687 | */ | |
688 | if (res->flags & IORESOURCE_IO) | |
689 | return round_up(start, max((resource_size_t)SZ_64K, size)); | |
690 | else if (res->flags & IORESOURCE_MEM) | |
691 | return round_up(start, max((resource_size_t)SZ_1M, size)); | |
692 | else | |
693 | return start; | |
694 | } | |
695 | ||
696 | static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie) | |
697 | { | |
698 | struct hw_pci hw; | |
699 | ||
700 | memset(&hw, 0, sizeof(hw)); | |
701 | ||
702 | hw.nr_controllers = 1; | |
703 | hw.private_data = (void **)&pcie; | |
704 | hw.setup = mvebu_pcie_setup; | |
705 | hw.scan = mvebu_pcie_scan_bus; | |
706 | hw.map_irq = mvebu_pcie_map_irq; | |
707 | hw.ops = &mvebu_pcie_ops; | |
708 | hw.align_resource = mvebu_pcie_align_resource; | |
709 | ||
710 | pci_common_init(&hw); | |
711 | } | |
712 | ||
713 | /* | |
714 | * Looks up the list of register addresses encoded into the reg = | |
715 | * <...> property for one that matches the given port/lane. Once | |
716 | * found, maps it. | |
717 | */ | |
718 | static void __iomem * __init | |
719 | mvebu_pcie_map_registers(struct platform_device *pdev, | |
720 | struct device_node *np, | |
721 | struct mvebu_pcie_port *port) | |
722 | { | |
723 | struct resource regs; | |
724 | int ret = 0; | |
725 | ||
726 | ret = of_address_to_resource(np, 0, ®s); | |
727 | if (ret) | |
728 | return NULL; | |
729 | ||
730 | return devm_request_and_ioremap(&pdev->dev, ®s); | |
731 | } | |
732 | ||
733 | static int __init mvebu_pcie_probe(struct platform_device *pdev) | |
734 | { | |
735 | struct mvebu_pcie *pcie; | |
736 | struct device_node *np = pdev->dev.of_node; | |
737 | struct of_pci_range range; | |
738 | struct of_pci_range_parser parser; | |
739 | struct device_node *child; | |
740 | int i, ret; | |
741 | ||
742 | pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), | |
743 | GFP_KERNEL); | |
744 | if (!pcie) | |
745 | return -ENOMEM; | |
746 | ||
747 | pcie->pdev = pdev; | |
748 | ||
749 | if (of_pci_range_parser_init(&parser, np)) | |
750 | return -EINVAL; | |
751 | ||
752 | /* Get the I/O and memory ranges from DT */ | |
753 | for_each_of_pci_range(&parser, &range) { | |
754 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; | |
755 | if (restype == IORESOURCE_IO) { | |
756 | of_pci_range_to_resource(&range, np, &pcie->io); | |
757 | of_pci_range_to_resource(&range, np, &pcie->realio); | |
758 | pcie->io.name = "I/O"; | |
759 | pcie->realio.start = max_t(resource_size_t, | |
760 | PCIBIOS_MIN_IO, | |
761 | range.pci_addr); | |
762 | pcie->realio.end = min_t(resource_size_t, | |
763 | IO_SPACE_LIMIT, | |
764 | range.pci_addr + range.size); | |
765 | } | |
766 | if (restype == IORESOURCE_MEM) { | |
767 | of_pci_range_to_resource(&range, np, &pcie->mem); | |
768 | pcie->mem.name = "MEM"; | |
769 | } | |
770 | } | |
771 | ||
772 | /* Get the bus range */ | |
773 | ret = of_pci_parse_bus_range(np, &pcie->busn); | |
774 | if (ret) { | |
775 | dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", | |
776 | ret); | |
777 | return ret; | |
778 | } | |
779 | ||
780 | for_each_child_of_node(pdev->dev.of_node, child) { | |
781 | if (!of_device_is_available(child)) | |
782 | continue; | |
783 | pcie->nports++; | |
784 | } | |
785 | ||
786 | pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports * | |
787 | sizeof(struct mvebu_pcie_port), | |
788 | GFP_KERNEL); | |
789 | if (!pcie->ports) | |
790 | return -ENOMEM; | |
791 | ||
792 | i = 0; | |
793 | for_each_child_of_node(pdev->dev.of_node, child) { | |
794 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
795 | ||
796 | if (!of_device_is_available(child)) | |
797 | continue; | |
798 | ||
799 | port->pcie = pcie; | |
800 | ||
801 | if (of_property_read_u32(child, "marvell,pcie-port", | |
802 | &port->port)) { | |
803 | dev_warn(&pdev->dev, | |
804 | "ignoring PCIe DT node, missing pcie-port property\n"); | |
805 | continue; | |
806 | } | |
807 | ||
808 | if (of_property_read_u32(child, "marvell,pcie-lane", | |
809 | &port->lane)) | |
810 | port->lane = 0; | |
811 | ||
812 | port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", | |
813 | port->port, port->lane); | |
814 | ||
815 | port->devfn = of_pci_get_devfn(child); | |
816 | if (port->devfn < 0) | |
817 | continue; | |
818 | ||
819 | port->base = mvebu_pcie_map_registers(pdev, child, port); | |
820 | if (!port->base) { | |
821 | dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", | |
822 | port->port, port->lane); | |
823 | continue; | |
824 | } | |
825 | ||
f4ac9901 TP |
826 | mvebu_pcie_set_local_dev_nr(port, 1); |
827 | ||
45361a4f TP |
828 | if (mvebu_pcie_link_up(port)) { |
829 | port->haslink = 1; | |
830 | dev_info(&pdev->dev, "PCIe%d.%d: link up\n", | |
831 | port->port, port->lane); | |
832 | } else { | |
833 | port->haslink = 0; | |
834 | dev_info(&pdev->dev, "PCIe%d.%d: link down\n", | |
835 | port->port, port->lane); | |
836 | } | |
837 | ||
838 | port->clk = of_clk_get_by_name(child, NULL); | |
3d9939c9 | 839 | if (IS_ERR(port->clk)) { |
45361a4f TP |
840 | dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n", |
841 | port->port, port->lane); | |
842 | iounmap(port->base); | |
843 | port->haslink = 0; | |
844 | continue; | |
845 | } | |
846 | ||
847 | port->dn = child; | |
848 | ||
849 | clk_prepare_enable(port->clk); | |
850 | spin_lock_init(&port->conf_lock); | |
851 | ||
852 | mvebu_sw_pci_bridge_init(port); | |
853 | ||
854 | i++; | |
855 | } | |
856 | ||
857 | mvebu_pcie_enable(pcie); | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
862 | static const struct of_device_id mvebu_pcie_of_match_table[] = { | |
863 | { .compatible = "marvell,armada-xp-pcie", }, | |
864 | { .compatible = "marvell,armada-370-pcie", }, | |
005625fc | 865 | { .compatible = "marvell,kirkwood-pcie", }, |
45361a4f TP |
866 | {}, |
867 | }; | |
868 | MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); | |
869 | ||
870 | static struct platform_driver mvebu_pcie_driver = { | |
871 | .driver = { | |
872 | .owner = THIS_MODULE, | |
873 | .name = "mvebu-pcie", | |
874 | .of_match_table = | |
875 | of_match_ptr(mvebu_pcie_of_match_table), | |
876 | }, | |
877 | }; | |
878 | ||
879 | static int __init mvebu_pcie_init(void) | |
880 | { | |
881 | return platform_driver_probe(&mvebu_pcie_driver, | |
882 | mvebu_pcie_probe); | |
883 | } | |
884 | ||
885 | subsys_initcall(mvebu_pcie_init); | |
886 | ||
887 | MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
888 | MODULE_DESCRIPTION("Marvell EBU PCIe driver"); | |
889 | MODULE_LICENSE("GPLv2"); |