[deliverable/linux.git] / drivers / pci / host / pci-rcar-gen2.c

/*
 *  pci-rcar-gen2: internal PCI bus support
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
#include <linux/slab.h>

/* AHB-PCI Bridge PCI communication registers */
#define RCAR_AHBPCI_PCICOM_OFFSET	0x800

#define RCAR_PCIAHB_WIN1_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
#define RCAR_PCIAHB_WIN2_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
#define RCAR_PCIAHB_PREFETCH0		0x0
#define RCAR_PCIAHB_PREFETCH4		0x1
#define RCAR_PCIAHB_PREFETCH8		0x2
#define RCAR_PCIAHB_PREFETCH16		0x3

#define RCAR_AHBPCI_WIN1_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
#define RCAR_AHBPCI_WIN2_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
#define RCAR_AHBPCI_WIN_CTR_MEM		(3 << 1)
#define RCAR_AHBPCI_WIN_CTR_CFG		(5 << 1)
#define RCAR_AHBPCI_WIN1_HOST		(1 << 30)
#define RCAR_AHBPCI_WIN1_DEVICE		(1 << 31)

#define RCAR_PCI_INT_ENABLE_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
#define RCAR_PCI_INT_STATUS_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
#define RCAR_PCI_INT_SIGTABORT		(1 << 0)
#define RCAR_PCI_INT_SIGRETABORT	(1 << 1)
#define RCAR_PCI_INT_REMABORT		(1 << 2)
#define RCAR_PCI_INT_PERR		(1 << 3)
#define RCAR_PCI_INT_SIGSERR		(1 << 4)
#define RCAR_PCI_INT_RESERR		(1 << 5)
#define RCAR_PCI_INT_WIN1ERR		(1 << 12)
#define RCAR_PCI_INT_WIN2ERR		(1 << 13)
#define RCAR_PCI_INT_A			(1 << 16)
#define RCAR_PCI_INT_B			(1 << 17)
#define RCAR_PCI_INT_PME		(1 << 19)
#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT		| \
				RCAR_PCI_INT_SIGRETABORT	| \
				RCAR_PCI_INT_SIGRETABORT	| \
				RCAR_PCI_INT_REMABORT		| \
				RCAR_PCI_INT_PERR		| \
				RCAR_PCI_INT_SIGSERR		| \
				RCAR_PCI_INT_RESERR		| \
				RCAR_PCI_INT_WIN1ERR		| \
				RCAR_PCI_INT_WIN2ERR)

#define RCAR_AHB_BUS_CTR_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
#define RCAR_AHB_BUS_MMODE_HTRANS	(1 << 0)
#define RCAR_AHB_BUS_MMODE_BYTE_BURST	(1 << 1)
#define RCAR_AHB_BUS_MMODE_WR_INCR	(1 << 2)
#define RCAR_AHB_BUS_MMODE_HBUS_REQ	(1 << 7)
#define RCAR_AHB_BUS_SMODE_READYCTR	(1 << 17)
#define RCAR_AHB_BUS_MODE		(RCAR_AHB_BUS_MMODE_HTRANS |	\
					RCAR_AHB_BUS_MMODE_BYTE_BURST |	\
					RCAR_AHB_BUS_MMODE_WR_INCR |	\
					RCAR_AHB_BUS_MMODE_HBUS_REQ |	\
					RCAR_AHB_BUS_SMODE_READYCTR)

#define RCAR_USBCTR_REG			(RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
#define RCAR_USBCTR_USBH_RST		(1 << 0)
#define RCAR_USBCTR_PCICLK_MASK		(1 << 1)
#define RCAR_USBCTR_PLL_RST		(1 << 2)
#define RCAR_USBCTR_DIRPD		(1 << 8)
#define RCAR_USBCTR_PCIAHB_WIN2_EN	(1 << 9)
#define RCAR_USBCTR_PCIAHB_WIN1_256M	(0 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_512M	(1 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_1G	(2 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_2G	(3 << 10)
#define RCAR_USBCTR_PCIAHB_WIN1_MASK	(3 << 10)

#define RCAR_PCI_ARBITER_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
#define RCAR_PCI_ARBITER_PCIREQ0	(1 << 0)
#define RCAR_PCI_ARBITER_PCIREQ1	(1 << 1)
#define RCAR_PCI_ARBITER_PCIBP_MODE	(1 << 12)

#define RCAR_PCI_UNIT_REV_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x48)

struct rcar_pci_priv {
	struct device *dev;
	void __iomem *reg;
	struct resource io_res;
	struct resource mem_res;
	struct resource *cfg_res;
	unsigned busnr;
	int irq;
	unsigned long window_size;
};

/* PCI configuration space operations */
static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
				       int where)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct rcar_pci_priv *priv = sys->private_data;
	int slot, val;

	if (sys->busnr != bus->number || PCI_FUNC(devfn))
		return NULL;

	/* Only one EHCI/OHCI device built-in */
	slot = PCI_SLOT(devfn);
	if (slot > 2)
		return NULL;

	/* bridge logic only has registers to 0x40 */
	if (slot == 0x0 && where >= 0x40)
		return NULL;

	val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
		     RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;

	iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
	return priv->reg + (slot >> 1) * 0x100 + where;
}

static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 *val)
{
	void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);

	if (!reg)
		return PCIBIOS_DEVICE_NOT_FOUND;

	switch (size) {
	case 1:
		*val = ioread8(reg);
		break;
	case 2:
		*val = ioread16(reg);
		break;
	default:
		*val = ioread32(reg);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
				 int where, int size, u32 val)
{
	void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);

	if (!reg)
		return PCIBIOS_DEVICE_NOT_FOUND;

	switch (size) {
	case 1:
		iowrite8(val, reg);
		break;
	case 2:
		iowrite16(val, reg);
		break;
	default:
		iowrite32(val, reg);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

/* PCI interrupt mapping */
static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_sys_data *sys = dev->bus->sysdata;
	struct rcar_pci_priv *priv = sys->private_data;
	int irq;

	irq = of_irq_parse_and_map_pci(dev, slot, pin);
	if (!irq)
		irq = priv->irq;

	return irq;
}

#ifdef CONFIG_PCI_DEBUG
/* if debug enabled, then attach an error handler irq to the bridge */

static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
{
	struct rcar_pci_priv *priv = pw;
	u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);

	if (status & RCAR_PCI_INT_ALLERRORS) {
		dev_err(priv->dev, "error irq: status %08x\n", status);

		/* clear the error(s) */
		iowrite32(status & RCAR_PCI_INT_ALLERRORS,
			  priv->reg + RCAR_PCI_INT_STATUS_REG);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
{
	int ret;
	u32 val;

	ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
			       IRQF_SHARED, "error irq", priv);
	if (ret) {
		dev_err(priv->dev, "cannot claim IRQ for error handling\n");
		return;
	}

	val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
	val |= RCAR_PCI_INT_ALLERRORS;
	iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
}
#else
static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
#endif

/* PCI host controller setup */
static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
{
	struct rcar_pci_priv *priv = sys->private_data;
	void __iomem *reg = priv->reg;
	u32 val;

	pm_runtime_enable(priv->dev);
	pm_runtime_get_sync(priv->dev);

	val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
	dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);

	/* Disable Direct Power Down State and assert reset */
	val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
	val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
	iowrite32(val, reg + RCAR_USBCTR_REG);
	udelay(4);

	/* De-assert reset and reset PCIAHB window1 size */
	val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
		 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);

	/* Setup PCIAHB window1 size */
	switch (priv->window_size) {
	case SZ_2G:
		val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
		break;
	case SZ_1G:
		val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
		break;
	case SZ_512M:
		val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
		break;
	default:
		pr_warn("unknown window size %ld - defaulting to 256M\n",
			priv->window_size);
		priv->window_size = SZ_256M;
		/* fall-through */
	case SZ_256M:
		val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
		break;
	}
	iowrite32(val, reg + RCAR_USBCTR_REG);

	/* Configure AHB master and slave modes */
	iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);

	/* Configure PCI arbiter */
	val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
	val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
	       RCAR_PCI_ARBITER_PCIBP_MODE;
	iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);

	/* PCI-AHB mapping: 0x40000000 base */
	iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
		  reg + RCAR_PCIAHB_WIN1_CTR_REG);

	/* AHB-PCI mapping: OHCI/EHCI registers */
	val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
	iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);

	/* Enable AHB-PCI bridge PCI configuration access */
	iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
		  reg + RCAR_AHBPCI_WIN1_CTR_REG);
	/* Set PCI-AHB Window1 address */
	iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
		  reg + PCI_BASE_ADDRESS_1);
	/* Set AHB-PCI bridge PCI communication area address */
	val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
	iowrite32(val, reg + PCI_BASE_ADDRESS_0);

	val = ioread32(reg + PCI_COMMAND);
	val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
	       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
	iowrite32(val, reg + PCI_COMMAND);

	/* Enable PCI interrupts */
	iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
		  reg + RCAR_PCI_INT_ENABLE_REG);

	if (priv->irq > 0)
		rcar_pci_setup_errirq(priv);

	/* Add PCI resources */
	pci_add_resource(&sys->resources, &priv->io_res);
	pci_add_resource(&sys->resources, &priv->mem_res);

	/* Setup bus number based on platform device id / of bus-range */
	sys->busnr = priv->busnr;
	return 1;
}

static struct pci_ops rcar_pci_ops = {
	.read	= rcar_pci_read_config,
	.write	= rcar_pci_write_config,
};

static int rcar_pci_probe(struct platform_device *pdev)
{
	struct resource *cfg_res, *mem_res;
	struct rcar_pci_priv *priv;
	void __iomem *reg;
	struct hw_pci hw;
	void *hw_private[1];

	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg = devm_ioremap_resource(&pdev->dev, cfg_res);
	if (IS_ERR(reg))
		return PTR_ERR(reg);

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!mem_res || !mem_res->start)
		return -ENODEV;

	priv = devm_kzalloc(&pdev->dev,
			    sizeof(struct rcar_pci_priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->mem_res = *mem_res;
	/*
	 * The controller does not support/use port I/O,
	 * so setup a dummy port I/O region here.
	 */
	priv->io_res.start = priv->mem_res.start;
	priv->io_res.end = priv->mem_res.end;
	priv->io_res.flags = IORESOURCE_IO;

	priv->cfg_res = cfg_res;

	priv->irq = platform_get_irq(pdev, 0);
	priv->reg = reg;
	priv->dev = &pdev->dev;

	if (priv->irq < 0) {
		dev_err(&pdev->dev, "no valid irq found\n");
		return priv->irq;
	}

	priv->window_size = SZ_1G;

	if (pdev->dev.of_node) {
		struct resource busnr;
		int ret;

		ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr);
		if (ret < 0) {
			dev_err(&pdev->dev, "failed to parse bus-range\n");
			return ret;
		}

		priv->busnr = busnr.start;
		if (busnr.end != busnr.start)
			dev_warn(&pdev->dev, "only one bus number supported\n");
	} else {
		priv->busnr = pdev->id;
	}

	hw_private[0] = priv;
	memset(&hw, 0, sizeof(hw));
	hw.nr_controllers = ARRAY_SIZE(hw_private);
	hw.private_data = hw_private;
	hw.map_irq = rcar_pci_map_irq;
	hw.ops = &rcar_pci_ops;
	hw.setup = rcar_pci_setup;
	pci_common_init_dev(&pdev->dev, &hw);
	return 0;
}

static struct of_device_id rcar_pci_of_match[] = {
	{ .compatible = "renesas,pci-r8a7790", },
	{ .compatible = "renesas,pci-r8a7791", },
	{ },
};

MODULE_DEVICE_TABLE(of, rcar_pci_of_match);

static struct platform_driver rcar_pci_driver = {
	.driver = {
		.name = "pci-rcar-gen2",
		.owner = THIS_MODULE,
		.suppress_bind_attrs = true,
		.of_match_table = rcar_pci_of_match,
	},
	.probe = rcar_pci_probe,
};

module_platform_driver(rcar_pci_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");
Commit	Line	Data
ba3eb9fc VB	1	/*
	2	* pci-rcar-gen2: internal PCI bus support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Cogent Embedded, Inc.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
b9bfe1bc	18	#include <linux/of_pci.h>
ba3eb9fc VB	19	#include <linux/pci.h>
ba3eb9fc VB	20	#include <linux/platform_device.h>
fb178d8b	21	#include <linux/pm_runtime.h>
33966fd9	22	#include <linux/sizes.h>
ba3eb9fc VB	23	#include <linux/slab.h>
	24
	25	/* AHB-PCI Bridge PCI communication registers */
	26	#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
	27
	28	#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
	29	#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
	30	#define RCAR_PCIAHB_PREFETCH0 0x0
	31	#define RCAR_PCIAHB_PREFETCH4 0x1
	32	#define RCAR_PCIAHB_PREFETCH8 0x2
	33	#define RCAR_PCIAHB_PREFETCH16 0x3
	34
	35	#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
	36	#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
	37	#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
	38	#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
	39	#define RCAR_AHBPCI_WIN1_HOST (1 << 30)
	40	#define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
	41
	42	#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
	43	#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
80a595d9 BD	44	#define RCAR_PCI_INT_SIGTABORT (1 << 0)
	45	#define RCAR_PCI_INT_SIGRETABORT (1 << 1)
	46	#define RCAR_PCI_INT_REMABORT (1 << 2)
	47	#define RCAR_PCI_INT_PERR (1 << 3)
	48	#define RCAR_PCI_INT_SIGSERR (1 << 4)
	49	#define RCAR_PCI_INT_RESERR (1 << 5)
	50	#define RCAR_PCI_INT_WIN1ERR (1 << 12)
	51	#define RCAR_PCI_INT_WIN2ERR (1 << 13)
ba3eb9fc VB	52	#define RCAR_PCI_INT_A (1 << 16)
	53	#define RCAR_PCI_INT_B (1 << 17)
	54	#define RCAR_PCI_INT_PME (1 << 19)
80a595d9 BD	55	#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT \| \
	56	RCAR_PCI_INT_SIGRETABORT \| \
	57	RCAR_PCI_INT_SIGRETABORT \| \
	58	RCAR_PCI_INT_REMABORT \| \
	59	RCAR_PCI_INT_PERR \| \
	60	RCAR_PCI_INT_SIGSERR \| \
	61	RCAR_PCI_INT_RESERR \| \
	62	RCAR_PCI_INT_WIN1ERR \| \
	63	RCAR_PCI_INT_WIN2ERR)
ba3eb9fc VB	64
	65	#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
	66	#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
	67	#define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
	68	#define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
	69	#define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
	70	#define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
	71	#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS \| \
	72	RCAR_AHB_BUS_MMODE_BYTE_BURST \| \
	73	RCAR_AHB_BUS_MMODE_WR_INCR \| \
	74	RCAR_AHB_BUS_MMODE_HBUS_REQ \| \
	75	RCAR_AHB_BUS_SMODE_READYCTR)
	76
	77	#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
	78	#define RCAR_USBCTR_USBH_RST (1 << 0)
	79	#define RCAR_USBCTR_PCICLK_MASK (1 << 1)
	80	#define RCAR_USBCTR_PLL_RST (1 << 2)
	81	#define RCAR_USBCTR_DIRPD (1 << 8)
	82	#define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
	83	#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
	84	#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
	85	#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
	86	#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
	87	#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
	88
	89	#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
	90	#define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
	91	#define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
	92	#define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
	93
	94	#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
	95
ba3eb9fc	96	struct rcar_pci_priv {
fb178d8b	97	struct device *dev;
ba3eb9fc VB	98	void __iomem *reg;
	99	struct resource io_res;
	100	struct resource mem_res;
	101	struct resource *cfg_res;
d47b62f4	102	unsigned busnr;
ba3eb9fc	103	int irq;
33966fd9	104	unsigned long window_size;
ba3eb9fc VB	105	};
	106
	107	/* PCI configuration space operations */
	108	static void __iomem rcar_pci_cfg_base(struct pci_bus bus, unsigned int devfn,
	109	int where)
	110	{
	111	struct pci_sys_data *sys = bus->sysdata;
	112	struct rcar_pci_priv *priv = sys->private_data;
	113	int slot, val;
	114
	115	if (sys->busnr != bus->number \|\| PCI_FUNC(devfn))
	116	return NULL;
	117
	118	/* Only one EHCI/OHCI device built-in */
	119	slot = PCI_SLOT(devfn);
	120	if (slot > 2)
	121	return NULL;
	122
e64a2a97 BD	123	/* bridge logic only has registers to 0x40 */
	124	if (slot == 0x0 && where >= 0x40)
	125	return NULL;
	126
ba3eb9fc VB	127	val = slot ? RCAR_AHBPCI_WIN1_DEVICE \| RCAR_AHBPCI_WIN_CTR_CFG :
	128	RCAR_AHBPCI_WIN1_HOST \| RCAR_AHBPCI_WIN_CTR_CFG;
	129
	130	iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
	131	return priv->reg + (slot >> 1) * 0x100 + where;
	132	}
	133
	134	static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
	135	int where, int size, u32 *val)
	136	{
	137	void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
	138
	139	if (!reg)
	140	return PCIBIOS_DEVICE_NOT_FOUND;
	141
	142	switch (size) {
	143	case 1:
	144	*val = ioread8(reg);
	145	break;
	146	case 2:
	147	*val = ioread16(reg);
	148	break;
	149	default:
	150	*val = ioread32(reg);
	151	break;
	152	}
	153
	154	return PCIBIOS_SUCCESSFUL;
	155	}
	156
	157	static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
	158	int where, int size, u32 val)
	159	{
	160	void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
	161
	162	if (!reg)
	163	return PCIBIOS_DEVICE_NOT_FOUND;
	164
	165	switch (size) {
	166	case 1:
	167	iowrite8(val, reg);
	168	break;
	169	case 2:
	170	iowrite16(val, reg);
	171	break;
	172	default:
	173	iowrite32(val, reg);
	174	break;
	175	}
	176
	177	return PCIBIOS_SUCCESSFUL;
	178	}
	179
	180	/* PCI interrupt mapping */
546cadda	181	static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
ba3eb9fc VB	182	{
	183	struct pci_sys_data *sys = dev->bus->sysdata;
	184	struct rcar_pci_priv *priv = sys->private_data;
b9bfe1bc LS	185	int irq;
	186
	187	irq = of_irq_parse_and_map_pci(dev, slot, pin);
	188	if (!irq)
	189	irq = priv->irq;
ba3eb9fc	190
b9bfe1bc	191	return irq;
ba3eb9fc VB	192	}
ba3eb9fc VB	193
80a595d9 BD	194	#ifdef CONFIG_PCI_DEBUG
	195	/* if debug enabled, then attach an error handler irq to the bridge */
	196
	197	static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
	198	{
	199	struct rcar_pci_priv *priv = pw;
	200	u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
	201
	202	if (status & RCAR_PCI_INT_ALLERRORS) {
	203	dev_err(priv->dev, "error irq: status %08x\n", status);
	204
	205	/* clear the error(s) */
	206	iowrite32(status & RCAR_PCI_INT_ALLERRORS,
	207	priv->reg + RCAR_PCI_INT_STATUS_REG);
	208	return IRQ_HANDLED;
	209	}
	210
	211	return IRQ_NONE;
	212	}
	213
	214	static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
	215	{
	216	int ret;
	217	u32 val;
	218
	219	ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
	220	IRQF_SHARED, "error irq", priv);
	221	if (ret) {
	222	dev_err(priv->dev, "cannot claim IRQ for error handling\n");
	223	return;
	224	}
	225
	226	val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
	227	val \|= RCAR_PCI_INT_ALLERRORS;
	228	iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
	229	}
	230	#else
	231	static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
	232	#endif
	233
ba3eb9fc	234	/* PCI host controller setup */
546cadda	235	static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
ba3eb9fc VB	236	{
	237	struct rcar_pci_priv *priv = sys->private_data;
	238	void __iomem *reg = priv->reg;
	239	u32 val;
	240
fb178d8b VB	241	pm_runtime_enable(priv->dev);
	242	pm_runtime_get_sync(priv->dev);
	243
ba3eb9fc	244	val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
fb178d8b	245	dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
ba3eb9fc VB	246
	247	/* Disable Direct Power Down State and assert reset */
	248	val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
	249	val \|= RCAR_USBCTR_USBH_RST \| RCAR_USBCTR_PLL_RST;
	250	iowrite32(val, reg + RCAR_USBCTR_REG);
	251	udelay(4);
	252
33966fd9	253	/* De-assert reset and reset PCIAHB window1 size */
ba3eb9fc VB	254	val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK \| RCAR_USBCTR_PCICLK_MASK \|
ba3eb9fc VB	255	RCAR_USBCTR_USBH_RST \| RCAR_USBCTR_PLL_RST);
33966fd9 MD	256
	257	/* Setup PCIAHB window1 size */
	258	switch (priv->window_size) {
	259	case SZ_2G:
	260	val \|= RCAR_USBCTR_PCIAHB_WIN1_2G;
	261	break;
	262	case SZ_1G:
	263	val \|= RCAR_USBCTR_PCIAHB_WIN1_1G;
	264	break;
	265	case SZ_512M:
	266	val \|= RCAR_USBCTR_PCIAHB_WIN1_512M;
	267	break;
	268	default:
	269	pr_warn("unknown window size %ld - defaulting to 256M\n",
	270	priv->window_size);
	271	priv->window_size = SZ_256M;
	272	/* fall-through */
	273	case SZ_256M:
	274	val \|= RCAR_USBCTR_PCIAHB_WIN1_256M;
	275	break;
	276	}
	277	iowrite32(val, reg + RCAR_USBCTR_REG);
ba3eb9fc VB	278
	279	/* Configure AHB master and slave modes */
	280	iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
	281
	282	/* Configure PCI arbiter */
	283	val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
	284	val \|= RCAR_PCI_ARBITER_PCIREQ0 \| RCAR_PCI_ARBITER_PCIREQ1 \|
	285	RCAR_PCI_ARBITER_PCIBP_MODE;
	286	iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
	287
33966fd9	288	/* PCI-AHB mapping: 0x40000000 base */
ba3eb9fc VB	289	iowrite32(0x40000000 \| RCAR_PCIAHB_PREFETCH16,
	290	reg + RCAR_PCIAHB_WIN1_CTR_REG);
	291
	292	/* AHB-PCI mapping: OHCI/EHCI registers */
	293	val = priv->mem_res.start \| RCAR_AHBPCI_WIN_CTR_MEM;
	294	iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
	295
	296	/* Enable AHB-PCI bridge PCI configuration access */
	297	iowrite32(RCAR_AHBPCI_WIN1_HOST \| RCAR_AHBPCI_WIN_CTR_CFG,
	298	reg + RCAR_AHBPCI_WIN1_CTR_REG);
	299	/* Set PCI-AHB Window1 address */
	300	iowrite32(0x40000000 \| PCI_BASE_ADDRESS_MEM_PREFETCH,
	301	reg + PCI_BASE_ADDRESS_1);
	302	/* Set AHB-PCI bridge PCI communication area address */
	303	val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
	304	iowrite32(val, reg + PCI_BASE_ADDRESS_0);
	305
	306	val = ioread32(reg + PCI_COMMAND);
	307	val \|= PCI_COMMAND_SERR \| PCI_COMMAND_PARITY \|
	308	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
	309	iowrite32(val, reg + PCI_COMMAND);
	310
	311	/* Enable PCI interrupts */
	312	iowrite32(RCAR_PCI_INT_A \| RCAR_PCI_INT_B \| RCAR_PCI_INT_PME,
	313	reg + RCAR_PCI_INT_ENABLE_REG);
	314
80a595d9 BD	315	if (priv->irq > 0)
	316	rcar_pci_setup_errirq(priv);
	317
ba3eb9fc VB	318	/* Add PCI resources */
	319	pci_add_resource(&sys->resources, &priv->io_res);
	320	pci_add_resource(&sys->resources, &priv->mem_res);
	321
d47b62f4 BD	322	/* Setup bus number based on platform device id / of bus-range */
d47b62f4 BD	323	sys->busnr = priv->busnr;
ba3eb9fc VB	324	return 1;
	325	}
	326
	327	static struct pci_ops rcar_pci_ops = {
	328	.read = rcar_pci_read_config,
	329	.write = rcar_pci_write_config,
	330	};
	331
546cadda	332	static int rcar_pci_probe(struct platform_device *pdev)
ba3eb9fc VB	333	{
	334	struct resource cfg_res, mem_res;
	335	struct rcar_pci_priv *priv;
	336	void __iomem *reg;
546cadda MD	337	struct hw_pci hw;
546cadda MD	338	void *hw_private[1];
ba3eb9fc VB	339
	340	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	341	reg = devm_ioremap_resource(&pdev->dev, cfg_res);
c176d1c7 WY	342	if (IS_ERR(reg))
c176d1c7 WY	343	return PTR_ERR(reg);
ba3eb9fc VB	344
	345	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	346	if (!mem_res \|\| !mem_res->start)
	347	return -ENODEV;
	348
	349	priv = devm_kzalloc(&pdev->dev,
	350	sizeof(struct rcar_pci_priv), GFP_KERNEL);
	351	if (!priv)
	352	return -ENOMEM;
	353
	354	priv->mem_res = *mem_res;
	355	/*
	356	* The controller does not support/use port I/O,
	357	* so setup a dummy port I/O region here.
	358	*/
	359	priv->io_res.start = priv->mem_res.start;
	360	priv->io_res.end = priv->mem_res.end;
	361	priv->io_res.flags = IORESOURCE_IO;
	362
	363	priv->cfg_res = cfg_res;
	364
	365	priv->irq = platform_get_irq(pdev, 0);
	366	priv->reg = reg;
fb178d8b	367	priv->dev = &pdev->dev;
ba3eb9fc	368
ed65b788 BD	369	if (priv->irq < 0) {
	370	dev_err(&pdev->dev, "no valid irq found\n");
	371	return priv->irq;
	372	}
	373
33966fd9 MD	374	priv->window_size = SZ_1G;
33966fd9 MD	375
d47b62f4 BD	376	if (pdev->dev.of_node) {
	377	struct resource busnr;
	378	int ret;
	379
	380	ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr);
	381	if (ret < 0) {
	382	dev_err(&pdev->dev, "failed to parse bus-range\n");
	383	return ret;
	384	}
	385
	386	priv->busnr = busnr.start;
	387	if (busnr.end != busnr.start)
	388	dev_warn(&pdev->dev, "only one bus number supported\n");
	389	} else {
	390	priv->busnr = pdev->id;
	391	}
	392
546cadda MD	393	hw_private[0] = priv;
	394	memset(&hw, 0, sizeof(hw));
	395	hw.nr_controllers = ARRAY_SIZE(hw_private);
	396	hw.private_data = hw_private;
	397	hw.map_irq = rcar_pci_map_irq;
	398	hw.ops = &rcar_pci_ops;
	399	hw.setup = rcar_pci_setup;
	400	pci_common_init_dev(&pdev->dev, &hw);
	401	return 0;
ba3eb9fc VB	402	}
ba3eb9fc VB	403
d47b62f4 BD	404	static struct of_device_id rcar_pci_of_match[] = {
	405	{ .compatible = "renesas,pci-r8a7790", },
	406	{ .compatible = "renesas,pci-r8a7791", },
	407	{ },
	408	};
	409
	410	MODULE_DEVICE_TABLE(of, rcar_pci_of_match);
	411
ba3eb9fc VB	412	static struct platform_driver rcar_pci_driver = {
	413	.driver = {
	414	.name = "pci-rcar-gen2",
546cadda MD	415	.owner = THIS_MODULE,
546cadda MD	416	.suppress_bind_attrs = true,
d47b62f4	417	.of_match_table = rcar_pci_of_match,
ba3eb9fc	418	},
546cadda	419	.probe = rcar_pci_probe,
ba3eb9fc VB	420	};
ba3eb9fc VB	421
546cadda	422	module_platform_driver(rcar_pci_driver);
ba3eb9fc VB	423
	424	MODULE_LICENSE("GPL v2");
	425	MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
	426	MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");