Commit | Line | Data |
---|---|---|
d1523b52 | 1 | /* |
94716cdd | 2 | * PCIe host controller driver for Tegra SoCs |
d1523b52 TR |
3 | * |
4 | * Copyright (c) 2010, CompuLab, Ltd. | |
5 | * Author: Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * Based on NVIDIA PCIe driver | |
8 | * Copyright (c) 2008-2009, NVIDIA Corporation. | |
9 | * | |
10 | * Bits taken from arch/arm/mach-dove/pcie.c | |
11 | * | |
ad183271 PG |
12 | * Author: Thierry Reding <treding@nvidia.com> |
13 | * | |
d1523b52 TR |
14 | * This program is free software; you can redistribute it and/or modify |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
20 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
21 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
22 | * more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
27 | */ | |
28 | ||
29 | #include <linux/clk.h> | |
2cb989f6 | 30 | #include <linux/debugfs.h> |
d1523b52 TR |
31 | #include <linux/delay.h> |
32 | #include <linux/export.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/irqdomain.h> | |
36 | #include <linux/kernel.h> | |
ad183271 | 37 | #include <linux/init.h> |
d1523b52 TR |
38 | #include <linux/msi.h> |
39 | #include <linux/of_address.h> | |
40 | #include <linux/of_pci.h> | |
41 | #include <linux/of_platform.h> | |
42 | #include <linux/pci.h> | |
7f1f054b | 43 | #include <linux/phy/phy.h> |
d1523b52 | 44 | #include <linux/platform_device.h> |
3127a6b2 | 45 | #include <linux/reset.h> |
d1523b52 TR |
46 | #include <linux/sizes.h> |
47 | #include <linux/slab.h> | |
d1523b52 TR |
48 | #include <linux/vmalloc.h> |
49 | #include <linux/regulator/consumer.h> | |
50 | ||
306a7f91 | 51 | #include <soc/tegra/cpuidle.h> |
7232398a | 52 | #include <soc/tegra/pmc.h> |
306a7f91 | 53 | |
d1523b52 TR |
54 | #include <asm/mach/irq.h> |
55 | #include <asm/mach/map.h> | |
56 | #include <asm/mach/pci.h> | |
57 | ||
58 | #define INT_PCI_MSI_NR (8 * 32) | |
d1523b52 TR |
59 | |
60 | /* register definitions */ | |
61 | ||
62 | #define AFI_AXI_BAR0_SZ 0x00 | |
63 | #define AFI_AXI_BAR1_SZ 0x04 | |
64 | #define AFI_AXI_BAR2_SZ 0x08 | |
65 | #define AFI_AXI_BAR3_SZ 0x0c | |
66 | #define AFI_AXI_BAR4_SZ 0x10 | |
67 | #define AFI_AXI_BAR5_SZ 0x14 | |
68 | ||
69 | #define AFI_AXI_BAR0_START 0x18 | |
70 | #define AFI_AXI_BAR1_START 0x1c | |
71 | #define AFI_AXI_BAR2_START 0x20 | |
72 | #define AFI_AXI_BAR3_START 0x24 | |
73 | #define AFI_AXI_BAR4_START 0x28 | |
74 | #define AFI_AXI_BAR5_START 0x2c | |
75 | ||
76 | #define AFI_FPCI_BAR0 0x30 | |
77 | #define AFI_FPCI_BAR1 0x34 | |
78 | #define AFI_FPCI_BAR2 0x38 | |
79 | #define AFI_FPCI_BAR3 0x3c | |
80 | #define AFI_FPCI_BAR4 0x40 | |
81 | #define AFI_FPCI_BAR5 0x44 | |
82 | ||
83 | #define AFI_CACHE_BAR0_SZ 0x48 | |
84 | #define AFI_CACHE_BAR0_ST 0x4c | |
85 | #define AFI_CACHE_BAR1_SZ 0x50 | |
86 | #define AFI_CACHE_BAR1_ST 0x54 | |
87 | ||
88 | #define AFI_MSI_BAR_SZ 0x60 | |
89 | #define AFI_MSI_FPCI_BAR_ST 0x64 | |
90 | #define AFI_MSI_AXI_BAR_ST 0x68 | |
91 | ||
92 | #define AFI_MSI_VEC0 0x6c | |
93 | #define AFI_MSI_VEC1 0x70 | |
94 | #define AFI_MSI_VEC2 0x74 | |
95 | #define AFI_MSI_VEC3 0x78 | |
96 | #define AFI_MSI_VEC4 0x7c | |
97 | #define AFI_MSI_VEC5 0x80 | |
98 | #define AFI_MSI_VEC6 0x84 | |
99 | #define AFI_MSI_VEC7 0x88 | |
100 | ||
101 | #define AFI_MSI_EN_VEC0 0x8c | |
102 | #define AFI_MSI_EN_VEC1 0x90 | |
103 | #define AFI_MSI_EN_VEC2 0x94 | |
104 | #define AFI_MSI_EN_VEC3 0x98 | |
105 | #define AFI_MSI_EN_VEC4 0x9c | |
106 | #define AFI_MSI_EN_VEC5 0xa0 | |
107 | #define AFI_MSI_EN_VEC6 0xa4 | |
108 | #define AFI_MSI_EN_VEC7 0xa8 | |
109 | ||
110 | #define AFI_CONFIGURATION 0xac | |
111 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) | |
112 | ||
113 | #define AFI_FPCI_ERROR_MASKS 0xb0 | |
114 | ||
115 | #define AFI_INTR_MASK 0xb4 | |
116 | #define AFI_INTR_MASK_INT_MASK (1 << 0) | |
117 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) | |
118 | ||
119 | #define AFI_INTR_CODE 0xb8 | |
120 | #define AFI_INTR_CODE_MASK 0xf | |
7f1f054b TR |
121 | #define AFI_INTR_INI_SLAVE_ERROR 1 |
122 | #define AFI_INTR_INI_DECODE_ERROR 2 | |
d1523b52 TR |
123 | #define AFI_INTR_TARGET_ABORT 3 |
124 | #define AFI_INTR_MASTER_ABORT 4 | |
125 | #define AFI_INTR_INVALID_WRITE 5 | |
126 | #define AFI_INTR_LEGACY 6 | |
127 | #define AFI_INTR_FPCI_DECODE_ERROR 7 | |
7f1f054b TR |
128 | #define AFI_INTR_AXI_DECODE_ERROR 8 |
129 | #define AFI_INTR_FPCI_TIMEOUT 9 | |
130 | #define AFI_INTR_PE_PRSNT_SENSE 10 | |
131 | #define AFI_INTR_PE_CLKREQ_SENSE 11 | |
132 | #define AFI_INTR_CLKCLAMP_SENSE 12 | |
133 | #define AFI_INTR_RDY4PD_SENSE 13 | |
134 | #define AFI_INTR_P2P_ERROR 14 | |
d1523b52 TR |
135 | |
136 | #define AFI_INTR_SIGNATURE 0xbc | |
137 | #define AFI_UPPER_FPCI_ADDRESS 0xc0 | |
138 | #define AFI_SM_INTR_ENABLE 0xc4 | |
139 | #define AFI_SM_INTR_INTA_ASSERT (1 << 0) | |
140 | #define AFI_SM_INTR_INTB_ASSERT (1 << 1) | |
141 | #define AFI_SM_INTR_INTC_ASSERT (1 << 2) | |
142 | #define AFI_SM_INTR_INTD_ASSERT (1 << 3) | |
143 | #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) | |
144 | #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) | |
145 | #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) | |
146 | #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) | |
147 | ||
148 | #define AFI_AFI_INTR_ENABLE 0xc8 | |
149 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) | |
150 | #define AFI_INTR_EN_INI_DECERR (1 << 1) | |
151 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) | |
152 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) | |
153 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) | |
154 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) | |
155 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) | |
156 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) | |
94716cdd | 157 | #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) |
d1523b52 TR |
158 | |
159 | #define AFI_PCIE_CONFIG 0x0f8 | |
160 | #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) | |
161 | #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe | |
162 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) | |
163 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) | |
94716cdd | 164 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) |
7f1f054b | 165 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) |
d1523b52 | 166 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) |
94716cdd | 167 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) |
7f1f054b | 168 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) |
94716cdd | 169 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) |
d1523b52 TR |
170 | |
171 | #define AFI_FUSE 0x104 | |
172 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) | |
173 | ||
174 | #define AFI_PEX0_CTRL 0x110 | |
175 | #define AFI_PEX1_CTRL 0x118 | |
94716cdd | 176 | #define AFI_PEX2_CTRL 0x128 |
d1523b52 | 177 | #define AFI_PEX_CTRL_RST (1 << 0) |
94716cdd | 178 | #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) |
d1523b52 | 179 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) |
7f1f054b TR |
180 | #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) |
181 | ||
182 | #define AFI_PLLE_CONTROL 0x160 | |
183 | #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) | |
184 | #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) | |
d1523b52 | 185 | |
94716cdd JA |
186 | #define AFI_PEXBIAS_CTRL_0 0x168 |
187 | ||
acb341e9 | 188 | #define RP_VEND_XP 0x00000f00 |
d1523b52 TR |
189 | #define RP_VEND_XP_DL_UP (1 << 30) |
190 | ||
acb341e9 TR |
191 | #define RP_PRIV_MISC 0x00000fe0 |
192 | #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) | |
193 | #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) | |
7f1f054b | 194 | |
d1523b52 TR |
195 | #define RP_LINK_CONTROL_STATUS 0x00000090 |
196 | #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 | |
197 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 | |
198 | ||
acb341e9 | 199 | #define PADS_CTL_SEL 0x0000009c |
d1523b52 | 200 | |
acb341e9 | 201 | #define PADS_CTL 0x000000a0 |
d1523b52 TR |
202 | #define PADS_CTL_IDDQ_1L (1 << 0) |
203 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) | |
204 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) | |
205 | ||
acb341e9 TR |
206 | #define PADS_PLL_CTL_TEGRA20 0x000000b8 |
207 | #define PADS_PLL_CTL_TEGRA30 0x000000b4 | |
d1523b52 TR |
208 | #define PADS_PLL_CTL_RST_B4SM (1 << 1) |
209 | #define PADS_PLL_CTL_LOCKDET (1 << 8) | |
210 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) | |
211 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) | |
212 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) | |
213 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) | |
214 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) | |
215 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) | |
216 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) | |
94716cdd JA |
217 | #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22) |
218 | ||
acb341e9 TR |
219 | #define PADS_REFCLK_CFG0 0x000000c8 |
220 | #define PADS_REFCLK_CFG1 0x000000cc | |
221 | #define PADS_REFCLK_BIAS 0x000000d0 | |
d1523b52 | 222 | |
b02b07ad SW |
223 | /* |
224 | * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit | |
225 | * entries, one entry per PCIe port. These field definitions and desired | |
226 | * values aren't in the TRM, but do come from NVIDIA. | |
227 | */ | |
228 | #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ | |
229 | #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 | |
230 | #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ | |
231 | #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ | |
232 | ||
d1523b52 | 233 | struct tegra_msi { |
c2791b80 | 234 | struct msi_controller chip; |
d1523b52 TR |
235 | DECLARE_BITMAP(used, INT_PCI_MSI_NR); |
236 | struct irq_domain *domain; | |
237 | unsigned long pages; | |
238 | struct mutex lock; | |
239 | int irq; | |
240 | }; | |
241 | ||
94716cdd JA |
242 | /* used to differentiate between Tegra SoC generations */ |
243 | struct tegra_pcie_soc_data { | |
244 | unsigned int num_ports; | |
245 | unsigned int msi_base_shift; | |
246 | u32 pads_pll_ctl; | |
247 | u32 tx_ref_sel; | |
f814430c SW |
248 | u32 pads_refclk_cfg0; |
249 | u32 pads_refclk_cfg1; | |
94716cdd JA |
250 | bool has_pex_clkreq_en; |
251 | bool has_pex_bias_ctrl; | |
252 | bool has_intr_prsnt_sense; | |
94716cdd | 253 | bool has_cml_clk; |
7f1f054b | 254 | bool has_gen2; |
94716cdd JA |
255 | }; |
256 | ||
c2791b80 | 257 | static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) |
d1523b52 TR |
258 | { |
259 | return container_of(chip, struct tegra_msi, chip); | |
260 | } | |
261 | ||
262 | struct tegra_pcie { | |
263 | struct device *dev; | |
264 | ||
265 | void __iomem *pads; | |
266 | void __iomem *afi; | |
267 | int irq; | |
268 | ||
f7625980 | 269 | struct list_head buses; |
d1523b52 TR |
270 | struct resource *cs; |
271 | ||
272 | struct resource io; | |
5106787a | 273 | struct resource pio; |
d1523b52 TR |
274 | struct resource mem; |
275 | struct resource prefetch; | |
276 | struct resource busn; | |
277 | ||
56e75e2a TR |
278 | struct { |
279 | resource_size_t mem; | |
280 | resource_size_t io; | |
281 | } offset; | |
282 | ||
d1523b52 TR |
283 | struct clk *pex_clk; |
284 | struct clk *afi_clk; | |
d1523b52 | 285 | struct clk *pll_e; |
94716cdd | 286 | struct clk *cml_clk; |
d1523b52 | 287 | |
3127a6b2 SW |
288 | struct reset_control *pex_rst; |
289 | struct reset_control *afi_rst; | |
290 | struct reset_control *pcie_xrst; | |
291 | ||
6fe7c187 | 292 | bool legacy_phy; |
7f1f054b TR |
293 | struct phy *phy; |
294 | ||
d1523b52 TR |
295 | struct tegra_msi msi; |
296 | ||
297 | struct list_head ports; | |
d1523b52 TR |
298 | u32 xbar_config; |
299 | ||
077fb158 TR |
300 | struct regulator_bulk_data *supplies; |
301 | unsigned int num_supplies; | |
94716cdd JA |
302 | |
303 | const struct tegra_pcie_soc_data *soc_data; | |
2cb989f6 | 304 | struct dentry *debugfs; |
d1523b52 TR |
305 | }; |
306 | ||
307 | struct tegra_pcie_port { | |
308 | struct tegra_pcie *pcie; | |
6fe7c187 | 309 | struct device_node *np; |
d1523b52 TR |
310 | struct list_head list; |
311 | struct resource regs; | |
312 | void __iomem *base; | |
313 | unsigned int index; | |
314 | unsigned int lanes; | |
6fe7c187 TR |
315 | |
316 | struct phy **phys; | |
d1523b52 TR |
317 | }; |
318 | ||
319 | struct tegra_pcie_bus { | |
320 | struct vm_struct *area; | |
321 | struct list_head list; | |
322 | unsigned int nr; | |
323 | }; | |
324 | ||
325 | static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys) | |
326 | { | |
327 | return sys->private_data; | |
328 | } | |
329 | ||
330 | static inline void afi_writel(struct tegra_pcie *pcie, u32 value, | |
331 | unsigned long offset) | |
332 | { | |
333 | writel(value, pcie->afi + offset); | |
334 | } | |
335 | ||
336 | static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) | |
337 | { | |
338 | return readl(pcie->afi + offset); | |
339 | } | |
340 | ||
341 | static inline void pads_writel(struct tegra_pcie *pcie, u32 value, | |
342 | unsigned long offset) | |
343 | { | |
344 | writel(value, pcie->pads + offset); | |
345 | } | |
346 | ||
347 | static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) | |
348 | { | |
349 | return readl(pcie->pads + offset); | |
350 | } | |
351 | ||
352 | /* | |
353 | * The configuration space mapping on Tegra is somewhat similar to the ECAM | |
354 | * defined by PCIe. However it deviates a bit in how the 4 bits for extended | |
355 | * register accesses are mapped: | |
356 | * | |
357 | * [27:24] extended register number | |
358 | * [23:16] bus number | |
359 | * [15:11] device number | |
360 | * [10: 8] function number | |
361 | * [ 7: 0] register number | |
362 | * | |
363 | * Mapping the whole extended configuration space would require 256 MiB of | |
364 | * virtual address space, only a small part of which will actually be used. | |
365 | * To work around this, a 1 MiB of virtual addresses are allocated per bus | |
366 | * when the bus is first accessed. When the physical range is mapped, the | |
367 | * the bus number bits are hidden so that the extended register number bits | |
368 | * appear as bits [19:16]. Therefore the virtual mapping looks like this: | |
369 | * | |
370 | * [19:16] extended register number | |
371 | * [15:11] device number | |
372 | * [10: 8] function number | |
373 | * [ 7: 0] register number | |
374 | * | |
375 | * This is achieved by stitching together 16 chunks of 64 KiB of physical | |
376 | * address space via the MMU. | |
377 | */ | |
378 | static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where) | |
379 | { | |
380 | return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) | | |
381 | (PCI_FUNC(devfn) << 8) | (where & 0xfc); | |
382 | } | |
383 | ||
384 | static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, | |
385 | unsigned int busnr) | |
386 | { | |
512ee2fd AB |
387 | pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
388 | L_PTE_XN | L_PTE_MT_DEV_SHARED | L_PTE_SHARED); | |
d1523b52 TR |
389 | phys_addr_t cs = pcie->cs->start; |
390 | struct tegra_pcie_bus *bus; | |
391 | unsigned int i; | |
392 | int err; | |
393 | ||
394 | bus = kzalloc(sizeof(*bus), GFP_KERNEL); | |
395 | if (!bus) | |
396 | return ERR_PTR(-ENOMEM); | |
397 | ||
398 | INIT_LIST_HEAD(&bus->list); | |
399 | bus->nr = busnr; | |
400 | ||
401 | /* allocate 1 MiB of virtual addresses */ | |
402 | bus->area = get_vm_area(SZ_1M, VM_IOREMAP); | |
403 | if (!bus->area) { | |
404 | err = -ENOMEM; | |
405 | goto free; | |
406 | } | |
407 | ||
408 | /* map each of the 16 chunks of 64 KiB each */ | |
409 | for (i = 0; i < 16; i++) { | |
410 | unsigned long virt = (unsigned long)bus->area->addr + | |
411 | i * SZ_64K; | |
8d41794c | 412 | phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K; |
d1523b52 TR |
413 | |
414 | err = ioremap_page_range(virt, virt + SZ_64K, phys, prot); | |
415 | if (err < 0) { | |
416 | dev_err(pcie->dev, "ioremap_page_range() failed: %d\n", | |
417 | err); | |
418 | goto unmap; | |
419 | } | |
420 | } | |
421 | ||
422 | return bus; | |
423 | ||
424 | unmap: | |
425 | vunmap(bus->area->addr); | |
426 | free: | |
427 | kfree(bus); | |
428 | return ERR_PTR(err); | |
429 | } | |
430 | ||
b4d18d71 | 431 | static int tegra_pcie_add_bus(struct pci_bus *bus) |
d1523b52 | 432 | { |
b4d18d71 TR |
433 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); |
434 | struct tegra_pcie_bus *b; | |
d1523b52 | 435 | |
b4d18d71 TR |
436 | b = tegra_pcie_bus_alloc(pcie, bus->number); |
437 | if (IS_ERR(b)) | |
438 | return PTR_ERR(b); | |
d1523b52 | 439 | |
b4d18d71 | 440 | list_add_tail(&b->list, &pcie->buses); |
d1523b52 | 441 | |
b4d18d71 TR |
442 | return 0; |
443 | } | |
d1523b52 | 444 | |
b4d18d71 TR |
445 | static void tegra_pcie_remove_bus(struct pci_bus *child) |
446 | { | |
447 | struct tegra_pcie *pcie = sys_to_pcie(child->sysdata); | |
448 | struct tegra_pcie_bus *bus, *tmp; | |
449 | ||
450 | list_for_each_entry_safe(bus, tmp, &pcie->buses, list) { | |
451 | if (bus->nr == child->number) { | |
452 | vunmap(bus->area->addr); | |
453 | list_del(&bus->list); | |
454 | kfree(bus); | |
455 | break; | |
456 | } | |
457 | } | |
d1523b52 TR |
458 | } |
459 | ||
b4d18d71 TR |
460 | static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, |
461 | unsigned int devfn, | |
462 | int where) | |
d1523b52 TR |
463 | { |
464 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); | |
465 | void __iomem *addr = NULL; | |
466 | ||
467 | if (bus->number == 0) { | |
468 | unsigned int slot = PCI_SLOT(devfn); | |
469 | struct tegra_pcie_port *port; | |
470 | ||
471 | list_for_each_entry(port, &pcie->ports, list) { | |
472 | if (port->index + 1 == slot) { | |
473 | addr = port->base + (where & ~3); | |
474 | break; | |
475 | } | |
476 | } | |
477 | } else { | |
b4d18d71 TR |
478 | struct tegra_pcie_bus *b; |
479 | ||
480 | list_for_each_entry(b, &pcie->buses, list) | |
481 | if (b->nr == bus->number) | |
482 | addr = (void __iomem *)b->area->addr; | |
483 | ||
d1523b52 TR |
484 | if (!addr) { |
485 | dev_err(pcie->dev, | |
486 | "failed to map cfg. space for bus %u\n", | |
487 | bus->number); | |
488 | return NULL; | |
489 | } | |
490 | ||
491 | addr += tegra_pcie_conf_offset(devfn, where); | |
492 | } | |
493 | ||
494 | return addr; | |
495 | } | |
496 | ||
d1523b52 | 497 | static struct pci_ops tegra_pcie_ops = { |
b4d18d71 TR |
498 | .add_bus = tegra_pcie_add_bus, |
499 | .remove_bus = tegra_pcie_remove_bus, | |
500 | .map_bus = tegra_pcie_map_bus, | |
0e7ac8de RH |
501 | .read = pci_generic_config_read32, |
502 | .write = pci_generic_config_write32, | |
d1523b52 TR |
503 | }; |
504 | ||
505 | static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) | |
506 | { | |
507 | unsigned long ret = 0; | |
508 | ||
509 | switch (port->index) { | |
510 | case 0: | |
511 | ret = AFI_PEX0_CTRL; | |
512 | break; | |
513 | ||
514 | case 1: | |
515 | ret = AFI_PEX1_CTRL; | |
516 | break; | |
94716cdd JA |
517 | |
518 | case 2: | |
519 | ret = AFI_PEX2_CTRL; | |
520 | break; | |
d1523b52 TR |
521 | } |
522 | ||
523 | return ret; | |
524 | } | |
525 | ||
526 | static void tegra_pcie_port_reset(struct tegra_pcie_port *port) | |
527 | { | |
528 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); | |
529 | unsigned long value; | |
530 | ||
531 | /* pulse reset signal */ | |
532 | value = afi_readl(port->pcie, ctrl); | |
533 | value &= ~AFI_PEX_CTRL_RST; | |
534 | afi_writel(port->pcie, value, ctrl); | |
535 | ||
536 | usleep_range(1000, 2000); | |
537 | ||
538 | value = afi_readl(port->pcie, ctrl); | |
539 | value |= AFI_PEX_CTRL_RST; | |
540 | afi_writel(port->pcie, value, ctrl); | |
541 | } | |
542 | ||
543 | static void tegra_pcie_port_enable(struct tegra_pcie_port *port) | |
544 | { | |
94716cdd | 545 | const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; |
d1523b52 TR |
546 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
547 | unsigned long value; | |
548 | ||
549 | /* enable reference clock */ | |
550 | value = afi_readl(port->pcie, ctrl); | |
551 | value |= AFI_PEX_CTRL_REFCLK_EN; | |
94716cdd JA |
552 | |
553 | if (soc->has_pex_clkreq_en) | |
554 | value |= AFI_PEX_CTRL_CLKREQ_EN; | |
555 | ||
7f1f054b TR |
556 | value |= AFI_PEX_CTRL_OVERRIDE_EN; |
557 | ||
d1523b52 TR |
558 | afi_writel(port->pcie, value, ctrl); |
559 | ||
560 | tegra_pcie_port_reset(port); | |
561 | } | |
562 | ||
563 | static void tegra_pcie_port_disable(struct tegra_pcie_port *port) | |
564 | { | |
0d20d621 | 565 | const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; |
d1523b52 TR |
566 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
567 | unsigned long value; | |
568 | ||
569 | /* assert port reset */ | |
570 | value = afi_readl(port->pcie, ctrl); | |
571 | value &= ~AFI_PEX_CTRL_RST; | |
572 | afi_writel(port->pcie, value, ctrl); | |
573 | ||
574 | /* disable reference clock */ | |
575 | value = afi_readl(port->pcie, ctrl); | |
0d20d621 TR |
576 | |
577 | if (soc->has_pex_clkreq_en) | |
578 | value &= ~AFI_PEX_CTRL_CLKREQ_EN; | |
579 | ||
d1523b52 TR |
580 | value &= ~AFI_PEX_CTRL_REFCLK_EN; |
581 | afi_writel(port->pcie, value, ctrl); | |
582 | } | |
583 | ||
584 | static void tegra_pcie_port_free(struct tegra_pcie_port *port) | |
585 | { | |
586 | struct tegra_pcie *pcie = port->pcie; | |
587 | ||
588 | devm_iounmap(pcie->dev, port->base); | |
589 | devm_release_mem_region(pcie->dev, port->regs.start, | |
590 | resource_size(&port->regs)); | |
591 | list_del(&port->list); | |
592 | devm_kfree(pcie->dev, port); | |
593 | } | |
594 | ||
d1523b52 TR |
595 | /* Tegra PCIE root complex wrongly reports device class */ |
596 | static void tegra_pcie_fixup_class(struct pci_dev *dev) | |
597 | { | |
598 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
599 | } | |
600 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); | |
601 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); | |
94716cdd JA |
602 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class); |
603 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class); | |
d1523b52 TR |
604 | |
605 | /* Tegra PCIE requires relaxed ordering */ | |
606 | static void tegra_pcie_relax_enable(struct pci_dev *dev) | |
607 | { | |
608 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); | |
609 | } | |
610 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); | |
611 | ||
612 | static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) | |
613 | { | |
614 | struct tegra_pcie *pcie = sys_to_pcie(sys); | |
41534e53 TR |
615 | int err; |
616 | ||
56e75e2a TR |
617 | sys->mem_offset = pcie->offset.mem; |
618 | sys->io_offset = pcie->offset.io; | |
619 | ||
c4102c92 | 620 | err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->io); |
41534e53 TR |
621 | if (err < 0) |
622 | return err; | |
623 | ||
56e75e2a | 624 | pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset); |
d1523b52 TR |
625 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); |
626 | pci_add_resource_offset(&sys->resources, &pcie->prefetch, | |
627 | sys->mem_offset); | |
628 | pci_add_resource(&sys->resources, &pcie->busn); | |
629 | ||
45c64b6a BH |
630 | err = devm_request_pci_bus_resources(pcie->dev, &sys->resources); |
631 | if (err < 0) | |
632 | return err; | |
d1523b52 | 633 | |
ea1f4e9d | 634 | pci_remap_iospace(&pcie->pio, pcie->io.start); |
d1523b52 TR |
635 | return 1; |
636 | } | |
637 | ||
638 | static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) | |
639 | { | |
640 | struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata); | |
f5d3352b | 641 | int irq; |
d1523b52 | 642 | |
b4f17375 SW |
643 | tegra_cpuidle_pcie_irqs_in_use(); |
644 | ||
f5d3352b LS |
645 | irq = of_irq_parse_and_map_pci(pdev, slot, pin); |
646 | if (!irq) | |
647 | irq = pcie->irq; | |
648 | ||
649 | return irq; | |
d1523b52 TR |
650 | } |
651 | ||
d1523b52 TR |
652 | static irqreturn_t tegra_pcie_isr(int irq, void *arg) |
653 | { | |
654 | const char *err_msg[] = { | |
655 | "Unknown", | |
656 | "AXI slave error", | |
657 | "AXI decode error", | |
658 | "Target abort", | |
659 | "Master abort", | |
660 | "Invalid write", | |
7f1f054b | 661 | "Legacy interrupt", |
d1523b52 TR |
662 | "Response decoding error", |
663 | "AXI response decoding error", | |
664 | "Transaction timeout", | |
7f1f054b TR |
665 | "Slot present pin change", |
666 | "Slot clock request change", | |
667 | "TMS clock ramp change", | |
668 | "TMS ready for power down", | |
669 | "Peer2Peer error", | |
d1523b52 TR |
670 | }; |
671 | struct tegra_pcie *pcie = arg; | |
672 | u32 code, signature; | |
673 | ||
674 | code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; | |
675 | signature = afi_readl(pcie, AFI_INTR_SIGNATURE); | |
676 | afi_writel(pcie, 0, AFI_INTR_CODE); | |
677 | ||
678 | if (code == AFI_INTR_LEGACY) | |
679 | return IRQ_NONE; | |
680 | ||
681 | if (code >= ARRAY_SIZE(err_msg)) | |
682 | code = 0; | |
683 | ||
684 | /* | |
685 | * do not pollute kernel log with master abort reports since they | |
686 | * happen a lot during enumeration | |
687 | */ | |
688 | if (code == AFI_INTR_MASTER_ABORT) | |
689 | dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code], | |
690 | signature); | |
691 | else | |
692 | dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code], | |
693 | signature); | |
694 | ||
695 | if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT || | |
696 | code == AFI_INTR_FPCI_DECODE_ERROR) { | |
697 | u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff; | |
698 | u64 address = (u64)fpci << 32 | (signature & 0xfffffffc); | |
699 | ||
700 | if (code == AFI_INTR_MASTER_ABORT) | |
701 | dev_dbg(pcie->dev, " FPCI address: %10llx\n", address); | |
702 | else | |
703 | dev_err(pcie->dev, " FPCI address: %10llx\n", address); | |
704 | } | |
705 | ||
706 | return IRQ_HANDLED; | |
707 | } | |
708 | ||
709 | /* | |
710 | * FPCI map is as follows: | |
711 | * - 0xfdfc000000: I/O space | |
712 | * - 0xfdfe000000: type 0 configuration space | |
713 | * - 0xfdff000000: type 1 configuration space | |
714 | * - 0xfe00000000: type 0 extended configuration space | |
715 | * - 0xfe10000000: type 1 extended configuration space | |
716 | */ | |
717 | static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) | |
718 | { | |
719 | u32 fpci_bar, size, axi_address; | |
720 | ||
721 | /* Bar 0: type 1 extended configuration space */ | |
722 | fpci_bar = 0xfe100000; | |
723 | size = resource_size(pcie->cs); | |
724 | axi_address = pcie->cs->start; | |
725 | afi_writel(pcie, axi_address, AFI_AXI_BAR0_START); | |
726 | afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); | |
727 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0); | |
728 | ||
729 | /* Bar 1: downstream IO bar */ | |
730 | fpci_bar = 0xfdfc0000; | |
731 | size = resource_size(&pcie->io); | |
5106787a | 732 | axi_address = pcie->io.start; |
d1523b52 TR |
733 | afi_writel(pcie, axi_address, AFI_AXI_BAR1_START); |
734 | afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); | |
735 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1); | |
736 | ||
737 | /* Bar 2: prefetchable memory BAR */ | |
738 | fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
739 | size = resource_size(&pcie->prefetch); | |
740 | axi_address = pcie->prefetch.start; | |
741 | afi_writel(pcie, axi_address, AFI_AXI_BAR2_START); | |
742 | afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); | |
743 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2); | |
744 | ||
745 | /* Bar 3: non prefetchable memory BAR */ | |
746 | fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
747 | size = resource_size(&pcie->mem); | |
748 | axi_address = pcie->mem.start; | |
749 | afi_writel(pcie, axi_address, AFI_AXI_BAR3_START); | |
750 | afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); | |
751 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3); | |
752 | ||
753 | /* NULL out the remaining BARs as they are not used */ | |
754 | afi_writel(pcie, 0, AFI_AXI_BAR4_START); | |
755 | afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); | |
756 | afi_writel(pcie, 0, AFI_FPCI_BAR4); | |
757 | ||
758 | afi_writel(pcie, 0, AFI_AXI_BAR5_START); | |
759 | afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); | |
760 | afi_writel(pcie, 0, AFI_FPCI_BAR5); | |
761 | ||
762 | /* map all upstream transactions as uncached */ | |
e32faa30 | 763 | afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); |
d1523b52 TR |
764 | afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); |
765 | afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); | |
766 | afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); | |
767 | ||
768 | /* MSI translations are setup only when needed */ | |
769 | afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); | |
770 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
771 | afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); | |
772 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
773 | } | |
774 | ||
7f1f054b | 775 | static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) |
d1523b52 | 776 | { |
94716cdd | 777 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
7f1f054b | 778 | u32 value; |
d1523b52 | 779 | |
7f1f054b | 780 | timeout = jiffies + msecs_to_jiffies(timeout); |
94716cdd | 781 | |
7f1f054b TR |
782 | while (time_before(jiffies, timeout)) { |
783 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
784 | if (value & PADS_PLL_CTL_LOCKDET) | |
785 | return 0; | |
786 | } | |
d1523b52 | 787 | |
7f1f054b TR |
788 | return -ETIMEDOUT; |
789 | } | |
d1523b52 | 790 | |
7f1f054b TR |
791 | static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) |
792 | { | |
793 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; | |
794 | u32 value; | |
795 | int err; | |
d1523b52 | 796 | |
f7625980 | 797 | /* initialize internal PHY, enable up to 16 PCIE lanes */ |
d1523b52 TR |
798 | pads_writel(pcie, 0x0, PADS_CTL_SEL); |
799 | ||
800 | /* override IDDQ to 1 on all 4 lanes */ | |
801 | value = pads_readl(pcie, PADS_CTL); | |
802 | value |= PADS_CTL_IDDQ_1L; | |
803 | pads_writel(pcie, value, PADS_CTL); | |
804 | ||
805 | /* | |
806 | * Set up PHY PLL inputs select PLLE output as refclock, | |
807 | * set TX ref sel to div10 (not div5). | |
808 | */ | |
94716cdd | 809 | value = pads_readl(pcie, soc->pads_pll_ctl); |
d1523b52 | 810 | value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); |
94716cdd JA |
811 | value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; |
812 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
d1523b52 | 813 | |
ec732762 EY |
814 | /* reset PLL */ |
815 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
816 | value &= ~PADS_PLL_CTL_RST_B4SM; | |
817 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
818 | ||
819 | usleep_range(20, 100); | |
820 | ||
d1523b52 | 821 | /* take PLL out of reset */ |
94716cdd | 822 | value = pads_readl(pcie, soc->pads_pll_ctl); |
d1523b52 | 823 | value |= PADS_PLL_CTL_RST_B4SM; |
94716cdd | 824 | pads_writel(pcie, value, soc->pads_pll_ctl); |
d1523b52 | 825 | |
d1523b52 | 826 | /* wait for the PLL to lock */ |
7f1f054b TR |
827 | err = tegra_pcie_pll_wait(pcie, 500); |
828 | if (err < 0) { | |
829 | dev_err(pcie->dev, "PLL failed to lock: %d\n", err); | |
830 | return err; | |
831 | } | |
d1523b52 TR |
832 | |
833 | /* turn off IDDQ override */ | |
834 | value = pads_readl(pcie, PADS_CTL); | |
835 | value &= ~PADS_CTL_IDDQ_1L; | |
836 | pads_writel(pcie, value, PADS_CTL); | |
837 | ||
838 | /* enable TX/RX data */ | |
839 | value = pads_readl(pcie, PADS_CTL); | |
840 | value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; | |
841 | pads_writel(pcie, value, PADS_CTL); | |
842 | ||
7f1f054b TR |
843 | return 0; |
844 | } | |
845 | ||
6fe7c187 TR |
846 | static int tegra_pcie_phy_disable(struct tegra_pcie *pcie) |
847 | { | |
848 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; | |
849 | u32 value; | |
850 | ||
851 | /* disable TX/RX data */ | |
852 | value = pads_readl(pcie, PADS_CTL); | |
853 | value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L); | |
854 | pads_writel(pcie, value, PADS_CTL); | |
855 | ||
856 | /* override IDDQ */ | |
857 | value = pads_readl(pcie, PADS_CTL); | |
858 | value |= PADS_CTL_IDDQ_1L; | |
859 | pads_writel(pcie, PADS_CTL, value); | |
860 | ||
861 | /* reset PLL */ | |
862 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
863 | value &= ~PADS_PLL_CTL_RST_B4SM; | |
864 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
865 | ||
866 | usleep_range(20, 100); | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
871 | static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port) | |
872 | { | |
873 | struct device *dev = port->pcie->dev; | |
874 | unsigned int i; | |
875 | int err; | |
876 | ||
877 | for (i = 0; i < port->lanes; i++) { | |
878 | err = phy_power_on(port->phys[i]); | |
879 | if (err < 0) { | |
880 | dev_err(dev, "failed to power on PHY#%u: %d\n", i, | |
881 | err); | |
882 | return err; | |
883 | } | |
884 | } | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
889 | static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port) | |
890 | { | |
891 | struct device *dev = port->pcie->dev; | |
892 | unsigned int i; | |
893 | int err; | |
894 | ||
895 | for (i = 0; i < port->lanes; i++) { | |
896 | err = phy_power_off(port->phys[i]); | |
897 | if (err < 0) { | |
898 | dev_err(dev, "failed to power off PHY#%u: %d\n", i, | |
899 | err); | |
900 | return err; | |
901 | } | |
902 | } | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) | |
908 | { | |
cf5d3180 | 909 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
6fe7c187 TR |
910 | struct tegra_pcie_port *port; |
911 | int err; | |
912 | ||
913 | if (pcie->legacy_phy) { | |
914 | if (pcie->phy) | |
915 | err = phy_power_on(pcie->phy); | |
916 | else | |
917 | err = tegra_pcie_phy_enable(pcie); | |
918 | ||
919 | if (err < 0) | |
920 | dev_err(pcie->dev, "failed to power on PHY: %d\n", err); | |
921 | ||
922 | return err; | |
923 | } | |
924 | ||
925 | list_for_each_entry(port, &pcie->ports, list) { | |
926 | err = tegra_pcie_port_phy_power_on(port); | |
927 | if (err < 0) { | |
928 | dev_err(pcie->dev, | |
929 | "failed to power on PCIe port %u PHY: %d\n", | |
930 | port->index, err); | |
931 | return err; | |
932 | } | |
933 | } | |
934 | ||
cf5d3180 | 935 | /* Configure the reference clock driver */ |
f814430c | 936 | pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); |
cf5d3180 SW |
937 | |
938 | if (soc->num_ports > 2) | |
f814430c | 939 | pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); |
cf5d3180 | 940 | |
6fe7c187 TR |
941 | return 0; |
942 | } | |
943 | ||
944 | static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie) | |
945 | { | |
946 | struct tegra_pcie_port *port; | |
947 | int err; | |
948 | ||
949 | if (pcie->legacy_phy) { | |
950 | if (pcie->phy) | |
951 | err = phy_power_off(pcie->phy); | |
952 | else | |
953 | err = tegra_pcie_phy_disable(pcie); | |
954 | ||
955 | if (err < 0) | |
956 | dev_err(pcie->dev, "failed to power off PHY: %d\n", | |
957 | err); | |
958 | ||
959 | return err; | |
960 | } | |
961 | ||
962 | list_for_each_entry(port, &pcie->ports, list) { | |
963 | err = tegra_pcie_port_phy_power_off(port); | |
964 | if (err < 0) { | |
965 | dev_err(pcie->dev, | |
966 | "failed to power off PCIe port %u PHY: %d\n", | |
967 | port->index, err); | |
968 | return err; | |
969 | } | |
970 | } | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
7f1f054b TR |
975 | static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) |
976 | { | |
977 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; | |
978 | struct tegra_pcie_port *port; | |
979 | unsigned long value; | |
980 | int err; | |
981 | ||
982 | /* enable PLL power down */ | |
983 | if (pcie->phy) { | |
984 | value = afi_readl(pcie, AFI_PLLE_CONTROL); | |
985 | value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; | |
986 | value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; | |
987 | afi_writel(pcie, value, AFI_PLLE_CONTROL); | |
988 | } | |
989 | ||
990 | /* power down PCIe slot clock bias pad */ | |
991 | if (soc->has_pex_bias_ctrl) | |
992 | afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); | |
993 | ||
994 | /* configure mode and disable all ports */ | |
995 | value = afi_readl(pcie, AFI_PCIE_CONFIG); | |
996 | value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; | |
997 | value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; | |
998 | ||
999 | list_for_each_entry(port, &pcie->ports, list) | |
1000 | value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); | |
1001 | ||
1002 | afi_writel(pcie, value, AFI_PCIE_CONFIG); | |
1003 | ||
1004 | if (soc->has_gen2) { | |
1005 | value = afi_readl(pcie, AFI_FUSE); | |
1006 | value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; | |
1007 | afi_writel(pcie, value, AFI_FUSE); | |
1008 | } else { | |
1009 | value = afi_readl(pcie, AFI_FUSE); | |
1010 | value |= AFI_FUSE_PCIE_T0_GEN2_DIS; | |
1011 | afi_writel(pcie, value, AFI_FUSE); | |
1012 | } | |
1013 | ||
6fe7c187 | 1014 | err = tegra_pcie_phy_power_on(pcie); |
7f1f054b | 1015 | if (err < 0) { |
6fe7c187 | 1016 | dev_err(pcie->dev, "failed to power on PHY(s): %d\n", err); |
7f1f054b TR |
1017 | return err; |
1018 | } | |
1019 | ||
d1523b52 | 1020 | /* take the PCIe interface module out of reset */ |
3127a6b2 | 1021 | reset_control_deassert(pcie->pcie_xrst); |
d1523b52 TR |
1022 | |
1023 | /* finally enable PCIe */ | |
1024 | value = afi_readl(pcie, AFI_CONFIGURATION); | |
1025 | value |= AFI_CONFIGURATION_EN_FPCI; | |
1026 | afi_writel(pcie, value, AFI_CONFIGURATION); | |
1027 | ||
1028 | value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | | |
1029 | AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | | |
1030 | AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR; | |
94716cdd JA |
1031 | |
1032 | if (soc->has_intr_prsnt_sense) | |
1033 | value |= AFI_INTR_EN_PRSNT_SENSE; | |
1034 | ||
d1523b52 TR |
1035 | afi_writel(pcie, value, AFI_AFI_INTR_ENABLE); |
1036 | afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE); | |
1037 | ||
1038 | /* don't enable MSI for now, only when needed */ | |
1039 | afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); | |
1040 | ||
1041 | /* disable all exceptions */ | |
1042 | afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | static void tegra_pcie_power_off(struct tegra_pcie *pcie) | |
1048 | { | |
1049 | int err; | |
1050 | ||
1051 | /* TODO: disable and unprepare clocks? */ | |
1052 | ||
6fe7c187 | 1053 | err = tegra_pcie_phy_power_off(pcie); |
7f1f054b | 1054 | if (err < 0) |
6fe7c187 | 1055 | dev_err(pcie->dev, "failed to power off PHY(s): %d\n", err); |
7f1f054b | 1056 | |
3127a6b2 SW |
1057 | reset_control_assert(pcie->pcie_xrst); |
1058 | reset_control_assert(pcie->afi_rst); | |
1059 | reset_control_assert(pcie->pex_rst); | |
d1523b52 TR |
1060 | |
1061 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | |
1062 | ||
077fb158 | 1063 | err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); |
d1523b52 | 1064 | if (err < 0) |
077fb158 | 1065 | dev_warn(pcie->dev, "failed to disable regulators: %d\n", err); |
d1523b52 TR |
1066 | } |
1067 | ||
1068 | static int tegra_pcie_power_on(struct tegra_pcie *pcie) | |
1069 | { | |
94716cdd | 1070 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
1071 | int err; |
1072 | ||
3127a6b2 SW |
1073 | reset_control_assert(pcie->pcie_xrst); |
1074 | reset_control_assert(pcie->afi_rst); | |
1075 | reset_control_assert(pcie->pex_rst); | |
d1523b52 TR |
1076 | |
1077 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | |
1078 | ||
1079 | /* enable regulators */ | |
077fb158 TR |
1080 | err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); |
1081 | if (err < 0) | |
1082 | dev_err(pcie->dev, "failed to enable regulators: %d\n", err); | |
94716cdd | 1083 | |
d1523b52 | 1084 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, |
80b28791 SW |
1085 | pcie->pex_clk, |
1086 | pcie->pex_rst); | |
d1523b52 TR |
1087 | if (err) { |
1088 | dev_err(pcie->dev, "powerup sequence failed: %d\n", err); | |
1089 | return err; | |
1090 | } | |
1091 | ||
3127a6b2 | 1092 | reset_control_deassert(pcie->afi_rst); |
d1523b52 TR |
1093 | |
1094 | err = clk_prepare_enable(pcie->afi_clk); | |
1095 | if (err < 0) { | |
1096 | dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err); | |
1097 | return err; | |
1098 | } | |
1099 | ||
94716cdd JA |
1100 | if (soc->has_cml_clk) { |
1101 | err = clk_prepare_enable(pcie->cml_clk); | |
1102 | if (err < 0) { | |
1103 | dev_err(pcie->dev, "failed to enable CML clock: %d\n", | |
1104 | err); | |
1105 | return err; | |
1106 | } | |
1107 | } | |
1108 | ||
d1523b52 TR |
1109 | err = clk_prepare_enable(pcie->pll_e); |
1110 | if (err < 0) { | |
1111 | dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err); | |
1112 | return err; | |
1113 | } | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static int tegra_pcie_clocks_get(struct tegra_pcie *pcie) | |
1119 | { | |
94716cdd JA |
1120 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
1121 | ||
d1523b52 TR |
1122 | pcie->pex_clk = devm_clk_get(pcie->dev, "pex"); |
1123 | if (IS_ERR(pcie->pex_clk)) | |
1124 | return PTR_ERR(pcie->pex_clk); | |
1125 | ||
1126 | pcie->afi_clk = devm_clk_get(pcie->dev, "afi"); | |
1127 | if (IS_ERR(pcie->afi_clk)) | |
1128 | return PTR_ERR(pcie->afi_clk); | |
1129 | ||
d1523b52 TR |
1130 | pcie->pll_e = devm_clk_get(pcie->dev, "pll_e"); |
1131 | if (IS_ERR(pcie->pll_e)) | |
1132 | return PTR_ERR(pcie->pll_e); | |
1133 | ||
94716cdd JA |
1134 | if (soc->has_cml_clk) { |
1135 | pcie->cml_clk = devm_clk_get(pcie->dev, "cml"); | |
1136 | if (IS_ERR(pcie->cml_clk)) | |
1137 | return PTR_ERR(pcie->cml_clk); | |
1138 | } | |
1139 | ||
d1523b52 TR |
1140 | return 0; |
1141 | } | |
1142 | ||
3127a6b2 SW |
1143 | static int tegra_pcie_resets_get(struct tegra_pcie *pcie) |
1144 | { | |
1145 | pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex"); | |
1146 | if (IS_ERR(pcie->pex_rst)) | |
1147 | return PTR_ERR(pcie->pex_rst); | |
1148 | ||
1149 | pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi"); | |
1150 | if (IS_ERR(pcie->afi_rst)) | |
1151 | return PTR_ERR(pcie->afi_rst); | |
1152 | ||
1153 | pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x"); | |
1154 | if (IS_ERR(pcie->pcie_xrst)) | |
1155 | return PTR_ERR(pcie->pcie_xrst); | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
6fe7c187 TR |
1160 | static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie) |
1161 | { | |
1162 | int err; | |
1163 | ||
1164 | pcie->phy = devm_phy_optional_get(pcie->dev, "pcie"); | |
1165 | if (IS_ERR(pcie->phy)) { | |
1166 | err = PTR_ERR(pcie->phy); | |
1167 | dev_err(pcie->dev, "failed to get PHY: %d\n", err); | |
1168 | return err; | |
1169 | } | |
1170 | ||
1171 | err = phy_init(pcie->phy); | |
1172 | if (err < 0) { | |
1173 | dev_err(pcie->dev, "failed to initialize PHY: %d\n", err); | |
1174 | return err; | |
1175 | } | |
1176 | ||
1177 | pcie->legacy_phy = true; | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | static struct phy *devm_of_phy_optional_get_index(struct device *dev, | |
1183 | struct device_node *np, | |
1184 | const char *consumer, | |
1185 | unsigned int index) | |
1186 | { | |
1187 | struct phy *phy; | |
1188 | char *name; | |
1189 | ||
1190 | name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index); | |
1191 | if (!name) | |
1192 | return ERR_PTR(-ENOMEM); | |
1193 | ||
1194 | phy = devm_of_phy_get(dev, np, name); | |
1195 | kfree(name); | |
1196 | ||
1197 | if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV) | |
1198 | phy = NULL; | |
1199 | ||
1200 | return phy; | |
1201 | } | |
1202 | ||
1203 | static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port) | |
1204 | { | |
1205 | struct device *dev = port->pcie->dev; | |
1206 | struct phy *phy; | |
1207 | unsigned int i; | |
1208 | int err; | |
1209 | ||
1210 | port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL); | |
1211 | if (!port->phys) | |
1212 | return -ENOMEM; | |
1213 | ||
1214 | for (i = 0; i < port->lanes; i++) { | |
1215 | phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i); | |
1216 | if (IS_ERR(phy)) { | |
1217 | dev_err(dev, "failed to get PHY#%u: %ld\n", i, | |
1218 | PTR_ERR(phy)); | |
1219 | return PTR_ERR(phy); | |
1220 | } | |
1221 | ||
1222 | err = phy_init(phy); | |
1223 | if (err < 0) { | |
1224 | dev_err(dev, "failed to initialize PHY#%u: %d\n", i, | |
1225 | err); | |
1226 | return err; | |
1227 | } | |
1228 | ||
1229 | port->phys[i] = phy; | |
1230 | } | |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | static int tegra_pcie_phys_get(struct tegra_pcie *pcie) | |
1236 | { | |
1237 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; | |
1238 | struct device_node *np = pcie->dev->of_node; | |
1239 | struct tegra_pcie_port *port; | |
1240 | int err; | |
1241 | ||
1242 | if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL) | |
1243 | return tegra_pcie_phys_get_legacy(pcie); | |
1244 | ||
1245 | list_for_each_entry(port, &pcie->ports, list) { | |
1246 | err = tegra_pcie_port_get_phys(port); | |
1247 | if (err < 0) | |
1248 | return err; | |
1249 | } | |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | ||
d1523b52 TR |
1254 | static int tegra_pcie_get_resources(struct tegra_pcie *pcie) |
1255 | { | |
1256 | struct platform_device *pdev = to_platform_device(pcie->dev); | |
1257 | struct resource *pads, *afi, *res; | |
1258 | int err; | |
1259 | ||
1260 | err = tegra_pcie_clocks_get(pcie); | |
1261 | if (err) { | |
1262 | dev_err(&pdev->dev, "failed to get clocks: %d\n", err); | |
1263 | return err; | |
1264 | } | |
1265 | ||
3127a6b2 SW |
1266 | err = tegra_pcie_resets_get(pcie); |
1267 | if (err) { | |
1268 | dev_err(&pdev->dev, "failed to get resets: %d\n", err); | |
1269 | return err; | |
1270 | } | |
1271 | ||
6fe7c187 | 1272 | err = tegra_pcie_phys_get(pcie); |
7f1f054b | 1273 | if (err < 0) { |
6fe7c187 | 1274 | dev_err(&pdev->dev, "failed to get PHYs: %d\n", err); |
7f1f054b TR |
1275 | return err; |
1276 | } | |
1277 | ||
d1523b52 TR |
1278 | err = tegra_pcie_power_on(pcie); |
1279 | if (err) { | |
1280 | dev_err(&pdev->dev, "failed to power up: %d\n", err); | |
1281 | return err; | |
1282 | } | |
1283 | ||
d1523b52 | 1284 | pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); |
dc05ee32 JL |
1285 | pcie->pads = devm_ioremap_resource(&pdev->dev, pads); |
1286 | if (IS_ERR(pcie->pads)) { | |
1287 | err = PTR_ERR(pcie->pads); | |
d1523b52 TR |
1288 | goto poweroff; |
1289 | } | |
1290 | ||
1291 | afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi"); | |
dc05ee32 JL |
1292 | pcie->afi = devm_ioremap_resource(&pdev->dev, afi); |
1293 | if (IS_ERR(pcie->afi)) { | |
1294 | err = PTR_ERR(pcie->afi); | |
d1523b52 TR |
1295 | goto poweroff; |
1296 | } | |
1297 | ||
dc05ee32 | 1298 | /* request configuration space, but remap later, on demand */ |
d1523b52 TR |
1299 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs"); |
1300 | if (!res) { | |
1301 | err = -EADDRNOTAVAIL; | |
1302 | goto poweroff; | |
1303 | } | |
1304 | ||
1305 | pcie->cs = devm_request_mem_region(pcie->dev, res->start, | |
1306 | resource_size(res), res->name); | |
1307 | if (!pcie->cs) { | |
1308 | err = -EADDRNOTAVAIL; | |
1309 | goto poweroff; | |
1310 | } | |
1311 | ||
1312 | /* request interrupt */ | |
1313 | err = platform_get_irq_byname(pdev, "intr"); | |
1314 | if (err < 0) { | |
1315 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); | |
1316 | goto poweroff; | |
1317 | } | |
1318 | ||
1319 | pcie->irq = err; | |
1320 | ||
1321 | err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); | |
1322 | if (err) { | |
1323 | dev_err(&pdev->dev, "failed to register IRQ: %d\n", err); | |
1324 | goto poweroff; | |
1325 | } | |
1326 | ||
1327 | return 0; | |
1328 | ||
1329 | poweroff: | |
1330 | tegra_pcie_power_off(pcie); | |
1331 | return err; | |
1332 | } | |
1333 | ||
1334 | static int tegra_pcie_put_resources(struct tegra_pcie *pcie) | |
1335 | { | |
7f1f054b TR |
1336 | int err; |
1337 | ||
d1523b52 TR |
1338 | if (pcie->irq > 0) |
1339 | free_irq(pcie->irq, pcie); | |
1340 | ||
1341 | tegra_pcie_power_off(pcie); | |
7f1f054b TR |
1342 | |
1343 | err = phy_exit(pcie->phy); | |
1344 | if (err < 0) | |
1345 | dev_err(pcie->dev, "failed to teardown PHY: %d\n", err); | |
1346 | ||
d1523b52 TR |
1347 | return 0; |
1348 | } | |
1349 | ||
1350 | static int tegra_msi_alloc(struct tegra_msi *chip) | |
1351 | { | |
1352 | int msi; | |
1353 | ||
1354 | mutex_lock(&chip->lock); | |
1355 | ||
1356 | msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); | |
1357 | if (msi < INT_PCI_MSI_NR) | |
1358 | set_bit(msi, chip->used); | |
1359 | else | |
1360 | msi = -ENOSPC; | |
1361 | ||
1362 | mutex_unlock(&chip->lock); | |
1363 | ||
1364 | return msi; | |
1365 | } | |
1366 | ||
1367 | static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq) | |
1368 | { | |
1369 | struct device *dev = chip->chip.dev; | |
1370 | ||
1371 | mutex_lock(&chip->lock); | |
1372 | ||
1373 | if (!test_bit(irq, chip->used)) | |
1374 | dev_err(dev, "trying to free unused MSI#%lu\n", irq); | |
1375 | else | |
1376 | clear_bit(irq, chip->used); | |
1377 | ||
1378 | mutex_unlock(&chip->lock); | |
1379 | } | |
1380 | ||
1381 | static irqreturn_t tegra_pcie_msi_irq(int irq, void *data) | |
1382 | { | |
1383 | struct tegra_pcie *pcie = data; | |
1384 | struct tegra_msi *msi = &pcie->msi; | |
1385 | unsigned int i, processed = 0; | |
1386 | ||
1387 | for (i = 0; i < 8; i++) { | |
1388 | unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); | |
1389 | ||
1390 | while (reg) { | |
1391 | unsigned int offset = find_first_bit(®, 32); | |
1392 | unsigned int index = i * 32 + offset; | |
1393 | unsigned int irq; | |
1394 | ||
1395 | /* clear the interrupt */ | |
1396 | afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4); | |
1397 | ||
1398 | irq = irq_find_mapping(msi->domain, index); | |
1399 | if (irq) { | |
1400 | if (test_bit(index, msi->used)) | |
1401 | generic_handle_irq(irq); | |
1402 | else | |
1403 | dev_info(pcie->dev, "unhandled MSI\n"); | |
1404 | } else { | |
1405 | /* | |
1406 | * that's weird who triggered this? | |
1407 | * just clear it | |
1408 | */ | |
1409 | dev_info(pcie->dev, "unexpected MSI\n"); | |
1410 | } | |
1411 | ||
1412 | /* see if there's any more pending in this vector */ | |
1413 | reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); | |
1414 | ||
1415 | processed++; | |
1416 | } | |
1417 | } | |
1418 | ||
1419 | return processed > 0 ? IRQ_HANDLED : IRQ_NONE; | |
1420 | } | |
1421 | ||
c2791b80 YW |
1422 | static int tegra_msi_setup_irq(struct msi_controller *chip, |
1423 | struct pci_dev *pdev, struct msi_desc *desc) | |
d1523b52 TR |
1424 | { |
1425 | struct tegra_msi *msi = to_tegra_msi(chip); | |
1426 | struct msi_msg msg; | |
1427 | unsigned int irq; | |
1428 | int hwirq; | |
1429 | ||
1430 | hwirq = tegra_msi_alloc(msi); | |
1431 | if (hwirq < 0) | |
1432 | return hwirq; | |
1433 | ||
1434 | irq = irq_create_mapping(msi->domain, hwirq); | |
019fa46e JZ |
1435 | if (!irq) { |
1436 | tegra_msi_free(msi, hwirq); | |
d1523b52 | 1437 | return -EINVAL; |
019fa46e | 1438 | } |
d1523b52 TR |
1439 | |
1440 | irq_set_msi_desc(irq, desc); | |
1441 | ||
1442 | msg.address_lo = virt_to_phys((void *)msi->pages); | |
1443 | /* 32 bit address only */ | |
1444 | msg.address_hi = 0; | |
1445 | msg.data = hwirq; | |
1446 | ||
83a18912 | 1447 | pci_write_msi_msg(irq, &msg); |
d1523b52 TR |
1448 | |
1449 | return 0; | |
1450 | } | |
1451 | ||
c2791b80 YW |
1452 | static void tegra_msi_teardown_irq(struct msi_controller *chip, |
1453 | unsigned int irq) | |
d1523b52 TR |
1454 | { |
1455 | struct tegra_msi *msi = to_tegra_msi(chip); | |
1456 | struct irq_data *d = irq_get_irq_data(irq); | |
019fa46e | 1457 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
d1523b52 | 1458 | |
019fa46e JZ |
1459 | irq_dispose_mapping(irq); |
1460 | tegra_msi_free(msi, hwirq); | |
d1523b52 TR |
1461 | } |
1462 | ||
1463 | static struct irq_chip tegra_msi_irq_chip = { | |
1464 | .name = "Tegra PCIe MSI", | |
280510f1 TG |
1465 | .irq_enable = pci_msi_unmask_irq, |
1466 | .irq_disable = pci_msi_mask_irq, | |
1467 | .irq_mask = pci_msi_mask_irq, | |
1468 | .irq_unmask = pci_msi_unmask_irq, | |
d1523b52 TR |
1469 | }; |
1470 | ||
1471 | static int tegra_msi_map(struct irq_domain *domain, unsigned int irq, | |
1472 | irq_hw_number_t hwirq) | |
1473 | { | |
1474 | irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq); | |
1475 | irq_set_chip_data(irq, domain->host_data); | |
d1523b52 | 1476 | |
b4f17375 SW |
1477 | tegra_cpuidle_pcie_irqs_in_use(); |
1478 | ||
d1523b52 TR |
1479 | return 0; |
1480 | } | |
1481 | ||
1482 | static const struct irq_domain_ops msi_domain_ops = { | |
1483 | .map = tegra_msi_map, | |
1484 | }; | |
1485 | ||
1486 | static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) | |
1487 | { | |
1488 | struct platform_device *pdev = to_platform_device(pcie->dev); | |
94716cdd | 1489 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
1490 | struct tegra_msi *msi = &pcie->msi; |
1491 | unsigned long base; | |
1492 | int err; | |
1493 | u32 reg; | |
1494 | ||
1495 | mutex_init(&msi->lock); | |
1496 | ||
1497 | msi->chip.dev = pcie->dev; | |
1498 | msi->chip.setup_irq = tegra_msi_setup_irq; | |
1499 | msi->chip.teardown_irq = tegra_msi_teardown_irq; | |
1500 | ||
1501 | msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR, | |
1502 | &msi_domain_ops, &msi->chip); | |
1503 | if (!msi->domain) { | |
1504 | dev_err(&pdev->dev, "failed to create IRQ domain\n"); | |
1505 | return -ENOMEM; | |
1506 | } | |
1507 | ||
1508 | err = platform_get_irq_byname(pdev, "msi"); | |
1509 | if (err < 0) { | |
1510 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); | |
1511 | goto err; | |
1512 | } | |
1513 | ||
1514 | msi->irq = err; | |
1515 | ||
8ff0ef99 | 1516 | err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, |
d1523b52 TR |
1517 | tegra_msi_irq_chip.name, pcie); |
1518 | if (err < 0) { | |
1519 | dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); | |
1520 | goto err; | |
1521 | } | |
1522 | ||
1523 | /* setup AFI/FPCI range */ | |
1524 | msi->pages = __get_free_pages(GFP_KERNEL, 0); | |
1525 | base = virt_to_phys((void *)msi->pages); | |
1526 | ||
94716cdd | 1527 | afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); |
d1523b52 TR |
1528 | afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST); |
1529 | /* this register is in 4K increments */ | |
1530 | afi_writel(pcie, 1, AFI_MSI_BAR_SZ); | |
1531 | ||
1532 | /* enable all MSI vectors */ | |
1533 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0); | |
1534 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1); | |
1535 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2); | |
1536 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3); | |
1537 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4); | |
1538 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5); | |
1539 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6); | |
1540 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7); | |
1541 | ||
1542 | /* and unmask the MSI interrupt */ | |
1543 | reg = afi_readl(pcie, AFI_INTR_MASK); | |
1544 | reg |= AFI_INTR_MASK_MSI_MASK; | |
1545 | afi_writel(pcie, reg, AFI_INTR_MASK); | |
1546 | ||
1547 | return 0; | |
1548 | ||
1549 | err: | |
1550 | irq_domain_remove(msi->domain); | |
1551 | return err; | |
1552 | } | |
1553 | ||
1554 | static int tegra_pcie_disable_msi(struct tegra_pcie *pcie) | |
1555 | { | |
1556 | struct tegra_msi *msi = &pcie->msi; | |
1557 | unsigned int i, irq; | |
1558 | u32 value; | |
1559 | ||
1560 | /* mask the MSI interrupt */ | |
1561 | value = afi_readl(pcie, AFI_INTR_MASK); | |
1562 | value &= ~AFI_INTR_MASK_MSI_MASK; | |
1563 | afi_writel(pcie, value, AFI_INTR_MASK); | |
1564 | ||
1565 | /* disable all MSI vectors */ | |
1566 | afi_writel(pcie, 0, AFI_MSI_EN_VEC0); | |
1567 | afi_writel(pcie, 0, AFI_MSI_EN_VEC1); | |
1568 | afi_writel(pcie, 0, AFI_MSI_EN_VEC2); | |
1569 | afi_writel(pcie, 0, AFI_MSI_EN_VEC3); | |
1570 | afi_writel(pcie, 0, AFI_MSI_EN_VEC4); | |
1571 | afi_writel(pcie, 0, AFI_MSI_EN_VEC5); | |
1572 | afi_writel(pcie, 0, AFI_MSI_EN_VEC6); | |
1573 | afi_writel(pcie, 0, AFI_MSI_EN_VEC7); | |
1574 | ||
1575 | free_pages(msi->pages, 0); | |
1576 | ||
1577 | if (msi->irq > 0) | |
1578 | free_irq(msi->irq, pcie); | |
1579 | ||
1580 | for (i = 0; i < INT_PCI_MSI_NR; i++) { | |
1581 | irq = irq_find_mapping(msi->domain, i); | |
1582 | if (irq > 0) | |
1583 | irq_dispose_mapping(irq); | |
1584 | } | |
1585 | ||
1586 | irq_domain_remove(msi->domain); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
1591 | static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, | |
1592 | u32 *xbar) | |
1593 | { | |
1594 | struct device_node *np = pcie->dev->of_node; | |
1595 | ||
7f1f054b TR |
1596 | if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { |
1597 | switch (lanes) { | |
1598 | case 0x0000104: | |
1599 | dev_info(pcie->dev, "4x1, 1x1 configuration\n"); | |
1600 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; | |
1601 | return 0; | |
1602 | ||
1603 | case 0x0000102: | |
1604 | dev_info(pcie->dev, "2x1, 1x1 configuration\n"); | |
1605 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; | |
1606 | return 0; | |
1607 | } | |
1608 | } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { | |
94716cdd JA |
1609 | switch (lanes) { |
1610 | case 0x00000204: | |
1611 | dev_info(pcie->dev, "4x1, 2x1 configuration\n"); | |
1612 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; | |
1613 | return 0; | |
1614 | ||
1615 | case 0x00020202: | |
1616 | dev_info(pcie->dev, "2x3 configuration\n"); | |
1617 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; | |
1618 | return 0; | |
1619 | ||
1620 | case 0x00010104: | |
1621 | dev_info(pcie->dev, "4x1, 1x2 configuration\n"); | |
1622 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; | |
1623 | return 0; | |
1624 | } | |
1625 | } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { | |
1626 | switch (lanes) { | |
1627 | case 0x00000004: | |
1628 | dev_info(pcie->dev, "single-mode configuration\n"); | |
1629 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; | |
1630 | return 0; | |
1631 | ||
1632 | case 0x00000202: | |
1633 | dev_info(pcie->dev, "dual-mode configuration\n"); | |
1634 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; | |
1635 | return 0; | |
1636 | } | |
d1523b52 TR |
1637 | } |
1638 | ||
1639 | return -EINVAL; | |
1640 | } | |
1641 | ||
077fb158 TR |
1642 | /* |
1643 | * Check whether a given set of supplies is available in a device tree node. | |
1644 | * This is used to check whether the new or the legacy device tree bindings | |
1645 | * should be used. | |
1646 | */ | |
1647 | static bool of_regulator_bulk_available(struct device_node *np, | |
1648 | struct regulator_bulk_data *supplies, | |
1649 | unsigned int num_supplies) | |
1650 | { | |
1651 | char property[32]; | |
1652 | unsigned int i; | |
1653 | ||
1654 | for (i = 0; i < num_supplies; i++) { | |
1655 | snprintf(property, 32, "%s-supply", supplies[i].supply); | |
1656 | ||
1657 | if (of_find_property(np, property, NULL) == NULL) | |
1658 | return false; | |
1659 | } | |
1660 | ||
1661 | return true; | |
1662 | } | |
1663 | ||
1664 | /* | |
1665 | * Old versions of the device tree binding for this device used a set of power | |
1666 | * supplies that didn't match the hardware inputs. This happened to work for a | |
1667 | * number of cases but is not future proof. However to preserve backwards- | |
1668 | * compatibility with old device trees, this function will try to use the old | |
1669 | * set of supplies. | |
1670 | */ | |
1671 | static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie) | |
1672 | { | |
1673 | struct device_node *np = pcie->dev->of_node; | |
1674 | ||
1675 | if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) | |
1676 | pcie->num_supplies = 3; | |
1677 | else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) | |
1678 | pcie->num_supplies = 2; | |
1679 | ||
1680 | if (pcie->num_supplies == 0) { | |
1681 | dev_err(pcie->dev, "device %s not supported in legacy mode\n", | |
1682 | np->full_name); | |
1683 | return -ENODEV; | |
1684 | } | |
1685 | ||
1686 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1687 | sizeof(*pcie->supplies), | |
1688 | GFP_KERNEL); | |
1689 | if (!pcie->supplies) | |
1690 | return -ENOMEM; | |
1691 | ||
1692 | pcie->supplies[0].supply = "pex-clk"; | |
1693 | pcie->supplies[1].supply = "vdd"; | |
1694 | ||
1695 | if (pcie->num_supplies > 2) | |
1696 | pcie->supplies[2].supply = "avdd"; | |
1697 | ||
1698 | return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, | |
1699 | pcie->supplies); | |
1700 | } | |
1701 | ||
1702 | /* | |
1703 | * Obtains the list of regulators required for a particular generation of the | |
1704 | * IP block. | |
1705 | * | |
1706 | * This would've been nice to do simply by providing static tables for use | |
1707 | * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky | |
1708 | * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB) | |
1709 | * and either seems to be optional depending on which ports are being used. | |
1710 | */ | |
1711 | static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask) | |
1712 | { | |
1713 | struct device_node *np = pcie->dev->of_node; | |
1714 | unsigned int i = 0; | |
1715 | ||
7f1f054b TR |
1716 | if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { |
1717 | pcie->num_supplies = 7; | |
1718 | ||
1719 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1720 | sizeof(*pcie->supplies), | |
1721 | GFP_KERNEL); | |
1722 | if (!pcie->supplies) | |
1723 | return -ENOMEM; | |
1724 | ||
1725 | pcie->supplies[i++].supply = "avddio-pex"; | |
1726 | pcie->supplies[i++].supply = "dvddio-pex"; | |
1727 | pcie->supplies[i++].supply = "avdd-pex-pll"; | |
1728 | pcie->supplies[i++].supply = "hvdd-pex"; | |
1729 | pcie->supplies[i++].supply = "hvdd-pex-pll-e"; | |
1730 | pcie->supplies[i++].supply = "vddio-pex-ctl"; | |
1731 | pcie->supplies[i++].supply = "avdd-pll-erefe"; | |
1732 | } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { | |
077fb158 TR |
1733 | bool need_pexa = false, need_pexb = false; |
1734 | ||
1735 | /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */ | |
1736 | if (lane_mask & 0x0f) | |
1737 | need_pexa = true; | |
1738 | ||
1739 | /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */ | |
1740 | if (lane_mask & 0x30) | |
1741 | need_pexb = true; | |
1742 | ||
1743 | pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + | |
1744 | (need_pexb ? 2 : 0); | |
1745 | ||
1746 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1747 | sizeof(*pcie->supplies), | |
1748 | GFP_KERNEL); | |
1749 | if (!pcie->supplies) | |
1750 | return -ENOMEM; | |
1751 | ||
1752 | pcie->supplies[i++].supply = "avdd-pex-pll"; | |
1753 | pcie->supplies[i++].supply = "hvdd-pex"; | |
1754 | pcie->supplies[i++].supply = "vddio-pex-ctl"; | |
1755 | pcie->supplies[i++].supply = "avdd-plle"; | |
1756 | ||
1757 | if (need_pexa) { | |
1758 | pcie->supplies[i++].supply = "avdd-pexa"; | |
1759 | pcie->supplies[i++].supply = "vdd-pexa"; | |
1760 | } | |
1761 | ||
1762 | if (need_pexb) { | |
1763 | pcie->supplies[i++].supply = "avdd-pexb"; | |
1764 | pcie->supplies[i++].supply = "vdd-pexb"; | |
1765 | } | |
1766 | } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { | |
1767 | pcie->num_supplies = 5; | |
1768 | ||
1769 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1770 | sizeof(*pcie->supplies), | |
1771 | GFP_KERNEL); | |
1772 | if (!pcie->supplies) | |
1773 | return -ENOMEM; | |
1774 | ||
1775 | pcie->supplies[0].supply = "avdd-pex"; | |
1776 | pcie->supplies[1].supply = "vdd-pex"; | |
1777 | pcie->supplies[2].supply = "avdd-pex-pll"; | |
1778 | pcie->supplies[3].supply = "avdd-plle"; | |
1779 | pcie->supplies[4].supply = "vddio-pex-clk"; | |
1780 | } | |
1781 | ||
1782 | if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies, | |
1783 | pcie->num_supplies)) | |
1784 | return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, | |
1785 | pcie->supplies); | |
1786 | ||
1787 | /* | |
1788 | * If not all regulators are available for this new scheme, assume | |
1789 | * that the device tree complies with an older version of the device | |
1790 | * tree binding. | |
1791 | */ | |
1792 | dev_info(pcie->dev, "using legacy DT binding for power supplies\n"); | |
1793 | ||
1794 | devm_kfree(pcie->dev, pcie->supplies); | |
1795 | pcie->num_supplies = 0; | |
1796 | ||
1797 | return tegra_pcie_get_legacy_regulators(pcie); | |
1798 | } | |
1799 | ||
d1523b52 TR |
1800 | static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) |
1801 | { | |
94716cdd | 1802 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
1803 | struct device_node *np = pcie->dev->of_node, *port; |
1804 | struct of_pci_range_parser parser; | |
1805 | struct of_pci_range range; | |
077fb158 TR |
1806 | u32 lanes = 0, mask = 0; |
1807 | unsigned int lane = 0; | |
d1523b52 | 1808 | struct resource res; |
d1523b52 TR |
1809 | int err; |
1810 | ||
1811 | if (of_pci_range_parser_init(&parser, np)) { | |
1812 | dev_err(pcie->dev, "missing \"ranges\" property\n"); | |
1813 | return -EINVAL; | |
1814 | } | |
1815 | ||
d1523b52 | 1816 | for_each_of_pci_range(&parser, &range) { |
0b0b0893 LD |
1817 | err = of_pci_range_to_resource(&range, np, &res); |
1818 | if (err < 0) | |
1819 | return err; | |
d1523b52 TR |
1820 | |
1821 | switch (res.flags & IORESOURCE_TYPE_BITS) { | |
1822 | case IORESOURCE_IO: | |
56e75e2a TR |
1823 | /* Track the bus -> CPU I/O mapping offset. */ |
1824 | pcie->offset.io = res.start - range.pci_addr; | |
1825 | ||
5106787a TR |
1826 | memcpy(&pcie->pio, &res, sizeof(res)); |
1827 | pcie->pio.name = np->full_name; | |
1828 | ||
1829 | /* | |
1830 | * The Tegra PCIe host bridge uses this to program the | |
1831 | * mapping of the I/O space to the physical address, | |
1832 | * so we override the .start and .end fields here that | |
1833 | * of_pci_range_to_resource() converted to I/O space. | |
1834 | * We also set the IORESOURCE_MEM type to clarify that | |
1835 | * the resource is in the physical memory space. | |
1836 | */ | |
1837 | pcie->io.start = range.cpu_addr; | |
1838 | pcie->io.end = range.cpu_addr + range.size - 1; | |
1839 | pcie->io.flags = IORESOURCE_MEM; | |
1840 | pcie->io.name = "I/O"; | |
1841 | ||
1842 | memcpy(&res, &pcie->io, sizeof(res)); | |
d1523b52 TR |
1843 | break; |
1844 | ||
1845 | case IORESOURCE_MEM: | |
56e75e2a TR |
1846 | /* |
1847 | * Track the bus -> CPU memory mapping offset. This | |
1848 | * assumes that the prefetchable and non-prefetchable | |
1849 | * regions will be the last of type IORESOURCE_MEM in | |
1850 | * the ranges property. | |
1851 | * */ | |
1852 | pcie->offset.mem = res.start - range.pci_addr; | |
1853 | ||
d1523b52 TR |
1854 | if (res.flags & IORESOURCE_PREFETCH) { |
1855 | memcpy(&pcie->prefetch, &res, sizeof(res)); | |
41534e53 | 1856 | pcie->prefetch.name = "prefetchable"; |
d1523b52 TR |
1857 | } else { |
1858 | memcpy(&pcie->mem, &res, sizeof(res)); | |
41534e53 | 1859 | pcie->mem.name = "non-prefetchable"; |
d1523b52 TR |
1860 | } |
1861 | break; | |
1862 | } | |
1863 | } | |
1864 | ||
1865 | err = of_pci_parse_bus_range(np, &pcie->busn); | |
1866 | if (err < 0) { | |
1867 | dev_err(pcie->dev, "failed to parse ranges property: %d\n", | |
1868 | err); | |
1869 | pcie->busn.name = np->name; | |
1870 | pcie->busn.start = 0; | |
1871 | pcie->busn.end = 0xff; | |
1872 | pcie->busn.flags = IORESOURCE_BUS; | |
1873 | } | |
1874 | ||
1875 | /* parse root ports */ | |
1876 | for_each_child_of_node(np, port) { | |
1877 | struct tegra_pcie_port *rp; | |
1878 | unsigned int index; | |
1879 | u32 value; | |
1880 | ||
1881 | err = of_pci_get_devfn(port); | |
1882 | if (err < 0) { | |
1883 | dev_err(pcie->dev, "failed to parse address: %d\n", | |
1884 | err); | |
1885 | return err; | |
1886 | } | |
1887 | ||
1888 | index = PCI_SLOT(err); | |
1889 | ||
94716cdd | 1890 | if (index < 1 || index > soc->num_ports) { |
d1523b52 TR |
1891 | dev_err(pcie->dev, "invalid port number: %d\n", index); |
1892 | return -EINVAL; | |
1893 | } | |
1894 | ||
1895 | index--; | |
1896 | ||
1897 | err = of_property_read_u32(port, "nvidia,num-lanes", &value); | |
1898 | if (err < 0) { | |
1899 | dev_err(pcie->dev, "failed to parse # of lanes: %d\n", | |
1900 | err); | |
1901 | return err; | |
1902 | } | |
1903 | ||
1904 | if (value > 16) { | |
1905 | dev_err(pcie->dev, "invalid # of lanes: %u\n", value); | |
1906 | return -EINVAL; | |
1907 | } | |
1908 | ||
1909 | lanes |= value << (index << 3); | |
1910 | ||
077fb158 TR |
1911 | if (!of_device_is_available(port)) { |
1912 | lane += value; | |
d1523b52 | 1913 | continue; |
077fb158 TR |
1914 | } |
1915 | ||
1916 | mask |= ((1 << value) - 1) << lane; | |
1917 | lane += value; | |
d1523b52 TR |
1918 | |
1919 | rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL); | |
1920 | if (!rp) | |
1921 | return -ENOMEM; | |
1922 | ||
1923 | err = of_address_to_resource(port, 0, &rp->regs); | |
1924 | if (err < 0) { | |
1925 | dev_err(pcie->dev, "failed to parse address: %d\n", | |
1926 | err); | |
1927 | return err; | |
1928 | } | |
1929 | ||
1930 | INIT_LIST_HEAD(&rp->list); | |
1931 | rp->index = index; | |
1932 | rp->lanes = value; | |
1933 | rp->pcie = pcie; | |
6fe7c187 | 1934 | rp->np = port; |
d1523b52 | 1935 | |
dc05ee32 JL |
1936 | rp->base = devm_ioremap_resource(pcie->dev, &rp->regs); |
1937 | if (IS_ERR(rp->base)) | |
1938 | return PTR_ERR(rp->base); | |
d1523b52 TR |
1939 | |
1940 | list_add_tail(&rp->list, &pcie->ports); | |
1941 | } | |
1942 | ||
1943 | err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); | |
1944 | if (err < 0) { | |
1945 | dev_err(pcie->dev, "invalid lane configuration\n"); | |
1946 | return err; | |
1947 | } | |
1948 | ||
077fb158 TR |
1949 | err = tegra_pcie_get_regulators(pcie, mask); |
1950 | if (err < 0) | |
1951 | return err; | |
1952 | ||
d1523b52 TR |
1953 | return 0; |
1954 | } | |
1955 | ||
1956 | /* | |
1957 | * FIXME: If there are no PCIe cards attached, then calling this function | |
1958 | * can result in the increase of the bootup time as there are big timeout | |
1959 | * loops. | |
1960 | */ | |
1961 | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ | |
1962 | static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) | |
1963 | { | |
1964 | unsigned int retries = 3; | |
1965 | unsigned long value; | |
1966 | ||
7f1f054b TR |
1967 | /* override presence detection */ |
1968 | value = readl(port->base + RP_PRIV_MISC); | |
1969 | value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; | |
1970 | value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; | |
1971 | writel(value, port->base + RP_PRIV_MISC); | |
1972 | ||
d1523b52 TR |
1973 | do { |
1974 | unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
1975 | ||
1976 | do { | |
1977 | value = readl(port->base + RP_VEND_XP); | |
1978 | ||
1979 | if (value & RP_VEND_XP_DL_UP) | |
1980 | break; | |
1981 | ||
1982 | usleep_range(1000, 2000); | |
1983 | } while (--timeout); | |
1984 | ||
1985 | if (!timeout) { | |
1986 | dev_err(port->pcie->dev, "link %u down, retrying\n", | |
1987 | port->index); | |
1988 | goto retry; | |
1989 | } | |
1990 | ||
1991 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
1992 | ||
1993 | do { | |
1994 | value = readl(port->base + RP_LINK_CONTROL_STATUS); | |
1995 | ||
1996 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) | |
1997 | return true; | |
1998 | ||
1999 | usleep_range(1000, 2000); | |
2000 | } while (--timeout); | |
2001 | ||
2002 | retry: | |
2003 | tegra_pcie_port_reset(port); | |
2004 | } while (--retries); | |
2005 | ||
2006 | return false; | |
2007 | } | |
2008 | ||
2009 | static int tegra_pcie_enable(struct tegra_pcie *pcie) | |
2010 | { | |
2011 | struct tegra_pcie_port *port, *tmp; | |
2012 | struct hw_pci hw; | |
2013 | ||
2014 | list_for_each_entry_safe(port, tmp, &pcie->ports, list) { | |
2015 | dev_info(pcie->dev, "probing port %u, using %u lanes\n", | |
2016 | port->index, port->lanes); | |
2017 | ||
2018 | tegra_pcie_port_enable(port); | |
2019 | ||
2020 | if (tegra_pcie_port_check_link(port)) | |
2021 | continue; | |
2022 | ||
2023 | dev_info(pcie->dev, "link %u down, ignoring\n", port->index); | |
2024 | ||
2025 | tegra_pcie_port_disable(port); | |
2026 | tegra_pcie_port_free(port); | |
2027 | } | |
2028 | ||
2029 | memset(&hw, 0, sizeof(hw)); | |
2030 | ||
7ec725b2 YW |
2031 | #ifdef CONFIG_PCI_MSI |
2032 | hw.msi_ctrl = &pcie->msi.chip; | |
2033 | #endif | |
2034 | ||
d1523b52 TR |
2035 | hw.nr_controllers = 1; |
2036 | hw.private_data = (void **)&pcie; | |
2037 | hw.setup = tegra_pcie_setup; | |
2038 | hw.map_irq = tegra_pcie_map_irq; | |
d1523b52 TR |
2039 | hw.ops = &tegra_pcie_ops; |
2040 | ||
2041 | pci_common_init_dev(pcie->dev, &hw); | |
2042 | ||
2043 | return 0; | |
2044 | } | |
2045 | ||
94716cdd JA |
2046 | static const struct tegra_pcie_soc_data tegra20_pcie_data = { |
2047 | .num_ports = 2, | |
2048 | .msi_base_shift = 0, | |
2049 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, | |
2050 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, | |
f814430c | 2051 | .pads_refclk_cfg0 = 0xfa5cfa5c, |
94716cdd JA |
2052 | .has_pex_clkreq_en = false, |
2053 | .has_pex_bias_ctrl = false, | |
2054 | .has_intr_prsnt_sense = false, | |
94716cdd | 2055 | .has_cml_clk = false, |
7f1f054b | 2056 | .has_gen2 = false, |
94716cdd JA |
2057 | }; |
2058 | ||
2059 | static const struct tegra_pcie_soc_data tegra30_pcie_data = { | |
2060 | .num_ports = 3, | |
2061 | .msi_base_shift = 8, | |
2062 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, | |
2063 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, | |
f814430c SW |
2064 | .pads_refclk_cfg0 = 0xfa5cfa5c, |
2065 | .pads_refclk_cfg1 = 0xfa5cfa5c, | |
94716cdd JA |
2066 | .has_pex_clkreq_en = true, |
2067 | .has_pex_bias_ctrl = true, | |
2068 | .has_intr_prsnt_sense = true, | |
94716cdd | 2069 | .has_cml_clk = true, |
7f1f054b TR |
2070 | .has_gen2 = false, |
2071 | }; | |
2072 | ||
2073 | static const struct tegra_pcie_soc_data tegra124_pcie_data = { | |
2074 | .num_ports = 2, | |
2075 | .msi_base_shift = 8, | |
2076 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, | |
2077 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, | |
f814430c | 2078 | .pads_refclk_cfg0 = 0x44ac44ac, |
7f1f054b TR |
2079 | .has_pex_clkreq_en = true, |
2080 | .has_pex_bias_ctrl = true, | |
2081 | .has_intr_prsnt_sense = true, | |
2082 | .has_cml_clk = true, | |
2083 | .has_gen2 = true, | |
94716cdd JA |
2084 | }; |
2085 | ||
2086 | static const struct of_device_id tegra_pcie_of_match[] = { | |
7f1f054b | 2087 | { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data }, |
94716cdd JA |
2088 | { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data }, |
2089 | { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data }, | |
2090 | { }, | |
2091 | }; | |
94716cdd | 2092 | |
2cb989f6 TR |
2093 | static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos) |
2094 | { | |
2095 | struct tegra_pcie *pcie = s->private; | |
2096 | ||
2097 | if (list_empty(&pcie->ports)) | |
2098 | return NULL; | |
2099 | ||
2100 | seq_printf(s, "Index Status\n"); | |
2101 | ||
2102 | return seq_list_start(&pcie->ports, *pos); | |
2103 | } | |
2104 | ||
2105 | static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos) | |
2106 | { | |
2107 | struct tegra_pcie *pcie = s->private; | |
2108 | ||
2109 | return seq_list_next(v, &pcie->ports, pos); | |
2110 | } | |
2111 | ||
2112 | static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v) | |
2113 | { | |
2114 | } | |
2115 | ||
2116 | static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v) | |
2117 | { | |
2118 | bool up = false, active = false; | |
2119 | struct tegra_pcie_port *port; | |
2120 | unsigned int value; | |
2121 | ||
2122 | port = list_entry(v, struct tegra_pcie_port, list); | |
2123 | ||
2124 | value = readl(port->base + RP_VEND_XP); | |
2125 | ||
2126 | if (value & RP_VEND_XP_DL_UP) | |
2127 | up = true; | |
2128 | ||
2129 | value = readl(port->base + RP_LINK_CONTROL_STATUS); | |
2130 | ||
2131 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) | |
2132 | active = true; | |
2133 | ||
2134 | seq_printf(s, "%2u ", port->index); | |
2135 | ||
2136 | if (up) | |
2137 | seq_printf(s, "up"); | |
2138 | ||
2139 | if (active) { | |
2140 | if (up) | |
2141 | seq_printf(s, ", "); | |
2142 | ||
2143 | seq_printf(s, "active"); | |
2144 | } | |
2145 | ||
2146 | seq_printf(s, "\n"); | |
2147 | return 0; | |
2148 | } | |
2149 | ||
2150 | static const struct seq_operations tegra_pcie_ports_seq_ops = { | |
2151 | .start = tegra_pcie_ports_seq_start, | |
2152 | .next = tegra_pcie_ports_seq_next, | |
2153 | .stop = tegra_pcie_ports_seq_stop, | |
2154 | .show = tegra_pcie_ports_seq_show, | |
2155 | }; | |
2156 | ||
2157 | static int tegra_pcie_ports_open(struct inode *inode, struct file *file) | |
2158 | { | |
2159 | struct tegra_pcie *pcie = inode->i_private; | |
2160 | struct seq_file *s; | |
2161 | int err; | |
2162 | ||
2163 | err = seq_open(file, &tegra_pcie_ports_seq_ops); | |
2164 | if (err) | |
2165 | return err; | |
2166 | ||
2167 | s = file->private_data; | |
2168 | s->private = pcie; | |
2169 | ||
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | static const struct file_operations tegra_pcie_ports_ops = { | |
2174 | .owner = THIS_MODULE, | |
2175 | .open = tegra_pcie_ports_open, | |
2176 | .read = seq_read, | |
2177 | .llseek = seq_lseek, | |
2178 | .release = seq_release, | |
2179 | }; | |
2180 | ||
2181 | static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) | |
2182 | { | |
2183 | struct dentry *file; | |
2184 | ||
2185 | pcie->debugfs = debugfs_create_dir("pcie", NULL); | |
2186 | if (!pcie->debugfs) | |
2187 | return -ENOMEM; | |
2188 | ||
2189 | file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, | |
2190 | pcie, &tegra_pcie_ports_ops); | |
2191 | if (!file) | |
2192 | goto remove; | |
2193 | ||
2194 | return 0; | |
2195 | ||
2196 | remove: | |
2197 | debugfs_remove_recursive(pcie->debugfs); | |
2198 | pcie->debugfs = NULL; | |
2199 | return -ENOMEM; | |
2200 | } | |
2201 | ||
d1523b52 TR |
2202 | static int tegra_pcie_probe(struct platform_device *pdev) |
2203 | { | |
94716cdd | 2204 | const struct of_device_id *match; |
d1523b52 TR |
2205 | struct tegra_pcie *pcie; |
2206 | int err; | |
2207 | ||
94716cdd JA |
2208 | match = of_match_device(tegra_pcie_of_match, &pdev->dev); |
2209 | if (!match) | |
2210 | return -ENODEV; | |
2211 | ||
d1523b52 TR |
2212 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); |
2213 | if (!pcie) | |
2214 | return -ENOMEM; | |
2215 | ||
f7625980 | 2216 | INIT_LIST_HEAD(&pcie->buses); |
d1523b52 | 2217 | INIT_LIST_HEAD(&pcie->ports); |
94716cdd | 2218 | pcie->soc_data = match->data; |
d1523b52 TR |
2219 | pcie->dev = &pdev->dev; |
2220 | ||
2221 | err = tegra_pcie_parse_dt(pcie); | |
2222 | if (err < 0) | |
2223 | return err; | |
2224 | ||
d1523b52 TR |
2225 | err = tegra_pcie_get_resources(pcie); |
2226 | if (err < 0) { | |
2227 | dev_err(&pdev->dev, "failed to request resources: %d\n", err); | |
2228 | return err; | |
2229 | } | |
2230 | ||
2231 | err = tegra_pcie_enable_controller(pcie); | |
2232 | if (err) | |
2233 | goto put_resources; | |
2234 | ||
2235 | /* setup the AFI address translations */ | |
2236 | tegra_pcie_setup_translations(pcie); | |
2237 | ||
2238 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
2239 | err = tegra_pcie_enable_msi(pcie); | |
2240 | if (err < 0) { | |
2241 | dev_err(&pdev->dev, | |
2242 | "failed to enable MSI support: %d\n", | |
2243 | err); | |
2244 | goto put_resources; | |
2245 | } | |
2246 | } | |
2247 | ||
2248 | err = tegra_pcie_enable(pcie); | |
2249 | if (err < 0) { | |
2250 | dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err); | |
2251 | goto disable_msi; | |
2252 | } | |
2253 | ||
2cb989f6 TR |
2254 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
2255 | err = tegra_pcie_debugfs_init(pcie); | |
2256 | if (err < 0) | |
2257 | dev_err(&pdev->dev, "failed to setup debugfs: %d\n", | |
2258 | err); | |
2259 | } | |
2260 | ||
d1523b52 TR |
2261 | platform_set_drvdata(pdev, pcie); |
2262 | return 0; | |
2263 | ||
2264 | disable_msi: | |
2265 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
2266 | tegra_pcie_disable_msi(pcie); | |
2267 | put_resources: | |
2268 | tegra_pcie_put_resources(pcie); | |
2269 | return err; | |
2270 | } | |
2271 | ||
d1523b52 TR |
2272 | static struct platform_driver tegra_pcie_driver = { |
2273 | .driver = { | |
2274 | .name = "tegra-pcie", | |
d1523b52 TR |
2275 | .of_match_table = tegra_pcie_of_match, |
2276 | .suppress_bind_attrs = true, | |
2277 | }, | |
2278 | .probe = tegra_pcie_probe, | |
2279 | }; | |
ad183271 | 2280 | builtin_platform_driver(tegra_pcie_driver); |