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f12b76e5 DD |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
13 | * | |
14 | * Copyright (C) 2015 - 2016 Cavium, Inc. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
0b3cd164 | 18 | #include <linux/init.h> |
f12b76e5 DD |
19 | #include <linux/of_address.h> |
20 | #include <linux/of_pci.h> | |
80955f9e | 21 | #include <linux/pci-ecam.h> |
f12b76e5 DD |
22 | #include <linux/platform_device.h> |
23 | ||
f12b76e5 DD |
24 | #define PEM_CFG_WR 0x28 |
25 | #define PEM_CFG_RD 0x30 | |
26 | ||
27 | struct thunder_pem_pci { | |
f12b76e5 DD |
28 | u32 ea_entry[3]; |
29 | void __iomem *pem_reg_base; | |
30 | }; | |
31 | ||
f12b76e5 DD |
32 | static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn, |
33 | int where, int size, u32 *val) | |
34 | { | |
35 | u64 read_val; | |
1958e717 J |
36 | struct pci_config_window *cfg = bus->sysdata; |
37 | struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; | |
f12b76e5 DD |
38 | |
39 | if (devfn != 0 || where >= 2048) { | |
40 | *val = ~0; | |
41 | return PCIBIOS_DEVICE_NOT_FOUND; | |
42 | } | |
43 | ||
44 | /* | |
45 | * 32-bit accesses only. Write the address to the low order | |
46 | * bits of PEM_CFG_RD, then trigger the read by reading back. | |
47 | * The config data lands in the upper 32-bits of PEM_CFG_RD. | |
48 | */ | |
49 | read_val = where & ~3ull; | |
50 | writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD); | |
51 | read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); | |
52 | read_val >>= 32; | |
53 | ||
54 | /* | |
55 | * The config space contains some garbage, fix it up. Also | |
56 | * synthesize an EA capability for the BAR used by MSI-X. | |
57 | */ | |
58 | switch (where & ~3) { | |
59 | case 0x40: | |
60 | read_val &= 0xffff00ff; | |
61 | read_val |= 0x00007000; /* Skip MSI CAP */ | |
62 | break; | |
63 | case 0x70: /* Express Cap */ | |
64 | /* PME interrupt on vector 2*/ | |
65 | read_val |= (2u << 25); | |
66 | break; | |
67 | case 0xb0: /* MSI-X Cap */ | |
68 | /* TableSize=4, Next Cap is EA */ | |
69 | read_val &= 0xc00000ff; | |
70 | read_val |= 0x0003bc00; | |
71 | break; | |
72 | case 0xb4: | |
73 | /* Table offset=0, BIR=0 */ | |
74 | read_val = 0x00000000; | |
75 | break; | |
76 | case 0xb8: | |
77 | /* BPA offset=0xf0000, BIR=0 */ | |
78 | read_val = 0x000f0000; | |
79 | break; | |
80 | case 0xbc: | |
81 | /* EA, 1 entry, no next Cap */ | |
82 | read_val = 0x00010014; | |
83 | break; | |
84 | case 0xc0: | |
85 | /* DW2 for type-1 */ | |
86 | read_val = 0x00000000; | |
87 | break; | |
88 | case 0xc4: | |
89 | /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */ | |
90 | read_val = 0x80ff0003; | |
91 | break; | |
92 | case 0xc8: | |
93 | read_val = pem_pci->ea_entry[0]; | |
94 | break; | |
95 | case 0xcc: | |
96 | read_val = pem_pci->ea_entry[1]; | |
97 | break; | |
98 | case 0xd0: | |
99 | read_val = pem_pci->ea_entry[2]; | |
100 | break; | |
101 | default: | |
102 | break; | |
103 | } | |
104 | read_val >>= (8 * (where & 3)); | |
105 | switch (size) { | |
106 | case 1: | |
107 | read_val &= 0xff; | |
108 | break; | |
109 | case 2: | |
110 | read_val &= 0xffff; | |
111 | break; | |
112 | default: | |
113 | break; | |
114 | } | |
115 | *val = read_val; | |
116 | return PCIBIOS_SUCCESSFUL; | |
117 | } | |
118 | ||
119 | static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn, | |
120 | int where, int size, u32 *val) | |
121 | { | |
1958e717 | 122 | struct pci_config_window *cfg = bus->sysdata; |
f12b76e5 | 123 | |
1958e717 J |
124 | if (bus->number < cfg->busr.start || |
125 | bus->number > cfg->busr.end) | |
f12b76e5 DD |
126 | return PCIBIOS_DEVICE_NOT_FOUND; |
127 | ||
128 | /* | |
129 | * The first device on the bus is the PEM PCIe bridge. | |
130 | * Special case its config access. | |
131 | */ | |
1958e717 | 132 | if (bus->number == cfg->busr.start) |
f12b76e5 DD |
133 | return thunder_pem_bridge_read(bus, devfn, where, size, val); |
134 | ||
135 | return pci_generic_config_read(bus, devfn, where, size, val); | |
136 | } | |
137 | ||
138 | /* | |
139 | * Some of the w1c_bits below also include read-only or non-writable | |
140 | * reserved bits, this makes the code simpler and is OK as the bits | |
141 | * are not affected by writing zeros to them. | |
142 | */ | |
93bf9073 | 143 | static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned) |
f12b76e5 DD |
144 | { |
145 | u32 w1c_bits = 0; | |
146 | ||
93bf9073 | 147 | switch (where_aligned) { |
f12b76e5 DD |
148 | case 0x04: /* Command/Status */ |
149 | case 0x1c: /* Base and I/O Limit/Secondary Status */ | |
150 | w1c_bits = 0xff000000; | |
151 | break; | |
152 | case 0x44: /* Power Management Control and Status */ | |
153 | w1c_bits = 0xfffffe00; | |
154 | break; | |
155 | case 0x78: /* Device Control/Device Status */ | |
156 | case 0x80: /* Link Control/Link Status */ | |
157 | case 0x88: /* Slot Control/Slot Status */ | |
158 | case 0x90: /* Root Status */ | |
159 | case 0xa0: /* Link Control 2 Registers/Link Status 2 */ | |
160 | w1c_bits = 0xffff0000; | |
161 | break; | |
162 | case 0x104: /* Uncorrectable Error Status */ | |
163 | case 0x110: /* Correctable Error Status */ | |
164 | case 0x130: /* Error Status */ | |
165 | case 0x160: /* Link Control 4 */ | |
166 | w1c_bits = 0xffffffff; | |
167 | break; | |
168 | default: | |
169 | break; | |
170 | } | |
171 | return w1c_bits; | |
172 | } | |
173 | ||
93bf9073 DD |
174 | /* Some bits must be written to one so they appear to be read-only. */ |
175 | static u32 thunder_pem_bridge_w1_bits(u64 where_aligned) | |
176 | { | |
177 | u32 w1_bits; | |
178 | ||
179 | switch (where_aligned) { | |
180 | case 0x1c: /* I/O Base / I/O Limit, Secondary Status */ | |
181 | /* Force 32-bit I/O addressing. */ | |
182 | w1_bits = 0x0101; | |
183 | break; | |
184 | case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */ | |
185 | /* Force 64-bit addressing */ | |
186 | w1_bits = 0x00010001; | |
187 | break; | |
188 | default: | |
189 | w1_bits = 0; | |
190 | break; | |
191 | } | |
192 | return w1_bits; | |
193 | } | |
194 | ||
f12b76e5 DD |
195 | static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn, |
196 | int where, int size, u32 val) | |
197 | { | |
1958e717 J |
198 | struct pci_config_window *cfg = bus->sysdata; |
199 | struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; | |
f12b76e5 | 200 | u64 write_val, read_val; |
93bf9073 | 201 | u64 where_aligned = where & ~3ull; |
f12b76e5 DD |
202 | u32 mask = 0; |
203 | ||
f12b76e5 DD |
204 | |
205 | if (devfn != 0 || where >= 2048) | |
206 | return PCIBIOS_DEVICE_NOT_FOUND; | |
207 | ||
208 | /* | |
209 | * 32-bit accesses only. If the write is for a size smaller | |
210 | * than 32-bits, we must first read the 32-bit value and merge | |
211 | * in the desired bits and then write the whole 32-bits back | |
212 | * out. | |
213 | */ | |
214 | switch (size) { | |
215 | case 1: | |
93bf9073 | 216 | writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); |
f12b76e5 DD |
217 | read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); |
218 | read_val >>= 32; | |
219 | mask = ~(0xff << (8 * (where & 3))); | |
220 | read_val &= mask; | |
221 | val = (val & 0xff) << (8 * (where & 3)); | |
222 | val |= (u32)read_val; | |
223 | break; | |
224 | case 2: | |
93bf9073 | 225 | writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); |
f12b76e5 DD |
226 | read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD); |
227 | read_val >>= 32; | |
228 | mask = ~(0xffff << (8 * (where & 3))); | |
229 | read_val &= mask; | |
230 | val = (val & 0xffff) << (8 * (where & 3)); | |
231 | val |= (u32)read_val; | |
232 | break; | |
233 | default: | |
234 | break; | |
235 | } | |
236 | ||
237 | /* | |
238 | * By expanding the write width to 32 bits, we may | |
239 | * inadvertently hit some W1C bits that were not intended to | |
240 | * be written. Calculate the mask that must be applied to the | |
241 | * data to be written to avoid these cases. | |
242 | */ | |
243 | if (mask) { | |
244 | u32 w1c_bits = thunder_pem_bridge_w1c_bits(where); | |
245 | ||
246 | if (w1c_bits) { | |
247 | mask &= w1c_bits; | |
248 | val &= ~mask; | |
249 | } | |
250 | } | |
251 | ||
93bf9073 DD |
252 | /* |
253 | * Some bits must be read-only with value of one. Since the | |
254 | * access method allows these to be cleared if a zero is | |
255 | * written, force them to one before writing. | |
256 | */ | |
257 | val |= thunder_pem_bridge_w1_bits(where_aligned); | |
258 | ||
f12b76e5 DD |
259 | /* |
260 | * Low order bits are the config address, the high order 32 | |
261 | * bits are the data to be written. | |
262 | */ | |
93bf9073 | 263 | write_val = (((u64)val) << 32) | where_aligned; |
f12b76e5 DD |
264 | writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR); |
265 | return PCIBIOS_SUCCESSFUL; | |
266 | } | |
267 | ||
268 | static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn, | |
269 | int where, int size, u32 val) | |
270 | { | |
1958e717 | 271 | struct pci_config_window *cfg = bus->sysdata; |
f12b76e5 | 272 | |
1958e717 J |
273 | if (bus->number < cfg->busr.start || |
274 | bus->number > cfg->busr.end) | |
f12b76e5 DD |
275 | return PCIBIOS_DEVICE_NOT_FOUND; |
276 | /* | |
277 | * The first device on the bus is the PEM PCIe bridge. | |
278 | * Special case its config access. | |
279 | */ | |
1958e717 | 280 | if (bus->number == cfg->busr.start) |
f12b76e5 DD |
281 | return thunder_pem_bridge_write(bus, devfn, where, size, val); |
282 | ||
283 | ||
284 | return pci_generic_config_write(bus, devfn, where, size, val); | |
285 | } | |
286 | ||
5c3d14f7 | 287 | static int thunder_pem_init(struct pci_config_window *cfg) |
f12b76e5 | 288 | { |
5c3d14f7 | 289 | struct device *dev = cfg->parent; |
f12b76e5 DD |
290 | resource_size_t bar4_start; |
291 | struct resource *res_pem; | |
292 | struct thunder_pem_pci *pem_pci; | |
1958e717 J |
293 | struct platform_device *pdev; |
294 | ||
295 | /* Only OF support for now */ | |
296 | if (!dev->of_node) | |
297 | return -EINVAL; | |
f12b76e5 DD |
298 | |
299 | pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL); | |
300 | if (!pem_pci) | |
301 | return -ENOMEM; | |
302 | ||
1958e717 | 303 | pdev = to_platform_device(dev); |
f12b76e5 DD |
304 | |
305 | /* | |
306 | * The second register range is the PEM bridge to the PCIe | |
307 | * bus. It has a different config access method than those | |
308 | * devices behind the bridge. | |
309 | */ | |
310 | res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
311 | if (!res_pem) { | |
312 | dev_err(dev, "missing \"reg[1]\"property\n"); | |
313 | return -EINVAL; | |
314 | } | |
315 | ||
316 | pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000); | |
317 | if (!pem_pci->pem_reg_base) | |
318 | return -ENOMEM; | |
319 | ||
320 | /* | |
321 | * The MSI-X BAR for the PEM and AER interrupts is located at | |
322 | * a fixed offset from the PEM register base. Generate a | |
323 | * fragment of the synthesized Enhanced Allocation capability | |
324 | * structure here for the BAR. | |
325 | */ | |
326 | bar4_start = res_pem->start + 0xf00000; | |
327 | pem_pci->ea_entry[0] = (u32)bar4_start | 2; | |
328 | pem_pci->ea_entry[1] = (u32)(res_pem->end - bar4_start) & ~3u; | |
329 | pem_pci->ea_entry[2] = (u32)(bar4_start >> 32); | |
330 | ||
1958e717 J |
331 | cfg->priv = pem_pci; |
332 | return 0; | |
333 | } | |
334 | ||
335 | static struct pci_ecam_ops pci_thunder_pem_ops = { | |
336 | .bus_shift = 24, | |
337 | .init = thunder_pem_init, | |
338 | .pci_ops = { | |
339 | .map_bus = pci_ecam_map_bus, | |
340 | .read = thunder_pem_config_read, | |
341 | .write = thunder_pem_config_write, | |
342 | } | |
343 | }; | |
344 | ||
345 | static const struct of_device_id thunder_pem_of_match[] = { | |
346 | { .compatible = "cavium,pci-host-thunder-pem" }, | |
347 | { }, | |
348 | }; | |
1958e717 J |
349 | |
350 | static int thunder_pem_probe(struct platform_device *pdev) | |
351 | { | |
352 | return pci_host_common_probe(pdev, &pci_thunder_pem_ops); | |
f12b76e5 DD |
353 | } |
354 | ||
355 | static struct platform_driver thunder_pem_driver = { | |
356 | .driver = { | |
357 | .name = KBUILD_MODNAME, | |
358 | .of_match_table = thunder_pem_of_match, | |
359 | }, | |
360 | .probe = thunder_pem_probe, | |
361 | }; | |
0b3cd164 | 362 | builtin_platform_driver(thunder_pem_driver); |