[deliverable/linux.git] / drivers / pci / host / pci-xgene.c

/**
 * APM X-Gene PCIe Driver
 *
 * Copyright (c) 2014 Applied Micro Circuits Corporation.
 *
 * Author: Tanmay Inamdar <tinamdar@apm.com>.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/memblock.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#define PCIECORE_CTLANDSTATUS		0x50
#define PIM1_1L				0x80
#define IBAR2				0x98
#define IR2MSK				0x9c
#define PIM2_1L				0xa0
#define IBAR3L				0xb4
#define IR3MSKL				0xbc
#define PIM3_1L				0xc4
#define OMR1BARL			0x100
#define OMR2BARL			0x118
#define OMR3BARL			0x130
#define CFGBARL				0x154
#define CFGBARH				0x158
#define CFGCTL				0x15c
#define RTDID				0x160
#define BRIDGE_CFG_0			0x2000
#define BRIDGE_CFG_4			0x2010
#define BRIDGE_STATUS_0			0x2600

#define LINK_UP_MASK			0x00000100
#define AXI_EP_CFG_ACCESS		0x10000
#define EN_COHERENCY			0xF0000000
#define EN_REG				0x00000001
#define OB_LO_IO			0x00000002
#define XGENE_PCIE_VENDORID		0x10E8
#define XGENE_PCIE_DEVICEID		0xE004
#define SZ_1T				(SZ_1G*1024ULL)
#define PIPE_PHY_RATE_RD(src)		((0xc000 & (u32)(src)) >> 0xe)

#define ROOT_CAP_AND_CTRL		0x5C

/* PCIe IP version */
#define XGENE_PCIE_IP_VER_UNKN		0
#define XGENE_PCIE_IP_VER_1		1

struct xgene_pcie_port {
	struct device_node	*node;
	struct device		*dev;
	struct clk		*clk;
	void __iomem		*csr_base;
	void __iomem		*cfg_base;
	unsigned long		cfg_addr;
	bool			link_up;
	u32			version;
};

static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
{
	return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
}

/*
 * When the address bit [17:16] is 2'b01, the Configuration access will be
 * treated as Type 1 and it will be forwarded to external PCIe device.
 */
static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
{
	struct xgene_pcie_port *port = bus->sysdata;

	if (bus->number >= (bus->primary + 1))
		return port->cfg_base + AXI_EP_CFG_ACCESS;

	return port->cfg_base;
}

/*
 * For Configuration request, RTDID register is used as Bus Number,
 * Device Number and Function number of the header fields.
 */
static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
{
	struct xgene_pcie_port *port = bus->sysdata;
	unsigned int b, d, f;
	u32 rtdid_val = 0;

	b = bus->number;
	d = PCI_SLOT(devfn);
	f = PCI_FUNC(devfn);

	if (!pci_is_root_bus(bus))
		rtdid_val = (b << 8) | (d << 3) | f;

	writel(rtdid_val, port->csr_base + RTDID);
	/* read the register back to ensure flush */
	readl(port->csr_base + RTDID);
}

/*
 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
 * the translation from PCI bus to native BUS.  Entire DDR region
 * is mapped into PCIe space using these registers, so it can be
 * reached by DMA from EP devices.  The BAR0/1 of bridge should be
 * hidden during enumeration to avoid the sizing and resource allocation
 * by PCIe core.
 */
static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
{
	if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
				     (offset == PCI_BASE_ADDRESS_1)))
		return true;

	return false;
}

static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
			      int offset)
{
	if ((pci_is_root_bus(bus) && devfn != 0) ||
	    xgene_pcie_hide_rc_bars(bus, offset))
		return NULL;

	xgene_pcie_set_rtdid_reg(bus, devfn);
	return xgene_pcie_get_cfg_base(bus) + offset;
}

static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
				    int where, int size, u32 *val)
{
	struct xgene_pcie_port *port = bus->sysdata;

	if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
	    PCIBIOS_SUCCESSFUL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	/*
	 * The v1 controller has a bug in its Configuration Request
	 * Retry Status (CRS) logic: when CRS is enabled and we read the
	 * Vendor and Device ID of a non-existent device, the controller
	 * fabricates return data of 0xFFFF0001 ("device exists but is not
	 * ready") instead of 0xFFFFFFFF ("device does not exist").  This
	 * causes the PCI core to retry the read until it times out.
	 * Avoid this by not claiming to support CRS.
	 */
	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
	    ((where & ~0x3) == ROOT_CAP_AND_CTRL))
		*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);

	if (size <= 2)
		*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops xgene_pcie_ops = {
	.map_bus = xgene_pcie_map_bus,
	.read = xgene_pcie_config_read32,
	.write = pci_generic_config_write32,
};

static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
				  u32 flags, u64 size)
{
	u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
	u32 val32 = 0;
	u32 val;

	val32 = readl(csr_base + addr);
	val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
	writel(val, csr_base + addr);

	val32 = readl(csr_base + addr + 0x04);
	val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
	writel(val, csr_base + addr + 0x04);

	val32 = readl(csr_base + addr + 0x04);
	val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
	writel(val, csr_base + addr + 0x04);

	val32 = readl(csr_base + addr + 0x08);
	val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
	writel(val, csr_base + addr + 0x08);

	return mask;
}

static void xgene_pcie_linkup(struct xgene_pcie_port *port,
				   u32 *lanes, u32 *speed)
{
	void __iomem *csr_base = port->csr_base;
	u32 val32;

	port->link_up = false;
	val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
	if (val32 & LINK_UP_MASK) {
		port->link_up = true;
		*speed = PIPE_PHY_RATE_RD(val32);
		val32 = readl(csr_base + BRIDGE_STATUS_0);
		*lanes = val32 >> 26;
	}
}

static int xgene_pcie_init_port(struct xgene_pcie_port *port)
{
	int rc;

	port->clk = clk_get(port->dev, NULL);
	if (IS_ERR(port->clk)) {
		dev_err(port->dev, "clock not available\n");
		return -ENODEV;
	}

	rc = clk_prepare_enable(port->clk);
	if (rc) {
		dev_err(port->dev, "clock enable failed\n");
		return rc;
	}

	return 0;
}

static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
			      struct platform_device *pdev)
{
	struct resource *res;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
	port->csr_base = devm_ioremap_resource(port->dev, res);
	if (IS_ERR(port->csr_base))
		return PTR_ERR(port->csr_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
	port->cfg_base = devm_ioremap_resource(port->dev, res);
	if (IS_ERR(port->cfg_base))
		return PTR_ERR(port->cfg_base);
	port->cfg_addr = res->start;

	return 0;
}

static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
				    struct resource *res, u32 offset,
				    u64 cpu_addr, u64 pci_addr)
{
	void __iomem *base = port->csr_base + offset;
	resource_size_t size = resource_size(res);
	u64 restype = resource_type(res);
	u64 mask = 0;
	u32 min_size;
	u32 flag = EN_REG;

	if (restype == IORESOURCE_MEM) {
		min_size = SZ_128M;
	} else {
		min_size = 128;
		flag |= OB_LO_IO;
	}

	if (size >= min_size)
		mask = ~(size - 1) | flag;
	else
		dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n",
			 (u64)size, min_size);

	writel(lower_32_bits(cpu_addr), base);
	writel(upper_32_bits(cpu_addr), base + 0x04);
	writel(lower_32_bits(mask), base + 0x08);
	writel(upper_32_bits(mask), base + 0x0c);
	writel(lower_32_bits(pci_addr), base + 0x10);
	writel(upper_32_bits(pci_addr), base + 0x14);
}

static void xgene_pcie_setup_cfg_reg(void __iomem *csr_base, u64 addr)
{
	writel(lower_32_bits(addr), csr_base + CFGBARL);
	writel(upper_32_bits(addr), csr_base + CFGBARH);
	writel(EN_REG, csr_base + CFGCTL);
}

static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
				 struct list_head *res,
				 resource_size_t io_base)
{
	struct resource_entry *window;
	struct device *dev = port->dev;
	int ret;

	resource_list_for_each_entry(window, res) {
		struct resource *res = window->res;
		u64 restype = resource_type(res);

		dev_dbg(port->dev, "%pR\n", res);

		switch (restype) {
		case IORESOURCE_IO:
			xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
						res->start - window->offset);
			ret = pci_remap_iospace(res, io_base);
			if (ret < 0)
				return ret;
			break;
		case IORESOURCE_MEM:
			xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start,
						res->start - window->offset);
			break;
		case IORESOURCE_BUS:
			break;
		default:
			dev_err(dev, "invalid resource %pR\n", res);
			return -EINVAL;
		}
	}
	xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr);

	return 0;
}

static void xgene_pcie_setup_pims(void *addr, u64 pim, u64 size)
{
	writel(lower_32_bits(pim), addr);
	writel(upper_32_bits(pim) | EN_COHERENCY, addr + 0x04);
	writel(lower_32_bits(size), addr + 0x10);
	writel(upper_32_bits(size), addr + 0x14);
}

/*
 * X-Gene PCIe support maximum 3 inbound memory regions
 * This function helps to select a region based on size of region
 */
static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
{
	if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
		*ib_reg_mask |= (1 << 1);
		return 1;
	}

	if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
		*ib_reg_mask |= (1 << 0);
		return 0;
	}

	if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
		*ib_reg_mask |= (1 << 2);
		return 2;
	}

	return -EINVAL;
}

static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
				    struct of_pci_range *range, u8 *ib_reg_mask)
{
	void __iomem *csr_base = port->csr_base;
	void __iomem *cfg_base = port->cfg_base;
	void *bar_addr;
	void *pim_addr;
	u64 cpu_addr = range->cpu_addr;
	u64 pci_addr = range->pci_addr;
	u64 size = range->size;
	u64 mask = ~(size - 1) | EN_REG;
	u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
	u32 bar_low;
	int region;

	region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
	if (region < 0) {
		dev_warn(port->dev, "invalid pcie dma-range config\n");
		return;
	}

	if (range->flags & IORESOURCE_PREFETCH)
		flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;

	bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
	switch (region) {
	case 0:
		xgene_pcie_set_ib_mask(csr_base, BRIDGE_CFG_4, flags, size);
		bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
		writel(bar_low, bar_addr);
		writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
		pim_addr = csr_base + PIM1_1L;
		break;
	case 1:
		bar_addr = csr_base + IBAR2;
		writel(bar_low, bar_addr);
		writel(lower_32_bits(mask), csr_base + IR2MSK);
		pim_addr = csr_base + PIM2_1L;
		break;
	case 2:
		bar_addr = csr_base + IBAR3L;
		writel(bar_low, bar_addr);
		writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
		writel(lower_32_bits(mask), csr_base + IR3MSKL);
		writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
		pim_addr = csr_base + PIM3_1L;
		break;
	}

	xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1));
}

static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
				     struct device_node *node)
{
	const int na = 3, ns = 2;
	int rlen;

	parser->node = node;
	parser->pna = of_n_addr_cells(node);
	parser->np = parser->pna + na + ns;

	parser->range = of_get_property(node, "dma-ranges", &rlen);
	if (!parser->range)
		return -ENOENT;
	parser->end = parser->range + rlen / sizeof(__be32);

	return 0;
}

static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
{
	struct device_node *np = port->node;
	struct of_pci_range range;
	struct of_pci_range_parser parser;
	struct device *dev = port->dev;
	u8 ib_reg_mask = 0;

	if (pci_dma_range_parser_init(&parser, np)) {
		dev_err(dev, "missing dma-ranges property\n");
		return -EINVAL;
	}

	/* Get the dma-ranges from DT */
	for_each_of_pci_range(&parser, &range) {
		u64 end = range.cpu_addr + range.size - 1;

		dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
			range.flags, range.cpu_addr, end, range.pci_addr);
		xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
	}
	return 0;
}

/* clear BAR configuration which was done by firmware */
static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
{
	int i;

	for (i = PIM1_1L; i <= CFGCTL; i += 4)
		writel(0x0, port->csr_base + i);
}

static int xgene_pcie_setup(struct xgene_pcie_port *port,
			    struct list_head *res,
			    resource_size_t io_base)
{
	u32 val, lanes = 0, speed = 0;
	int ret;

	xgene_pcie_clear_config(port);

	/* setup the vendor and device IDs correctly */
	val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
	writel(val, port->csr_base + BRIDGE_CFG_0);

	ret = xgene_pcie_map_ranges(port, res, io_base);
	if (ret)
		return ret;

	ret = xgene_pcie_parse_map_dma_ranges(port);
	if (ret)
		return ret;

	xgene_pcie_linkup(port, &lanes, &speed);
	if (!port->link_up)
		dev_info(port->dev, "(rc) link down\n");
	else
		dev_info(port->dev, "(rc) x%d gen-%d link up\n",
				lanes, speed + 1);
	return 0;
}

static int xgene_pcie_msi_enable(struct pci_bus *bus)
{
	struct device_node *msi_node;

	msi_node = of_parse_phandle(bus->dev.of_node,
					"msi-parent", 0);
	if (!msi_node)
		return -ENODEV;

	bus->msi = of_pci_find_msi_chip_by_node(msi_node);
	if (!bus->msi)
		return -ENODEV;

	bus->msi->dev = &bus->dev;
	return 0;
}

static int xgene_pcie_probe_bridge(struct platform_device *pdev)
{
	struct device_node *dn = pdev->dev.of_node;
	struct xgene_pcie_port *port;
	resource_size_t iobase = 0;
	struct pci_bus *bus;
	int ret;
	LIST_HEAD(res);

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;
	port->node = of_node_get(pdev->dev.of_node);
	port->dev = &pdev->dev;

	port->version = XGENE_PCIE_IP_VER_UNKN;
	if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
		port->version = XGENE_PCIE_IP_VER_1;

	ret = xgene_pcie_map_reg(port, pdev);
	if (ret)
		return ret;

	ret = xgene_pcie_init_port(port);
	if (ret)
		return ret;

	ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
	if (ret)
		return ret;

	ret = xgene_pcie_setup(port, &res, iobase);
	if (ret)
		return ret;

	bus = pci_create_root_bus(&pdev->dev, 0,
					&xgene_pcie_ops, port, &res);
	if (!bus)
		return -ENOMEM;

	if (IS_ENABLED(CONFIG_PCI_MSI))
		if (xgene_pcie_msi_enable(bus))
			dev_info(port->dev, "failed to enable MSI\n");

	pci_scan_child_bus(bus);
	pci_assign_unassigned_bus_resources(bus);
	pci_bus_add_devices(bus);

	platform_set_drvdata(pdev, port);
	return 0;
}

static const struct of_device_id xgene_pcie_match_table[] = {
	{.compatible = "apm,xgene-pcie",},
	{},
};

static struct platform_driver xgene_pcie_driver = {
	.driver = {
		   .name = "xgene-pcie",
		   .of_match_table = of_match_ptr(xgene_pcie_match_table),
	},
	.probe = xgene_pcie_probe_bridge,
};
module_platform_driver(xgene_pcie_driver);

MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>");
MODULE_DESCRIPTION("APM X-Gene PCIe driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
5f6b6ccd TI	1	/**
	2	* APM X-Gene PCIe Driver
	3	*
	4	* Copyright (c) 2014 Applied Micro Circuits Corporation.
	5	*
	6	* Author: Tanmay Inamdar <tinamdar@apm.com>.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
29ef7091	19	#include <linux/clk.h>
5f6b6ccd TI	20	#include <linux/delay.h>
	21	#include <linux/io.h>
	22	#include <linux/jiffies.h>
	23	#include <linux/memblock.h>
	24	#include <linux/module.h>
	25	#include <linux/of.h>
	26	#include <linux/of_address.h>
	27	#include <linux/of_irq.h>
	28	#include <linux/of_pci.h>
	29	#include <linux/pci.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/slab.h>
	32
	33	#define PCIECORE_CTLANDSTATUS 0x50
	34	#define PIM1_1L 0x80
	35	#define IBAR2 0x98
	36	#define IR2MSK 0x9c
	37	#define PIM2_1L 0xa0
	38	#define IBAR3L 0xb4
	39	#define IR3MSKL 0xbc
	40	#define PIM3_1L 0xc4
	41	#define OMR1BARL 0x100
	42	#define OMR2BARL 0x118
	43	#define OMR3BARL 0x130
	44	#define CFGBARL 0x154
	45	#define CFGBARH 0x158
	46	#define CFGCTL 0x15c
	47	#define RTDID 0x160
	48	#define BRIDGE_CFG_0 0x2000
	49	#define BRIDGE_CFG_4 0x2010
	50	#define BRIDGE_STATUS_0 0x2600
	51
	52	#define LINK_UP_MASK 0x00000100
	53	#define AXI_EP_CFG_ACCESS 0x10000
	54	#define EN_COHERENCY 0xF0000000
	55	#define EN_REG 0x00000001
	56	#define OB_LO_IO 0x00000002
	57	#define XGENE_PCIE_VENDORID 0x10E8
	58	#define XGENE_PCIE_DEVICEID 0xE004
	59	#define SZ_1T (SZ_1G*1024ULL)
	60	#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
	61
f09f8735 DD	62	#define ROOT_CAP_AND_CTRL 0x5C
	63
	64	/* PCIe IP version */
	65	#define XGENE_PCIE_IP_VER_UNKN 0
	66	#define XGENE_PCIE_IP_VER_1 1
	67
5f6b6ccd TI	68	struct xgene_pcie_port {
	69	struct device_node *node;
	70	struct device *dev;
	71	struct clk *clk;
	72	void __iomem *csr_base;
	73	void __iomem *cfg_base;
	74	unsigned long cfg_addr;
	75	bool link_up;
f09f8735	76	u32 version;
5f6b6ccd TI	77	};
	78
	79	static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
	80	{
	81	return (addr & PCI_BASE_ADDRESS_MEM_MASK) \| flags;
	82	}
	83
5f6b6ccd TI	84	/*
	85	* When the address bit [17:16] is 2'b01, the Configuration access will be
	86	* treated as Type 1 and it will be forwarded to external PCIe device.
	87	*/
	88	static void __iomem xgene_pcie_get_cfg_base(struct pci_bus bus)
	89	{
	90	struct xgene_pcie_port *port = bus->sysdata;
	91
	92	if (bus->number >= (bus->primary + 1))
	93	return port->cfg_base + AXI_EP_CFG_ACCESS;
	94
	95	return port->cfg_base;
	96	}
	97
	98	/*
	99	* For Configuration request, RTDID register is used as Bus Number,
	100	* Device Number and Function number of the header fields.
	101	*/
	102	static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
	103	{
	104	struct xgene_pcie_port *port = bus->sysdata;
	105	unsigned int b, d, f;
	106	u32 rtdid_val = 0;
	107
	108	b = bus->number;
	109	d = PCI_SLOT(devfn);
	110	f = PCI_FUNC(devfn);
	111
	112	if (!pci_is_root_bus(bus))
	113	rtdid_val = (b << 8) \| (d << 3) \| f;
	114
	115	writel(rtdid_val, port->csr_base + RTDID);
	116	/* read the register back to ensure flush */
	117	readl(port->csr_base + RTDID);
	118	}
	119
	120	/*
	121	* X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
	122	* the translation from PCI bus to native BUS. Entire DDR region
	123	* is mapped into PCIe space using these registers, so it can be
	124	* reached by DMA from EP devices. The BAR0/1 of bridge should be
	125	* hidden during enumeration to avoid the sizing and resource allocation
	126	* by PCIe core.
	127	*/
	128	static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
	129	{
	130	if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) \|\|
	131	(offset == PCI_BASE_ADDRESS_1)))
	132	return true;
	133
	134	return false;
	135	}
	136
085a68d0	137	static void __iomem xgene_pcie_map_bus(struct pci_bus bus, unsigned int devfn,
350f8be5	138	int offset)
5f6b6ccd	139	{
ae4fa5f4	140	if ((pci_is_root_bus(bus) && devfn != 0) \|\|
350f8be5 RH	141	xgene_pcie_hide_rc_bars(bus, offset))
350f8be5 RH	142	return NULL;
5f6b6ccd TI	143
5f6b6ccd TI	144	xgene_pcie_set_rtdid_reg(bus, devfn);
085a68d0	145	return xgene_pcie_get_cfg_base(bus) + offset;
5f6b6ccd TI	146	}
5f6b6ccd TI	147
f09f8735 DD	148	static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
	149	int where, int size, u32 *val)
	150	{
	151	struct xgene_pcie_port *port = bus->sysdata;
	152
	153	if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
	154	PCIBIOS_SUCCESSFUL)
	155	return PCIBIOS_DEVICE_NOT_FOUND;
	156
	157	/*
	158	* The v1 controller has a bug in its Configuration Request
	159	* Retry Status (CRS) logic: when CRS is enabled and we read the
	160	* Vendor and Device ID of a non-existent device, the controller
	161	* fabricates return data of 0xFFFF0001 ("device exists but is not
	162	* ready") instead of 0xFFFFFFFF ("device does not exist"). This
	163	* causes the PCI core to retry the read until it times out.
	164	* Avoid this by not claiming to support CRS.
	165	*/
	166	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
	167	((where & ~0x3) == ROOT_CAP_AND_CTRL))
	168	*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
	169
	170	if (size <= 2)
	171	val = (val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
	172
	173	return PCIBIOS_SUCCESSFUL;
	174	}
	175
5f6b6ccd	176	static struct pci_ops xgene_pcie_ops = {
350f8be5	177	.map_bus = xgene_pcie_map_bus,
f09f8735	178	.read = xgene_pcie_config_read32,
350f8be5	179	.write = pci_generic_config_write32,
5f6b6ccd TI	180	};
	181
	182	static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
	183	u32 flags, u64 size)
	184	{
	185	u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) \| flags;
	186	u32 val32 = 0;
	187	u32 val;
	188
	189	val32 = readl(csr_base + addr);
	190	val = (val32 & 0x0000ffff) \| (lower_32_bits(mask) << 16);
	191	writel(val, csr_base + addr);
	192
	193	val32 = readl(csr_base + addr + 0x04);
	194	val = (val32 & 0xffff0000) \| (lower_32_bits(mask) >> 16);
	195	writel(val, csr_base + addr + 0x04);
	196
	197	val32 = readl(csr_base + addr + 0x04);
	198	val = (val32 & 0x0000ffff) \| (upper_32_bits(mask) << 16);
	199	writel(val, csr_base + addr + 0x04);
	200
	201	val32 = readl(csr_base + addr + 0x08);
	202	val = (val32 & 0xffff0000) \| (upper_32_bits(mask) >> 16);
	203	writel(val, csr_base + addr + 0x08);
	204
	205	return mask;
	206	}
	207
	208	static void xgene_pcie_linkup(struct xgene_pcie_port *port,
	209	u32 lanes, u32 speed)
	210	{
	211	void __iomem *csr_base = port->csr_base;
	212	u32 val32;
	213
	214	port->link_up = false;
	215	val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
	216	if (val32 & LINK_UP_MASK) {
	217	port->link_up = true;
	218	*speed = PIPE_PHY_RATE_RD(val32);
	219	val32 = readl(csr_base + BRIDGE_STATUS_0);
	220	*lanes = val32 >> 26;
	221	}
	222	}
	223
	224	static int xgene_pcie_init_port(struct xgene_pcie_port *port)
	225	{
	226	int rc;
	227
	228	port->clk = clk_get(port->dev, NULL);
	229	if (IS_ERR(port->clk)) {
	230	dev_err(port->dev, "clock not available\n");
	231	return -ENODEV;
	232	}
	233
	234	rc = clk_prepare_enable(port->clk);
	235	if (rc) {
	236	dev_err(port->dev, "clock enable failed\n");
	237	return rc;
	238	}
	239
	240	return 0;
	241	}
	242
	243	static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
244	struct platform_device *pdev)
245	{
246	struct resource *res;
247
248	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
249	port->csr_base = devm_ioremap_resource(port->dev, res);
250	if (IS_ERR(port->csr_base))
251	return PTR_ERR(port->csr_base);
252
253	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
254	port->cfg_base = devm_ioremap_resource(port->dev, res);
255	if (IS_ERR(port->cfg_base))
256	return PTR_ERR(port->cfg_base);
257	port->cfg_addr = res->start;
258
259	return 0;
260	}
261
262	static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
263	struct resource *res, u32 offset,
264	u64 cpu_addr, u64 pci_addr)
265	{
266	void __iomem *base = port->csr_base + offset;
267	resource_size_t size = resource_size(res);
268	u64 restype = resource_type(res);
269	u64 mask = 0;
270	u32 min_size;
271	u32 flag = EN_REG;
272
273	if (restype == IORESOURCE_MEM) {
274	min_size = SZ_128M;
275	} else {
276	min_size = 128;
277	flag \|= OB_LO_IO;
278	}
279
280	if (size >= min_size)
281	mask = ~(size - 1) \| flag;
282	else
283	dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n",
284	(u64)size, min_size);
285
286	writel(lower_32_bits(cpu_addr), base);
287	writel(upper_32_bits(cpu_addr), base + 0x04);
288	writel(lower_32_bits(mask), base + 0x08);
289	writel(upper_32_bits(mask), base + 0x0c);
290	writel(lower_32_bits(pci_addr), base + 0x10);
291	writel(upper_32_bits(pci_addr), base + 0x14);
292	}
293
294	static void xgene_pcie_setup_cfg_reg(void __iomem *csr_base, u64 addr)
295	{
296	writel(lower_32_bits(addr), csr_base + CFGBARL);
297	writel(upper_32_bits(addr), csr_base + CFGBARH);
298	writel(EN_REG, csr_base + CFGCTL);
299	}
300
301	static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
302	struct list_head *res,
303	resource_size_t io_base)
304	{
14d76b68	305	struct resource_entry *window;
5f6b6ccd TI	306	struct device *dev = port->dev;
	307	int ret;
	308
14d76b68	309	resource_list_for_each_entry(window, res) {
5f6b6ccd TI	310	struct resource *res = window->res;
	311	u64 restype = resource_type(res);
	312
	313	dev_dbg(port->dev, "%pR\n", res);
	314
	315	switch (restype) {
	316	case IORESOURCE_IO:
	317	xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
	318	res->start - window->offset);
	319	ret = pci_remap_iospace(res, io_base);
	320	if (ret < 0)
	321	return ret;
	322	break;
	323	case IORESOURCE_MEM:
	324	xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start,
	325	res->start - window->offset);
	326	break;
	327	case IORESOURCE_BUS:
	328	break;
	329	default:
	330	dev_err(dev, "invalid resource %pR\n", res);
	331	return -EINVAL;
	332	}
	333	}
	334	xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr);
	335
	336	return 0;
	337	}
	338
	339	static void xgene_pcie_setup_pims(void *addr, u64 pim, u64 size)
	340	{
	341	writel(lower_32_bits(pim), addr);
	342	writel(upper_32_bits(pim) \| EN_COHERENCY, addr + 0x04);
	343	writel(lower_32_bits(size), addr + 0x10);
	344	writel(upper_32_bits(size), addr + 0x14);
	345	}
	346
	347	/*
	348	* X-Gene PCIe support maximum 3 inbound memory regions
	349	* This function helps to select a region based on size of region
	350	*/
	351	static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
	352	{
	353	if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
	354	*ib_reg_mask \|= (1 << 1);
	355	return 1;
	356	}
	357
	358	if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
	359	*ib_reg_mask \|= (1 << 0);
	360	return 0;
	361	}
	362
	363	if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
	364	*ib_reg_mask \|= (1 << 2);
	365	return 2;
	366	}
	367
	368	return -EINVAL;
	369	}
	370
	371	static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
	372	struct of_pci_range range, u8 ib_reg_mask)
	373	{
374	void __iomem *csr_base = port->csr_base;
375	void __iomem *cfg_base = port->cfg_base;
376	void *bar_addr;
377	void *pim_addr;
378	u64 cpu_addr = range->cpu_addr;
379	u64 pci_addr = range->pci_addr;
380	u64 size = range->size;
381	u64 mask = ~(size - 1) \| EN_REG;
382	u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
383	u32 bar_low;
384	int region;
385
386	region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
387	if (region < 0) {
388	dev_warn(port->dev, "invalid pcie dma-range config\n");
389	return;
390	}
391
392	if (range->flags & IORESOURCE_PREFETCH)
393	flags \|= PCI_BASE_ADDRESS_MEM_PREFETCH;
394
395	bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
396	switch (region) {
397	case 0:
398	xgene_pcie_set_ib_mask(csr_base, BRIDGE_CFG_4, flags, size);
399	bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
400	writel(bar_low, bar_addr);
401	writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
402	pim_addr = csr_base + PIM1_1L;
403	break;
404	case 1:
405	bar_addr = csr_base + IBAR2;
406	writel(bar_low, bar_addr);
407	writel(lower_32_bits(mask), csr_base + IR2MSK);
408	pim_addr = csr_base + PIM2_1L;
409	break;
410	case 2:
411	bar_addr = csr_base + IBAR3L;
412	writel(bar_low, bar_addr);
413	writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
414	writel(lower_32_bits(mask), csr_base + IR3MSKL);
415	writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
416	pim_addr = csr_base + PIM3_1L;
417	break;
418	}
419
420	xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1));
421	}
422
423	static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
424	struct device_node *node)
425	{
426	const int na = 3, ns = 2;
427	int rlen;
428
429	parser->node = node;
430	parser->pna = of_n_addr_cells(node);
431	parser->np = parser->pna + na + ns;
432
433	parser->range = of_get_property(node, "dma-ranges", &rlen);
434	if (!parser->range)
435	return -ENOENT;
436	parser->end = parser->range + rlen / sizeof(__be32);
437
438	return 0;
439	}
440
441	static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
442	{
443	struct device_node *np = port->node;
444	struct of_pci_range range;
445	struct of_pci_range_parser parser;
446	struct device *dev = port->dev;
447	u8 ib_reg_mask = 0;
448
449	if (pci_dma_range_parser_init(&parser, np)) {
450	dev_err(dev, "missing dma-ranges property\n");
451	return -EINVAL;
452	}
453
454	/* Get the dma-ranges from DT */
455	for_each_of_pci_range(&parser, &range) {
456	u64 end = range.cpu_addr + range.size - 1;
457
458	dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
459	range.flags, range.cpu_addr, end, range.pci_addr);
460	xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
461	}
462	return 0;
463	}
464
465	/* clear BAR configuration which was done by firmware */
466	static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
467	{
468	int i;
469
470	for (i = PIM1_1L; i <= CFGCTL; i += 4)
471	writel(0x0, port->csr_base + i);
472	}
473
474	static int xgene_pcie_setup(struct xgene_pcie_port *port,
475	struct list_head *res,
476	resource_size_t io_base)
477	{
478	u32 val, lanes = 0, speed = 0;
479	int ret;
480
481	xgene_pcie_clear_config(port);
482
483	/* setup the vendor and device IDs correctly */
484	val = (XGENE_PCIE_DEVICEID << 16) \| XGENE_PCIE_VENDORID;
485	writel(val, port->csr_base + BRIDGE_CFG_0);
486
487	ret = xgene_pcie_map_ranges(port, res, io_base);
488	if (ret)
489	return ret;
490
491	ret = xgene_pcie_parse_map_dma_ranges(port);
492	if (ret)
493	return ret;
494
495	xgene_pcie_linkup(port, &lanes, &speed);
496	if (!port->link_up)
497	dev_info(port->dev, "(rc) link down\n");
498	else
499	dev_info(port->dev, "(rc) x%d gen-%d link up\n",
500	lanes, speed + 1);
501	return 0;
502	}
503
dcd19de3 DD	504	static int xgene_pcie_msi_enable(struct pci_bus *bus)
	505	{
	506	struct device_node *msi_node;
	507
	508	msi_node = of_parse_phandle(bus->dev.of_node,
	509	"msi-parent", 0);
	510	if (!msi_node)
	511	return -ENODEV;
	512
	513	bus->msi = of_pci_find_msi_chip_by_node(msi_node);
	514	if (!bus->msi)
	515	return -ENODEV;
	516
	517	bus->msi->dev = &bus->dev;
	518	return 0;
	519	}
	520
5f6b6ccd TI	521	static int xgene_pcie_probe_bridge(struct platform_device *pdev)
	522	{
	523	struct device_node *dn = pdev->dev.of_node;
	524	struct xgene_pcie_port *port;
	525	resource_size_t iobase = 0;
	526	struct pci_bus *bus;
	527	int ret;
	528	LIST_HEAD(res);
	529
	530	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	531	if (!port)
	532	return -ENOMEM;
	533	port->node = of_node_get(pdev->dev.of_node);
	534	port->dev = &pdev->dev;
	535
f09f8735 DD	536	port->version = XGENE_PCIE_IP_VER_UNKN;
	537	if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
	538	port->version = XGENE_PCIE_IP_VER_1;
	539
5f6b6ccd TI	540	ret = xgene_pcie_map_reg(port, pdev);
	541	if (ret)
	542	return ret;
	543
	544	ret = xgene_pcie_init_port(port);
	545	if (ret)
	546	return ret;
	547
	548	ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
	549	if (ret)
	550	return ret;
	551
	552	ret = xgene_pcie_setup(port, &res, iobase);
	553	if (ret)
	554	return ret;
	555
336b5be2 DD	556	bus = pci_create_root_bus(&pdev->dev, 0,
336b5be2 DD	557	&xgene_pcie_ops, port, &res);
5f6b6ccd TI	558	if (!bus)
	559	return -ENOMEM;
	560
dcd19de3 DD	561	if (IS_ENABLED(CONFIG_PCI_MSI))
	562	if (xgene_pcie_msi_enable(bus))
	563	dev_info(port->dev, "failed to enable MSI\n");
	564
336b5be2 DD	565	pci_scan_child_bus(bus);
	566	pci_assign_unassigned_bus_resources(bus);
	567	pci_bus_add_devices(bus);
	568
5f6b6ccd TI	569	platform_set_drvdata(pdev, port);
	570	return 0;
	571	}
	572
	573	static const struct of_device_id xgene_pcie_match_table[] = {
	574	{.compatible = "apm,xgene-pcie",},
	575	{},
	576	};
	577
	578	static struct platform_driver xgene_pcie_driver = {
	579	.driver = {
	580	.name = "xgene-pcie",
5f6b6ccd TI	581	.of_match_table = of_match_ptr(xgene_pcie_match_table),
	582	},
	583	.probe = xgene_pcie_probe_bridge,
	584	};
	585	module_platform_driver(xgene_pcie_driver);
	586
	587	MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>");
	588	MODULE_DESCRIPTION("APM X-Gene PCIe driver");
	589	MODULE_LICENSE("GPL v2");