[deliverable/linux.git] / drivers / pci / host / pcie-altera.c

/*
 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#define RP_TX_REG0			0x2000
#define RP_TX_REG1			0x2004
#define RP_TX_CNTRL			0x2008
#define RP_TX_EOP			0x2
#define RP_TX_SOP			0x1
#define RP_RXCPL_STATUS			0x2010
#define RP_RXCPL_EOP			0x2
#define RP_RXCPL_SOP			0x1
#define RP_RXCPL_REG0			0x2014
#define RP_RXCPL_REG1			0x2018
#define P2A_INT_STATUS			0x3060
#define P2A_INT_STS_ALL			0xf
#define P2A_INT_ENABLE			0x3070
#define P2A_INT_ENA_ALL			0xf
#define RP_LTSSM			0x3c64
#define RP_LTSSM_MASK			0x1f
#define LTSSM_L0			0xf

/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0		0x04	/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0		0x44	/* Configuration Write Type 0 */
#define TLP_FMTTYPE_CFGRD1		0x05	/* Configuration Read Type 1 */
#define TLP_FMTTYPE_CFGWR1		0x45	/* Configuration Write Type 1 */
#define TLP_PAYLOAD_SIZE		0x01
#define TLP_READ_TAG			0x1d
#define TLP_WRITE_TAG			0x10
#define TLP_CFG_DW0(fmttype)		(((fmttype) << 24) | TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(reqid, tag, be)	(((reqid) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)	\
				(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_REQ_ID(bus, devfn)		(((bus) << 8) | (devfn))
#define TLP_COMP_STATUS(s)		(((s) >> 12) & 7)
#define TLP_HDR_SIZE			3
#define TLP_LOOP			500
#define RP_DEVFN			0

#define LINK_UP_TIMEOUT			5000

#define INTX_NUM			4

#define DWORD_MASK			3

struct altera_pcie {
	struct platform_device	*pdev;
	void __iomem		*cra_base;
	int			irq;
	u8			root_bus_nr;
	struct irq_domain	*irq_domain;
	struct resource		bus_range;
	struct list_head	resources;
};

struct tlp_rp_regpair_t {
	u32 ctrl;
	u32 reg0;
	u32 reg1;
};

static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
			      const u32 reg)
{
	writel_relaxed(value, pcie->cra_base + reg);
}

static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
{
	return readl_relaxed(pcie->cra_base + reg);
}

static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
{
	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}

static void altera_pcie_retrain(struct pci_dev *dev)
{
	u16 linkcap, linkstat;
	struct altera_pcie *pcie = dev->bus->sysdata;
	int timeout =  0;

	if (!altera_pcie_link_is_up(pcie))
		return;

	/*
	 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
	 * current speed is 2.5 GB/s.
	 */
	pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);

	if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
		return;

	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
		pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
					 PCI_EXP_LNKCTL_RL);
		while (!altera_pcie_link_is_up(pcie)) {
			timeout++;
			if (timeout > LINK_UP_TIMEOUT)
				break;
			udelay(5);
		}
	}
}
DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);

/*
 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
 * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
 * using these registers, so it can be reached by DMA from EP devices.
 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
 * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
 * should be hidden during enumeration to avoid the sizing and resource
 * allocation by PCIe core.
 */
static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
				    int offset)
{
	if (pci_is_root_bus(bus) && (devfn == 0) &&
	    (offset == PCI_BASE_ADDRESS_0))
		return true;

	return false;
}

static void tlp_write_tx(struct altera_pcie *pcie,
			 struct tlp_rp_regpair_t *tlp_rp_regdata)
{
	cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
	cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
	cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
}

static bool altera_pcie_valid_config(struct altera_pcie *pcie,
				     struct pci_bus *bus, int dev)
{
	/* If there is no link, then there is no device */
	if (bus->number != pcie->root_bus_nr) {
		if (!altera_pcie_link_is_up(pcie))
			return false;
	}

	/* access only one slot on each root port */
	if (bus->number == pcie->root_bus_nr && dev > 0)
		return false;

	/*
	 * Do not read more than one device on the bus directly attached
	 * to root port, root port can only attach to one downstream port.
	 */
	if (bus->primary == pcie->root_bus_nr && dev > 0)
		return false;

	 return true;
}

static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
{
	int i;
	bool sop = 0;
	u32 ctrl;
	u32 reg0, reg1;
	u32 comp_status = 1;

	/*
	 * Minimum 2 loops to read TLP headers and 1 loop to read data
	 * payload.
	 */
	for (i = 0; i < TLP_LOOP; i++) {
		ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
		if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
			reg0 = cra_readl(pcie, RP_RXCPL_REG0);
			reg1 = cra_readl(pcie, RP_RXCPL_REG1);

			if (ctrl & RP_RXCPL_SOP) {
				sop = true;
				comp_status = TLP_COMP_STATUS(reg1);
			}

			if (ctrl & RP_RXCPL_EOP) {
				if (comp_status)
					return PCIBIOS_DEVICE_NOT_FOUND;

				if (value)
					*value = reg0;

				return PCIBIOS_SUCCESSFUL;
			}
		}
		udelay(5);
	}

	return PCIBIOS_DEVICE_NOT_FOUND;
}

static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
			     u32 data, bool align)
{
	struct tlp_rp_regpair_t tlp_rp_regdata;

	tlp_rp_regdata.reg0 = headers[0];
	tlp_rp_regdata.reg1 = headers[1];
	tlp_rp_regdata.ctrl = RP_TX_SOP;
	tlp_write_tx(pcie, &tlp_rp_regdata);

	if (align) {
		tlp_rp_regdata.reg0 = headers[2];
		tlp_rp_regdata.reg1 = 0;
		tlp_rp_regdata.ctrl = 0;
		tlp_write_tx(pcie, &tlp_rp_regdata);

		tlp_rp_regdata.reg0 = data;
		tlp_rp_regdata.reg1 = 0;
	} else {
		tlp_rp_regdata.reg0 = headers[2];
		tlp_rp_regdata.reg1 = data;
	}

	tlp_rp_regdata.ctrl = RP_TX_EOP;
	tlp_write_tx(pcie, &tlp_rp_regdata);
}

static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
			      int where, u8 byte_en, u32 *value)
{
	u32 headers[TLP_HDR_SIZE];

	if (bus == pcie->root_bus_nr)
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
	else
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);

	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
					TLP_READ_TAG, byte_en);
	headers[2] = TLP_CFG_DW2(bus, devfn, where);

	tlp_write_packet(pcie, headers, 0, false);

	return tlp_read_packet(pcie, value);
}

static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
			       int where, u8 byte_en, u32 value)
{
	u32 headers[TLP_HDR_SIZE];
	int ret;

	if (bus == pcie->root_bus_nr)
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
	else
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);

	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
					TLP_WRITE_TAG, byte_en);
	headers[2] = TLP_CFG_DW2(bus, devfn, where);

	/* check alignment to Qword */
	if ((where & 0x7) == 0)
		tlp_write_packet(pcie, headers, value, true);
	else
		tlp_write_packet(pcie, headers, value, false);

	ret = tlp_read_packet(pcie, NULL);
	if (ret != PCIBIOS_SUCCESSFUL)
		return ret;

	/*
	 * Monitor changes to PCI_PRIMARY_BUS register on root port
	 * and update local copy of root bus number accordingly.
	 */
	if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
		pcie->root_bus_nr = (u8)(value);

	return PCIBIOS_SUCCESSFUL;
}

static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 *value)
{
	struct altera_pcie *pcie = bus->sysdata;
	int ret;
	u32 data;
	u8 byte_en;

	if (altera_pcie_hide_rc_bar(bus, devfn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
		*value = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	switch (size) {
	case 1:
		byte_en = 1 << (where & 3);
		break;
	case 2:
		byte_en = 3 << (where & 3);
		break;
	default:
		byte_en = 0xf;
		break;
	}

	ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
				 (where & ~DWORD_MASK), byte_en, &data);
	if (ret != PCIBIOS_SUCCESSFUL)
		return ret;

	switch (size) {
	case 1:
		*value = (data >> (8 * (where & 0x3))) & 0xff;
		break;
	case 2:
		*value = (data >> (8 * (where & 0x2))) & 0xffff;
		break;
	default:
		*value = data;
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
				 int where, int size, u32 value)
{
	struct altera_pcie *pcie = bus->sysdata;
	u32 data32;
	u32 shift = 8 * (where & 3);
	u8 byte_en;

	if (altera_pcie_hide_rc_bar(bus, devfn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
		return PCIBIOS_DEVICE_NOT_FOUND;

	switch (size) {
	case 1:
		data32 = (value & 0xff) << shift;
		byte_en = 1 << (where & 3);
		break;
	case 2:
		data32 = (value & 0xffff) << shift;
		byte_en = 3 << (where & 3);
		break;
	default:
		data32 = value;
		byte_en = 0xf;
		break;
	}

	return tlp_cfg_dword_write(pcie, bus->number, devfn,
		(where & ~DWORD_MASK), byte_en, data32);
}

static struct pci_ops altera_pcie_ops = {
	.read = altera_pcie_cfg_read,
	.write = altera_pcie_cfg_write,
};

static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	irq_set_chip_data(irq, domain->host_data);

	return 0;
}

static const struct irq_domain_ops intx_domain_ops = {
	.map = altera_pcie_intx_map,
};

static void altera_pcie_isr(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct altera_pcie *pcie;
	unsigned long status;
	u32 bit;
	u32 virq;

	chained_irq_enter(chip, desc);
	pcie = irq_desc_get_handler_data(desc);

	while ((status = cra_readl(pcie, P2A_INT_STATUS)
		& P2A_INT_STS_ALL) != 0) {
		for_each_set_bit(bit, &status, INTX_NUM) {
			/* clear interrupts */
			cra_writel(pcie, 1 << bit, P2A_INT_STATUS);

			virq = irq_find_mapping(pcie->irq_domain, bit + 1);
			if (virq)
				generic_handle_irq(virq);
			else
				dev_err(&pcie->pdev->dev,
					"unexpected IRQ, INT%d\n", bit);
		}
	}

	chained_irq_exit(chip, desc);
}

static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
{
	int err, res_valid = 0;
	struct device *dev = &pcie->pdev->dev;
	struct device_node *np = dev->of_node;
	struct resource_entry *win;

	err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
					       NULL);
	if (err)
		return err;

	err = devm_request_pci_bus_resources(dev, &pcie->resources);
	if (err)
		goto out_release_res;

	resource_list_for_each_entry(win, &pcie->resources) {
		struct resource *res = win->res;

		if (resource_type(res) == IORESOURCE_MEM)
			res_valid |= !(res->flags & IORESOURCE_PREFETCH);
	}

	if (res_valid)
		return 0;

	dev_err(dev, "non-prefetchable memory resource required\n");
	err = -EINVAL;

out_release_res:
	pci_free_resource_list(&pcie->resources);
	return err;
}

static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
{
	struct device *dev = &pcie->pdev->dev;
	struct device_node *node = dev->of_node;

	/* Setup INTx */
	pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
					&intx_domain_ops, pcie);
	if (!pcie->irq_domain) {
		dev_err(dev, "Failed to get a INTx IRQ domain\n");
		return -ENOMEM;
	}

	return 0;
}

static int altera_pcie_parse_dt(struct altera_pcie *pcie)
{
	struct resource *cra;
	struct platform_device *pdev = pcie->pdev;

	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
	if (!cra) {
		dev_err(&pdev->dev, "no Cra memory resource defined\n");
		return -ENODEV;
	}

	pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
	if (IS_ERR(pcie->cra_base)) {
		dev_err(&pdev->dev, "failed to map cra memory\n");
		return PTR_ERR(pcie->cra_base);
	}

	/* setup IRQ */
	pcie->irq = platform_get_irq(pdev, 0);
	if (pcie->irq <= 0) {
		dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
		return -EINVAL;
	}

	irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);

	return 0;
}

static int altera_pcie_probe(struct platform_device *pdev)
{
	struct altera_pcie *pcie;
	struct pci_bus *bus;
	struct pci_bus *child;
	int ret;

	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
	if (!pcie)
		return -ENOMEM;

	pcie->pdev = pdev;

	ret = altera_pcie_parse_dt(pcie);
	if (ret) {
		dev_err(&pdev->dev, "Parsing DT failed\n");
		return ret;
	}

	INIT_LIST_HEAD(&pcie->resources);

	ret = altera_pcie_parse_request_of_pci_ranges(pcie);
	if (ret) {
		dev_err(&pdev->dev, "Failed add resources\n");
		return ret;
	}

	ret = altera_pcie_init_irq_domain(pcie);
	if (ret) {
		dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
		return ret;
	}

	/* clear all interrupts */
	cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
	/* enable all interrupts */
	cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);

	bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
				pcie, &pcie->resources);
	if (!bus)
		return -ENOMEM;

	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
	pci_assign_unassigned_bus_resources(bus);

	/* Configure PCI Express setting. */
	list_for_each_entry(child, &bus->children, node)
		pcie_bus_configure_settings(child);

	pci_bus_add_devices(bus);

	platform_set_drvdata(pdev, pcie);
	return ret;
}

static const struct of_device_id altera_pcie_of_match[] = {
	{ .compatible = "altr,pcie-root-port-1.0", },
	{},
};
MODULE_DEVICE_TABLE(of, altera_pcie_of_match);

static struct platform_driver altera_pcie_driver = {
	.probe		= altera_pcie_probe,
	.driver = {
		.name	= "altera-pcie",
		.of_match_table = altera_pcie_of_match,
		.suppress_bind_attrs = true,
	},
};

static int altera_pcie_init(void)
{
	return platform_driver_register(&altera_pcie_driver);
}
module_init(altera_pcie_init);

MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
MODULE_DESCRIPTION("Altera PCIe host controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
eaa6111b LFT	1	/*
	2	* Copyright Altera Corporation (C) 2013-2015. All rights reserved
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/delay.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/irqchip/chained_irq.h>
	20	#include <linux/module.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
	23	#include <linux/of_pci.h>
	24	#include <linux/pci.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/slab.h>
	27
	28	#define RP_TX_REG0 0x2000
	29	#define RP_TX_REG1 0x2004
	30	#define RP_TX_CNTRL 0x2008
	31	#define RP_TX_EOP 0x2
	32	#define RP_TX_SOP 0x1
	33	#define RP_RXCPL_STATUS 0x2010
	34	#define RP_RXCPL_EOP 0x2
	35	#define RP_RXCPL_SOP 0x1
	36	#define RP_RXCPL_REG0 0x2014
	37	#define RP_RXCPL_REG1 0x2018
	38	#define P2A_INT_STATUS 0x3060
	39	#define P2A_INT_STS_ALL 0xf
	40	#define P2A_INT_ENABLE 0x3070
	41	#define P2A_INT_ENA_ALL 0xf
	42	#define RP_LTSSM 0x3c64
eff31f40	43	#define RP_LTSSM_MASK 0x1f
eaa6111b LFT	44	#define LTSSM_L0 0xf
	45
	46	/* TLP configuration type 0 and 1 */
	47	#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
	48	#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
	49	#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
	50	#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
	51	#define TLP_PAYLOAD_SIZE 0x01
	52	#define TLP_READ_TAG 0x1d
	53	#define TLP_WRITE_TAG 0x10
	54	#define TLP_CFG_DW0(fmttype) (((fmttype) << 24) \| TLP_PAYLOAD_SIZE)
	55	#define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) \| (tag << 8) \| (be))
	56	#define TLP_CFG_DW2(bus, devfn, offset) \
	57	(((bus) << 24) \| ((devfn) << 16) \| (offset))
	58	#define TLP_REQ_ID(bus, devfn) (((bus) << 8) \| (devfn))
ea1d3795	59	#define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
eaa6111b LFT	60	#define TLP_HDR_SIZE 3
eaa6111b LFT	61	#define TLP_LOOP 500
23ec5670	62	#define RP_DEVFN 0
eaa6111b	63
3a928e98 LFT	64	#define LINK_UP_TIMEOUT 5000
3a928e98 LFT	65
eaa6111b LFT	66	#define INTX_NUM 4
	67
	68	#define DWORD_MASK 3
	69
	70	struct altera_pcie {
	71	struct platform_device *pdev;
	72	void __iomem *cra_base;
	73	int irq;
	74	u8 root_bus_nr;
	75	struct irq_domain *irq_domain;
	76	struct resource bus_range;
	77	struct list_head resources;
	78	};
	79
	80	struct tlp_rp_regpair_t {
	81	u32 ctrl;
	82	u32 reg0;
	83	u32 reg1;
	84	};
	85
f8be11ae BH	86	static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
	87	const u32 reg)
	88	{
	89	writel_relaxed(value, pcie->cra_base + reg);
	90	}
	91
	92	static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
	93	{
	94	return readl_relaxed(pcie->cra_base + reg);
	95	}
	96
	97	static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
	98	{
	99	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
	100	}
	101
eaa6111b LFT	102	static void altera_pcie_retrain(struct pci_dev *dev)
	103	{
	104	u16 linkcap, linkstat;
c622032e	105	struct altera_pcie *pcie = dev->bus->sysdata;
3a928e98	106	int timeout = 0;
c622032e LFT	107
	108	if (!altera_pcie_link_is_up(pcie))
	109	return;
eaa6111b LFT	110
	111	/*
	112	* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
	113	* current speed is 2.5 GB/s.
	114	*/
	115	pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
	116
	117	if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
	118	return;
	119
	120	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
3a928e98	121	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
eaa6111b LFT	122	pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
eaa6111b LFT	123	PCI_EXP_LNKCTL_RL);
3a928e98 LFT	124	while (!altera_pcie_link_is_up(pcie)) {
	125	timeout++;
	126	if (timeout > LINK_UP_TIMEOUT)
	127	break;
	128	udelay(5);
	129	}
	130	}
eaa6111b LFT	131	}
	132	DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
	133
	134	/*
	135	* Altera PCIe port uses BAR0 of RC's configuration space as the translation
	136	* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
	137	* using these registers, so it can be reached by DMA from EP devices.
	138	* This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
	139	* from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
	140	* should be hidden during enumeration to avoid the sizing and resource
	141	* allocation by PCIe core.
	142	*/
	143	static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
	144	int offset)
	145	{
	146	if (pci_is_root_bus(bus) && (devfn == 0) &&
	147	(offset == PCI_BASE_ADDRESS_0))
	148	return true;
	149
	150	return false;
	151	}
	152
eaa6111b LFT	153	static void tlp_write_tx(struct altera_pcie *pcie,
	154	struct tlp_rp_regpair_t *tlp_rp_regdata)
	155	{
	156	cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
	157	cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
	158	cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
	159	}
	160
eaa6111b LFT	161	static bool altera_pcie_valid_config(struct altera_pcie *pcie,
	162	struct pci_bus *bus, int dev)
	163	{
	164	/* If there is no link, then there is no device */
	165	if (bus->number != pcie->root_bus_nr) {
	166	if (!altera_pcie_link_is_up(pcie))
	167	return false;
	168	}
	169
	170	/* access only one slot on each root port */
	171	if (bus->number == pcie->root_bus_nr && dev > 0)
	172	return false;
	173
	174	/*
	175	* Do not read more than one device on the bus directly attached
	176	* to root port, root port can only attach to one downstream port.
	177	*/
	178	if (bus->primary == pcie->root_bus_nr && dev > 0)
	179	return false;
	180
	181	return true;
	182	}
	183
	184	static int tlp_read_packet(struct altera_pcie pcie, u32 value)
	185	{
7f52f314	186	int i;
eaa6111b LFT	187	bool sop = 0;
	188	u32 ctrl;
	189	u32 reg0, reg1;
ea1d3795	190	u32 comp_status = 1;
eaa6111b LFT	191
	192	/*
	193	* Minimum 2 loops to read TLP headers and 1 loop to read data
	194	* payload.
	195	*/
7f52f314	196	for (i = 0; i < TLP_LOOP; i++) {
eaa6111b LFT	197	ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
	198	if ((ctrl & RP_RXCPL_SOP) \|\| (ctrl & RP_RXCPL_EOP) \|\| sop) {
	199	reg0 = cra_readl(pcie, RP_RXCPL_REG0);
	200	reg1 = cra_readl(pcie, RP_RXCPL_REG1);
	201
ea1d3795	202	if (ctrl & RP_RXCPL_SOP) {
eaa6111b	203	sop = true;
ea1d3795 LFT	204	comp_status = TLP_COMP_STATUS(reg1);
ea1d3795 LFT	205	}
eaa6111b LFT	206
eaa6111b LFT	207	if (ctrl & RP_RXCPL_EOP) {
ea1d3795 LFT	208	if (comp_status)
	209	return PCIBIOS_DEVICE_NOT_FOUND;
	210
eaa6111b LFT	211	if (value)
eaa6111b LFT	212	*value = reg0;
ea1d3795	213
eaa6111b LFT	214	return PCIBIOS_SUCCESSFUL;
	215	}
	216	}
	217	udelay(5);
	218	}
	219
ea1d3795	220	return PCIBIOS_DEVICE_NOT_FOUND;
eaa6111b LFT	221	}
	222
	223	static void tlp_write_packet(struct altera_pcie pcie, u32 headers,
	224	u32 data, bool align)
	225	{
	226	struct tlp_rp_regpair_t tlp_rp_regdata;
	227
	228	tlp_rp_regdata.reg0 = headers[0];
	229	tlp_rp_regdata.reg1 = headers[1];
	230	tlp_rp_regdata.ctrl = RP_TX_SOP;
	231	tlp_write_tx(pcie, &tlp_rp_regdata);
	232
	233	if (align) {
	234	tlp_rp_regdata.reg0 = headers[2];
	235	tlp_rp_regdata.reg1 = 0;
	236	tlp_rp_regdata.ctrl = 0;
	237	tlp_write_tx(pcie, &tlp_rp_regdata);
	238
	239	tlp_rp_regdata.reg0 = data;
	240	tlp_rp_regdata.reg1 = 0;
	241	} else {
	242	tlp_rp_regdata.reg0 = headers[2];
	243	tlp_rp_regdata.reg1 = data;
	244	}
	245
	246	tlp_rp_regdata.ctrl = RP_TX_EOP;
	247	tlp_write_tx(pcie, &tlp_rp_regdata);
	248	}
	249
	250	static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
	251	int where, u8 byte_en, u32 *value)
	252	{
	253	u32 headers[TLP_HDR_SIZE];
	254
	255	if (bus == pcie->root_bus_nr)
	256	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
	257	else
	258	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
	259
23ec5670	260	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
eaa6111b LFT	261	TLP_READ_TAG, byte_en);
	262	headers[2] = TLP_CFG_DW2(bus, devfn, where);
	263
	264	tlp_write_packet(pcie, headers, 0, false);
	265
	266	return tlp_read_packet(pcie, value);
	267	}
	268
	269	static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
	270	int where, u8 byte_en, u32 value)
	271	{
	272	u32 headers[TLP_HDR_SIZE];
	273	int ret;
	274
	275	if (bus == pcie->root_bus_nr)
	276	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
	277	else
	278	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
	279
23ec5670	280	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
eaa6111b LFT	281	TLP_WRITE_TAG, byte_en);
	282	headers[2] = TLP_CFG_DW2(bus, devfn, where);
	283
	284	/* check alignment to Qword */
	285	if ((where & 0x7) == 0)
	286	tlp_write_packet(pcie, headers, value, true);
	287	else
	288	tlp_write_packet(pcie, headers, value, false);
	289
	290	ret = tlp_read_packet(pcie, NULL);
	291	if (ret != PCIBIOS_SUCCESSFUL)
	292	return ret;
	293
	294	/*
	295	* Monitor changes to PCI_PRIMARY_BUS register on root port
	296	* and update local copy of root bus number accordingly.
	297	*/
	298	if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
	299	pcie->root_bus_nr = (u8)(value);
	300
	301	return PCIBIOS_SUCCESSFUL;
	302	}
	303
	304	static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
	305	int where, int size, u32 *value)
	306	{
	307	struct altera_pcie *pcie = bus->sysdata;
	308	int ret;
	309	u32 data;
	310	u8 byte_en;
	311
	312	if (altera_pcie_hide_rc_bar(bus, devfn, where))
	313	return PCIBIOS_BAD_REGISTER_NUMBER;
	314
	315	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
	316	*value = 0xffffffff;
	317	return PCIBIOS_DEVICE_NOT_FOUND;
	318	}
	319
	320	switch (size) {
	321	case 1:
	322	byte_en = 1 << (where & 3);
	323	break;
	324	case 2:
	325	byte_en = 3 << (where & 3);
	326	break;
	327	default:
	328	byte_en = 0xf;
	329	break;
	330	}
	331
	332	ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
	333	(where & ~DWORD_MASK), byte_en, &data);
	334	if (ret != PCIBIOS_SUCCESSFUL)
	335	return ret;
	336
	337	switch (size) {
	338	case 1:
	339	value = (data >> (8 (where & 0x3))) & 0xff;
	340	break;
	341	case 2:
	342	value = (data >> (8 (where & 0x2))) & 0xffff;
	343	break;
	344	default:
345	*value = data;
346	break;
347	}
348
349	return PCIBIOS_SUCCESSFUL;
350	}
351
352	static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
353	int where, int size, u32 value)
354	{
355	struct altera_pcie *pcie = bus->sysdata;
356	u32 data32;
357	u32 shift = 8 * (where & 3);
358	u8 byte_en;
359
360	if (altera_pcie_hide_rc_bar(bus, devfn, where))
361	return PCIBIOS_BAD_REGISTER_NUMBER;
362
363	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
364	return PCIBIOS_DEVICE_NOT_FOUND;
365
366	switch (size) {
367	case 1:
368	data32 = (value & 0xff) << shift;
369	byte_en = 1 << (where & 3);
370	break;
371	case 2:
372	data32 = (value & 0xffff) << shift;
373	byte_en = 3 << (where & 3);
374	break;
375	default:
376	data32 = value;
377	byte_en = 0xf;
378	break;
379	}
380
381	return tlp_cfg_dword_write(pcie, bus->number, devfn,
382	(where & ~DWORD_MASK), byte_en, data32);
383	}
384
385	static struct pci_ops altera_pcie_ops = {
386	.read = altera_pcie_cfg_read,
387	.write = altera_pcie_cfg_write,
388	};
389
390	static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
391	irq_hw_number_t hwirq)
392	{
393	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
394	irq_set_chip_data(irq, domain->host_data);
395
396	return 0;
397	}
398
399	static const struct irq_domain_ops intx_domain_ops = {
400	.map = altera_pcie_intx_map,
401	};
402
403	static void altera_pcie_isr(struct irq_desc *desc)
404	{
405	struct irq_chip *chip = irq_desc_get_chip(desc);
406	struct altera_pcie *pcie;
407	unsigned long status;
408	u32 bit;
409	u32 virq;
410
411	chained_irq_enter(chip, desc);
412	pcie = irq_desc_get_handler_data(desc);
413
414	while ((status = cra_readl(pcie, P2A_INT_STATUS)
415	& P2A_INT_STS_ALL) != 0) {
416	for_each_set_bit(bit, &status, INTX_NUM) {
417	/* clear interrupts */
418	cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
419
420	virq = irq_find_mapping(pcie->irq_domain, bit + 1);
421	if (virq)
422	generic_handle_irq(virq);
423	else
424	dev_err(&pcie->pdev->dev,
425	"unexpected IRQ, INT%d\n", bit);
426	}
427	}
428
429	chained_irq_exit(chip, desc);
430	}
431
eaa6111b LFT	432	static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
	433	{
	434	int err, res_valid = 0;
	435	struct device *dev = &pcie->pdev->dev;
	436	struct device_node *np = dev->of_node;
	437	struct resource_entry *win;
	438
	439	err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
	440	NULL);
	441	if (err)
	442	return err;
	443
74462284 BH	444	err = devm_request_pci_bus_resources(dev, &pcie->resources);
	445	if (err)
	446	goto out_release_res;
	447
eaa6111b	448	resource_list_for_each_entry(win, &pcie->resources) {
74462284	449	struct resource *res = win->res;
eaa6111b	450
ba4f6d92	451	if (resource_type(res) == IORESOURCE_MEM)
eaa6111b	452	res_valid \|= !(res->flags & IORESOURCE_PREFETCH);
eaa6111b LFT	453	}
eaa6111b LFT	454
ba4f6d92 BH	455	if (res_valid)
ba4f6d92 BH	456	return 0;
eaa6111b	457
ba4f6d92 BH	458	dev_err(dev, "non-prefetchable memory resource required\n");
ba4f6d92 BH	459	err = -EINVAL;
eaa6111b LFT	460
eaa6111b LFT	461	out_release_res:
ba4f6d92	462	pci_free_resource_list(&pcie->resources);
eaa6111b LFT	463	return err;
	464	}
	465
	466	static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
	467	{
	468	struct device *dev = &pcie->pdev->dev;
	469	struct device_node *node = dev->of_node;
	470
	471	/* Setup INTx */
99496bd2	472	pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
eaa6111b LFT	473	&intx_domain_ops, pcie);
	474	if (!pcie->irq_domain) {
	475	dev_err(dev, "Failed to get a INTx IRQ domain\n");
	476	return -ENOMEM;
	477	}
	478
	479	return 0;
	480	}
	481
	482	static int altera_pcie_parse_dt(struct altera_pcie *pcie)
	483	{
	484	struct resource *cra;
	485	struct platform_device *pdev = pcie->pdev;
	486
	487	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
	488	if (!cra) {
	489	dev_err(&pdev->dev, "no Cra memory resource defined\n");
	490	return -ENODEV;
	491	}
	492
	493	pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
	494	if (IS_ERR(pcie->cra_base)) {
	495	dev_err(&pdev->dev, "failed to map cra memory\n");
	496	return PTR_ERR(pcie->cra_base);
	497	}
	498
	499	/* setup IRQ */
	500	pcie->irq = platform_get_irq(pdev, 0);
	501	if (pcie->irq <= 0) {
	502	dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
	503	return -EINVAL;
	504	}
	505
	506	irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
	507
	508	return 0;
	509	}
	510
	511	static int altera_pcie_probe(struct platform_device *pdev)
	512	{
	513	struct altera_pcie *pcie;
	514	struct pci_bus *bus;
	515	struct pci_bus *child;
	516	int ret;
	517
	518	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
	519	if (!pcie)
	520	return -ENOMEM;
	521
	522	pcie->pdev = pdev;
	523
	524	ret = altera_pcie_parse_dt(pcie);
	525	if (ret) {
	526	dev_err(&pdev->dev, "Parsing DT failed\n");
	527	return ret;
	528	}
	529
	530	INIT_LIST_HEAD(&pcie->resources);
	531
	532	ret = altera_pcie_parse_request_of_pci_ranges(pcie);
	533	if (ret) {
	534	dev_err(&pdev->dev, "Failed add resources\n");
	535	return ret;
	536	}
537
538	ret = altera_pcie_init_irq_domain(pcie);
539	if (ret) {
540	dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
541	return ret;
542	}
543
544	/* clear all interrupts */
545	cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
546	/* enable all interrupts */
547	cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
548
549	bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
550	pcie, &pcie->resources);
551	if (!bus)
552	return -ENOMEM;
553
554	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
555	pci_assign_unassigned_bus_resources(bus);
556
557	/* Configure PCI Express setting. */
558	list_for_each_entry(child, &bus->children, node)
559	pcie_bus_configure_settings(child);
560
561	pci_bus_add_devices(bus);
562
563	platform_set_drvdata(pdev, pcie);
564	return ret;
565	}
566
567	static const struct of_device_id altera_pcie_of_match[] = {
568	{ .compatible = "altr,pcie-root-port-1.0", },
569	{},
570	};
571	MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
572
573	static struct platform_driver altera_pcie_driver = {
574	.probe = altera_pcie_probe,
575	.driver = {
576	.name = "altera-pcie",
577	.of_match_table = altera_pcie_of_match,
578	.suppress_bind_attrs = true,
579	},
580	};
581
582	static int altera_pcie_init(void)
583	{
584	return platform_driver_register(&altera_pcie_driver);
585	}
586	module_init(altera_pcie_init);
587
588	MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
589	MODULE_DESCRIPTION("Altera PCIe host controller driver");
590	MODULE_LICENSE("GPL v2");