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eaa6111b LFT |
1 | /* |
2 | * Copyright Altera Corporation (C) 2013-2015. All rights reserved | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irqchip/chained_irq.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_pci.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/slab.h> | |
27 | ||
28 | #define RP_TX_REG0 0x2000 | |
29 | #define RP_TX_REG1 0x2004 | |
30 | #define RP_TX_CNTRL 0x2008 | |
31 | #define RP_TX_EOP 0x2 | |
32 | #define RP_TX_SOP 0x1 | |
33 | #define RP_RXCPL_STATUS 0x2010 | |
34 | #define RP_RXCPL_EOP 0x2 | |
35 | #define RP_RXCPL_SOP 0x1 | |
36 | #define RP_RXCPL_REG0 0x2014 | |
37 | #define RP_RXCPL_REG1 0x2018 | |
38 | #define P2A_INT_STATUS 0x3060 | |
39 | #define P2A_INT_STS_ALL 0xf | |
40 | #define P2A_INT_ENABLE 0x3070 | |
41 | #define P2A_INT_ENA_ALL 0xf | |
42 | #define RP_LTSSM 0x3c64 | |
43 | #define LTSSM_L0 0xf | |
44 | ||
45 | /* TLP configuration type 0 and 1 */ | |
46 | #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ | |
47 | #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ | |
48 | #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ | |
49 | #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ | |
50 | #define TLP_PAYLOAD_SIZE 0x01 | |
51 | #define TLP_READ_TAG 0x1d | |
52 | #define TLP_WRITE_TAG 0x10 | |
53 | #define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE) | |
54 | #define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be)) | |
55 | #define TLP_CFG_DW2(bus, devfn, offset) \ | |
56 | (((bus) << 24) | ((devfn) << 16) | (offset)) | |
57 | #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) | |
58 | #define TLP_HDR_SIZE 3 | |
59 | #define TLP_LOOP 500 | |
60 | ||
61 | #define INTX_NUM 4 | |
62 | ||
63 | #define DWORD_MASK 3 | |
64 | ||
65 | struct altera_pcie { | |
66 | struct platform_device *pdev; | |
67 | void __iomem *cra_base; | |
68 | int irq; | |
69 | u8 root_bus_nr; | |
70 | struct irq_domain *irq_domain; | |
71 | struct resource bus_range; | |
72 | struct list_head resources; | |
73 | }; | |
74 | ||
75 | struct tlp_rp_regpair_t { | |
76 | u32 ctrl; | |
77 | u32 reg0; | |
78 | u32 reg1; | |
79 | }; | |
80 | ||
81 | static void altera_pcie_retrain(struct pci_dev *dev) | |
82 | { | |
83 | u16 linkcap, linkstat; | |
84 | ||
85 | /* | |
86 | * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but | |
87 | * current speed is 2.5 GB/s. | |
88 | */ | |
89 | pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap); | |
90 | ||
91 | if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) | |
92 | return; | |
93 | ||
94 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat); | |
95 | if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) | |
96 | pcie_capability_set_word(dev, PCI_EXP_LNKCTL, | |
97 | PCI_EXP_LNKCTL_RL); | |
98 | } | |
99 | DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain); | |
100 | ||
101 | /* | |
102 | * Altera PCIe port uses BAR0 of RC's configuration space as the translation | |
103 | * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space | |
104 | * using these registers, so it can be reached by DMA from EP devices. | |
105 | * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt | |
106 | * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge | |
107 | * should be hidden during enumeration to avoid the sizing and resource | |
108 | * allocation by PCIe core. | |
109 | */ | |
110 | static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, | |
111 | int offset) | |
112 | { | |
113 | if (pci_is_root_bus(bus) && (devfn == 0) && | |
114 | (offset == PCI_BASE_ADDRESS_0)) | |
115 | return true; | |
116 | ||
117 | return false; | |
118 | } | |
119 | ||
120 | static inline void cra_writel(struct altera_pcie *pcie, const u32 value, | |
121 | const u32 reg) | |
122 | { | |
123 | writel_relaxed(value, pcie->cra_base + reg); | |
124 | } | |
125 | ||
126 | static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) | |
127 | { | |
128 | return readl_relaxed(pcie->cra_base + reg); | |
129 | } | |
130 | ||
131 | static void tlp_write_tx(struct altera_pcie *pcie, | |
132 | struct tlp_rp_regpair_t *tlp_rp_regdata) | |
133 | { | |
134 | cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0); | |
135 | cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); | |
136 | cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL); | |
137 | } | |
138 | ||
139 | static bool altera_pcie_link_is_up(struct altera_pcie *pcie) | |
140 | { | |
141 | return !!(cra_readl(pcie, RP_LTSSM) & LTSSM_L0); | |
142 | } | |
143 | ||
144 | static bool altera_pcie_valid_config(struct altera_pcie *pcie, | |
145 | struct pci_bus *bus, int dev) | |
146 | { | |
147 | /* If there is no link, then there is no device */ | |
148 | if (bus->number != pcie->root_bus_nr) { | |
149 | if (!altera_pcie_link_is_up(pcie)) | |
150 | return false; | |
151 | } | |
152 | ||
153 | /* access only one slot on each root port */ | |
154 | if (bus->number == pcie->root_bus_nr && dev > 0) | |
155 | return false; | |
156 | ||
157 | /* | |
158 | * Do not read more than one device on the bus directly attached | |
159 | * to root port, root port can only attach to one downstream port. | |
160 | */ | |
161 | if (bus->primary == pcie->root_bus_nr && dev > 0) | |
162 | return false; | |
163 | ||
164 | return true; | |
165 | } | |
166 | ||
167 | static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) | |
168 | { | |
7f52f314 | 169 | int i; |
eaa6111b LFT |
170 | bool sop = 0; |
171 | u32 ctrl; | |
172 | u32 reg0, reg1; | |
173 | ||
174 | /* | |
175 | * Minimum 2 loops to read TLP headers and 1 loop to read data | |
176 | * payload. | |
177 | */ | |
7f52f314 | 178 | for (i = 0; i < TLP_LOOP; i++) { |
eaa6111b LFT |
179 | ctrl = cra_readl(pcie, RP_RXCPL_STATUS); |
180 | if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) { | |
181 | reg0 = cra_readl(pcie, RP_RXCPL_REG0); | |
182 | reg1 = cra_readl(pcie, RP_RXCPL_REG1); | |
183 | ||
184 | if (ctrl & RP_RXCPL_SOP) | |
185 | sop = true; | |
186 | ||
187 | if (ctrl & RP_RXCPL_EOP) { | |
188 | if (value) | |
189 | *value = reg0; | |
190 | return PCIBIOS_SUCCESSFUL; | |
191 | } | |
192 | } | |
193 | udelay(5); | |
194 | } | |
195 | ||
196 | return -ENOENT; | |
197 | } | |
198 | ||
199 | static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers, | |
200 | u32 data, bool align) | |
201 | { | |
202 | struct tlp_rp_regpair_t tlp_rp_regdata; | |
203 | ||
204 | tlp_rp_regdata.reg0 = headers[0]; | |
205 | tlp_rp_regdata.reg1 = headers[1]; | |
206 | tlp_rp_regdata.ctrl = RP_TX_SOP; | |
207 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
208 | ||
209 | if (align) { | |
210 | tlp_rp_regdata.reg0 = headers[2]; | |
211 | tlp_rp_regdata.reg1 = 0; | |
212 | tlp_rp_regdata.ctrl = 0; | |
213 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
214 | ||
215 | tlp_rp_regdata.reg0 = data; | |
216 | tlp_rp_regdata.reg1 = 0; | |
217 | } else { | |
218 | tlp_rp_regdata.reg0 = headers[2]; | |
219 | tlp_rp_regdata.reg1 = data; | |
220 | } | |
221 | ||
222 | tlp_rp_regdata.ctrl = RP_TX_EOP; | |
223 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
224 | } | |
225 | ||
226 | static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, | |
227 | int where, u8 byte_en, u32 *value) | |
228 | { | |
229 | u32 headers[TLP_HDR_SIZE]; | |
230 | ||
231 | if (bus == pcie->root_bus_nr) | |
232 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0); | |
233 | else | |
234 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1); | |
235 | ||
236 | headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn), | |
237 | TLP_READ_TAG, byte_en); | |
238 | headers[2] = TLP_CFG_DW2(bus, devfn, where); | |
239 | ||
240 | tlp_write_packet(pcie, headers, 0, false); | |
241 | ||
242 | return tlp_read_packet(pcie, value); | |
243 | } | |
244 | ||
245 | static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, | |
246 | int where, u8 byte_en, u32 value) | |
247 | { | |
248 | u32 headers[TLP_HDR_SIZE]; | |
249 | int ret; | |
250 | ||
251 | if (bus == pcie->root_bus_nr) | |
252 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0); | |
253 | else | |
254 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1); | |
255 | ||
256 | headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn), | |
257 | TLP_WRITE_TAG, byte_en); | |
258 | headers[2] = TLP_CFG_DW2(bus, devfn, where); | |
259 | ||
260 | /* check alignment to Qword */ | |
261 | if ((where & 0x7) == 0) | |
262 | tlp_write_packet(pcie, headers, value, true); | |
263 | else | |
264 | tlp_write_packet(pcie, headers, value, false); | |
265 | ||
266 | ret = tlp_read_packet(pcie, NULL); | |
267 | if (ret != PCIBIOS_SUCCESSFUL) | |
268 | return ret; | |
269 | ||
270 | /* | |
271 | * Monitor changes to PCI_PRIMARY_BUS register on root port | |
272 | * and update local copy of root bus number accordingly. | |
273 | */ | |
274 | if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) | |
275 | pcie->root_bus_nr = (u8)(value); | |
276 | ||
277 | return PCIBIOS_SUCCESSFUL; | |
278 | } | |
279 | ||
280 | static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, | |
281 | int where, int size, u32 *value) | |
282 | { | |
283 | struct altera_pcie *pcie = bus->sysdata; | |
284 | int ret; | |
285 | u32 data; | |
286 | u8 byte_en; | |
287 | ||
288 | if (altera_pcie_hide_rc_bar(bus, devfn, where)) | |
289 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
290 | ||
291 | if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) { | |
292 | *value = 0xffffffff; | |
293 | return PCIBIOS_DEVICE_NOT_FOUND; | |
294 | } | |
295 | ||
296 | switch (size) { | |
297 | case 1: | |
298 | byte_en = 1 << (where & 3); | |
299 | break; | |
300 | case 2: | |
301 | byte_en = 3 << (where & 3); | |
302 | break; | |
303 | default: | |
304 | byte_en = 0xf; | |
305 | break; | |
306 | } | |
307 | ||
308 | ret = tlp_cfg_dword_read(pcie, bus->number, devfn, | |
309 | (where & ~DWORD_MASK), byte_en, &data); | |
310 | if (ret != PCIBIOS_SUCCESSFUL) | |
311 | return ret; | |
312 | ||
313 | switch (size) { | |
314 | case 1: | |
315 | *value = (data >> (8 * (where & 0x3))) & 0xff; | |
316 | break; | |
317 | case 2: | |
318 | *value = (data >> (8 * (where & 0x2))) & 0xffff; | |
319 | break; | |
320 | default: | |
321 | *value = data; | |
322 | break; | |
323 | } | |
324 | ||
325 | return PCIBIOS_SUCCESSFUL; | |
326 | } | |
327 | ||
328 | static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, | |
329 | int where, int size, u32 value) | |
330 | { | |
331 | struct altera_pcie *pcie = bus->sysdata; | |
332 | u32 data32; | |
333 | u32 shift = 8 * (where & 3); | |
334 | u8 byte_en; | |
335 | ||
336 | if (altera_pcie_hide_rc_bar(bus, devfn, where)) | |
337 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
338 | ||
339 | if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) | |
340 | return PCIBIOS_DEVICE_NOT_FOUND; | |
341 | ||
342 | switch (size) { | |
343 | case 1: | |
344 | data32 = (value & 0xff) << shift; | |
345 | byte_en = 1 << (where & 3); | |
346 | break; | |
347 | case 2: | |
348 | data32 = (value & 0xffff) << shift; | |
349 | byte_en = 3 << (where & 3); | |
350 | break; | |
351 | default: | |
352 | data32 = value; | |
353 | byte_en = 0xf; | |
354 | break; | |
355 | } | |
356 | ||
357 | return tlp_cfg_dword_write(pcie, bus->number, devfn, | |
358 | (where & ~DWORD_MASK), byte_en, data32); | |
359 | } | |
360 | ||
361 | static struct pci_ops altera_pcie_ops = { | |
362 | .read = altera_pcie_cfg_read, | |
363 | .write = altera_pcie_cfg_write, | |
364 | }; | |
365 | ||
366 | static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, | |
367 | irq_hw_number_t hwirq) | |
368 | { | |
369 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); | |
370 | irq_set_chip_data(irq, domain->host_data); | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | static const struct irq_domain_ops intx_domain_ops = { | |
376 | .map = altera_pcie_intx_map, | |
377 | }; | |
378 | ||
379 | static void altera_pcie_isr(struct irq_desc *desc) | |
380 | { | |
381 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
382 | struct altera_pcie *pcie; | |
383 | unsigned long status; | |
384 | u32 bit; | |
385 | u32 virq; | |
386 | ||
387 | chained_irq_enter(chip, desc); | |
388 | pcie = irq_desc_get_handler_data(desc); | |
389 | ||
390 | while ((status = cra_readl(pcie, P2A_INT_STATUS) | |
391 | & P2A_INT_STS_ALL) != 0) { | |
392 | for_each_set_bit(bit, &status, INTX_NUM) { | |
393 | /* clear interrupts */ | |
394 | cra_writel(pcie, 1 << bit, P2A_INT_STATUS); | |
395 | ||
396 | virq = irq_find_mapping(pcie->irq_domain, bit + 1); | |
397 | if (virq) | |
398 | generic_handle_irq(virq); | |
399 | else | |
400 | dev_err(&pcie->pdev->dev, | |
401 | "unexpected IRQ, INT%d\n", bit); | |
402 | } | |
403 | } | |
404 | ||
405 | chained_irq_exit(chip, desc); | |
406 | } | |
407 | ||
408 | static void altera_pcie_release_of_pci_ranges(struct altera_pcie *pcie) | |
409 | { | |
410 | pci_free_resource_list(&pcie->resources); | |
411 | } | |
412 | ||
413 | static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie) | |
414 | { | |
415 | int err, res_valid = 0; | |
416 | struct device *dev = &pcie->pdev->dev; | |
417 | struct device_node *np = dev->of_node; | |
418 | struct resource_entry *win; | |
419 | ||
420 | err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources, | |
421 | NULL); | |
422 | if (err) | |
423 | return err; | |
424 | ||
425 | resource_list_for_each_entry(win, &pcie->resources) { | |
426 | struct resource *parent, *res = win->res; | |
427 | ||
428 | switch (resource_type(res)) { | |
429 | case IORESOURCE_MEM: | |
430 | parent = &iomem_resource; | |
431 | res_valid |= !(res->flags & IORESOURCE_PREFETCH); | |
432 | break; | |
433 | default: | |
434 | continue; | |
435 | } | |
436 | ||
437 | err = devm_request_resource(dev, parent, res); | |
438 | if (err) | |
439 | goto out_release_res; | |
440 | } | |
441 | ||
442 | if (!res_valid) { | |
443 | dev_err(dev, "non-prefetchable memory resource required\n"); | |
444 | err = -EINVAL; | |
445 | goto out_release_res; | |
446 | } | |
447 | ||
448 | return 0; | |
449 | ||
450 | out_release_res: | |
451 | altera_pcie_release_of_pci_ranges(pcie); | |
452 | return err; | |
453 | } | |
454 | ||
455 | static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) | |
456 | { | |
457 | struct device *dev = &pcie->pdev->dev; | |
458 | struct device_node *node = dev->of_node; | |
459 | ||
460 | /* Setup INTx */ | |
461 | pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM, | |
462 | &intx_domain_ops, pcie); | |
463 | if (!pcie->irq_domain) { | |
464 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
465 | return -ENOMEM; | |
466 | } | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | static int altera_pcie_parse_dt(struct altera_pcie *pcie) | |
472 | { | |
473 | struct resource *cra; | |
474 | struct platform_device *pdev = pcie->pdev; | |
475 | ||
476 | cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra"); | |
477 | if (!cra) { | |
478 | dev_err(&pdev->dev, "no Cra memory resource defined\n"); | |
479 | return -ENODEV; | |
480 | } | |
481 | ||
482 | pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra); | |
483 | if (IS_ERR(pcie->cra_base)) { | |
484 | dev_err(&pdev->dev, "failed to map cra memory\n"); | |
485 | return PTR_ERR(pcie->cra_base); | |
486 | } | |
487 | ||
488 | /* setup IRQ */ | |
489 | pcie->irq = platform_get_irq(pdev, 0); | |
490 | if (pcie->irq <= 0) { | |
491 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq); | |
492 | return -EINVAL; | |
493 | } | |
494 | ||
495 | irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static int altera_pcie_probe(struct platform_device *pdev) | |
501 | { | |
502 | struct altera_pcie *pcie; | |
503 | struct pci_bus *bus; | |
504 | struct pci_bus *child; | |
505 | int ret; | |
506 | ||
507 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); | |
508 | if (!pcie) | |
509 | return -ENOMEM; | |
510 | ||
511 | pcie->pdev = pdev; | |
512 | ||
513 | ret = altera_pcie_parse_dt(pcie); | |
514 | if (ret) { | |
515 | dev_err(&pdev->dev, "Parsing DT failed\n"); | |
516 | return ret; | |
517 | } | |
518 | ||
519 | INIT_LIST_HEAD(&pcie->resources); | |
520 | ||
521 | ret = altera_pcie_parse_request_of_pci_ranges(pcie); | |
522 | if (ret) { | |
523 | dev_err(&pdev->dev, "Failed add resources\n"); | |
524 | return ret; | |
525 | } | |
526 | ||
527 | ret = altera_pcie_init_irq_domain(pcie); | |
528 | if (ret) { | |
529 | dev_err(&pdev->dev, "Failed creating IRQ Domain\n"); | |
530 | return ret; | |
531 | } | |
532 | ||
533 | /* clear all interrupts */ | |
534 | cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); | |
535 | /* enable all interrupts */ | |
536 | cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE); | |
537 | ||
538 | bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops, | |
539 | pcie, &pcie->resources); | |
540 | if (!bus) | |
541 | return -ENOMEM; | |
542 | ||
543 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); | |
544 | pci_assign_unassigned_bus_resources(bus); | |
545 | ||
546 | /* Configure PCI Express setting. */ | |
547 | list_for_each_entry(child, &bus->children, node) | |
548 | pcie_bus_configure_settings(child); | |
549 | ||
550 | pci_bus_add_devices(bus); | |
551 | ||
552 | platform_set_drvdata(pdev, pcie); | |
553 | return ret; | |
554 | } | |
555 | ||
556 | static const struct of_device_id altera_pcie_of_match[] = { | |
557 | { .compatible = "altr,pcie-root-port-1.0", }, | |
558 | {}, | |
559 | }; | |
560 | MODULE_DEVICE_TABLE(of, altera_pcie_of_match); | |
561 | ||
562 | static struct platform_driver altera_pcie_driver = { | |
563 | .probe = altera_pcie_probe, | |
564 | .driver = { | |
565 | .name = "altera-pcie", | |
566 | .of_match_table = altera_pcie_of_match, | |
567 | .suppress_bind_attrs = true, | |
568 | }, | |
569 | }; | |
570 | ||
571 | static int altera_pcie_init(void) | |
572 | { | |
573 | return platform_driver_register(&altera_pcie_driver); | |
574 | } | |
575 | module_init(altera_pcie_init); | |
576 | ||
577 | MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); | |
578 | MODULE_DESCRIPTION("Altera PCIe host controller driver"); | |
579 | MODULE_LICENSE("GPL v2"); |