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eaa6111b LFT |
1 | /* |
2 | * Copyright Altera Corporation (C) 2013-2015. All rights reserved | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irqchip/chained_irq.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_pci.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/slab.h> | |
27 | ||
28 | #define RP_TX_REG0 0x2000 | |
29 | #define RP_TX_REG1 0x2004 | |
30 | #define RP_TX_CNTRL 0x2008 | |
31 | #define RP_TX_EOP 0x2 | |
32 | #define RP_TX_SOP 0x1 | |
33 | #define RP_RXCPL_STATUS 0x2010 | |
34 | #define RP_RXCPL_EOP 0x2 | |
35 | #define RP_RXCPL_SOP 0x1 | |
36 | #define RP_RXCPL_REG0 0x2014 | |
37 | #define RP_RXCPL_REG1 0x2018 | |
38 | #define P2A_INT_STATUS 0x3060 | |
39 | #define P2A_INT_STS_ALL 0xf | |
40 | #define P2A_INT_ENABLE 0x3070 | |
41 | #define P2A_INT_ENA_ALL 0xf | |
42 | #define RP_LTSSM 0x3c64 | |
eff31f40 | 43 | #define RP_LTSSM_MASK 0x1f |
eaa6111b LFT |
44 | #define LTSSM_L0 0xf |
45 | ||
46 | /* TLP configuration type 0 and 1 */ | |
47 | #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ | |
48 | #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ | |
49 | #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ | |
50 | #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ | |
51 | #define TLP_PAYLOAD_SIZE 0x01 | |
52 | #define TLP_READ_TAG 0x1d | |
53 | #define TLP_WRITE_TAG 0x10 | |
54 | #define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE) | |
55 | #define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be)) | |
56 | #define TLP_CFG_DW2(bus, devfn, offset) \ | |
57 | (((bus) << 24) | ((devfn) << 16) | (offset)) | |
58 | #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) | |
ea1d3795 | 59 | #define TLP_COMP_STATUS(s) (((s) >> 12) & 7) |
eaa6111b LFT |
60 | #define TLP_HDR_SIZE 3 |
61 | #define TLP_LOOP 500 | |
23ec5670 | 62 | #define RP_DEVFN 0 |
eaa6111b LFT |
63 | |
64 | #define INTX_NUM 4 | |
65 | ||
66 | #define DWORD_MASK 3 | |
67 | ||
68 | struct altera_pcie { | |
69 | struct platform_device *pdev; | |
70 | void __iomem *cra_base; | |
71 | int irq; | |
72 | u8 root_bus_nr; | |
73 | struct irq_domain *irq_domain; | |
74 | struct resource bus_range; | |
75 | struct list_head resources; | |
76 | }; | |
77 | ||
78 | struct tlp_rp_regpair_t { | |
79 | u32 ctrl; | |
80 | u32 reg0; | |
81 | u32 reg1; | |
82 | }; | |
83 | ||
84 | static void altera_pcie_retrain(struct pci_dev *dev) | |
85 | { | |
86 | u16 linkcap, linkstat; | |
87 | ||
88 | /* | |
89 | * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but | |
90 | * current speed is 2.5 GB/s. | |
91 | */ | |
92 | pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap); | |
93 | ||
94 | if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) | |
95 | return; | |
96 | ||
97 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat); | |
98 | if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) | |
99 | pcie_capability_set_word(dev, PCI_EXP_LNKCTL, | |
100 | PCI_EXP_LNKCTL_RL); | |
101 | } | |
102 | DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain); | |
103 | ||
104 | /* | |
105 | * Altera PCIe port uses BAR0 of RC's configuration space as the translation | |
106 | * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space | |
107 | * using these registers, so it can be reached by DMA from EP devices. | |
108 | * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt | |
109 | * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge | |
110 | * should be hidden during enumeration to avoid the sizing and resource | |
111 | * allocation by PCIe core. | |
112 | */ | |
113 | static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, | |
114 | int offset) | |
115 | { | |
116 | if (pci_is_root_bus(bus) && (devfn == 0) && | |
117 | (offset == PCI_BASE_ADDRESS_0)) | |
118 | return true; | |
119 | ||
120 | return false; | |
121 | } | |
122 | ||
123 | static inline void cra_writel(struct altera_pcie *pcie, const u32 value, | |
124 | const u32 reg) | |
125 | { | |
126 | writel_relaxed(value, pcie->cra_base + reg); | |
127 | } | |
128 | ||
129 | static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) | |
130 | { | |
131 | return readl_relaxed(pcie->cra_base + reg); | |
132 | } | |
133 | ||
134 | static void tlp_write_tx(struct altera_pcie *pcie, | |
135 | struct tlp_rp_regpair_t *tlp_rp_regdata) | |
136 | { | |
137 | cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0); | |
138 | cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); | |
139 | cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL); | |
140 | } | |
141 | ||
142 | static bool altera_pcie_link_is_up(struct altera_pcie *pcie) | |
143 | { | |
eff31f40 | 144 | return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0); |
eaa6111b LFT |
145 | } |
146 | ||
147 | static bool altera_pcie_valid_config(struct altera_pcie *pcie, | |
148 | struct pci_bus *bus, int dev) | |
149 | { | |
150 | /* If there is no link, then there is no device */ | |
151 | if (bus->number != pcie->root_bus_nr) { | |
152 | if (!altera_pcie_link_is_up(pcie)) | |
153 | return false; | |
154 | } | |
155 | ||
156 | /* access only one slot on each root port */ | |
157 | if (bus->number == pcie->root_bus_nr && dev > 0) | |
158 | return false; | |
159 | ||
160 | /* | |
161 | * Do not read more than one device on the bus directly attached | |
162 | * to root port, root port can only attach to one downstream port. | |
163 | */ | |
164 | if (bus->primary == pcie->root_bus_nr && dev > 0) | |
165 | return false; | |
166 | ||
167 | return true; | |
168 | } | |
169 | ||
170 | static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) | |
171 | { | |
7f52f314 | 172 | int i; |
eaa6111b LFT |
173 | bool sop = 0; |
174 | u32 ctrl; | |
175 | u32 reg0, reg1; | |
ea1d3795 | 176 | u32 comp_status = 1; |
eaa6111b LFT |
177 | |
178 | /* | |
179 | * Minimum 2 loops to read TLP headers and 1 loop to read data | |
180 | * payload. | |
181 | */ | |
7f52f314 | 182 | for (i = 0; i < TLP_LOOP; i++) { |
eaa6111b LFT |
183 | ctrl = cra_readl(pcie, RP_RXCPL_STATUS); |
184 | if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) { | |
185 | reg0 = cra_readl(pcie, RP_RXCPL_REG0); | |
186 | reg1 = cra_readl(pcie, RP_RXCPL_REG1); | |
187 | ||
ea1d3795 | 188 | if (ctrl & RP_RXCPL_SOP) { |
eaa6111b | 189 | sop = true; |
ea1d3795 LFT |
190 | comp_status = TLP_COMP_STATUS(reg1); |
191 | } | |
eaa6111b LFT |
192 | |
193 | if (ctrl & RP_RXCPL_EOP) { | |
ea1d3795 LFT |
194 | if (comp_status) |
195 | return PCIBIOS_DEVICE_NOT_FOUND; | |
196 | ||
eaa6111b LFT |
197 | if (value) |
198 | *value = reg0; | |
ea1d3795 | 199 | |
eaa6111b LFT |
200 | return PCIBIOS_SUCCESSFUL; |
201 | } | |
202 | } | |
203 | udelay(5); | |
204 | } | |
205 | ||
ea1d3795 | 206 | return PCIBIOS_DEVICE_NOT_FOUND; |
eaa6111b LFT |
207 | } |
208 | ||
209 | static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers, | |
210 | u32 data, bool align) | |
211 | { | |
212 | struct tlp_rp_regpair_t tlp_rp_regdata; | |
213 | ||
214 | tlp_rp_regdata.reg0 = headers[0]; | |
215 | tlp_rp_regdata.reg1 = headers[1]; | |
216 | tlp_rp_regdata.ctrl = RP_TX_SOP; | |
217 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
218 | ||
219 | if (align) { | |
220 | tlp_rp_regdata.reg0 = headers[2]; | |
221 | tlp_rp_regdata.reg1 = 0; | |
222 | tlp_rp_regdata.ctrl = 0; | |
223 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
224 | ||
225 | tlp_rp_regdata.reg0 = data; | |
226 | tlp_rp_regdata.reg1 = 0; | |
227 | } else { | |
228 | tlp_rp_regdata.reg0 = headers[2]; | |
229 | tlp_rp_regdata.reg1 = data; | |
230 | } | |
231 | ||
232 | tlp_rp_regdata.ctrl = RP_TX_EOP; | |
233 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
234 | } | |
235 | ||
236 | static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, | |
237 | int where, u8 byte_en, u32 *value) | |
238 | { | |
239 | u32 headers[TLP_HDR_SIZE]; | |
240 | ||
241 | if (bus == pcie->root_bus_nr) | |
242 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0); | |
243 | else | |
244 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1); | |
245 | ||
23ec5670 | 246 | headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN), |
eaa6111b LFT |
247 | TLP_READ_TAG, byte_en); |
248 | headers[2] = TLP_CFG_DW2(bus, devfn, where); | |
249 | ||
250 | tlp_write_packet(pcie, headers, 0, false); | |
251 | ||
252 | return tlp_read_packet(pcie, value); | |
253 | } | |
254 | ||
255 | static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, | |
256 | int where, u8 byte_en, u32 value) | |
257 | { | |
258 | u32 headers[TLP_HDR_SIZE]; | |
259 | int ret; | |
260 | ||
261 | if (bus == pcie->root_bus_nr) | |
262 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0); | |
263 | else | |
264 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1); | |
265 | ||
23ec5670 | 266 | headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN), |
eaa6111b LFT |
267 | TLP_WRITE_TAG, byte_en); |
268 | headers[2] = TLP_CFG_DW2(bus, devfn, where); | |
269 | ||
270 | /* check alignment to Qword */ | |
271 | if ((where & 0x7) == 0) | |
272 | tlp_write_packet(pcie, headers, value, true); | |
273 | else | |
274 | tlp_write_packet(pcie, headers, value, false); | |
275 | ||
276 | ret = tlp_read_packet(pcie, NULL); | |
277 | if (ret != PCIBIOS_SUCCESSFUL) | |
278 | return ret; | |
279 | ||
280 | /* | |
281 | * Monitor changes to PCI_PRIMARY_BUS register on root port | |
282 | * and update local copy of root bus number accordingly. | |
283 | */ | |
284 | if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) | |
285 | pcie->root_bus_nr = (u8)(value); | |
286 | ||
287 | return PCIBIOS_SUCCESSFUL; | |
288 | } | |
289 | ||
290 | static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, | |
291 | int where, int size, u32 *value) | |
292 | { | |
293 | struct altera_pcie *pcie = bus->sysdata; | |
294 | int ret; | |
295 | u32 data; | |
296 | u8 byte_en; | |
297 | ||
298 | if (altera_pcie_hide_rc_bar(bus, devfn, where)) | |
299 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
300 | ||
301 | if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) { | |
302 | *value = 0xffffffff; | |
303 | return PCIBIOS_DEVICE_NOT_FOUND; | |
304 | } | |
305 | ||
306 | switch (size) { | |
307 | case 1: | |
308 | byte_en = 1 << (where & 3); | |
309 | break; | |
310 | case 2: | |
311 | byte_en = 3 << (where & 3); | |
312 | break; | |
313 | default: | |
314 | byte_en = 0xf; | |
315 | break; | |
316 | } | |
317 | ||
318 | ret = tlp_cfg_dword_read(pcie, bus->number, devfn, | |
319 | (where & ~DWORD_MASK), byte_en, &data); | |
320 | if (ret != PCIBIOS_SUCCESSFUL) | |
321 | return ret; | |
322 | ||
323 | switch (size) { | |
324 | case 1: | |
325 | *value = (data >> (8 * (where & 0x3))) & 0xff; | |
326 | break; | |
327 | case 2: | |
328 | *value = (data >> (8 * (where & 0x2))) & 0xffff; | |
329 | break; | |
330 | default: | |
331 | *value = data; | |
332 | break; | |
333 | } | |
334 | ||
335 | return PCIBIOS_SUCCESSFUL; | |
336 | } | |
337 | ||
338 | static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, | |
339 | int where, int size, u32 value) | |
340 | { | |
341 | struct altera_pcie *pcie = bus->sysdata; | |
342 | u32 data32; | |
343 | u32 shift = 8 * (where & 3); | |
344 | u8 byte_en; | |
345 | ||
346 | if (altera_pcie_hide_rc_bar(bus, devfn, where)) | |
347 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
348 | ||
349 | if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) | |
350 | return PCIBIOS_DEVICE_NOT_FOUND; | |
351 | ||
352 | switch (size) { | |
353 | case 1: | |
354 | data32 = (value & 0xff) << shift; | |
355 | byte_en = 1 << (where & 3); | |
356 | break; | |
357 | case 2: | |
358 | data32 = (value & 0xffff) << shift; | |
359 | byte_en = 3 << (where & 3); | |
360 | break; | |
361 | default: | |
362 | data32 = value; | |
363 | byte_en = 0xf; | |
364 | break; | |
365 | } | |
366 | ||
367 | return tlp_cfg_dword_write(pcie, bus->number, devfn, | |
368 | (where & ~DWORD_MASK), byte_en, data32); | |
369 | } | |
370 | ||
371 | static struct pci_ops altera_pcie_ops = { | |
372 | .read = altera_pcie_cfg_read, | |
373 | .write = altera_pcie_cfg_write, | |
374 | }; | |
375 | ||
376 | static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, | |
377 | irq_hw_number_t hwirq) | |
378 | { | |
379 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); | |
380 | irq_set_chip_data(irq, domain->host_data); | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | static const struct irq_domain_ops intx_domain_ops = { | |
386 | .map = altera_pcie_intx_map, | |
387 | }; | |
388 | ||
389 | static void altera_pcie_isr(struct irq_desc *desc) | |
390 | { | |
391 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
392 | struct altera_pcie *pcie; | |
393 | unsigned long status; | |
394 | u32 bit; | |
395 | u32 virq; | |
396 | ||
397 | chained_irq_enter(chip, desc); | |
398 | pcie = irq_desc_get_handler_data(desc); | |
399 | ||
400 | while ((status = cra_readl(pcie, P2A_INT_STATUS) | |
401 | & P2A_INT_STS_ALL) != 0) { | |
402 | for_each_set_bit(bit, &status, INTX_NUM) { | |
403 | /* clear interrupts */ | |
404 | cra_writel(pcie, 1 << bit, P2A_INT_STATUS); | |
405 | ||
406 | virq = irq_find_mapping(pcie->irq_domain, bit + 1); | |
407 | if (virq) | |
408 | generic_handle_irq(virq); | |
409 | else | |
410 | dev_err(&pcie->pdev->dev, | |
411 | "unexpected IRQ, INT%d\n", bit); | |
412 | } | |
413 | } | |
414 | ||
415 | chained_irq_exit(chip, desc); | |
416 | } | |
417 | ||
418 | static void altera_pcie_release_of_pci_ranges(struct altera_pcie *pcie) | |
419 | { | |
420 | pci_free_resource_list(&pcie->resources); | |
421 | } | |
422 | ||
423 | static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie) | |
424 | { | |
425 | int err, res_valid = 0; | |
426 | struct device *dev = &pcie->pdev->dev; | |
427 | struct device_node *np = dev->of_node; | |
428 | struct resource_entry *win; | |
429 | ||
430 | err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources, | |
431 | NULL); | |
432 | if (err) | |
433 | return err; | |
434 | ||
435 | resource_list_for_each_entry(win, &pcie->resources) { | |
436 | struct resource *parent, *res = win->res; | |
437 | ||
438 | switch (resource_type(res)) { | |
439 | case IORESOURCE_MEM: | |
440 | parent = &iomem_resource; | |
441 | res_valid |= !(res->flags & IORESOURCE_PREFETCH); | |
442 | break; | |
443 | default: | |
444 | continue; | |
445 | } | |
446 | ||
447 | err = devm_request_resource(dev, parent, res); | |
448 | if (err) | |
449 | goto out_release_res; | |
450 | } | |
451 | ||
452 | if (!res_valid) { | |
453 | dev_err(dev, "non-prefetchable memory resource required\n"); | |
454 | err = -EINVAL; | |
455 | goto out_release_res; | |
456 | } | |
457 | ||
458 | return 0; | |
459 | ||
460 | out_release_res: | |
461 | altera_pcie_release_of_pci_ranges(pcie); | |
462 | return err; | |
463 | } | |
464 | ||
465 | static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) | |
466 | { | |
467 | struct device *dev = &pcie->pdev->dev; | |
468 | struct device_node *node = dev->of_node; | |
469 | ||
470 | /* Setup INTx */ | |
99496bd2 | 471 | pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1, |
eaa6111b LFT |
472 | &intx_domain_ops, pcie); |
473 | if (!pcie->irq_domain) { | |
474 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
475 | return -ENOMEM; | |
476 | } | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | static int altera_pcie_parse_dt(struct altera_pcie *pcie) | |
482 | { | |
483 | struct resource *cra; | |
484 | struct platform_device *pdev = pcie->pdev; | |
485 | ||
486 | cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra"); | |
487 | if (!cra) { | |
488 | dev_err(&pdev->dev, "no Cra memory resource defined\n"); | |
489 | return -ENODEV; | |
490 | } | |
491 | ||
492 | pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra); | |
493 | if (IS_ERR(pcie->cra_base)) { | |
494 | dev_err(&pdev->dev, "failed to map cra memory\n"); | |
495 | return PTR_ERR(pcie->cra_base); | |
496 | } | |
497 | ||
498 | /* setup IRQ */ | |
499 | pcie->irq = platform_get_irq(pdev, 0); | |
500 | if (pcie->irq <= 0) { | |
501 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq); | |
502 | return -EINVAL; | |
503 | } | |
504 | ||
505 | irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int altera_pcie_probe(struct platform_device *pdev) | |
511 | { | |
512 | struct altera_pcie *pcie; | |
513 | struct pci_bus *bus; | |
514 | struct pci_bus *child; | |
515 | int ret; | |
516 | ||
517 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); | |
518 | if (!pcie) | |
519 | return -ENOMEM; | |
520 | ||
521 | pcie->pdev = pdev; | |
522 | ||
523 | ret = altera_pcie_parse_dt(pcie); | |
524 | if (ret) { | |
525 | dev_err(&pdev->dev, "Parsing DT failed\n"); | |
526 | return ret; | |
527 | } | |
528 | ||
529 | INIT_LIST_HEAD(&pcie->resources); | |
530 | ||
531 | ret = altera_pcie_parse_request_of_pci_ranges(pcie); | |
532 | if (ret) { | |
533 | dev_err(&pdev->dev, "Failed add resources\n"); | |
534 | return ret; | |
535 | } | |
536 | ||
537 | ret = altera_pcie_init_irq_domain(pcie); | |
538 | if (ret) { | |
539 | dev_err(&pdev->dev, "Failed creating IRQ Domain\n"); | |
540 | return ret; | |
541 | } | |
542 | ||
543 | /* clear all interrupts */ | |
544 | cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); | |
545 | /* enable all interrupts */ | |
546 | cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE); | |
547 | ||
548 | bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops, | |
549 | pcie, &pcie->resources); | |
550 | if (!bus) | |
551 | return -ENOMEM; | |
552 | ||
553 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); | |
554 | pci_assign_unassigned_bus_resources(bus); | |
555 | ||
556 | /* Configure PCI Express setting. */ | |
557 | list_for_each_entry(child, &bus->children, node) | |
558 | pcie_bus_configure_settings(child); | |
559 | ||
560 | pci_bus_add_devices(bus); | |
561 | ||
562 | platform_set_drvdata(pdev, pcie); | |
563 | return ret; | |
564 | } | |
565 | ||
566 | static const struct of_device_id altera_pcie_of_match[] = { | |
567 | { .compatible = "altr,pcie-root-port-1.0", }, | |
568 | {}, | |
569 | }; | |
570 | MODULE_DEVICE_TABLE(of, altera_pcie_of_match); | |
571 | ||
572 | static struct platform_driver altera_pcie_driver = { | |
573 | .probe = altera_pcie_probe, | |
574 | .driver = { | |
575 | .name = "altera-pcie", | |
576 | .of_match_table = altera_pcie_of_match, | |
577 | .suppress_bind_attrs = true, | |
578 | }, | |
579 | }; | |
580 | ||
581 | static int altera_pcie_init(void) | |
582 | { | |
583 | return platform_driver_register(&altera_pcie_driver); | |
584 | } | |
585 | module_init(altera_pcie_init); | |
586 | ||
587 | MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); | |
588 | MODULE_DESCRIPTION("Altera PCIe host controller driver"); | |
589 | MODULE_LICENSE("GPL v2"); |