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eaa6111b LFT |
1 | /* |
2 | * Copyright Altera Corporation (C) 2013-2015. All rights reserved | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irqchip/chained_irq.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_pci.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/slab.h> | |
27 | ||
28 | #define RP_TX_REG0 0x2000 | |
29 | #define RP_TX_REG1 0x2004 | |
30 | #define RP_TX_CNTRL 0x2008 | |
31 | #define RP_TX_EOP 0x2 | |
32 | #define RP_TX_SOP 0x1 | |
33 | #define RP_RXCPL_STATUS 0x2010 | |
34 | #define RP_RXCPL_EOP 0x2 | |
35 | #define RP_RXCPL_SOP 0x1 | |
36 | #define RP_RXCPL_REG0 0x2014 | |
37 | #define RP_RXCPL_REG1 0x2018 | |
38 | #define P2A_INT_STATUS 0x3060 | |
39 | #define P2A_INT_STS_ALL 0xf | |
40 | #define P2A_INT_ENABLE 0x3070 | |
41 | #define P2A_INT_ENA_ALL 0xf | |
42 | #define RP_LTSSM 0x3c64 | |
eff31f40 | 43 | #define RP_LTSSM_MASK 0x1f |
eaa6111b LFT |
44 | #define LTSSM_L0 0xf |
45 | ||
46 | /* TLP configuration type 0 and 1 */ | |
47 | #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ | |
48 | #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ | |
49 | #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ | |
50 | #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ | |
51 | #define TLP_PAYLOAD_SIZE 0x01 | |
52 | #define TLP_READ_TAG 0x1d | |
53 | #define TLP_WRITE_TAG 0x10 | |
54 | #define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE) | |
55 | #define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be)) | |
56 | #define TLP_CFG_DW2(bus, devfn, offset) \ | |
57 | (((bus) << 24) | ((devfn) << 16) | (offset)) | |
58 | #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) | |
ea1d3795 | 59 | #define TLP_COMP_STATUS(s) (((s) >> 12) & 7) |
eaa6111b LFT |
60 | #define TLP_HDR_SIZE 3 |
61 | #define TLP_LOOP 500 | |
23ec5670 | 62 | #define RP_DEVFN 0 |
eaa6111b LFT |
63 | |
64 | #define INTX_NUM 4 | |
65 | ||
66 | #define DWORD_MASK 3 | |
67 | ||
68 | struct altera_pcie { | |
69 | struct platform_device *pdev; | |
70 | void __iomem *cra_base; | |
71 | int irq; | |
72 | u8 root_bus_nr; | |
73 | struct irq_domain *irq_domain; | |
74 | struct resource bus_range; | |
75 | struct list_head resources; | |
76 | }; | |
77 | ||
78 | struct tlp_rp_regpair_t { | |
79 | u32 ctrl; | |
80 | u32 reg0; | |
81 | u32 reg1; | |
82 | }; | |
83 | ||
f8be11ae BH |
84 | static inline void cra_writel(struct altera_pcie *pcie, const u32 value, |
85 | const u32 reg) | |
86 | { | |
87 | writel_relaxed(value, pcie->cra_base + reg); | |
88 | } | |
89 | ||
90 | static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) | |
91 | { | |
92 | return readl_relaxed(pcie->cra_base + reg); | |
93 | } | |
94 | ||
95 | static bool altera_pcie_link_is_up(struct altera_pcie *pcie) | |
96 | { | |
97 | return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0); | |
98 | } | |
99 | ||
eaa6111b LFT |
100 | static void altera_pcie_retrain(struct pci_dev *dev) |
101 | { | |
102 | u16 linkcap, linkstat; | |
c622032e LFT |
103 | struct altera_pcie *pcie = dev->bus->sysdata; |
104 | ||
105 | if (!altera_pcie_link_is_up(pcie)) | |
106 | return; | |
eaa6111b LFT |
107 | |
108 | /* | |
109 | * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but | |
110 | * current speed is 2.5 GB/s. | |
111 | */ | |
112 | pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap); | |
113 | ||
114 | if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) | |
115 | return; | |
116 | ||
117 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat); | |
118 | if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) | |
119 | pcie_capability_set_word(dev, PCI_EXP_LNKCTL, | |
120 | PCI_EXP_LNKCTL_RL); | |
121 | } | |
122 | DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain); | |
123 | ||
124 | /* | |
125 | * Altera PCIe port uses BAR0 of RC's configuration space as the translation | |
126 | * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space | |
127 | * using these registers, so it can be reached by DMA from EP devices. | |
128 | * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt | |
129 | * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge | |
130 | * should be hidden during enumeration to avoid the sizing and resource | |
131 | * allocation by PCIe core. | |
132 | */ | |
133 | static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, | |
134 | int offset) | |
135 | { | |
136 | if (pci_is_root_bus(bus) && (devfn == 0) && | |
137 | (offset == PCI_BASE_ADDRESS_0)) | |
138 | return true; | |
139 | ||
140 | return false; | |
141 | } | |
142 | ||
eaa6111b LFT |
143 | static void tlp_write_tx(struct altera_pcie *pcie, |
144 | struct tlp_rp_regpair_t *tlp_rp_regdata) | |
145 | { | |
146 | cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0); | |
147 | cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); | |
148 | cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL); | |
149 | } | |
150 | ||
eaa6111b LFT |
151 | static bool altera_pcie_valid_config(struct altera_pcie *pcie, |
152 | struct pci_bus *bus, int dev) | |
153 | { | |
154 | /* If there is no link, then there is no device */ | |
155 | if (bus->number != pcie->root_bus_nr) { | |
156 | if (!altera_pcie_link_is_up(pcie)) | |
157 | return false; | |
158 | } | |
159 | ||
160 | /* access only one slot on each root port */ | |
161 | if (bus->number == pcie->root_bus_nr && dev > 0) | |
162 | return false; | |
163 | ||
164 | /* | |
165 | * Do not read more than one device on the bus directly attached | |
166 | * to root port, root port can only attach to one downstream port. | |
167 | */ | |
168 | if (bus->primary == pcie->root_bus_nr && dev > 0) | |
169 | return false; | |
170 | ||
171 | return true; | |
172 | } | |
173 | ||
174 | static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) | |
175 | { | |
7f52f314 | 176 | int i; |
eaa6111b LFT |
177 | bool sop = 0; |
178 | u32 ctrl; | |
179 | u32 reg0, reg1; | |
ea1d3795 | 180 | u32 comp_status = 1; |
eaa6111b LFT |
181 | |
182 | /* | |
183 | * Minimum 2 loops to read TLP headers and 1 loop to read data | |
184 | * payload. | |
185 | */ | |
7f52f314 | 186 | for (i = 0; i < TLP_LOOP; i++) { |
eaa6111b LFT |
187 | ctrl = cra_readl(pcie, RP_RXCPL_STATUS); |
188 | if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) { | |
189 | reg0 = cra_readl(pcie, RP_RXCPL_REG0); | |
190 | reg1 = cra_readl(pcie, RP_RXCPL_REG1); | |
191 | ||
ea1d3795 | 192 | if (ctrl & RP_RXCPL_SOP) { |
eaa6111b | 193 | sop = true; |
ea1d3795 LFT |
194 | comp_status = TLP_COMP_STATUS(reg1); |
195 | } | |
eaa6111b LFT |
196 | |
197 | if (ctrl & RP_RXCPL_EOP) { | |
ea1d3795 LFT |
198 | if (comp_status) |
199 | return PCIBIOS_DEVICE_NOT_FOUND; | |
200 | ||
eaa6111b LFT |
201 | if (value) |
202 | *value = reg0; | |
ea1d3795 | 203 | |
eaa6111b LFT |
204 | return PCIBIOS_SUCCESSFUL; |
205 | } | |
206 | } | |
207 | udelay(5); | |
208 | } | |
209 | ||
ea1d3795 | 210 | return PCIBIOS_DEVICE_NOT_FOUND; |
eaa6111b LFT |
211 | } |
212 | ||
213 | static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers, | |
214 | u32 data, bool align) | |
215 | { | |
216 | struct tlp_rp_regpair_t tlp_rp_regdata; | |
217 | ||
218 | tlp_rp_regdata.reg0 = headers[0]; | |
219 | tlp_rp_regdata.reg1 = headers[1]; | |
220 | tlp_rp_regdata.ctrl = RP_TX_SOP; | |
221 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
222 | ||
223 | if (align) { | |
224 | tlp_rp_regdata.reg0 = headers[2]; | |
225 | tlp_rp_regdata.reg1 = 0; | |
226 | tlp_rp_regdata.ctrl = 0; | |
227 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
228 | ||
229 | tlp_rp_regdata.reg0 = data; | |
230 | tlp_rp_regdata.reg1 = 0; | |
231 | } else { | |
232 | tlp_rp_regdata.reg0 = headers[2]; | |
233 | tlp_rp_regdata.reg1 = data; | |
234 | } | |
235 | ||
236 | tlp_rp_regdata.ctrl = RP_TX_EOP; | |
237 | tlp_write_tx(pcie, &tlp_rp_regdata); | |
238 | } | |
239 | ||
240 | static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, | |
241 | int where, u8 byte_en, u32 *value) | |
242 | { | |
243 | u32 headers[TLP_HDR_SIZE]; | |
244 | ||
245 | if (bus == pcie->root_bus_nr) | |
246 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0); | |
247 | else | |
248 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1); | |
249 | ||
23ec5670 | 250 | headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN), |
eaa6111b LFT |
251 | TLP_READ_TAG, byte_en); |
252 | headers[2] = TLP_CFG_DW2(bus, devfn, where); | |
253 | ||
254 | tlp_write_packet(pcie, headers, 0, false); | |
255 | ||
256 | return tlp_read_packet(pcie, value); | |
257 | } | |
258 | ||
259 | static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, | |
260 | int where, u8 byte_en, u32 value) | |
261 | { | |
262 | u32 headers[TLP_HDR_SIZE]; | |
263 | int ret; | |
264 | ||
265 | if (bus == pcie->root_bus_nr) | |
266 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0); | |
267 | else | |
268 | headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1); | |
269 | ||
23ec5670 | 270 | headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN), |
eaa6111b LFT |
271 | TLP_WRITE_TAG, byte_en); |
272 | headers[2] = TLP_CFG_DW2(bus, devfn, where); | |
273 | ||
274 | /* check alignment to Qword */ | |
275 | if ((where & 0x7) == 0) | |
276 | tlp_write_packet(pcie, headers, value, true); | |
277 | else | |
278 | tlp_write_packet(pcie, headers, value, false); | |
279 | ||
280 | ret = tlp_read_packet(pcie, NULL); | |
281 | if (ret != PCIBIOS_SUCCESSFUL) | |
282 | return ret; | |
283 | ||
284 | /* | |
285 | * Monitor changes to PCI_PRIMARY_BUS register on root port | |
286 | * and update local copy of root bus number accordingly. | |
287 | */ | |
288 | if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) | |
289 | pcie->root_bus_nr = (u8)(value); | |
290 | ||
291 | return PCIBIOS_SUCCESSFUL; | |
292 | } | |
293 | ||
294 | static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, | |
295 | int where, int size, u32 *value) | |
296 | { | |
297 | struct altera_pcie *pcie = bus->sysdata; | |
298 | int ret; | |
299 | u32 data; | |
300 | u8 byte_en; | |
301 | ||
302 | if (altera_pcie_hide_rc_bar(bus, devfn, where)) | |
303 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
304 | ||
305 | if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) { | |
306 | *value = 0xffffffff; | |
307 | return PCIBIOS_DEVICE_NOT_FOUND; | |
308 | } | |
309 | ||
310 | switch (size) { | |
311 | case 1: | |
312 | byte_en = 1 << (where & 3); | |
313 | break; | |
314 | case 2: | |
315 | byte_en = 3 << (where & 3); | |
316 | break; | |
317 | default: | |
318 | byte_en = 0xf; | |
319 | break; | |
320 | } | |
321 | ||
322 | ret = tlp_cfg_dword_read(pcie, bus->number, devfn, | |
323 | (where & ~DWORD_MASK), byte_en, &data); | |
324 | if (ret != PCIBIOS_SUCCESSFUL) | |
325 | return ret; | |
326 | ||
327 | switch (size) { | |
328 | case 1: | |
329 | *value = (data >> (8 * (where & 0x3))) & 0xff; | |
330 | break; | |
331 | case 2: | |
332 | *value = (data >> (8 * (where & 0x2))) & 0xffff; | |
333 | break; | |
334 | default: | |
335 | *value = data; | |
336 | break; | |
337 | } | |
338 | ||
339 | return PCIBIOS_SUCCESSFUL; | |
340 | } | |
341 | ||
342 | static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, | |
343 | int where, int size, u32 value) | |
344 | { | |
345 | struct altera_pcie *pcie = bus->sysdata; | |
346 | u32 data32; | |
347 | u32 shift = 8 * (where & 3); | |
348 | u8 byte_en; | |
349 | ||
350 | if (altera_pcie_hide_rc_bar(bus, devfn, where)) | |
351 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
352 | ||
353 | if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) | |
354 | return PCIBIOS_DEVICE_NOT_FOUND; | |
355 | ||
356 | switch (size) { | |
357 | case 1: | |
358 | data32 = (value & 0xff) << shift; | |
359 | byte_en = 1 << (where & 3); | |
360 | break; | |
361 | case 2: | |
362 | data32 = (value & 0xffff) << shift; | |
363 | byte_en = 3 << (where & 3); | |
364 | break; | |
365 | default: | |
366 | data32 = value; | |
367 | byte_en = 0xf; | |
368 | break; | |
369 | } | |
370 | ||
371 | return tlp_cfg_dword_write(pcie, bus->number, devfn, | |
372 | (where & ~DWORD_MASK), byte_en, data32); | |
373 | } | |
374 | ||
375 | static struct pci_ops altera_pcie_ops = { | |
376 | .read = altera_pcie_cfg_read, | |
377 | .write = altera_pcie_cfg_write, | |
378 | }; | |
379 | ||
380 | static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, | |
381 | irq_hw_number_t hwirq) | |
382 | { | |
383 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); | |
384 | irq_set_chip_data(irq, domain->host_data); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static const struct irq_domain_ops intx_domain_ops = { | |
390 | .map = altera_pcie_intx_map, | |
391 | }; | |
392 | ||
393 | static void altera_pcie_isr(struct irq_desc *desc) | |
394 | { | |
395 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
396 | struct altera_pcie *pcie; | |
397 | unsigned long status; | |
398 | u32 bit; | |
399 | u32 virq; | |
400 | ||
401 | chained_irq_enter(chip, desc); | |
402 | pcie = irq_desc_get_handler_data(desc); | |
403 | ||
404 | while ((status = cra_readl(pcie, P2A_INT_STATUS) | |
405 | & P2A_INT_STS_ALL) != 0) { | |
406 | for_each_set_bit(bit, &status, INTX_NUM) { | |
407 | /* clear interrupts */ | |
408 | cra_writel(pcie, 1 << bit, P2A_INT_STATUS); | |
409 | ||
410 | virq = irq_find_mapping(pcie->irq_domain, bit + 1); | |
411 | if (virq) | |
412 | generic_handle_irq(virq); | |
413 | else | |
414 | dev_err(&pcie->pdev->dev, | |
415 | "unexpected IRQ, INT%d\n", bit); | |
416 | } | |
417 | } | |
418 | ||
419 | chained_irq_exit(chip, desc); | |
420 | } | |
421 | ||
422 | static void altera_pcie_release_of_pci_ranges(struct altera_pcie *pcie) | |
423 | { | |
424 | pci_free_resource_list(&pcie->resources); | |
425 | } | |
426 | ||
427 | static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie) | |
428 | { | |
429 | int err, res_valid = 0; | |
430 | struct device *dev = &pcie->pdev->dev; | |
431 | struct device_node *np = dev->of_node; | |
432 | struct resource_entry *win; | |
433 | ||
434 | err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources, | |
435 | NULL); | |
436 | if (err) | |
437 | return err; | |
438 | ||
439 | resource_list_for_each_entry(win, &pcie->resources) { | |
440 | struct resource *parent, *res = win->res; | |
441 | ||
442 | switch (resource_type(res)) { | |
443 | case IORESOURCE_MEM: | |
444 | parent = &iomem_resource; | |
445 | res_valid |= !(res->flags & IORESOURCE_PREFETCH); | |
446 | break; | |
447 | default: | |
448 | continue; | |
449 | } | |
450 | ||
451 | err = devm_request_resource(dev, parent, res); | |
452 | if (err) | |
453 | goto out_release_res; | |
454 | } | |
455 | ||
456 | if (!res_valid) { | |
457 | dev_err(dev, "non-prefetchable memory resource required\n"); | |
458 | err = -EINVAL; | |
459 | goto out_release_res; | |
460 | } | |
461 | ||
462 | return 0; | |
463 | ||
464 | out_release_res: | |
465 | altera_pcie_release_of_pci_ranges(pcie); | |
466 | return err; | |
467 | } | |
468 | ||
469 | static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) | |
470 | { | |
471 | struct device *dev = &pcie->pdev->dev; | |
472 | struct device_node *node = dev->of_node; | |
473 | ||
474 | /* Setup INTx */ | |
99496bd2 | 475 | pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1, |
eaa6111b LFT |
476 | &intx_domain_ops, pcie); |
477 | if (!pcie->irq_domain) { | |
478 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
479 | return -ENOMEM; | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static int altera_pcie_parse_dt(struct altera_pcie *pcie) | |
486 | { | |
487 | struct resource *cra; | |
488 | struct platform_device *pdev = pcie->pdev; | |
489 | ||
490 | cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra"); | |
491 | if (!cra) { | |
492 | dev_err(&pdev->dev, "no Cra memory resource defined\n"); | |
493 | return -ENODEV; | |
494 | } | |
495 | ||
496 | pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra); | |
497 | if (IS_ERR(pcie->cra_base)) { | |
498 | dev_err(&pdev->dev, "failed to map cra memory\n"); | |
499 | return PTR_ERR(pcie->cra_base); | |
500 | } | |
501 | ||
502 | /* setup IRQ */ | |
503 | pcie->irq = platform_get_irq(pdev, 0); | |
504 | if (pcie->irq <= 0) { | |
505 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq); | |
506 | return -EINVAL; | |
507 | } | |
508 | ||
509 | irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | static int altera_pcie_probe(struct platform_device *pdev) | |
515 | { | |
516 | struct altera_pcie *pcie; | |
517 | struct pci_bus *bus; | |
518 | struct pci_bus *child; | |
519 | int ret; | |
520 | ||
521 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); | |
522 | if (!pcie) | |
523 | return -ENOMEM; | |
524 | ||
525 | pcie->pdev = pdev; | |
526 | ||
527 | ret = altera_pcie_parse_dt(pcie); | |
528 | if (ret) { | |
529 | dev_err(&pdev->dev, "Parsing DT failed\n"); | |
530 | return ret; | |
531 | } | |
532 | ||
533 | INIT_LIST_HEAD(&pcie->resources); | |
534 | ||
535 | ret = altera_pcie_parse_request_of_pci_ranges(pcie); | |
536 | if (ret) { | |
537 | dev_err(&pdev->dev, "Failed add resources\n"); | |
538 | return ret; | |
539 | } | |
540 | ||
541 | ret = altera_pcie_init_irq_domain(pcie); | |
542 | if (ret) { | |
543 | dev_err(&pdev->dev, "Failed creating IRQ Domain\n"); | |
544 | return ret; | |
545 | } | |
546 | ||
547 | /* clear all interrupts */ | |
548 | cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); | |
549 | /* enable all interrupts */ | |
550 | cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE); | |
551 | ||
552 | bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops, | |
553 | pcie, &pcie->resources); | |
554 | if (!bus) | |
555 | return -ENOMEM; | |
556 | ||
557 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); | |
558 | pci_assign_unassigned_bus_resources(bus); | |
559 | ||
560 | /* Configure PCI Express setting. */ | |
561 | list_for_each_entry(child, &bus->children, node) | |
562 | pcie_bus_configure_settings(child); | |
563 | ||
564 | pci_bus_add_devices(bus); | |
565 | ||
566 | platform_set_drvdata(pdev, pcie); | |
567 | return ret; | |
568 | } | |
569 | ||
570 | static const struct of_device_id altera_pcie_of_match[] = { | |
571 | { .compatible = "altr,pcie-root-port-1.0", }, | |
572 | {}, | |
573 | }; | |
574 | MODULE_DEVICE_TABLE(of, altera_pcie_of_match); | |
575 | ||
576 | static struct platform_driver altera_pcie_driver = { | |
577 | .probe = altera_pcie_probe, | |
578 | .driver = { | |
579 | .name = "altera-pcie", | |
580 | .of_match_table = altera_pcie_of_match, | |
581 | .suppress_bind_attrs = true, | |
582 | }, | |
583 | }; | |
584 | ||
585 | static int altera_pcie_init(void) | |
586 | { | |
587 | return platform_driver_register(&altera_pcie_driver); | |
588 | } | |
589 | module_init(altera_pcie_init); | |
590 | ||
591 | MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); | |
592 | MODULE_DESCRIPTION("Altera PCIe host controller driver"); | |
593 | MODULE_LICENSE("GPL v2"); |