Commit | Line | Data |
---|---|---|
1c52a513 TP |
1 | /* |
2 | * PCIe host controller driver for Marvell Armada-8K SoCs | |
3 | * | |
4 | * Armada-8K PCIe Glue Layer Source Code | |
5 | * | |
6 | * Copyright (C) 2016 Marvell Technology Group Ltd. | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/phy/phy.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/resource.h> | |
23 | #include <linux/of_pci.h> | |
24 | #include <linux/of_irq.h> | |
25 | ||
26 | #include "pcie-designware.h" | |
27 | ||
28 | struct armada8k_pcie { | |
29 | void __iomem *base; | |
30 | struct clk *clk; | |
31 | struct pcie_port pp; | |
32 | }; | |
33 | ||
34 | #define PCIE_VENDOR_REGS_OFFSET 0x8000 | |
35 | ||
36 | #define PCIE_GLOBAL_CONTROL_REG 0x0 | |
37 | #define PCIE_APP_LTSSM_EN BIT(2) | |
38 | #define PCIE_DEVICE_TYPE_SHIFT 4 | |
39 | #define PCIE_DEVICE_TYPE_MASK 0xF | |
40 | #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ | |
41 | ||
42 | #define PCIE_GLOBAL_STATUS_REG 0x8 | |
43 | #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1) | |
44 | #define PCIE_GLB_STS_PHY_LINK_UP BIT(9) | |
45 | ||
46 | #define PCIE_GLOBAL_INT_CAUSE1_REG 0x1C | |
47 | #define PCIE_GLOBAL_INT_MASK1_REG 0x20 | |
48 | #define PCIE_INT_A_ASSERT_MASK BIT(9) | |
49 | #define PCIE_INT_B_ASSERT_MASK BIT(10) | |
50 | #define PCIE_INT_C_ASSERT_MASK BIT(11) | |
51 | #define PCIE_INT_D_ASSERT_MASK BIT(12) | |
52 | ||
53 | #define PCIE_ARCACHE_TRC_REG 0x50 | |
54 | #define PCIE_AWCACHE_TRC_REG 0x54 | |
55 | #define PCIE_ARUSER_REG 0x5C | |
56 | #define PCIE_AWUSER_REG 0x60 | |
57 | /* | |
58 | * AR/AW Cache defauls: Normal memory, Write-Back, Read / Write | |
59 | * allocate | |
60 | */ | |
61 | #define ARCACHE_DEFAULT_VALUE 0x3511 | |
62 | #define AWCACHE_DEFAULT_VALUE 0x5311 | |
63 | ||
64 | #define DOMAIN_OUTER_SHAREABLE 0x2 | |
65 | #define AX_USER_DOMAIN_MASK 0x3 | |
66 | #define AX_USER_DOMAIN_SHIFT 4 | |
67 | ||
68 | #define to_armada8k_pcie(x) container_of(x, struct armada8k_pcie, pp) | |
69 | ||
70 | static int armada8k_pcie_link_up(struct pcie_port *pp) | |
71 | { | |
72 | struct armada8k_pcie *pcie = to_armada8k_pcie(pp); | |
73 | u32 reg; | |
74 | u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; | |
75 | ||
76 | reg = readl(pcie->base + PCIE_GLOBAL_STATUS_REG); | |
77 | ||
78 | if ((reg & mask) == mask) | |
79 | return 1; | |
80 | ||
81 | dev_dbg(pp->dev, "No link detected (Global-Status: 0x%08x).\n", reg); | |
82 | return 0; | |
83 | } | |
84 | ||
85 | static void armada8k_pcie_establish_link(struct pcie_port *pp) | |
86 | { | |
87 | struct armada8k_pcie *pcie = to_armada8k_pcie(pp); | |
88 | void __iomem *base = pcie->base; | |
89 | u32 reg; | |
90 | ||
91 | if (!dw_pcie_link_up(pp)) { | |
92 | /* Disable LTSSM state machine to enable configuration */ | |
93 | reg = readl(base + PCIE_GLOBAL_CONTROL_REG); | |
94 | reg &= ~(PCIE_APP_LTSSM_EN); | |
95 | writel(reg, base + PCIE_GLOBAL_CONTROL_REG); | |
96 | } | |
97 | ||
98 | /* Set the device to root complex mode */ | |
99 | reg = readl(base + PCIE_GLOBAL_CONTROL_REG); | |
100 | reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); | |
101 | reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; | |
102 | writel(reg, base + PCIE_GLOBAL_CONTROL_REG); | |
103 | ||
104 | /* Set the PCIe master AxCache attributes */ | |
105 | writel(ARCACHE_DEFAULT_VALUE, base + PCIE_ARCACHE_TRC_REG); | |
106 | writel(AWCACHE_DEFAULT_VALUE, base + PCIE_AWCACHE_TRC_REG); | |
107 | ||
108 | /* Set the PCIe master AxDomain attributes */ | |
109 | reg = readl(base + PCIE_ARUSER_REG); | |
110 | reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); | |
111 | reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; | |
112 | writel(reg, base + PCIE_ARUSER_REG); | |
113 | ||
114 | reg = readl(base + PCIE_AWUSER_REG); | |
115 | reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); | |
116 | reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; | |
117 | writel(reg, base + PCIE_AWUSER_REG); | |
118 | ||
119 | /* Enable INT A-D interrupts */ | |
120 | reg = readl(base + PCIE_GLOBAL_INT_MASK1_REG); | |
121 | reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | | |
122 | PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; | |
123 | writel(reg, base + PCIE_GLOBAL_INT_MASK1_REG); | |
124 | ||
125 | if (!dw_pcie_link_up(pp)) { | |
126 | /* Configuration done. Start LTSSM */ | |
127 | reg = readl(base + PCIE_GLOBAL_CONTROL_REG); | |
128 | reg |= PCIE_APP_LTSSM_EN; | |
129 | writel(reg, base + PCIE_GLOBAL_CONTROL_REG); | |
130 | } | |
131 | ||
132 | /* Wait until the link becomes active again */ | |
133 | if (dw_pcie_wait_for_link(pp)) | |
134 | dev_err(pp->dev, "Link not up after reconfiguration\n"); | |
135 | } | |
136 | ||
137 | static void armada8k_pcie_host_init(struct pcie_port *pp) | |
138 | { | |
139 | dw_pcie_setup_rc(pp); | |
140 | armada8k_pcie_establish_link(pp); | |
141 | } | |
142 | ||
143 | static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) | |
144 | { | |
145 | struct pcie_port *pp = arg; | |
146 | struct armada8k_pcie *pcie = to_armada8k_pcie(pp); | |
147 | void __iomem *base = pcie->base; | |
148 | u32 val; | |
149 | ||
150 | /* | |
151 | * Interrupts are directly handled by the device driver of the | |
152 | * PCI device. However, they are also latched into the PCIe | |
153 | * controller, so we simply discard them. | |
154 | */ | |
155 | val = readl(base + PCIE_GLOBAL_INT_CAUSE1_REG); | |
156 | writel(val, base + PCIE_GLOBAL_INT_CAUSE1_REG); | |
157 | ||
158 | return IRQ_HANDLED; | |
159 | } | |
160 | ||
161 | static struct pcie_host_ops armada8k_pcie_host_ops = { | |
162 | .link_up = armada8k_pcie_link_up, | |
163 | .host_init = armada8k_pcie_host_init, | |
164 | }; | |
165 | ||
166 | static int armada8k_add_pcie_port(struct pcie_port *pp, | |
167 | struct platform_device *pdev) | |
168 | { | |
169 | struct device *dev = &pdev->dev; | |
170 | int ret; | |
171 | ||
172 | pp->root_bus_nr = -1; | |
173 | pp->ops = &armada8k_pcie_host_ops; | |
174 | ||
175 | pp->irq = platform_get_irq(pdev, 0); | |
176 | if (!pp->irq) { | |
177 | dev_err(dev, "failed to get irq for port\n"); | |
178 | return -ENODEV; | |
179 | } | |
180 | ||
181 | ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler, | |
182 | IRQF_SHARED, "armada8k-pcie", pp); | |
183 | if (ret) { | |
184 | dev_err(dev, "failed to request irq %d\n", pp->irq); | |
185 | return ret; | |
186 | } | |
187 | ||
188 | ret = dw_pcie_host_init(pp); | |
189 | if (ret) { | |
190 | dev_err(dev, "failed to initialize host: %d\n", ret); | |
191 | return ret; | |
192 | } | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | static int armada8k_pcie_probe(struct platform_device *pdev) | |
198 | { | |
199 | struct armada8k_pcie *pcie; | |
200 | struct pcie_port *pp; | |
201 | struct device *dev = &pdev->dev; | |
202 | struct resource *base; | |
203 | int ret; | |
204 | ||
205 | pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); | |
206 | if (!pcie) | |
207 | return -ENOMEM; | |
208 | ||
209 | pcie->clk = devm_clk_get(dev, NULL); | |
210 | if (IS_ERR(pcie->clk)) | |
211 | return PTR_ERR(pcie->clk); | |
212 | ||
213 | clk_prepare_enable(pcie->clk); | |
214 | ||
215 | pp = &pcie->pp; | |
216 | pp->dev = dev; | |
217 | platform_set_drvdata(pdev, pcie); | |
218 | ||
219 | /* Get the dw-pcie unit configuration/control registers base. */ | |
220 | base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); | |
221 | pp->dbi_base = devm_ioremap_resource(dev, base); | |
222 | if (IS_ERR(pp->dbi_base)) { | |
223 | dev_err(dev, "couldn't remap regs base %p\n", base); | |
224 | ret = PTR_ERR(pp->dbi_base); | |
225 | goto fail; | |
226 | } | |
227 | ||
228 | pcie->base = pp->dbi_base + PCIE_VENDOR_REGS_OFFSET; | |
229 | ||
230 | ret = armada8k_add_pcie_port(pp, pdev); | |
231 | if (ret) | |
232 | goto fail; | |
233 | ||
234 | return 0; | |
235 | ||
236 | fail: | |
237 | if (!IS_ERR(pcie->clk)) | |
238 | clk_disable_unprepare(pcie->clk); | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | static const struct of_device_id armada8k_pcie_of_match[] = { | |
244 | { .compatible = "marvell,armada8k-pcie", }, | |
245 | {}, | |
246 | }; | |
247 | MODULE_DEVICE_TABLE(of, armada8k_pcie_of_match); | |
248 | ||
249 | static struct platform_driver armada8k_pcie_driver = { | |
250 | .probe = armada8k_pcie_probe, | |
251 | .driver = { | |
252 | .name = "armada8k-pcie", | |
253 | .of_match_table = of_match_ptr(armada8k_pcie_of_match), | |
254 | }, | |
255 | }; | |
256 | ||
257 | module_platform_driver(armada8k_pcie_driver); | |
258 | ||
259 | MODULE_DESCRIPTION("Armada 8k PCIe host controller driver"); | |
260 | MODULE_AUTHOR("Yehuda Yitshak <yehuday@marvell.com>"); | |
261 | MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); | |
262 | MODULE_LICENSE("GPL v2"); |