Commit | Line | Data |
---|---|---|
340cba60 | 1 | /* |
4b1ced84 | 2 | * Synopsys Designware PCIe host controller driver |
340cba60 JH |
3 | * |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Author: Jingoo Han <jg1.han@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
f342d940 JH |
14 | #include <linux/irq.h> |
15 | #include <linux/irqdomain.h> | |
340cba60 | 16 | #include <linux/kernel.h> |
340cba60 | 17 | #include <linux/module.h> |
f342d940 | 18 | #include <linux/msi.h> |
340cba60 | 19 | #include <linux/of_address.h> |
804f57b1 | 20 | #include <linux/of_pci.h> |
340cba60 JH |
21 | #include <linux/pci.h> |
22 | #include <linux/pci_regs.h> | |
4dd964df | 23 | #include <linux/platform_device.h> |
340cba60 | 24 | #include <linux/types.h> |
886bc5ce | 25 | #include <linux/delay.h> |
340cba60 | 26 | |
4b1ced84 | 27 | #include "pcie-designware.h" |
340cba60 JH |
28 | |
29 | /* Synopsis specific PCIE configuration registers */ | |
30 | #define PCIE_PORT_LINK_CONTROL 0x710 | |
31 | #define PORT_LINK_MODE_MASK (0x3f << 16) | |
4b1ced84 JH |
32 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
33 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) | |
340cba60 | 34 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
5b0f0738 | 35 | #define PORT_LINK_MODE_8_LANES (0xf << 16) |
340cba60 JH |
36 | |
37 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | |
38 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
ed8b472d | 39 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) |
4b1ced84 JH |
40 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
41 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) | |
42 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) | |
5b0f0738 | 43 | #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) |
340cba60 JH |
44 | |
45 | #define PCIE_MSI_ADDR_LO 0x820 | |
46 | #define PCIE_MSI_ADDR_HI 0x824 | |
47 | #define PCIE_MSI_INTR0_ENABLE 0x828 | |
48 | #define PCIE_MSI_INTR0_MASK 0x82C | |
49 | #define PCIE_MSI_INTR0_STATUS 0x830 | |
50 | ||
51 | #define PCIE_ATU_VIEWPORT 0x900 | |
52 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | |
53 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | |
54 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) | |
55 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | |
56 | #define PCIE_ATU_CR1 0x904 | |
57 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | |
58 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | |
59 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | |
60 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | |
61 | #define PCIE_ATU_CR2 0x908 | |
62 | #define PCIE_ATU_ENABLE (0x1 << 31) | |
63 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | |
64 | #define PCIE_ATU_LOWER_BASE 0x90C | |
65 | #define PCIE_ATU_UPPER_BASE 0x910 | |
66 | #define PCIE_ATU_LIMIT 0x914 | |
67 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
68 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | |
69 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | |
70 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | |
71 | #define PCIE_ATU_UPPER_TARGET 0x91C | |
72 | ||
dac29e6c JP |
73 | /* PCIe Port Logic registers */ |
74 | #define PLR_OFFSET 0x700 | |
75 | #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) | |
76 | #define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010 | |
77 | ||
cbce7900 | 78 | static struct pci_ops dw_pcie_ops; |
340cba60 | 79 | |
4c45852f | 80 | int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) |
340cba60 | 81 | { |
b6b18f58 GP |
82 | if ((uintptr_t)addr & (size - 1)) { |
83 | *val = 0; | |
84 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
85 | } | |
86 | ||
c003ca99 GP |
87 | if (size == 4) |
88 | *val = readl(addr); | |
340cba60 | 89 | else if (size == 2) |
4c45852f | 90 | *val = readw(addr); |
c003ca99 | 91 | else if (size == 1) |
4c45852f | 92 | *val = readb(addr); |
c003ca99 GP |
93 | else { |
94 | *val = 0; | |
340cba60 | 95 | return PCIBIOS_BAD_REGISTER_NUMBER; |
c003ca99 | 96 | } |
340cba60 JH |
97 | |
98 | return PCIBIOS_SUCCESSFUL; | |
99 | } | |
100 | ||
4c45852f | 101 | int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) |
340cba60 | 102 | { |
b6b18f58 GP |
103 | if ((uintptr_t)addr & (size - 1)) |
104 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
105 | ||
340cba60 JH |
106 | if (size == 4) |
107 | writel(val, addr); | |
108 | else if (size == 2) | |
4c45852f | 109 | writew(val, addr); |
340cba60 | 110 | else if (size == 1) |
4c45852f | 111 | writeb(val, addr); |
340cba60 JH |
112 | else |
113 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
114 | ||
115 | return PCIBIOS_SUCCESSFUL; | |
116 | } | |
117 | ||
f7b7868c | 118 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) |
340cba60 | 119 | { |
4b1ced84 | 120 | if (pp->ops->readl_rc) |
f7b7868c | 121 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); |
4b1ced84 | 122 | else |
f7b7868c | 123 | *val = readl(pp->dbi_base + reg); |
340cba60 JH |
124 | } |
125 | ||
f7b7868c | 126 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
340cba60 | 127 | { |
4b1ced84 | 128 | if (pp->ops->writel_rc) |
f7b7868c | 129 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
4b1ced84 | 130 | else |
f7b7868c | 131 | writel(val, pp->dbi_base + reg); |
340cba60 JH |
132 | } |
133 | ||
73e40850 BH |
134 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
135 | u32 *val) | |
340cba60 | 136 | { |
4b1ced84 | 137 | if (pp->ops->rd_own_conf) |
116a489d | 138 | return pp->ops->rd_own_conf(pp, where, size, val); |
4b1ced84 | 139 | |
116a489d | 140 | return dw_pcie_cfg_read(pp->dbi_base + where, size, val); |
340cba60 JH |
141 | } |
142 | ||
73e40850 BH |
143 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
144 | u32 val) | |
340cba60 | 145 | { |
4b1ced84 | 146 | if (pp->ops->wr_own_conf) |
116a489d | 147 | return pp->ops->wr_own_conf(pp, where, size, val); |
4b1ced84 | 148 | |
116a489d | 149 | return dw_pcie_cfg_write(pp->dbi_base + where, size, val); |
340cba60 JH |
150 | } |
151 | ||
63503c87 JZ |
152 | static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, |
153 | int type, u64 cpu_addr, u64 pci_addr, u32 size) | |
154 | { | |
17209dfb SV |
155 | u32 val; |
156 | ||
63503c87 JZ |
157 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, |
158 | PCIE_ATU_VIEWPORT); | |
159 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE); | |
160 | dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE); | |
161 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1), | |
162 | PCIE_ATU_LIMIT); | |
163 | dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET); | |
164 | dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); | |
165 | dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); | |
166 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | |
17209dfb SV |
167 | |
168 | /* | |
169 | * Make sure ATU enable takes effect before any subsequent config | |
170 | * and I/O accesses. | |
171 | */ | |
172 | dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val); | |
63503c87 JZ |
173 | } |
174 | ||
f342d940 JH |
175 | static struct irq_chip dw_msi_irq_chip = { |
176 | .name = "PCI-MSI", | |
280510f1 TG |
177 | .irq_enable = pci_msi_unmask_irq, |
178 | .irq_disable = pci_msi_mask_irq, | |
179 | .irq_mask = pci_msi_mask_irq, | |
180 | .irq_unmask = pci_msi_unmask_irq, | |
f342d940 JH |
181 | }; |
182 | ||
183 | /* MSI int handler */ | |
7f4f16ee | 184 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
f342d940 JH |
185 | { |
186 | unsigned long val; | |
904d0e78 | 187 | int i, pos, irq; |
7f4f16ee | 188 | irqreturn_t ret = IRQ_NONE; |
f342d940 JH |
189 | |
190 | for (i = 0; i < MAX_MSI_CTRLS; i++) { | |
191 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, | |
192 | (u32 *)&val); | |
193 | if (val) { | |
7f4f16ee | 194 | ret = IRQ_HANDLED; |
f342d940 JH |
195 | pos = 0; |
196 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { | |
904d0e78 PA |
197 | irq = irq_find_mapping(pp->irq_domain, |
198 | i * 32 + pos); | |
ca165892 HH |
199 | dw_pcie_wr_own_conf(pp, |
200 | PCIE_MSI_INTR0_STATUS + i * 12, | |
201 | 4, 1 << pos); | |
904d0e78 | 202 | generic_handle_irq(irq); |
f342d940 JH |
203 | pos++; |
204 | } | |
205 | } | |
f342d940 | 206 | } |
7f4f16ee LS |
207 | |
208 | return ret; | |
f342d940 JH |
209 | } |
210 | ||
211 | void dw_pcie_msi_init(struct pcie_port *pp) | |
212 | { | |
c8947fbb LS |
213 | u64 msi_target; |
214 | ||
f342d940 | 215 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
c8947fbb | 216 | msi_target = virt_to_phys((void *)pp->msi_data); |
f342d940 JH |
217 | |
218 | /* program the msi_data */ | |
219 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, | |
c8947fbb LS |
220 | (u32)(msi_target & 0xffffffff)); |
221 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, | |
222 | (u32)(msi_target >> 32 & 0xffffffff)); | |
f342d940 JH |
223 | } |
224 | ||
2f37c5a8 MK |
225 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
226 | { | |
227 | unsigned int res, bit, val; | |
228 | ||
229 | res = (irq / 32) * 12; | |
230 | bit = irq % 32; | |
231 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
232 | val &= ~(1 << bit); | |
233 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
234 | } | |
235 | ||
be3f48cb | 236 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
58275f2f | 237 | unsigned int nvec, unsigned int pos) |
be3f48cb | 238 | { |
2f37c5a8 | 239 | unsigned int i; |
be3f48cb | 240 | |
0b8cfb6a | 241 | for (i = 0; i < nvec; i++) { |
be3f48cb | 242 | irq_set_msi_desc_off(irq_base, i, NULL); |
58275f2f | 243 | /* Disable corresponding interrupt on MSI controller */ |
2f37c5a8 MK |
244 | if (pp->ops->msi_clear_irq) |
245 | pp->ops->msi_clear_irq(pp, pos + i); | |
246 | else | |
247 | dw_pcie_msi_clear_irq(pp, pos + i); | |
be3f48cb | 248 | } |
c8df6ac9 LS |
249 | |
250 | bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); | |
be3f48cb BEN |
251 | } |
252 | ||
2f37c5a8 MK |
253 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
254 | { | |
255 | unsigned int res, bit, val; | |
256 | ||
257 | res = (irq / 32) * 12; | |
258 | bit = irq % 32; | |
259 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
260 | val |= 1 << bit; | |
261 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
262 | } | |
263 | ||
f342d940 JH |
264 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
265 | { | |
c8df6ac9 | 266 | int irq, pos0, i; |
cbce7900 | 267 | struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc); |
f342d940 | 268 | |
c8df6ac9 LS |
269 | pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, |
270 | order_base_2(no_irqs)); | |
271 | if (pos0 < 0) | |
272 | goto no_valid_irq; | |
f342d940 | 273 | |
904d0e78 PA |
274 | irq = irq_find_mapping(pp->irq_domain, pos0); |
275 | if (!irq) | |
f342d940 JH |
276 | goto no_valid_irq; |
277 | ||
be3f48cb BEN |
278 | /* |
279 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates | |
280 | * descs so there is no need to allocate descs here. We can therefore | |
281 | * assume that if irq_find_mapping above returns non-zero, then the | |
282 | * descs are also successfully allocated. | |
283 | */ | |
284 | ||
0b8cfb6a | 285 | for (i = 0; i < no_irqs; i++) { |
be3f48cb BEN |
286 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
287 | clear_irq_range(pp, irq, i, pos0); | |
288 | goto no_valid_irq; | |
289 | } | |
f342d940 | 290 | /*Enable corresponding interrupt in MSI interrupt controller */ |
2f37c5a8 MK |
291 | if (pp->ops->msi_set_irq) |
292 | pp->ops->msi_set_irq(pp, pos0 + i); | |
293 | else | |
294 | dw_pcie_msi_set_irq(pp, pos0 + i); | |
f342d940 JH |
295 | } |
296 | ||
297 | *pos = pos0; | |
79707374 LS |
298 | desc->nvec_used = no_irqs; |
299 | desc->msi_attrib.multiple = order_base_2(no_irqs); | |
300 | ||
f342d940 JH |
301 | return irq; |
302 | ||
303 | no_valid_irq: | |
304 | *pos = pos0; | |
305 | return -ENOSPC; | |
306 | } | |
307 | ||
ea643e1a | 308 | static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) |
f342d940 | 309 | { |
f342d940 | 310 | struct msi_msg msg; |
c8947fbb | 311 | u64 msi_target; |
f342d940 | 312 | |
450e344e | 313 | if (pp->ops->get_msi_addr) |
c8947fbb | 314 | msi_target = pp->ops->get_msi_addr(pp); |
2f37c5a8 | 315 | else |
c8947fbb LS |
316 | msi_target = virt_to_phys((void *)pp->msi_data); |
317 | ||
318 | msg.address_lo = (u32)(msi_target & 0xffffffff); | |
319 | msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff); | |
24832b4d ML |
320 | |
321 | if (pp->ops->get_msi_data) | |
322 | msg.data = pp->ops->get_msi_data(pp, pos); | |
323 | else | |
324 | msg.data = pos; | |
325 | ||
83a18912 | 326 | pci_write_msi_msg(irq, &msg); |
ea643e1a LS |
327 | } |
328 | ||
329 | static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, | |
330 | struct msi_desc *desc) | |
331 | { | |
332 | int irq, pos; | |
cbce7900 | 333 | struct pcie_port *pp = pdev->bus->sysdata; |
ea643e1a LS |
334 | |
335 | if (desc->msi_attrib.is_msix) | |
336 | return -EINVAL; | |
337 | ||
338 | irq = assign_irq(1, desc, &pos); | |
339 | if (irq < 0) | |
340 | return irq; | |
341 | ||
342 | dw_msi_setup_msg(pp, irq, pos); | |
f342d940 JH |
343 | |
344 | return 0; | |
345 | } | |
346 | ||
79707374 LS |
347 | static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev, |
348 | int nvec, int type) | |
349 | { | |
350 | #ifdef CONFIG_PCI_MSI | |
351 | int irq, pos; | |
352 | struct msi_desc *desc; | |
cbce7900 | 353 | struct pcie_port *pp = pdev->bus->sysdata; |
79707374 LS |
354 | |
355 | /* MSI-X interrupts are not supported */ | |
356 | if (type == PCI_CAP_ID_MSIX) | |
357 | return -EINVAL; | |
358 | ||
359 | WARN_ON(!list_is_singular(&pdev->dev.msi_list)); | |
360 | desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); | |
361 | ||
362 | irq = assign_irq(nvec, desc, &pos); | |
363 | if (irq < 0) | |
364 | return irq; | |
365 | ||
366 | dw_msi_setup_msg(pp, irq, pos); | |
367 | ||
368 | return 0; | |
369 | #else | |
370 | return -EINVAL; | |
371 | #endif | |
372 | } | |
373 | ||
c2791b80 | 374 | static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
f342d940 | 375 | { |
91f8ae82 | 376 | struct irq_data *data = irq_get_irq_data(irq); |
c391f262 | 377 | struct msi_desc *msi = irq_data_get_msi_desc(data); |
cbce7900 | 378 | struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi); |
91f8ae82 LS |
379 | |
380 | clear_irq_range(pp, irq, 1, data->hwirq); | |
f342d940 JH |
381 | } |
382 | ||
c2791b80 | 383 | static struct msi_controller dw_pcie_msi_chip = { |
f342d940 | 384 | .setup_irq = dw_msi_setup_irq, |
79707374 | 385 | .setup_irqs = dw_msi_setup_irqs, |
f342d940 JH |
386 | .teardown_irq = dw_msi_teardown_irq, |
387 | }; | |
388 | ||
886bc5ce JP |
389 | int dw_pcie_wait_for_link(struct pcie_port *pp) |
390 | { | |
391 | int retries; | |
392 | ||
393 | /* check if the link is up or not */ | |
394 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { | |
395 | if (dw_pcie_link_up(pp)) { | |
396 | dev_info(pp->dev, "link up\n"); | |
397 | return 0; | |
398 | } | |
399 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); | |
400 | } | |
401 | ||
402 | dev_err(pp->dev, "phy link never came up\n"); | |
403 | ||
404 | return -ETIMEDOUT; | |
405 | } | |
406 | ||
4b1ced84 JH |
407 | int dw_pcie_link_up(struct pcie_port *pp) |
408 | { | |
dac29e6c JP |
409 | u32 val; |
410 | ||
4b1ced84 JH |
411 | if (pp->ops->link_up) |
412 | return pp->ops->link_up(pp); | |
116a489d | 413 | |
dac29e6c JP |
414 | val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); |
415 | return val & PCIE_PHY_DEBUG_R1_LINK_UP; | |
4b1ced84 JH |
416 | } |
417 | ||
f342d940 JH |
418 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
419 | irq_hw_number_t hwirq) | |
420 | { | |
421 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); | |
422 | irq_set_chip_data(irq, domain->host_data); | |
f342d940 JH |
423 | |
424 | return 0; | |
425 | } | |
426 | ||
427 | static const struct irq_domain_ops msi_domain_ops = { | |
428 | .map = dw_pcie_msi_map, | |
429 | }; | |
430 | ||
a43f32d6 | 431 | int dw_pcie_host_init(struct pcie_port *pp) |
4b1ced84 JH |
432 | { |
433 | struct device_node *np = pp->dev->of_node; | |
4dd964df | 434 | struct platform_device *pdev = to_platform_device(pp->dev); |
cbce7900 | 435 | struct pci_bus *bus, *child; |
4dd964df | 436 | struct resource *cfg_res; |
9cdce1cd | 437 | int i, ret; |
0021d22b ZW |
438 | LIST_HEAD(res); |
439 | struct resource_entry *win; | |
f342d940 | 440 | |
4dd964df KVA |
441 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
442 | if (cfg_res) { | |
adf70fc0 PA |
443 | pp->cfg0_size = resource_size(cfg_res)/2; |
444 | pp->cfg1_size = resource_size(cfg_res)/2; | |
4dd964df | 445 | pp->cfg0_base = cfg_res->start; |
adf70fc0 | 446 | pp->cfg1_base = cfg_res->start + pp->cfg0_size; |
0f414212 | 447 | } else if (!pp->va_cfg0_base) { |
4dd964df KVA |
448 | dev_err(pp->dev, "missing *config* reg space\n"); |
449 | } | |
450 | ||
0021d22b ZW |
451 | ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); |
452 | if (ret) | |
453 | return ret; | |
4b1ced84 | 454 | |
12722dbb BH |
455 | ret = devm_request_pci_bus_resources(&pdev->dev, &res); |
456 | if (ret) | |
457 | goto error; | |
458 | ||
4b1ced84 | 459 | /* Get the I/O and memory ranges from DT */ |
0021d22b ZW |
460 | resource_list_for_each_entry(win, &res) { |
461 | switch (resource_type(win->res)) { | |
462 | case IORESOURCE_IO: | |
463 | pp->io = win->res; | |
464 | pp->io->name = "I/O"; | |
465 | pp->io_size = resource_size(pp->io); | |
466 | pp->io_bus_addr = pp->io->start - win->offset; | |
cbce7900 | 467 | ret = pci_remap_iospace(pp->io, pp->io_base); |
7baf69c7 | 468 | if (ret) |
cbce7900 ZW |
469 | dev_warn(pp->dev, "error %d: failed to map resource %pR\n", |
470 | ret, pp->io); | |
0021d22b ZW |
471 | break; |
472 | case IORESOURCE_MEM: | |
473 | pp->mem = win->res; | |
474 | pp->mem->name = "MEM"; | |
475 | pp->mem_size = resource_size(pp->mem); | |
476 | pp->mem_bus_addr = pp->mem->start - win->offset; | |
477 | break; | |
478 | case 0: | |
479 | pp->cfg = win->res; | |
480 | pp->cfg0_size = resource_size(pp->cfg)/2; | |
481 | pp->cfg1_size = resource_size(pp->cfg)/2; | |
482 | pp->cfg0_base = pp->cfg->start; | |
483 | pp->cfg1_base = pp->cfg->start + pp->cfg0_size; | |
484 | break; | |
485 | case IORESOURCE_BUS: | |
486 | pp->busn = win->res; | |
487 | break; | |
4b1ced84 | 488 | } |
4f2ebe00 LS |
489 | } |
490 | ||
4b1ced84 | 491 | if (!pp->dbi_base) { |
0021d22b ZW |
492 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start, |
493 | resource_size(pp->cfg)); | |
4b1ced84 JH |
494 | if (!pp->dbi_base) { |
495 | dev_err(pp->dev, "error with ioremap\n"); | |
27d9cb7e BH |
496 | ret = -ENOMEM; |
497 | goto error; | |
4b1ced84 JH |
498 | } |
499 | } | |
500 | ||
0021d22b | 501 | pp->mem_base = pp->mem->start; |
4b1ced84 | 502 | |
4b1ced84 | 503 | if (!pp->va_cfg0_base) { |
b14a3d17 | 504 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
adf70fc0 | 505 | pp->cfg0_size); |
b14a3d17 MK |
506 | if (!pp->va_cfg0_base) { |
507 | dev_err(pp->dev, "error with ioremap in function\n"); | |
27d9cb7e BH |
508 | ret = -ENOMEM; |
509 | goto error; | |
b14a3d17 | 510 | } |
4b1ced84 | 511 | } |
b14a3d17 | 512 | |
4b1ced84 | 513 | if (!pp->va_cfg1_base) { |
b14a3d17 | 514 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
adf70fc0 | 515 | pp->cfg1_size); |
b14a3d17 MK |
516 | if (!pp->va_cfg1_base) { |
517 | dev_err(pp->dev, "error with ioremap\n"); | |
27d9cb7e BH |
518 | ret = -ENOMEM; |
519 | goto error; | |
b14a3d17 | 520 | } |
4b1ced84 JH |
521 | } |
522 | ||
907fce09 GP |
523 | ret = of_property_read_u32(np, "num-lanes", &pp->lanes); |
524 | if (ret) | |
525 | pp->lanes = 0; | |
4b1ced84 | 526 | |
f342d940 | 527 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
b14a3d17 MK |
528 | if (!pp->ops->msi_host_init) { |
529 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, | |
530 | MAX_MSI_IRQS, &msi_domain_ops, | |
531 | &dw_pcie_msi_chip); | |
532 | if (!pp->irq_domain) { | |
533 | dev_err(pp->dev, "irq domain init failed\n"); | |
27d9cb7e BH |
534 | ret = -ENXIO; |
535 | goto error; | |
b14a3d17 | 536 | } |
f342d940 | 537 | |
b14a3d17 MK |
538 | for (i = 0; i < MAX_MSI_IRQS; i++) |
539 | irq_create_mapping(pp->irq_domain, i); | |
540 | } else { | |
541 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); | |
542 | if (ret < 0) | |
27d9cb7e | 543 | goto error; |
b14a3d17 | 544 | } |
f342d940 JH |
545 | } |
546 | ||
4b1ced84 JH |
547 | if (pp->ops->host_init) |
548 | pp->ops->host_init(pp); | |
549 | ||
cbce7900 ZW |
550 | pp->root_bus_nr = pp->busn->start; |
551 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
552 | bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr, | |
553 | &dw_pcie_ops, pp, &res, | |
554 | &dw_pcie_msi_chip); | |
555 | dw_pcie_msi_chip.dev = pp->dev; | |
556 | } else | |
557 | bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, | |
558 | pp, &res); | |
27d9cb7e BH |
559 | if (!bus) { |
560 | ret = -ENOMEM; | |
561 | goto error; | |
562 | } | |
cbce7900 ZW |
563 | |
564 | if (pp->ops->scan_bus) | |
565 | pp->ops->scan_bus(pp); | |
566 | ||
567 | #ifdef CONFIG_ARM | |
568 | /* support old dtbs that incorrectly describe IRQs */ | |
569 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); | |
0815f957 YW |
570 | #endif |
571 | ||
ed00c83c LP |
572 | pci_bus_size_bridges(bus); |
573 | pci_bus_assign_resources(bus); | |
4b1ced84 | 574 | |
ed00c83c LP |
575 | list_for_each_entry(child, &bus->children, node) |
576 | pcie_bus_configure_settings(child); | |
4b1ced84 | 577 | |
cbce7900 | 578 | pci_bus_add_devices(bus); |
4b1ced84 | 579 | return 0; |
27d9cb7e BH |
580 | |
581 | error: | |
582 | pci_free_resource_list(&res); | |
583 | return ret; | |
4b1ced84 JH |
584 | } |
585 | ||
4b1ced84 | 586 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
587 | u32 devfn, int where, int size, u32 *val) |
588 | { | |
2d91b491 | 589 | int ret, type; |
4c45852f | 590 | u32 busdev, cfg_size; |
2d91b491 JZ |
591 | u64 cpu_addr; |
592 | void __iomem *va_cfg_base; | |
340cba60 | 593 | |
67de2dc3 BH |
594 | if (pp->ops->rd_other_conf) |
595 | return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); | |
596 | ||
340cba60 JH |
597 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
598 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
340cba60 JH |
599 | |
600 | if (bus->parent->number == pp->root_bus_nr) { | |
2d91b491 | 601 | type = PCIE_ATU_TYPE_CFG0; |
9cdce1cd | 602 | cpu_addr = pp->cfg0_base; |
2d91b491 JZ |
603 | cfg_size = pp->cfg0_size; |
604 | va_cfg_base = pp->va_cfg0_base; | |
340cba60 | 605 | } else { |
2d91b491 | 606 | type = PCIE_ATU_TYPE_CFG1; |
9cdce1cd | 607 | cpu_addr = pp->cfg1_base; |
2d91b491 JZ |
608 | cfg_size = pp->cfg1_size; |
609 | va_cfg_base = pp->va_cfg1_base; | |
340cba60 JH |
610 | } |
611 | ||
2d91b491 JZ |
612 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
613 | type, cpu_addr, | |
614 | busdev, cfg_size); | |
4c45852f | 615 | ret = dw_pcie_cfg_read(va_cfg_base + where, size, val); |
2d91b491 | 616 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
9cdce1cd | 617 | PCIE_ATU_TYPE_IO, pp->io_base, |
2d91b491 JZ |
618 | pp->io_bus_addr, pp->io_size); |
619 | ||
340cba60 JH |
620 | return ret; |
621 | } | |
622 | ||
4b1ced84 | 623 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
624 | u32 devfn, int where, int size, u32 val) |
625 | { | |
2d91b491 | 626 | int ret, type; |
4c45852f | 627 | u32 busdev, cfg_size; |
2d91b491 JZ |
628 | u64 cpu_addr; |
629 | void __iomem *va_cfg_base; | |
340cba60 | 630 | |
67de2dc3 BH |
631 | if (pp->ops->wr_other_conf) |
632 | return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); | |
633 | ||
340cba60 JH |
634 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
635 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
340cba60 JH |
636 | |
637 | if (bus->parent->number == pp->root_bus_nr) { | |
2d91b491 | 638 | type = PCIE_ATU_TYPE_CFG0; |
9cdce1cd | 639 | cpu_addr = pp->cfg0_base; |
2d91b491 JZ |
640 | cfg_size = pp->cfg0_size; |
641 | va_cfg_base = pp->va_cfg0_base; | |
340cba60 | 642 | } else { |
2d91b491 | 643 | type = PCIE_ATU_TYPE_CFG1; |
9cdce1cd | 644 | cpu_addr = pp->cfg1_base; |
2d91b491 JZ |
645 | cfg_size = pp->cfg1_size; |
646 | va_cfg_base = pp->va_cfg1_base; | |
340cba60 JH |
647 | } |
648 | ||
2d91b491 JZ |
649 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
650 | type, cpu_addr, | |
651 | busdev, cfg_size); | |
4c45852f | 652 | ret = dw_pcie_cfg_write(va_cfg_base + where, size, val); |
2d91b491 | 653 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
9cdce1cd | 654 | PCIE_ATU_TYPE_IO, pp->io_base, |
2d91b491 JZ |
655 | pp->io_bus_addr, pp->io_size); |
656 | ||
340cba60 JH |
657 | return ret; |
658 | } | |
659 | ||
4b1ced84 | 660 | static int dw_pcie_valid_config(struct pcie_port *pp, |
340cba60 JH |
661 | struct pci_bus *bus, int dev) |
662 | { | |
663 | /* If there is no link, then there is no device */ | |
664 | if (bus->number != pp->root_bus_nr) { | |
4b1ced84 | 665 | if (!dw_pcie_link_up(pp)) |
340cba60 JH |
666 | return 0; |
667 | } | |
668 | ||
669 | /* access only one slot on each root port */ | |
670 | if (bus->number == pp->root_bus_nr && dev > 0) | |
671 | return 0; | |
672 | ||
673 | /* | |
674 | * do not read more than one device on the bus directly attached | |
675 | * to RC's (Virtual Bridge's) DS side. | |
676 | */ | |
677 | if (bus->primary == pp->root_bus_nr && dev > 0) | |
678 | return 0; | |
679 | ||
680 | return 1; | |
681 | } | |
682 | ||
4b1ced84 | 683 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
340cba60 JH |
684 | int size, u32 *val) |
685 | { | |
cbce7900 | 686 | struct pcie_port *pp = bus->sysdata; |
340cba60 | 687 | |
4b1ced84 | 688 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
340cba60 JH |
689 | *val = 0xffffffff; |
690 | return PCIBIOS_DEVICE_NOT_FOUND; | |
691 | } | |
692 | ||
116a489d BH |
693 | if (bus->number == pp->root_bus_nr) |
694 | return dw_pcie_rd_own_conf(pp, where, size, val); | |
340cba60 | 695 | |
116a489d | 696 | return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); |
340cba60 JH |
697 | } |
698 | ||
4b1ced84 | 699 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
340cba60 JH |
700 | int where, int size, u32 val) |
701 | { | |
cbce7900 | 702 | struct pcie_port *pp = bus->sysdata; |
340cba60 | 703 | |
4b1ced84 | 704 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
340cba60 JH |
705 | return PCIBIOS_DEVICE_NOT_FOUND; |
706 | ||
116a489d BH |
707 | if (bus->number == pp->root_bus_nr) |
708 | return dw_pcie_wr_own_conf(pp, where, size, val); | |
340cba60 | 709 | |
116a489d | 710 | return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); |
340cba60 JH |
711 | } |
712 | ||
4b1ced84 JH |
713 | static struct pci_ops dw_pcie_ops = { |
714 | .read = dw_pcie_rd_conf, | |
715 | .write = dw_pcie_wr_conf, | |
340cba60 JH |
716 | }; |
717 | ||
4b1ced84 | 718 | void dw_pcie_setup_rc(struct pcie_port *pp) |
340cba60 | 719 | { |
340cba60 | 720 | u32 val; |
340cba60 | 721 | |
66c5c34b | 722 | /* set the number of lanes */ |
f7b7868c | 723 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); |
340cba60 | 724 | val &= ~PORT_LINK_MODE_MASK; |
4b1ced84 JH |
725 | switch (pp->lanes) { |
726 | case 1: | |
727 | val |= PORT_LINK_MODE_1_LANES; | |
728 | break; | |
729 | case 2: | |
730 | val |= PORT_LINK_MODE_2_LANES; | |
731 | break; | |
732 | case 4: | |
733 | val |= PORT_LINK_MODE_4_LANES; | |
734 | break; | |
5b0f0738 ZW |
735 | case 8: |
736 | val |= PORT_LINK_MODE_8_LANES; | |
737 | break; | |
907fce09 GP |
738 | default: |
739 | dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); | |
740 | return; | |
4b1ced84 | 741 | } |
f7b7868c | 742 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
340cba60 JH |
743 | |
744 | /* set link width speed control register */ | |
f7b7868c | 745 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); |
340cba60 | 746 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
4b1ced84 JH |
747 | switch (pp->lanes) { |
748 | case 1: | |
749 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; | |
750 | break; | |
751 | case 2: | |
752 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; | |
753 | break; | |
754 | case 4: | |
755 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; | |
756 | break; | |
5b0f0738 ZW |
757 | case 8: |
758 | val |= PORT_LOGIC_LINK_WIDTH_8_LANES; | |
759 | break; | |
4b1ced84 | 760 | } |
f7b7868c | 761 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
340cba60 JH |
762 | |
763 | /* setup RC BARs */ | |
f7b7868c | 764 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
dbffdd68 | 765 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
340cba60 JH |
766 | |
767 | /* setup interrupt pins */ | |
f7b7868c | 768 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); |
340cba60 JH |
769 | val &= 0xffff00ff; |
770 | val |= 0x00000100; | |
f7b7868c | 771 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
340cba60 JH |
772 | |
773 | /* setup bus numbers */ | |
f7b7868c | 774 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); |
340cba60 JH |
775 | val &= 0xff000000; |
776 | val |= 0x00010100; | |
f7b7868c | 777 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
340cba60 | 778 | |
340cba60 | 779 | /* setup command register */ |
f7b7868c | 780 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); |
340cba60 JH |
781 | val &= 0xffff0000; |
782 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
783 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | |
f7b7868c | 784 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
7e57fd14 JZ |
785 | |
786 | /* | |
787 | * If the platform provides ->rd_other_conf, it means the platform | |
788 | * uses its own address translation component rather than ATU, so | |
789 | * we should not program the ATU here. | |
790 | */ | |
791 | if (!pp->ops->rd_other_conf) | |
792 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, | |
793 | PCIE_ATU_TYPE_MEM, pp->mem_base, | |
794 | pp->mem_bus_addr, pp->mem_size); | |
795 | ||
796 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); | |
797 | ||
798 | /* program correct class for RC */ | |
799 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); | |
800 | ||
801 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); | |
802 | val |= PORT_LOGIC_SPEED_CHANGE; | |
803 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); | |
340cba60 | 804 | } |
340cba60 JH |
805 | |
806 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); | |
4b1ced84 | 807 | MODULE_DESCRIPTION("Designware PCIe host controller driver"); |
340cba60 | 808 | MODULE_LICENSE("GPL v2"); |