projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / drivers / pci / host / pcie-designware.c
CommitLineData
340cba60 1/*
4b1ced84 2 * Synopsys Designware PCIe host controller driver
340cba60
JH		 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
f342d940
JH		 14#include <linux/irq.h>
15#include <linux/irqdomain.h>
340cba60 16#include <linux/kernel.h>
340cba60 17#include <linux/module.h>
f342d940 18#include <linux/msi.h>
340cba60 19#include <linux/of_address.h>
804f57b1 20#include <linux/of_pci.h>
340cba60
JH		 21#include <linux/pci.h>
22#include <linux/pci_regs.h>
4dd964df 23#include <linux/platform_device.h>
340cba60
JH		 24#include <linux/types.h>
25
4b1ced84 26#include "pcie-designware.h"
340cba60
JH		 27
28/* Synopsis specific PCIE configuration registers */
29#define PCIE_PORT_LINK_CONTROL 0x710
30#define PORT_LINK_MODE_MASK (0x3f << 16)
4b1ced84
JH		 31#define PORT_LINK_MODE_1_LANES (0x1 << 16)
32#define PORT_LINK_MODE_2_LANES (0x3 << 16)
340cba60 33#define PORT_LINK_MODE_4_LANES (0x7 << 16)
5b0f0738 34#define PORT_LINK_MODE_8_LANES (0xf << 16)
340cba60
JH		 35
36#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
37#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
ed8b472d 38#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
4b1ced84
JH		 39#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
40#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
41#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
5b0f0738 42#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
340cba60
JH		 43
44#define PCIE_MSI_ADDR_LO 0x820
45#define PCIE_MSI_ADDR_HI 0x824
46#define PCIE_MSI_INTR0_ENABLE 0x828
47#define PCIE_MSI_INTR0_MASK 0x82C
48#define PCIE_MSI_INTR0_STATUS 0x830
49
50#define PCIE_ATU_VIEWPORT 0x900
51#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
52#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
53#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
54#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
55#define PCIE_ATU_CR1 0x904
56#define PCIE_ATU_TYPE_MEM (0x0 << 0)
57#define PCIE_ATU_TYPE_IO (0x2 << 0)
58#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
59#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
60#define PCIE_ATU_CR2 0x908
61#define PCIE_ATU_ENABLE (0x1 << 31)
62#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
63#define PCIE_ATU_LOWER_BASE 0x90C
64#define PCIE_ATU_UPPER_BASE 0x910
65#define PCIE_ATU_LIMIT 0x914
66#define PCIE_ATU_LOWER_TARGET 0x918
67#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
68#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
69#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
70#define PCIE_ATU_UPPER_TARGET 0x91C
71
cbce7900 72static struct pci_ops dw_pcie_ops;
340cba60 73
4c45852f 74int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
340cba60 75{
b6b18f58
GP		 76 if ((uintptr_t)addr & (size - 1)) {
77 *val = 0;
78 return PCIBIOS_BAD_REGISTER_NUMBER;
79 }
80
c003ca99
GP		 81 if (size == 4)
82 *val = readl(addr);
340cba60 83 else if (size == 2)
4c45852f 84 *val = readw(addr);
c003ca99 85 else if (size == 1)
4c45852f 86 *val = readb(addr);
c003ca99
GP		 87 else {
88 *val = 0;
340cba60 89 return PCIBIOS_BAD_REGISTER_NUMBER;
c003ca99 90 }
340cba60
JH		 91
92 return PCIBIOS_SUCCESSFUL;
93}
94
4c45852f 95int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
340cba60 96{
b6b18f58
GP		 97 if ((uintptr_t)addr & (size - 1))
98 return PCIBIOS_BAD_REGISTER_NUMBER;
99
340cba60
JH		 100 if (size == 4)
101 writel(val, addr);
102 else if (size == 2)
4c45852f 103 writew(val, addr);
340cba60 104 else if (size == 1)
4c45852f 105 writeb(val, addr);
340cba60
JH		 106 else
107 return PCIBIOS_BAD_REGISTER_NUMBER;
108
109 return PCIBIOS_SUCCESSFUL;
110}
111
f7b7868c 112static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
340cba60 113{
4b1ced84 114 if (pp->ops->readl_rc)
f7b7868c 115 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
4b1ced84 116 else
f7b7868c 117 *val = readl(pp->dbi_base + reg);
340cba60
JH		 118}
119
f7b7868c 120static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
340cba60 121{
4b1ced84 122 if (pp->ops->writel_rc)
f7b7868c 123 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
4b1ced84 124 else
f7b7868c 125 writel(val, pp->dbi_base + reg);
340cba60
JH		 126}
127
73e40850
BH		 128static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
129 u32 *val)
340cba60 130{
4b1ced84 131 if (pp->ops->rd_own_conf)
116a489d 132 return pp->ops->rd_own_conf(pp, where, size, val);
4b1ced84 133
116a489d 134 return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
340cba60
JH		 135}
136
73e40850
BH		 137static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
138 u32 val)
340cba60 139{
4b1ced84 140 if (pp->ops->wr_own_conf)
116a489d 141 return pp->ops->wr_own_conf(pp, where, size, val);
4b1ced84 142
116a489d 143 return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
340cba60
JH		 144}
145
63503c87
JZ		 146static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
147 int type, u64 cpu_addr, u64 pci_addr, u32 size)
148{
17209dfb
SV		 149 u32 val;
150
63503c87
JZ		 151 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
152 PCIE_ATU_VIEWPORT);
153 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
154 dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
155 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
156 PCIE_ATU_LIMIT);
157 dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
158 dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
159 dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
160 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
17209dfb
SV		 161
162 /*
163 * Make sure ATU enable takes effect before any subsequent config
164 * and I/O accesses.
165 */
166 dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
63503c87
JZ		 167}
168
f342d940
JH		 169static struct irq_chip dw_msi_irq_chip = {
170 .name = "PCI-MSI",
280510f1
TG		 171 .irq_enable = pci_msi_unmask_irq,
172 .irq_disable = pci_msi_mask_irq,
173 .irq_mask = pci_msi_mask_irq,
174 .irq_unmask = pci_msi_unmask_irq,
f342d940
JH		 175};
176
177/* MSI int handler */
7f4f16ee 178irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
f342d940
JH		 179{
180 unsigned long val;
904d0e78 181 int i, pos, irq;
7f4f16ee 182 irqreturn_t ret = IRQ_NONE;
f342d940
JH		 183
184 for (i = 0; i < MAX_MSI_CTRLS; i++) {
185 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
186 (u32 *)&val);
187 if (val) {
7f4f16ee 188 ret = IRQ_HANDLED;
f342d940
JH		 189 pos = 0;
190 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
904d0e78
PA		 191 irq = irq_find_mapping(pp->irq_domain,
192 i * 32 + pos);
ca165892
HH		 193 dw_pcie_wr_own_conf(pp,
194 PCIE_MSI_INTR0_STATUS + i * 12,
195 4, 1 << pos);
904d0e78 196 generic_handle_irq(irq);
f342d940
JH		 197 pos++;
198 }
199 }
f342d940 200 }
7f4f16ee
LS		 201
202 return ret;
f342d940
JH		 203}
204
205void dw_pcie_msi_init(struct pcie_port *pp)
206{
c8947fbb
LS		 207 u64 msi_target;
208
f342d940 209 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
c8947fbb 210 msi_target = virt_to_phys((void *)pp->msi_data);
f342d940
JH		 211
212 /* program the msi_data */
213 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
c8947fbb
LS		 214 (u32)(msi_target & 0xffffffff));
215 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
216 (u32)(msi_target >> 32 & 0xffffffff));
f342d940
JH		 217}
218
2f37c5a8
MK		 219static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
220{
221 unsigned int res, bit, val;
222
223 res = (irq / 32) * 12;
224 bit = irq % 32;
225 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
226 val &= ~(1 << bit);
227 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
228}
229
be3f48cb 230static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
58275f2f 231 unsigned int nvec, unsigned int pos)
be3f48cb 232{
2f37c5a8 233 unsigned int i;
be3f48cb 234
0b8cfb6a 235 for (i = 0; i < nvec; i++) {
be3f48cb 236 irq_set_msi_desc_off(irq_base, i, NULL);
58275f2f 237 /* Disable corresponding interrupt on MSI controller */
2f37c5a8
MK		 238 if (pp->ops->msi_clear_irq)
239 pp->ops->msi_clear_irq(pp, pos + i);
240 else
241 dw_pcie_msi_clear_irq(pp, pos + i);
be3f48cb 242 }
c8df6ac9
LS		 243
244 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
be3f48cb
BEN		 245}
246
2f37c5a8
MK		 247static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
248{
249 unsigned int res, bit, val;
250
251 res = (irq / 32) * 12;
252 bit = irq % 32;
253 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
254 val |= 1 << bit;
255 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
256}
257
f342d940
JH		 258static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
259{
c8df6ac9 260 int irq, pos0, i;
cbce7900 261 struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc);
f342d940 262
c8df6ac9
LS		 263 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
264 order_base_2(no_irqs));
265 if (pos0 < 0)
266 goto no_valid_irq;
f342d940 267
904d0e78
PA		 268 irq = irq_find_mapping(pp->irq_domain, pos0);
269 if (!irq)
f342d940
JH		 270 goto no_valid_irq;
271
be3f48cb
BEN		 272 /*
273 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
274 * descs so there is no need to allocate descs here. We can therefore
275 * assume that if irq_find_mapping above returns non-zero, then the
276 * descs are also successfully allocated.
277 */
278
0b8cfb6a 279 for (i = 0; i < no_irqs; i++) {
be3f48cb
BEN		 280 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
281 clear_irq_range(pp, irq, i, pos0);
282 goto no_valid_irq;
283 }
f342d940 284 /*Enable corresponding interrupt in MSI interrupt controller */
2f37c5a8
MK		 285 if (pp->ops->msi_set_irq)
286 pp->ops->msi_set_irq(pp, pos0 + i);
287 else
288 dw_pcie_msi_set_irq(pp, pos0 + i);
f342d940
JH		 289 }
290
291 *pos = pos0;
79707374
LS		 292 desc->nvec_used = no_irqs;
293 desc->msi_attrib.multiple = order_base_2(no_irqs);
294
f342d940
JH		 295 return irq;
296
297no_valid_irq:
298 *pos = pos0;
299 return -ENOSPC;
300}
301
ea643e1a 302static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
f342d940 303{
f342d940 304 struct msi_msg msg;
c8947fbb 305 u64 msi_target;
f342d940 306
450e344e 307 if (pp->ops->get_msi_addr)
c8947fbb 308 msi_target = pp->ops->get_msi_addr(pp);
2f37c5a8 309 else
c8947fbb
LS		 310 msi_target = virt_to_phys((void *)pp->msi_data);
311
312 msg.address_lo = (u32)(msi_target & 0xffffffff);
313 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
24832b4d
ML		 314
315 if (pp->ops->get_msi_data)
316 msg.data = pp->ops->get_msi_data(pp, pos);
317 else
318 msg.data = pos;
319
83a18912 320 pci_write_msi_msg(irq, &msg);
ea643e1a
LS		 321}
322
323static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
324 struct msi_desc *desc)
325{
326 int irq, pos;
cbce7900 327 struct pcie_port *pp = pdev->bus->sysdata;
ea643e1a
LS		 328
329 if (desc->msi_attrib.is_msix)
330 return -EINVAL;
331
332 irq = assign_irq(1, desc, &pos);
333 if (irq < 0)
334 return irq;
335
336 dw_msi_setup_msg(pp, irq, pos);
f342d940
JH		 337
338 return 0;
339}
340
79707374
LS		 341static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
342 int nvec, int type)
343{
344#ifdef CONFIG_PCI_MSI
345 int irq, pos;
346 struct msi_desc *desc;
cbce7900 347 struct pcie_port *pp = pdev->bus->sysdata;
79707374
LS		 348
349 /* MSI-X interrupts are not supported */
350 if (type == PCI_CAP_ID_MSIX)
351 return -EINVAL;
352
353 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
354 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
355
356 irq = assign_irq(nvec, desc, &pos);
357 if (irq < 0)
358 return irq;
359
360 dw_msi_setup_msg(pp, irq, pos);
361
362 return 0;
363#else
364 return -EINVAL;
365#endif
366}
367
c2791b80 368static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
f342d940 369{
91f8ae82 370 struct irq_data *data = irq_get_irq_data(irq);
c391f262 371 struct msi_desc *msi = irq_data_get_msi_desc(data);
cbce7900 372 struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
91f8ae82
LS		 373
374 clear_irq_range(pp, irq, 1, data->hwirq);
f342d940
JH		 375}
376
c2791b80 377static struct msi_controller dw_pcie_msi_chip = {
f342d940 378 .setup_irq = dw_msi_setup_irq,
79707374 379 .setup_irqs = dw_msi_setup_irqs,
f342d940
JH		 380 .teardown_irq = dw_msi_teardown_irq,
381};
382
4b1ced84
JH		 383int dw_pcie_link_up(struct pcie_port *pp)
384{
385 if (pp->ops->link_up)
386 return pp->ops->link_up(pp);
116a489d
BH		 387
388 return 0;
4b1ced84
JH		 389}
390
f342d940
JH		 391static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
392 irq_hw_number_t hwirq)
393{
394 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
395 irq_set_chip_data(irq, domain->host_data);
f342d940
JH		 396
397 return 0;
398}
399
400static const struct irq_domain_ops msi_domain_ops = {
401 .map = dw_pcie_msi_map,
402};
403
a43f32d6 404int dw_pcie_host_init(struct pcie_port *pp)
4b1ced84
JH		 405{
406 struct device_node *np = pp->dev->of_node;
4dd964df 407 struct platform_device *pdev = to_platform_device(pp->dev);
cbce7900 408 struct pci_bus *bus, *child;
4dd964df 409 struct resource *cfg_res;
9cdce1cd
ZW		 410 u32 val;
411 int i, ret;
0021d22b
ZW		 412 LIST_HEAD(res);
413 struct resource_entry *win;
f342d940 414
4dd964df
KVA		 415 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
416 if (cfg_res) {
adf70fc0
PA		 417 pp->cfg0_size = resource_size(cfg_res)/2;
418 pp->cfg1_size = resource_size(cfg_res)/2;
4dd964df 419 pp->cfg0_base = cfg_res->start;
adf70fc0 420 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
0f414212 421 } else if (!pp->va_cfg0_base) {
4dd964df
KVA		 422 dev_err(pp->dev, "missing *config* reg space\n");
423 }
424
0021d22b
ZW		 425 ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
426 if (ret)
427 return ret;
4b1ced84
JH		 428
429 /* Get the I/O and memory ranges from DT */
0021d22b
ZW		 430 resource_list_for_each_entry(win, &res) {
431 switch (resource_type(win->res)) {
432 case IORESOURCE_IO:
433 pp->io = win->res;
434 pp->io->name = "I/O";
435 pp->io_size = resource_size(pp->io);
436 pp->io_bus_addr = pp->io->start - win->offset;
cbce7900
ZW		 437 ret = pci_remap_iospace(pp->io, pp->io_base);
438 if (ret) {
439 dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
440 ret, pp->io);
441 continue;
442 }
0021d22b
ZW		 443 break;
444 case IORESOURCE_MEM:
445 pp->mem = win->res;
446 pp->mem->name = "MEM";
447 pp->mem_size = resource_size(pp->mem);
448 pp->mem_bus_addr = pp->mem->start - win->offset;
449 break;
450 case 0:
451 pp->cfg = win->res;
452 pp->cfg0_size = resource_size(pp->cfg)/2;
453 pp->cfg1_size = resource_size(pp->cfg)/2;
454 pp->cfg0_base = pp->cfg->start;
455 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
456 break;
457 case IORESOURCE_BUS:
458 pp->busn = win->res;
459 break;
460 default:
461 continue;
4b1ced84 462 }
4f2ebe00
LS		 463 }
464
4b1ced84 465 if (!pp->dbi_base) {
0021d22b
ZW		 466 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
467 resource_size(pp->cfg));
4b1ced84
JH		 468 if (!pp->dbi_base) {
469 dev_err(pp->dev, "error with ioremap\n");
470 return -ENOMEM;
471 }
472 }
473
0021d22b 474 pp->mem_base = pp->mem->start;
4b1ced84 475
4b1ced84 476 if (!pp->va_cfg0_base) {
b14a3d17 477 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
adf70fc0 478 pp->cfg0_size);
b14a3d17
MK		 479 if (!pp->va_cfg0_base) {
480 dev_err(pp->dev, "error with ioremap in function\n");
481 return -ENOMEM;
482 }
4b1ced84 483 }
b14a3d17 484
4b1ced84 485 if (!pp->va_cfg1_base) {
b14a3d17 486 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
adf70fc0 487 pp->cfg1_size);
b14a3d17
MK		 488 if (!pp->va_cfg1_base) {
489 dev_err(pp->dev, "error with ioremap\n");
490 return -ENOMEM;
491 }
4b1ced84
JH		 492 }
493
907fce09
GP		 494 ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
495 if (ret)
496 pp->lanes = 0;
4b1ced84 497
f342d940 498 if (IS_ENABLED(CONFIG_PCI_MSI)) {
b14a3d17
MK		 499 if (!pp->ops->msi_host_init) {
500 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
501 MAX_MSI_IRQS, &msi_domain_ops,
502 &dw_pcie_msi_chip);
503 if (!pp->irq_domain) {
504 dev_err(pp->dev, "irq domain init failed\n");
505 return -ENXIO;
506 }
f342d940 507
b14a3d17
MK		 508 for (i = 0; i < MAX_MSI_IRQS; i++)
509 irq_create_mapping(pp->irq_domain, i);
510 } else {
511 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
512 if (ret < 0)
513 return ret;
514 }
f342d940
JH		 515 }
516
4b1ced84
JH		 517 if (pp->ops->host_init)
518 pp->ops->host_init(pp);
519
2d91b491
JZ		 520 if (!pp->ops->rd_other_conf)
521 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
9cdce1cd 522 PCIE_ATU_TYPE_MEM, pp->mem_base,
2d91b491
JZ		 523 pp->mem_bus_addr, pp->mem_size);
524
4b1ced84
JH		 525 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
526
527 /* program correct class for RC */
528 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
529
530 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
531 val |= PORT_LOGIC_SPEED_CHANGE;
532 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
533
cbce7900
ZW		 534 pp->root_bus_nr = pp->busn->start;
535 if (IS_ENABLED(CONFIG_PCI_MSI)) {
536 bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
537 &dw_pcie_ops, pp, &res,
538 &dw_pcie_msi_chip);
539 dw_pcie_msi_chip.dev = pp->dev;
540 } else
541 bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
542 pp, &res);
543 if (!bus)
544 return -ENOMEM;
545
546 if (pp->ops->scan_bus)
547 pp->ops->scan_bus(pp);
548
549#ifdef CONFIG_ARM
550 /* support old dtbs that incorrectly describe IRQs */
551 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
0815f957
YW		 552#endif
553
cbce7900
ZW		 554 if (!pci_has_flag(PCI_PROBE_ONLY)) {
555 pci_bus_size_bridges(bus);
556 pci_bus_assign_resources(bus);
4b1ced84 557
cbce7900
ZW		 558 list_for_each_entry(child, &bus->children, node)
559 pcie_bus_configure_settings(child);
560 }
4b1ced84 561
cbce7900 562 pci_bus_add_devices(bus);
4b1ced84
JH		 563 return 0;
564}
565
4b1ced84 566static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 567 u32 devfn, int where, int size, u32 *val)
568{
2d91b491 569 int ret, type;
4c45852f 570 u32 busdev, cfg_size;
2d91b491
JZ		 571 u64 cpu_addr;
572 void __iomem *va_cfg_base;
340cba60 573
67de2dc3
BH		 574 if (pp->ops->rd_other_conf)
575 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
576
340cba60
JH		 577 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
578 PCIE_ATU_FUNC(PCI_FUNC(devfn));
340cba60
JH		 579
580 if (bus->parent->number == pp->root_bus_nr) {
2d91b491 581 type = PCIE_ATU_TYPE_CFG0;
9cdce1cd 582 cpu_addr = pp->cfg0_base;
2d91b491
JZ		 583 cfg_size = pp->cfg0_size;
584 va_cfg_base = pp->va_cfg0_base;
340cba60 585 } else {
2d91b491 586 type = PCIE_ATU_TYPE_CFG1;
9cdce1cd 587 cpu_addr = pp->cfg1_base;
2d91b491
JZ		 588 cfg_size = pp->cfg1_size;
589 va_cfg_base = pp->va_cfg1_base;
340cba60
JH		 590 }
591
2d91b491
JZ		 592 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
593 type, cpu_addr,
594 busdev, cfg_size);
4c45852f 595 ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
2d91b491 596 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
9cdce1cd 597 PCIE_ATU_TYPE_IO, pp->io_base,
2d91b491
JZ		 598 pp->io_bus_addr, pp->io_size);
599
340cba60
JH		 600 return ret;
601}
602
4b1ced84 603static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 604 u32 devfn, int where, int size, u32 val)
605{
2d91b491 606 int ret, type;
4c45852f 607 u32 busdev, cfg_size;
2d91b491
JZ		 608 u64 cpu_addr;
609 void __iomem *va_cfg_base;
340cba60 610
67de2dc3
BH		 611 if (pp->ops->wr_other_conf)
612 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
613
340cba60
JH		 614 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
615 PCIE_ATU_FUNC(PCI_FUNC(devfn));
340cba60
JH		 616
617 if (bus->parent->number == pp->root_bus_nr) {
2d91b491 618 type = PCIE_ATU_TYPE_CFG0;
9cdce1cd 619 cpu_addr = pp->cfg0_base;
2d91b491
JZ		 620 cfg_size = pp->cfg0_size;
621 va_cfg_base = pp->va_cfg0_base;
340cba60 622 } else {
2d91b491 623 type = PCIE_ATU_TYPE_CFG1;
9cdce1cd 624 cpu_addr = pp->cfg1_base;
2d91b491
JZ		 625 cfg_size = pp->cfg1_size;
626 va_cfg_base = pp->va_cfg1_base;
340cba60
JH		 627 }
628
2d91b491
JZ		 629 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
630 type, cpu_addr,
631 busdev, cfg_size);
4c45852f 632 ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
2d91b491 633 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
9cdce1cd 634 PCIE_ATU_TYPE_IO, pp->io_base,
2d91b491
JZ		 635 pp->io_bus_addr, pp->io_size);
636
340cba60
JH		 637 return ret;
638}
639
4b1ced84 640static int dw_pcie_valid_config(struct pcie_port *pp,
340cba60
JH		 641 struct pci_bus *bus, int dev)
642{
643 /* If there is no link, then there is no device */
644 if (bus->number != pp->root_bus_nr) {
4b1ced84 645 if (!dw_pcie_link_up(pp))
340cba60
JH		 646 return 0;
647 }
648
649 /* access only one slot on each root port */
650 if (bus->number == pp->root_bus_nr && dev > 0)
651 return 0;
652
653 /*
654 * do not read more than one device on the bus directly attached
655 * to RC's (Virtual Bridge's) DS side.
656 */
657 if (bus->primary == pp->root_bus_nr && dev > 0)
658 return 0;
659
660 return 1;
661}
662
4b1ced84 663static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
340cba60
JH		 664 int size, u32 *val)
665{
cbce7900 666 struct pcie_port *pp = bus->sysdata;
340cba60 667
4b1ced84 668 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
340cba60
JH		 669 *val = 0xffffffff;
670 return PCIBIOS_DEVICE_NOT_FOUND;
671 }
672
116a489d
BH		 673 if (bus->number == pp->root_bus_nr)
674 return dw_pcie_rd_own_conf(pp, where, size, val);
340cba60 675
116a489d 676 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
340cba60
JH		 677}
678
4b1ced84 679static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
340cba60
JH		 680 int where, int size, u32 val)
681{
cbce7900 682 struct pcie_port *pp = bus->sysdata;
340cba60 683
4b1ced84 684 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
340cba60
JH		 685 return PCIBIOS_DEVICE_NOT_FOUND;
686
116a489d
BH		 687 if (bus->number == pp->root_bus_nr)
688 return dw_pcie_wr_own_conf(pp, where, size, val);
340cba60 689
116a489d 690 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
340cba60
JH		 691}
692
4b1ced84
JH		 693static struct pci_ops dw_pcie_ops = {
694 .read = dw_pcie_rd_conf,
695 .write = dw_pcie_wr_conf,
340cba60
JH		 696};
697
4b1ced84 698void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60 699{
340cba60
JH		 700 u32 val;
701 u32 membase;
702 u32 memlimit;
703
66c5c34b 704 /* set the number of lanes */
f7b7868c 705 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
340cba60 706 val &= ~PORT_LINK_MODE_MASK;
4b1ced84
JH		 707 switch (pp->lanes) {
708 case 1:
709 val |= PORT_LINK_MODE_1_LANES;
710 break;
711 case 2:
712 val |= PORT_LINK_MODE_2_LANES;
713 break;
714 case 4:
715 val |= PORT_LINK_MODE_4_LANES;
716 break;
5b0f0738
ZW		 717 case 8:
718 val |= PORT_LINK_MODE_8_LANES;
719 break;
907fce09
GP		 720 default:
721 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
722 return;
4b1ced84 723 }
f7b7868c 724 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
340cba60
JH		 725
726 /* set link width speed control register */
f7b7868c 727 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
340cba60 728 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
4b1ced84
JH		 729 switch (pp->lanes) {
730 case 1:
731 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
732 break;
733 case 2:
734 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
735 break;
736 case 4:
737 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
738 break;
5b0f0738
ZW		 739 case 8:
740 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
741 break;
4b1ced84 742 }
f7b7868c 743 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60
JH		 744
745 /* setup RC BARs */
f7b7868c 746 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
dbffdd68 747 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
340cba60
JH		 748
749 /* setup interrupt pins */
f7b7868c 750 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
340cba60
JH		 751 val &= 0xffff00ff;
752 val |= 0x00000100;
f7b7868c 753 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
340cba60
JH		 754
755 /* setup bus numbers */
f7b7868c 756 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
340cba60
JH		 757 val &= 0xff000000;
758 val |= 0x00010100;
f7b7868c 759 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
340cba60
JH		 760
761 /* setup memory base, memory limit */
762 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
adf70fc0 763 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
340cba60 764 val = memlimit | membase;
f7b7868c 765 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
340cba60
JH		 766
767 /* setup command register */
f7b7868c 768 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
340cba60
JH		 769 val &= 0xffff0000;
770 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
771 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
f7b7868c 772 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
340cba60 773}
340cba60
JH		 774
775MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
4b1ced84 776MODULE_DESCRIPTION("Designware PCIe host controller driver");
340cba60 777MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.185964 seconds and 5 git commands to generate.