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PCI/MSI: Rename mask/unmask_msi_irq treewide
[deliverable/linux.git] / drivers / pci / host / pcie-designware.c
CommitLineData
340cba60 1/*
4b1ced84 2 * Synopsys Designware PCIe host controller driver
340cba60
JH		 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
f342d940
JH		 14#include <linux/irq.h>
15#include <linux/irqdomain.h>
340cba60 16#include <linux/kernel.h>
340cba60 17#include <linux/module.h>
f342d940 18#include <linux/msi.h>
340cba60 19#include <linux/of_address.h>
804f57b1 20#include <linux/of_pci.h>
340cba60
JH		 21#include <linux/pci.h>
22#include <linux/pci_regs.h>
4dd964df 23#include <linux/platform_device.h>
340cba60
JH		 24#include <linux/types.h>
25
4b1ced84 26#include "pcie-designware.h"
340cba60
JH		 27
28/* Synopsis specific PCIE configuration registers */
29#define PCIE_PORT_LINK_CONTROL 0x710
30#define PORT_LINK_MODE_MASK (0x3f << 16)
4b1ced84
JH		 31#define PORT_LINK_MODE_1_LANES (0x1 << 16)
32#define PORT_LINK_MODE_2_LANES (0x3 << 16)
340cba60
JH		 33#define PORT_LINK_MODE_4_LANES (0x7 << 16)
34
35#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
4b1ced84
JH		 38#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
340cba60
JH		 41
42#define PCIE_MSI_ADDR_LO 0x820
43#define PCIE_MSI_ADDR_HI 0x824
44#define PCIE_MSI_INTR0_ENABLE 0x828
45#define PCIE_MSI_INTR0_MASK 0x82C
46#define PCIE_MSI_INTR0_STATUS 0x830
47
48#define PCIE_ATU_VIEWPORT 0x900
49#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53#define PCIE_ATU_CR1 0x904
54#define PCIE_ATU_TYPE_MEM (0x0 << 0)
55#define PCIE_ATU_TYPE_IO (0x2 << 0)
56#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58#define PCIE_ATU_CR2 0x908
59#define PCIE_ATU_ENABLE (0x1 << 31)
60#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61#define PCIE_ATU_LOWER_BASE 0x90C
62#define PCIE_ATU_UPPER_BASE 0x910
63#define PCIE_ATU_LIMIT 0x914
64#define PCIE_ATU_LOWER_TARGET 0x918
65#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68#define PCIE_ATU_UPPER_TARGET 0x91C
69
4b1ced84
JH		 70static struct hw_pci dw_pci;
71
73e40850 72static unsigned long global_io_offset;
340cba60
JH		 73
74static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75{
84a263f3
LS		 76 BUG_ON(!sys->private_data);
77
340cba60
JH		 78 return sys->private_data;
79}
80
a01ef59e 81int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
340cba60
JH		 82{
83 *val = readl(addr);
84
85 if (size == 1)
86 *val = (*val >> (8 * (where & 3))) & 0xff;
87 else if (size == 2)
88 *val = (*val >> (8 * (where & 3))) & 0xffff;
89 else if (size != 4)
90 return PCIBIOS_BAD_REGISTER_NUMBER;
91
92 return PCIBIOS_SUCCESSFUL;
93}
94
a01ef59e 95int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
340cba60
JH		 96{
97 if (size == 4)
98 writel(val, addr);
99 else if (size == 2)
100 writew(val, addr + (where & 2));
101 else if (size == 1)
102 writeb(val, addr + (where & 3));
103 else
104 return PCIBIOS_BAD_REGISTER_NUMBER;
105
106 return PCIBIOS_SUCCESSFUL;
107}
108
f7b7868c 109static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
340cba60 110{
4b1ced84 111 if (pp->ops->readl_rc)
f7b7868c 112 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
4b1ced84 113 else
f7b7868c 114 *val = readl(pp->dbi_base + reg);
340cba60
JH		 115}
116
f7b7868c 117static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
340cba60 118{
4b1ced84 119 if (pp->ops->writel_rc)
f7b7868c 120 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
4b1ced84 121 else
f7b7868c 122 writel(val, pp->dbi_base + reg);
340cba60
JH		 123}
124
73e40850
BH		 125static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
126 u32 *val)
340cba60
JH		 127{
128 int ret;
129
4b1ced84
JH		 130 if (pp->ops->rd_own_conf)
131 ret = pp->ops->rd_own_conf(pp, where, size, val);
132 else
a01ef59e
PA		 133 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
134 size, val);
4b1ced84 135
340cba60
JH		 136 return ret;
137}
138
73e40850
BH		 139static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
140 u32 val)
340cba60
JH		 141{
142 int ret;
143
4b1ced84
JH		 144 if (pp->ops->wr_own_conf)
145 ret = pp->ops->wr_own_conf(pp, where, size, val);
146 else
a01ef59e
PA		 147 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
148 size, val);
4b1ced84 149
340cba60
JH		 150 return ret;
151}
152
f342d940
JH		 153static struct irq_chip dw_msi_irq_chip = {
154 .name = "PCI-MSI",
280510f1
TG		 155 .irq_enable = pci_msi_unmask_irq,
156 .irq_disable = pci_msi_mask_irq,
157 .irq_mask = pci_msi_mask_irq,
158 .irq_unmask = pci_msi_unmask_irq,
f342d940
JH		 159};
160
161/* MSI int handler */
7f4f16ee 162irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
f342d940
JH		 163{
164 unsigned long val;
904d0e78 165 int i, pos, irq;
7f4f16ee 166 irqreturn_t ret = IRQ_NONE;
f342d940
JH		 167
168 for (i = 0; i < MAX_MSI_CTRLS; i++) {
169 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
170 (u32 *)&val);
171 if (val) {
7f4f16ee 172 ret = IRQ_HANDLED;
f342d940
JH		 173 pos = 0;
174 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
904d0e78
PA		 175 irq = irq_find_mapping(pp->irq_domain,
176 i * 32 + pos);
ca165892
HH		 177 dw_pcie_wr_own_conf(pp,
178 PCIE_MSI_INTR0_STATUS + i * 12,
179 4, 1 << pos);
904d0e78 180 generic_handle_irq(irq);
f342d940
JH		 181 pos++;
182 }
183 }
f342d940 184 }
7f4f16ee
LS		 185
186 return ret;
f342d940
JH		 187}
188
189void dw_pcie_msi_init(struct pcie_port *pp)
190{
191 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
192
193 /* program the msi_data */
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
195 virt_to_phys((void *)pp->msi_data));
196 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
197}
198
2f37c5a8
MK		 199static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
200{
201 unsigned int res, bit, val;
202
203 res = (irq / 32) * 12;
204 bit = irq % 32;
205 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
206 val &= ~(1 << bit);
207 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
208}
209
be3f48cb 210static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
58275f2f 211 unsigned int nvec, unsigned int pos)
be3f48cb 212{
2f37c5a8 213 unsigned int i;
be3f48cb 214
0b8cfb6a 215 for (i = 0; i < nvec; i++) {
be3f48cb 216 irq_set_msi_desc_off(irq_base, i, NULL);
58275f2f 217 /* Disable corresponding interrupt on MSI controller */
2f37c5a8
MK		 218 if (pp->ops->msi_clear_irq)
219 pp->ops->msi_clear_irq(pp, pos + i);
220 else
221 dw_pcie_msi_clear_irq(pp, pos + i);
be3f48cb 222 }
c8df6ac9
LS		 223
224 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
be3f48cb
BEN		 225}
226
2f37c5a8
MK		 227static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
228{
229 unsigned int res, bit, val;
230
231 res = (irq / 32) * 12;
232 bit = irq % 32;
233 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
234 val |= 1 << bit;
235 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
236}
237
f342d940
JH		 238static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
239{
c8df6ac9 240 int irq, pos0, i;
f342d940
JH		 241 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
242
c8df6ac9
LS		 243 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
244 order_base_2(no_irqs));
245 if (pos0 < 0)
246 goto no_valid_irq;
f342d940 247
904d0e78
PA		 248 irq = irq_find_mapping(pp->irq_domain, pos0);
249 if (!irq)
f342d940
JH		 250 goto no_valid_irq;
251
be3f48cb
BEN		 252 /*
253 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
254 * descs so there is no need to allocate descs here. We can therefore
255 * assume that if irq_find_mapping above returns non-zero, then the
256 * descs are also successfully allocated.
257 */
258
0b8cfb6a 259 for (i = 0; i < no_irqs; i++) {
be3f48cb
BEN		 260 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
261 clear_irq_range(pp, irq, i, pos0);
262 goto no_valid_irq;
263 }
f342d940 264 /*Enable corresponding interrupt in MSI interrupt controller */
2f37c5a8
MK		 265 if (pp->ops->msi_set_irq)
266 pp->ops->msi_set_irq(pp, pos0 + i);
267 else
268 dw_pcie_msi_set_irq(pp, pos0 + i);
f342d940
JH		 269 }
270
271 *pos = pos0;
272 return irq;
273
274no_valid_irq:
275 *pos = pos0;
276 return -ENOSPC;
277}
278
c2791b80 279static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
f342d940
JH		 280 struct msi_desc *desc)
281{
91f8ae82 282 int irq, pos;
f342d940
JH		 283 struct msi_msg msg;
284 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
285
91f8ae82 286 irq = assign_irq(1, desc, &pos);
f342d940
JH		 287 if (irq < 0)
288 return irq;
289
450e344e
ML		 290 if (pp->ops->get_msi_addr)
291 msg.address_lo = pp->ops->get_msi_addr(pp);
2f37c5a8
MK		 292 else
293 msg.address_lo = virt_to_phys((void *)pp->msi_data);
f342d940 294 msg.address_hi = 0x0;
24832b4d
ML		 295
296 if (pp->ops->get_msi_data)
297 msg.data = pp->ops->get_msi_data(pp, pos);
298 else
299 msg.data = pos;
300
83a18912 301 pci_write_msi_msg(irq, &msg);
f342d940
JH		 302
303 return 0;
304}
305
c2791b80 306static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
f342d940 307{
91f8ae82
LS		 308 struct irq_data *data = irq_get_irq_data(irq);
309 struct msi_desc *msi = irq_data_get_msi(data);
310 struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
311
312 clear_irq_range(pp, irq, 1, data->hwirq);
f342d940
JH		 313}
314
c2791b80 315static struct msi_controller dw_pcie_msi_chip = {
f342d940
JH		 316 .setup_irq = dw_msi_setup_irq,
317 .teardown_irq = dw_msi_teardown_irq,
318};
319
4b1ced84
JH		 320int dw_pcie_link_up(struct pcie_port *pp)
321{
322 if (pp->ops->link_up)
323 return pp->ops->link_up(pp);
324 else
325 return 0;
326}
327
f342d940
JH		 328static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
329 irq_hw_number_t hwirq)
330{
331 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
332 irq_set_chip_data(irq, domain->host_data);
333 set_irq_flags(irq, IRQF_VALID);
334
335 return 0;
336}
337
338static const struct irq_domain_ops msi_domain_ops = {
339 .map = dw_pcie_msi_map,
340};
341
4b1ced84
JH		 342int __init dw_pcie_host_init(struct pcie_port *pp)
343{
344 struct device_node *np = pp->dev->of_node;
4dd964df 345 struct platform_device *pdev = to_platform_device(pp->dev);
4b1ced84
JH		 346 struct of_pci_range range;
347 struct of_pci_range_parser parser;
4dd964df 348 struct resource *cfg_res;
f4c55c5a
KVA		 349 u32 val, na, ns;
350 const __be32 *addrp;
b14a3d17 351 int i, index, ret;
f4c55c5a
KVA		 352
353 /* Find the address cell size and the number of cells in order to get
354 * the untranslated address.
355 */
356 of_property_read_u32(np, "#address-cells", &na);
357 ns = of_n_size_cells(np);
f342d940 358
4dd964df
KVA		 359 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
360 if (cfg_res) {
adf70fc0
PA		 361 pp->cfg0_size = resource_size(cfg_res)/2;
362 pp->cfg1_size = resource_size(cfg_res)/2;
4dd964df 363 pp->cfg0_base = cfg_res->start;
adf70fc0 364 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
f4c55c5a
KVA		 365
366 /* Find the untranslated configuration space address */
367 index = of_property_match_string(np, "reg-names", "config");
9f0dbe08 368 addrp = of_get_address(np, index, NULL, NULL);
f4c55c5a 369 pp->cfg0_mod_base = of_read_number(addrp, ns);
adf70fc0 370 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
4dd964df
KVA		 371 } else {
372 dev_err(pp->dev, "missing *config* reg space\n");
373 }
374
4b1ced84
JH		 375 if (of_pci_range_parser_init(&parser, np)) {
376 dev_err(pp->dev, "missing ranges property\n");
377 return -EINVAL;
378 }
379
380 /* Get the I/O and memory ranges from DT */
381 for_each_of_pci_range(&parser, &range) {
382 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
383 if (restype == IORESOURCE_IO) {
384 of_pci_range_to_resource(&range, np, &pp->io);
385 pp->io.name = "I/O";
386 pp->io.start = max_t(resource_size_t,
387 PCIBIOS_MIN_IO,
388 range.pci_addr + global_io_offset);
389 pp->io.end = min_t(resource_size_t,
390 IO_SPACE_LIMIT,
391 range.pci_addr + range.size
0c61ea77 392 + global_io_offset - 1);
adf70fc0
PA		 393 pp->io_size = resource_size(&pp->io);
394 pp->io_bus_addr = range.pci_addr;
fce8591f 395 pp->io_base = range.cpu_addr;
f4c55c5a
KVA		 396
397 /* Find the untranslated IO space address */
398 pp->io_mod_base = of_read_number(parser.range -
399 parser.np + na, ns);
4b1ced84
JH		 400 }
401 if (restype == IORESOURCE_MEM) {
402 of_pci_range_to_resource(&range, np, &pp->mem);
403 pp->mem.name = "MEM";
adf70fc0
PA		 404 pp->mem_size = resource_size(&pp->mem);
405 pp->mem_bus_addr = range.pci_addr;
f4c55c5a
KVA		 406
407 /* Find the untranslated MEM space address */
408 pp->mem_mod_base = of_read_number(parser.range -
409 parser.np + na, ns);
4b1ced84
JH		 410 }
411 if (restype == 0) {
412 of_pci_range_to_resource(&range, np, &pp->cfg);
adf70fc0
PA		 413 pp->cfg0_size = resource_size(&pp->cfg)/2;
414 pp->cfg1_size = resource_size(&pp->cfg)/2;
4dd964df 415 pp->cfg0_base = pp->cfg.start;
adf70fc0 416 pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
f4c55c5a
KVA		 417
418 /* Find the untranslated configuration space address */
419 pp->cfg0_mod_base = of_read_number(parser.range -
420 parser.np + na, ns);
421 pp->cfg1_mod_base = pp->cfg0_mod_base +
adf70fc0 422 pp->cfg0_size;
4b1ced84
JH		 423 }
424 }
425
4f2ebe00
LS		 426 ret = of_pci_parse_bus_range(np, &pp->busn);
427 if (ret < 0) {
428 pp->busn.name = np->name;
429 pp->busn.start = 0;
430 pp->busn.end = 0xff;
431 pp->busn.flags = IORESOURCE_BUS;
432 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
433 ret, &pp->busn);
434 }
435
4b1ced84
JH		 436 if (!pp->dbi_base) {
437 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
438 resource_size(&pp->cfg));
439 if (!pp->dbi_base) {
440 dev_err(pp->dev, "error with ioremap\n");
441 return -ENOMEM;
442 }
443 }
444
4b1ced84
JH		 445 pp->mem_base = pp->mem.start;
446
4b1ced84 447 if (!pp->va_cfg0_base) {
b14a3d17 448 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
adf70fc0 449 pp->cfg0_size);
b14a3d17
MK		 450 if (!pp->va_cfg0_base) {
451 dev_err(pp->dev, "error with ioremap in function\n");
452 return -ENOMEM;
453 }
4b1ced84 454 }
b14a3d17 455
4b1ced84 456 if (!pp->va_cfg1_base) {
b14a3d17 457 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
adf70fc0 458 pp->cfg1_size);
b14a3d17
MK		 459 if (!pp->va_cfg1_base) {
460 dev_err(pp->dev, "error with ioremap\n");
461 return -ENOMEM;
462 }
4b1ced84
JH		 463 }
464
465 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
466 dev_err(pp->dev, "Failed to parse the number of lanes\n");
467 return -EINVAL;
468 }
469
f342d940 470 if (IS_ENABLED(CONFIG_PCI_MSI)) {
b14a3d17
MK		 471 if (!pp->ops->msi_host_init) {
472 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
473 MAX_MSI_IRQS, &msi_domain_ops,
474 &dw_pcie_msi_chip);
475 if (!pp->irq_domain) {
476 dev_err(pp->dev, "irq domain init failed\n");
477 return -ENXIO;
478 }
f342d940 479
b14a3d17
MK		 480 for (i = 0; i < MAX_MSI_IRQS; i++)
481 irq_create_mapping(pp->irq_domain, i);
482 } else {
483 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
484 if (ret < 0)
485 return ret;
486 }
f342d940
JH		 487 }
488
4b1ced84
JH		 489 if (pp->ops->host_init)
490 pp->ops->host_init(pp);
491
492 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
493
494 /* program correct class for RC */
495 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
496
497 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
498 val |= PORT_LOGIC_SPEED_CHANGE;
499 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
500
0815f957
YW		 501#ifdef CONFIG_PCI_MSI
502 dw_pcie_msi_chip.dev = pp->dev;
503 dw_pci.msi_ctrl = &dw_pcie_msi_chip;
504#endif
505
4b1ced84
JH		 506 dw_pci.nr_controllers = 1;
507 dw_pci.private_data = (void **)&pp;
508
804f57b1 509 pci_common_init_dev(pp->dev, &dw_pci);
4b1ced84
JH		 510#ifdef CONFIG_PCI_DOMAINS
511 dw_pci.domain++;
512#endif
513
514 return 0;
515}
516
517static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
340cba60 518{
340cba60 519 /* Program viewport 0 : OUTBOUND : CFG0 */
f7b7868c
SJ		 520 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
521 PCIE_ATU_VIEWPORT);
f4c55c5a
KVA		 522 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
523 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
adf70fc0 524 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
f7b7868c
SJ		 525 PCIE_ATU_LIMIT);
526 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
527 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
528 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
529 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 530}
531
4b1ced84 532static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
340cba60 533{
340cba60 534 /* Program viewport 1 : OUTBOUND : CFG1 */
f7b7868c
SJ		 535 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
536 PCIE_ATU_VIEWPORT);
537 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
f4c55c5a
KVA		 538 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
539 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
adf70fc0 540 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
f7b7868c
SJ		 541 PCIE_ATU_LIMIT);
542 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
543 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
a19f88bd 544 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 545}
546
4b1ced84 547static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
340cba60 548{
340cba60 549 /* Program viewport 0 : OUTBOUND : MEM */
f7b7868c
SJ		 550 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
551 PCIE_ATU_VIEWPORT);
552 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
f4c55c5a
KVA		 553 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
554 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
adf70fc0 555 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
f7b7868c 556 PCIE_ATU_LIMIT);
adf70fc0
PA		 557 dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
558 dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
f7b7868c 559 PCIE_ATU_UPPER_TARGET);
a19f88bd 560 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 561}
562
4b1ced84 563static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
340cba60 564{
340cba60 565 /* Program viewport 1 : OUTBOUND : IO */
f7b7868c
SJ		 566 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
567 PCIE_ATU_VIEWPORT);
568 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
f4c55c5a
KVA		 569 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
570 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
adf70fc0 571 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
f7b7868c 572 PCIE_ATU_LIMIT);
adf70fc0
PA		 573 dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
574 dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
f7b7868c 575 PCIE_ATU_UPPER_TARGET);
a19f88bd 576 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 577}
578
4b1ced84 579static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 580 u32 devfn, int where, int size, u32 *val)
581{
582 int ret = PCIBIOS_SUCCESSFUL;
583 u32 address, busdev;
584
585 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
586 PCIE_ATU_FUNC(PCI_FUNC(devfn));
587 address = where & ~0x3;
588
589 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 590 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 591 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
592 val);
4b1ced84 593 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 594 } else {
4b1ced84 595 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 596 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
597 val);
4b1ced84 598 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 599 }
600
601 return ret;
602}
603
4b1ced84 604static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 605 u32 devfn, int where, int size, u32 val)
606{
607 int ret = PCIBIOS_SUCCESSFUL;
608 u32 address, busdev;
609
610 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
611 PCIE_ATU_FUNC(PCI_FUNC(devfn));
612 address = where & ~0x3;
613
614 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 615 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 616 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
617 val);
4b1ced84 618 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 619 } else {
4b1ced84 620 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 621 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
622 val);
4b1ced84 623 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 624 }
625
626 return ret;
627}
628
4b1ced84 629static int dw_pcie_valid_config(struct pcie_port *pp,
340cba60
JH		 630 struct pci_bus *bus, int dev)
631{
632 /* If there is no link, then there is no device */
633 if (bus->number != pp->root_bus_nr) {
4b1ced84 634 if (!dw_pcie_link_up(pp))
340cba60
JH		 635 return 0;
636 }
637
638 /* access only one slot on each root port */
639 if (bus->number == pp->root_bus_nr && dev > 0)
640 return 0;
641
642 /*
643 * do not read more than one device on the bus directly attached
644 * to RC's (Virtual Bridge's) DS side.
645 */
646 if (bus->primary == pp->root_bus_nr && dev > 0)
647 return 0;
648
649 return 1;
650}
651
4b1ced84 652static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
340cba60
JH		 653 int size, u32 *val)
654{
655 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 656 int ret;
657
4b1ced84 658 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
340cba60
JH		 659 *val = 0xffffffff;
660 return PCIBIOS_DEVICE_NOT_FOUND;
661 }
662
340cba60 663 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 664 if (pp->ops->rd_other_conf)
665 ret = pp->ops->rd_other_conf(pp, bus, devfn,
666 where, size, val);
667 else
668 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
340cba60
JH		 669 where, size, val);
670 else
4b1ced84 671 ret = dw_pcie_rd_own_conf(pp, where, size, val);
340cba60
JH		 672
673 return ret;
674}
675
4b1ced84 676static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
340cba60
JH		 677 int where, int size, u32 val)
678{
679 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 680 int ret;
681
4b1ced84 682 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
340cba60
JH		 683 return PCIBIOS_DEVICE_NOT_FOUND;
684
340cba60 685 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 686 if (pp->ops->wr_other_conf)
687 ret = pp->ops->wr_other_conf(pp, bus, devfn,
688 where, size, val);
689 else
690 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
340cba60
JH		 691 where, size, val);
692 else
4b1ced84 693 ret = dw_pcie_wr_own_conf(pp, where, size, val);
340cba60
JH		 694
695 return ret;
696}
697
4b1ced84
JH		 698static struct pci_ops dw_pcie_ops = {
699 .read = dw_pcie_rd_conf,
700 .write = dw_pcie_wr_conf,
340cba60
JH		 701};
702
73e40850 703static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
4b1ced84
JH		 704{
705 struct pcie_port *pp;
706
707 pp = sys_to_pcie(sys);
708
adf70fc0
PA		 709 if (global_io_offset < SZ_1M && pp->io_size > 0) {
710 sys->io_offset = global_io_offset - pp->io_bus_addr;
fce8591f 711 pci_ioremap_io(global_io_offset, pp->io_base);
4b1ced84
JH		 712 global_io_offset += SZ_64K;
713 pci_add_resource_offset(&sys->resources, &pp->io,
714 sys->io_offset);
715 }
716
adf70fc0 717 sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
4b1ced84 718 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
4f2ebe00 719 pci_add_resource(&sys->resources, &pp->busn);
4b1ced84
JH		 720
721 return 1;
722}
723
73e40850 724static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
340cba60
JH		 725{
726 struct pci_bus *bus;
727 struct pcie_port *pp = sys_to_pcie(sys);
728
92483df2
LS		 729 pp->root_bus_nr = sys->busnr;
730 bus = pci_create_root_bus(pp->dev, sys->busnr,
731 &dw_pcie_ops, sys, &sys->resources);
732 if (!bus)
733 return NULL;
734
735 pci_scan_child_bus(bus);
340cba60 736
b14a3d17
MK		 737 if (bus && pp->ops->scan_bus)
738 pp->ops->scan_bus(pp);
739
340cba60
JH		 740 return bus;
741}
742
73e40850 743static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
340cba60
JH		 744{
745 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
804f57b1 746 int irq;
340cba60 747
804f57b1
LS		 748 irq = of_irq_parse_and_map_pci(dev, slot, pin);
749 if (!irq)
750 irq = pp->irq;
340cba60 751
804f57b1 752 return irq;
340cba60
JH		 753}
754
4b1ced84
JH		 755static struct hw_pci dw_pci = {
756 .setup = dw_pcie_setup,
757 .scan = dw_pcie_scan_bus,
758 .map_irq = dw_pcie_map_irq,
340cba60
JH		 759};
760
4b1ced84 761void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60 762{
340cba60
JH		 763 u32 val;
764 u32 membase;
765 u32 memlimit;
766
66c5c34b 767 /* set the number of lanes */
f7b7868c 768 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
340cba60 769 val &= ~PORT_LINK_MODE_MASK;
4b1ced84
JH		 770 switch (pp->lanes) {
771 case 1:
772 val |= PORT_LINK_MODE_1_LANES;
773 break;
774 case 2:
775 val |= PORT_LINK_MODE_2_LANES;
776 break;
777 case 4:
778 val |= PORT_LINK_MODE_4_LANES;
779 break;
780 }
f7b7868c 781 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
340cba60
JH		 782
783 /* set link width speed control register */
f7b7868c 784 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
340cba60 785 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
4b1ced84
JH		 786 switch (pp->lanes) {
787 case 1:
788 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
789 break;
790 case 2:
791 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
792 break;
793 case 4:
794 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
795 break;
796 }
f7b7868c 797 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60
JH		 798
799 /* setup RC BARs */
f7b7868c 800 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
dbffdd68 801 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
340cba60
JH		 802
803 /* setup interrupt pins */
f7b7868c 804 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
340cba60
JH		 805 val &= 0xffff00ff;
806 val |= 0x00000100;
f7b7868c 807 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
340cba60
JH		 808
809 /* setup bus numbers */
f7b7868c 810 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
340cba60
JH		 811 val &= 0xff000000;
812 val |= 0x00010100;
f7b7868c 813 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
340cba60
JH		 814
815 /* setup memory base, memory limit */
816 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
adf70fc0 817 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
340cba60 818 val = memlimit | membase;
f7b7868c 819 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
340cba60
JH		 820
821 /* setup command register */
f7b7868c 822 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
340cba60
JH		 823 val &= 0xffff0000;
824 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
825 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
f7b7868c 826 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
340cba60 827}
340cba60
JH		 828
829MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
4b1ced84 830MODULE_DESCRIPTION("Designware PCIe host controller driver");
340cba60 831MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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