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PCI: designware: Add config access-related pcie_host_ops for v3.65 hardware
[deliverable/linux.git] / drivers / pci / host / pcie-designware.c
CommitLineData
340cba60 1/*
4b1ced84 2 * Synopsys Designware PCIe host controller driver
340cba60
JH		 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
f342d940
JH		 14#include <linux/irq.h>
15#include <linux/irqdomain.h>
340cba60 16#include <linux/kernel.h>
340cba60 17#include <linux/module.h>
f342d940 18#include <linux/msi.h>
340cba60 19#include <linux/of_address.h>
804f57b1 20#include <linux/of_pci.h>
340cba60
JH		 21#include <linux/pci.h>
22#include <linux/pci_regs.h>
4dd964df 23#include <linux/platform_device.h>
340cba60
JH		 24#include <linux/types.h>
25
4b1ced84 26#include "pcie-designware.h"
340cba60
JH		 27
28/* Synopsis specific PCIE configuration registers */
29#define PCIE_PORT_LINK_CONTROL 0x710
30#define PORT_LINK_MODE_MASK (0x3f << 16)
4b1ced84
JH		 31#define PORT_LINK_MODE_1_LANES (0x1 << 16)
32#define PORT_LINK_MODE_2_LANES (0x3 << 16)
340cba60
JH		 33#define PORT_LINK_MODE_4_LANES (0x7 << 16)
34
35#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
4b1ced84
JH		 38#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
340cba60
JH		 41
42#define PCIE_MSI_ADDR_LO 0x820
43#define PCIE_MSI_ADDR_HI 0x824
44#define PCIE_MSI_INTR0_ENABLE 0x828
45#define PCIE_MSI_INTR0_MASK 0x82C
46#define PCIE_MSI_INTR0_STATUS 0x830
47
48#define PCIE_ATU_VIEWPORT 0x900
49#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53#define PCIE_ATU_CR1 0x904
54#define PCIE_ATU_TYPE_MEM (0x0 << 0)
55#define PCIE_ATU_TYPE_IO (0x2 << 0)
56#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58#define PCIE_ATU_CR2 0x908
59#define PCIE_ATU_ENABLE (0x1 << 31)
60#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61#define PCIE_ATU_LOWER_BASE 0x90C
62#define PCIE_ATU_UPPER_BASE 0x910
63#define PCIE_ATU_LIMIT 0x914
64#define PCIE_ATU_LOWER_TARGET 0x918
65#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68#define PCIE_ATU_UPPER_TARGET 0x91C
69
4b1ced84
JH		 70static struct hw_pci dw_pci;
71
73e40850 72static unsigned long global_io_offset;
340cba60
JH		 73
74static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75{
76 return sys->private_data;
77}
78
a01ef59e 79int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
340cba60
JH		 80{
81 *val = readl(addr);
82
83 if (size == 1)
84 *val = (*val >> (8 * (where & 3))) & 0xff;
85 else if (size == 2)
86 *val = (*val >> (8 * (where & 3))) & 0xffff;
87 else if (size != 4)
88 return PCIBIOS_BAD_REGISTER_NUMBER;
89
90 return PCIBIOS_SUCCESSFUL;
91}
92
a01ef59e 93int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
340cba60
JH		 94{
95 if (size == 4)
96 writel(val, addr);
97 else if (size == 2)
98 writew(val, addr + (where & 2));
99 else if (size == 1)
100 writeb(val, addr + (where & 3));
101 else
102 return PCIBIOS_BAD_REGISTER_NUMBER;
103
104 return PCIBIOS_SUCCESSFUL;
105}
106
f7b7868c 107static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
340cba60 108{
4b1ced84 109 if (pp->ops->readl_rc)
f7b7868c 110 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
4b1ced84 111 else
f7b7868c 112 *val = readl(pp->dbi_base + reg);
340cba60
JH		 113}
114
f7b7868c 115static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
340cba60 116{
4b1ced84 117 if (pp->ops->writel_rc)
f7b7868c 118 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
4b1ced84 119 else
f7b7868c 120 writel(val, pp->dbi_base + reg);
340cba60
JH		 121}
122
73e40850
BH		 123static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
124 u32 *val)
340cba60
JH		 125{
126 int ret;
127
4b1ced84
JH		 128 if (pp->ops->rd_own_conf)
129 ret = pp->ops->rd_own_conf(pp, where, size, val);
130 else
a01ef59e
PA		 131 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
132 size, val);
4b1ced84 133
340cba60
JH		 134 return ret;
135}
136
73e40850
BH		 137static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
138 u32 val)
340cba60
JH		 139{
140 int ret;
141
4b1ced84
JH		 142 if (pp->ops->wr_own_conf)
143 ret = pp->ops->wr_own_conf(pp, where, size, val);
144 else
a01ef59e
PA		 145 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
146 size, val);
4b1ced84 147
340cba60
JH		 148 return ret;
149}
150
f342d940
JH		 151static struct irq_chip dw_msi_irq_chip = {
152 .name = "PCI-MSI",
153 .irq_enable = unmask_msi_irq,
154 .irq_disable = mask_msi_irq,
155 .irq_mask = mask_msi_irq,
156 .irq_unmask = unmask_msi_irq,
157};
158
159/* MSI int handler */
7f4f16ee 160irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
f342d940
JH		 161{
162 unsigned long val;
904d0e78 163 int i, pos, irq;
7f4f16ee 164 irqreturn_t ret = IRQ_NONE;
f342d940
JH		 165
166 for (i = 0; i < MAX_MSI_CTRLS; i++) {
167 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
168 (u32 *)&val);
169 if (val) {
7f4f16ee 170 ret = IRQ_HANDLED;
f342d940
JH		 171 pos = 0;
172 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
904d0e78
PA		 173 irq = irq_find_mapping(pp->irq_domain,
174 i * 32 + pos);
ca165892
HH		 175 dw_pcie_wr_own_conf(pp,
176 PCIE_MSI_INTR0_STATUS + i * 12,
177 4, 1 << pos);
904d0e78 178 generic_handle_irq(irq);
f342d940
JH		 179 pos++;
180 }
181 }
f342d940 182 }
7f4f16ee
LS		 183
184 return ret;
f342d940
JH		 185}
186
187void dw_pcie_msi_init(struct pcie_port *pp)
188{
189 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
190
191 /* program the msi_data */
192 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
193 virt_to_phys((void *)pp->msi_data));
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
195}
196
197static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
198{
199 int flag = 1;
200
201 do {
202 pos = find_next_zero_bit(pp->msi_irq_in_use,
203 MAX_MSI_IRQS, pos);
204 /*if you have reached to the end then get out from here.*/
205 if (pos == MAX_MSI_IRQS)
206 return -ENOSPC;
207 /*
208 * Check if this position is at correct offset.nvec is always a
f7625980 209 * power of two. pos0 must be nvec bit aligned.
f342d940
JH		 210 */
211 if (pos % msgvec)
212 pos += msgvec - (pos % msgvec);
213 else
214 flag = 0;
215 } while (flag);
216
217 *pos0 = pos;
218 return 0;
219}
220
be3f48cb 221static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
58275f2f 222 unsigned int nvec, unsigned int pos)
be3f48cb
BEN		 223{
224 unsigned int i, res, bit, val;
225
0b8cfb6a 226 for (i = 0; i < nvec; i++) {
be3f48cb
BEN		 227 irq_set_msi_desc_off(irq_base, i, NULL);
228 clear_bit(pos + i, pp->msi_irq_in_use);
58275f2f 229 /* Disable corresponding interrupt on MSI controller */
be3f48cb
BEN		 230 res = ((pos + i) / 32) * 12;
231 bit = (pos + i) % 32;
232 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
233 val &= ~(1 << bit);
234 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
be3f48cb
BEN		 235 }
236}
237
f342d940
JH		 238static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
239{
240 int res, bit, irq, pos0, pos1, i;
241 u32 val;
242 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
243
244 if (!pp) {
245 BUG();
246 return -EINVAL;
247 }
248
249 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
250 MAX_MSI_IRQS);
251 if (pos0 % no_irqs) {
252 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
253 goto no_valid_irq;
254 }
255 if (no_irqs > 1) {
256 pos1 = find_next_bit(pp->msi_irq_in_use,
257 MAX_MSI_IRQS, pos0);
258 /* there must be nvec number of consecutive free bits */
259 while ((pos1 - pos0) < no_irqs) {
260 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
261 goto no_valid_irq;
262 pos1 = find_next_bit(pp->msi_irq_in_use,
263 MAX_MSI_IRQS, pos0);
264 }
265 }
266
904d0e78
PA		 267 irq = irq_find_mapping(pp->irq_domain, pos0);
268 if (!irq)
f342d940
JH		 269 goto no_valid_irq;
270
be3f48cb
BEN		 271 /*
272 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
273 * descs so there is no need to allocate descs here. We can therefore
274 * assume that if irq_find_mapping above returns non-zero, then the
275 * descs are also successfully allocated.
276 */
277
0b8cfb6a 278 for (i = 0; i < no_irqs; i++) {
be3f48cb
BEN		 279 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
280 clear_irq_range(pp, irq, i, pos0);
281 goto no_valid_irq;
282 }
f342d940 283 set_bit(pos0 + i, pp->msi_irq_in_use);
f342d940
JH		 284 /*Enable corresponding interrupt in MSI interrupt controller */
285 res = ((pos0 + i) / 32) * 12;
286 bit = (pos0 + i) % 32;
287 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
288 val |= 1 << bit;
289 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
f342d940
JH		 290 }
291
292 *pos = pos0;
293 return irq;
294
295no_valid_irq:
296 *pos = pos0;
297 return -ENOSPC;
298}
299
300static void clear_irq(unsigned int irq)
301{
be3f48cb 302 unsigned int pos, nvec;
f342d940
JH		 303 struct msi_desc *msi;
304 struct pcie_port *pp;
904d0e78 305 struct irq_data *data = irq_get_irq_data(irq);
f342d940
JH		 306
307 /* get the port structure */
f7bfca6d 308 msi = irq_data_get_msi(data);
f342d940
JH		 309 pp = sys_to_pcie(msi->dev->bus->sysdata);
310 if (!pp) {
311 BUG();
312 return;
313 }
314
be3f48cb 315 /* undo what was done in assign_irq */
904d0e78 316 pos = data->hwirq;
be3f48cb 317 nvec = 1 << msi->msi_attrib.multiple;
f342d940 318
be3f48cb 319 clear_irq_range(pp, irq, nvec, pos);
f342d940 320
be3f48cb
BEN		 321 /* all irqs cleared; reset attributes */
322 msi->irq = 0;
323 msi->msi_attrib.multiple = 0;
f342d940
JH		 324}
325
326static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
327 struct msi_desc *desc)
328{
329 int irq, pos, msgvec;
330 u16 msg_ctr;
331 struct msi_msg msg;
332 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
333
334 if (!pp) {
335 BUG();
336 return -EINVAL;
337 }
338
339 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
340 &msg_ctr);
341 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
342 if (msgvec == 0)
343 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
344 if (msgvec > 5)
345 msgvec = 0;
346
347 irq = assign_irq((1 << msgvec), desc, &pos);
348 if (irq < 0)
349 return irq;
350
64989e73
BEN		 351 /*
352 * write_msi_msg() will update PCI_MSI_FLAGS so there is
353 * no need to explicitly call pci_write_config_word().
354 */
f342d940
JH		 355 desc->msi_attrib.multiple = msgvec;
356
357 msg.address_lo = virt_to_phys((void *)pp->msi_data);
358 msg.address_hi = 0x0;
359 msg.data = pos;
360 write_msi_msg(irq, &msg);
361
362 return 0;
363}
364
365static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
366{
367 clear_irq(irq);
368}
369
370static struct msi_chip dw_pcie_msi_chip = {
371 .setup_irq = dw_msi_setup_irq,
372 .teardown_irq = dw_msi_teardown_irq,
373};
374
4b1ced84
JH		 375int dw_pcie_link_up(struct pcie_port *pp)
376{
377 if (pp->ops->link_up)
378 return pp->ops->link_up(pp);
379 else
380 return 0;
381}
382
f342d940
JH		 383static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
384 irq_hw_number_t hwirq)
385{
386 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
387 irq_set_chip_data(irq, domain->host_data);
388 set_irq_flags(irq, IRQF_VALID);
389
390 return 0;
391}
392
393static const struct irq_domain_ops msi_domain_ops = {
394 .map = dw_pcie_msi_map,
395};
396
4b1ced84
JH		 397int __init dw_pcie_host_init(struct pcie_port *pp)
398{
399 struct device_node *np = pp->dev->of_node;
4dd964df 400 struct platform_device *pdev = to_platform_device(pp->dev);
4b1ced84
JH		 401 struct of_pci_range range;
402 struct of_pci_range_parser parser;
4dd964df 403 struct resource *cfg_res;
f4c55c5a
KVA		 404 u32 val, na, ns;
405 const __be32 *addrp;
406 int i, index;
407
408 /* Find the address cell size and the number of cells in order to get
409 * the untranslated address.
410 */
411 of_property_read_u32(np, "#address-cells", &na);
412 ns = of_n_size_cells(np);
f342d940 413
4dd964df
KVA		 414 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
415 if (cfg_res) {
416 pp->config.cfg0_size = resource_size(cfg_res)/2;
417 pp->config.cfg1_size = resource_size(cfg_res)/2;
418 pp->cfg0_base = cfg_res->start;
419 pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
f4c55c5a
KVA		 420
421 /* Find the untranslated configuration space address */
422 index = of_property_match_string(np, "reg-names", "config");
423 addrp = of_get_address(np, index, false, false);
424 pp->cfg0_mod_base = of_read_number(addrp, ns);
425 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->config.cfg0_size;
4dd964df
KVA		 426 } else {
427 dev_err(pp->dev, "missing *config* reg space\n");
428 }
429
4b1ced84
JH		 430 if (of_pci_range_parser_init(&parser, np)) {
431 dev_err(pp->dev, "missing ranges property\n");
432 return -EINVAL;
433 }
434
435 /* Get the I/O and memory ranges from DT */
436 for_each_of_pci_range(&parser, &range) {
437 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
438 if (restype == IORESOURCE_IO) {
439 of_pci_range_to_resource(&range, np, &pp->io);
440 pp->io.name = "I/O";
441 pp->io.start = max_t(resource_size_t,
442 PCIBIOS_MIN_IO,
443 range.pci_addr + global_io_offset);
444 pp->io.end = min_t(resource_size_t,
445 IO_SPACE_LIMIT,
446 range.pci_addr + range.size
447 + global_io_offset);
448 pp->config.io_size = resource_size(&pp->io);
449 pp->config.io_bus_addr = range.pci_addr;
fce8591f 450 pp->io_base = range.cpu_addr;
f4c55c5a
KVA		 451
452 /* Find the untranslated IO space address */
453 pp->io_mod_base = of_read_number(parser.range -
454 parser.np + na, ns);
4b1ced84
JH		 455 }
456 if (restype == IORESOURCE_MEM) {
457 of_pci_range_to_resource(&range, np, &pp->mem);
458 pp->mem.name = "MEM";
459 pp->config.mem_size = resource_size(&pp->mem);
460 pp->config.mem_bus_addr = range.pci_addr;
f4c55c5a
KVA		 461
462 /* Find the untranslated MEM space address */
463 pp->mem_mod_base = of_read_number(parser.range -
464 parser.np + na, ns);
4b1ced84
JH		 465 }
466 if (restype == 0) {
467 of_pci_range_to_resource(&range, np, &pp->cfg);
468 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
469 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
4dd964df
KVA		 470 pp->cfg0_base = pp->cfg.start;
471 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
f4c55c5a
KVA		 472
473 /* Find the untranslated configuration space address */
474 pp->cfg0_mod_base = of_read_number(parser.range -
475 parser.np + na, ns);
476 pp->cfg1_mod_base = pp->cfg0_mod_base +
477 pp->config.cfg0_size;
4b1ced84
JH		 478 }
479 }
480
481 if (!pp->dbi_base) {
482 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
483 resource_size(&pp->cfg));
484 if (!pp->dbi_base) {
485 dev_err(pp->dev, "error with ioremap\n");
486 return -ENOMEM;
487 }
488 }
489
4b1ced84
JH		 490 pp->mem_base = pp->mem.start;
491
492 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
493 pp->config.cfg0_size);
494 if (!pp->va_cfg0_base) {
495 dev_err(pp->dev, "error with ioremap in function\n");
496 return -ENOMEM;
497 }
498 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
499 pp->config.cfg1_size);
500 if (!pp->va_cfg1_base) {
501 dev_err(pp->dev, "error with ioremap\n");
502 return -ENOMEM;
503 }
504
505 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
506 dev_err(pp->dev, "Failed to parse the number of lanes\n");
507 return -EINVAL;
508 }
509
f342d940 510 if (IS_ENABLED(CONFIG_PCI_MSI)) {
904d0e78 511 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
f342d940
JH		 512 MAX_MSI_IRQS, &msi_domain_ops,
513 &dw_pcie_msi_chip);
904d0e78 514 if (!pp->irq_domain) {
f342d940
JH		 515 dev_err(pp->dev, "irq domain init failed\n");
516 return -ENXIO;
517 }
518
904d0e78
PA		 519 for (i = 0; i < MAX_MSI_IRQS; i++)
520 irq_create_mapping(pp->irq_domain, i);
f342d940
JH		 521 }
522
4b1ced84
JH		 523 if (pp->ops->host_init)
524 pp->ops->host_init(pp);
525
526 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
527
528 /* program correct class for RC */
529 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
530
531 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
532 val |= PORT_LOGIC_SPEED_CHANGE;
533 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
534
535 dw_pci.nr_controllers = 1;
536 dw_pci.private_data = (void **)&pp;
537
804f57b1 538 pci_common_init_dev(pp->dev, &dw_pci);
4b1ced84
JH		 539 pci_assign_unassigned_resources();
540#ifdef CONFIG_PCI_DOMAINS
541 dw_pci.domain++;
542#endif
543
544 return 0;
545}
546
547static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
340cba60 548{
340cba60 549 /* Program viewport 0 : OUTBOUND : CFG0 */
f7b7868c
SJ		 550 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
551 PCIE_ATU_VIEWPORT);
f4c55c5a
KVA		 552 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
553 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
554 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->config.cfg0_size - 1,
f7b7868c
SJ		 555 PCIE_ATU_LIMIT);
556 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
557 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
558 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
559 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 560}
561
4b1ced84 562static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
340cba60 563{
340cba60 564 /* Program viewport 1 : OUTBOUND : CFG1 */
f7b7868c
SJ		 565 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
566 PCIE_ATU_VIEWPORT);
567 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
f4c55c5a
KVA		 568 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
569 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
570 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->config.cfg1_size - 1,
f7b7868c
SJ		 571 PCIE_ATU_LIMIT);
572 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
573 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
a19f88bd 574 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 575}
576
4b1ced84 577static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
340cba60 578{
340cba60 579 /* Program viewport 0 : OUTBOUND : MEM */
f7b7868c
SJ		 580 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
581 PCIE_ATU_VIEWPORT);
582 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
f4c55c5a
KVA		 583 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
584 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
585 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->config.mem_size - 1,
f7b7868c
SJ		 586 PCIE_ATU_LIMIT);
587 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 588 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
f7b7868c 589 PCIE_ATU_UPPER_TARGET);
a19f88bd 590 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 591}
592
4b1ced84 593static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
340cba60 594{
340cba60 595 /* Program viewport 1 : OUTBOUND : IO */
f7b7868c
SJ		 596 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
597 PCIE_ATU_VIEWPORT);
598 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
f4c55c5a
KVA		 599 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
600 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
601 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->config.io_size - 1,
f7b7868c
SJ		 602 PCIE_ATU_LIMIT);
603 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 604 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
f7b7868c 605 PCIE_ATU_UPPER_TARGET);
a19f88bd 606 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 607}
608
4b1ced84 609static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 610 u32 devfn, int where, int size, u32 *val)
611{
612 int ret = PCIBIOS_SUCCESSFUL;
613 u32 address, busdev;
614
615 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
616 PCIE_ATU_FUNC(PCI_FUNC(devfn));
617 address = where & ~0x3;
618
619 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 620 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 621 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
622 val);
4b1ced84 623 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 624 } else {
4b1ced84 625 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 626 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
627 val);
4b1ced84 628 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 629 }
630
631 return ret;
632}
633
4b1ced84 634static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 635 u32 devfn, int where, int size, u32 val)
636{
637 int ret = PCIBIOS_SUCCESSFUL;
638 u32 address, busdev;
639
640 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
641 PCIE_ATU_FUNC(PCI_FUNC(devfn));
642 address = where & ~0x3;
643
644 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 645 dw_pcie_prog_viewport_cfg0(pp, busdev);
a01ef59e
PA		 646 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
647 val);
4b1ced84 648 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 649 } else {
4b1ced84 650 dw_pcie_prog_viewport_cfg1(pp, busdev);
a01ef59e
PA		 651 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
652 val);
4b1ced84 653 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 654 }
655
656 return ret;
657}
658
4b1ced84 659static int dw_pcie_valid_config(struct pcie_port *pp,
340cba60
JH		 660 struct pci_bus *bus, int dev)
661{
662 /* If there is no link, then there is no device */
663 if (bus->number != pp->root_bus_nr) {
4b1ced84 664 if (!dw_pcie_link_up(pp))
340cba60
JH		 665 return 0;
666 }
667
668 /* access only one slot on each root port */
669 if (bus->number == pp->root_bus_nr && dev > 0)
670 return 0;
671
672 /*
673 * do not read more than one device on the bus directly attached
674 * to RC's (Virtual Bridge's) DS side.
675 */
676 if (bus->primary == pp->root_bus_nr && dev > 0)
677 return 0;
678
679 return 1;
680}
681
4b1ced84 682static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
340cba60
JH		 683 int size, u32 *val)
684{
685 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 686 int ret;
687
688 if (!pp) {
689 BUG();
690 return -EINVAL;
691 }
692
4b1ced84 693 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
340cba60
JH		 694 *val = 0xffffffff;
695 return PCIBIOS_DEVICE_NOT_FOUND;
696 }
697
340cba60 698 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 699 if (pp->ops->rd_other_conf)
700 ret = pp->ops->rd_other_conf(pp, bus, devfn,
701 where, size, val);
702 else
703 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
340cba60
JH		 704 where, size, val);
705 else
4b1ced84 706 ret = dw_pcie_rd_own_conf(pp, where, size, val);
340cba60
JH		 707
708 return ret;
709}
710
4b1ced84 711static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
340cba60
JH		 712 int where, int size, u32 val)
713{
714 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 715 int ret;
716
717 if (!pp) {
718 BUG();
719 return -EINVAL;
720 }
721
4b1ced84 722 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
340cba60
JH		 723 return PCIBIOS_DEVICE_NOT_FOUND;
724
340cba60 725 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 726 if (pp->ops->wr_other_conf)
727 ret = pp->ops->wr_other_conf(pp, bus, devfn,
728 where, size, val);
729 else
730 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
340cba60
JH		 731 where, size, val);
732 else
4b1ced84 733 ret = dw_pcie_wr_own_conf(pp, where, size, val);
340cba60
JH		 734
735 return ret;
736}
737
4b1ced84
JH		 738static struct pci_ops dw_pcie_ops = {
739 .read = dw_pcie_rd_conf,
740 .write = dw_pcie_wr_conf,
340cba60
JH		 741};
742
73e40850 743static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
4b1ced84
JH		 744{
745 struct pcie_port *pp;
746
747 pp = sys_to_pcie(sys);
748
749 if (!pp)
750 return 0;
751
752 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
753 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
fce8591f 754 pci_ioremap_io(global_io_offset, pp->io_base);
4b1ced84
JH		 755 global_io_offset += SZ_64K;
756 pci_add_resource_offset(&sys->resources, &pp->io,
757 sys->io_offset);
758 }
759
760 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
761 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
762
763 return 1;
764}
765
73e40850 766static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
340cba60
JH		 767{
768 struct pci_bus *bus;
769 struct pcie_port *pp = sys_to_pcie(sys);
770
771 if (pp) {
772 pp->root_bus_nr = sys->busnr;
804f57b1 773 bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
340cba60
JH		 774 sys, &sys->resources);
775 } else {
776 bus = NULL;
777 BUG();
778 }
779
780 return bus;
781}
782
73e40850 783static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
340cba60
JH		 784{
785 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
804f57b1 786 int irq;
340cba60 787
804f57b1
LS		 788 irq = of_irq_parse_and_map_pci(dev, slot, pin);
789 if (!irq)
790 irq = pp->irq;
340cba60 791
804f57b1 792 return irq;
340cba60
JH		 793}
794
f342d940
JH		 795static void dw_pcie_add_bus(struct pci_bus *bus)
796{
797 if (IS_ENABLED(CONFIG_PCI_MSI)) {
798 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
799
800 dw_pcie_msi_chip.dev = pp->dev;
801 bus->msi = &dw_pcie_msi_chip;
802 }
803}
804
4b1ced84
JH		 805static struct hw_pci dw_pci = {
806 .setup = dw_pcie_setup,
807 .scan = dw_pcie_scan_bus,
808 .map_irq = dw_pcie_map_irq,
f342d940 809 .add_bus = dw_pcie_add_bus,
340cba60
JH		 810};
811
4b1ced84 812void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60
JH		 813{
814 struct pcie_port_info *config = &pp->config;
340cba60
JH		 815 u32 val;
816 u32 membase;
817 u32 memlimit;
818
66c5c34b 819 /* set the number of lanes */
f7b7868c 820 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
340cba60 821 val &= ~PORT_LINK_MODE_MASK;
4b1ced84
JH		 822 switch (pp->lanes) {
823 case 1:
824 val |= PORT_LINK_MODE_1_LANES;
825 break;
826 case 2:
827 val |= PORT_LINK_MODE_2_LANES;
828 break;
829 case 4:
830 val |= PORT_LINK_MODE_4_LANES;
831 break;
832 }
f7b7868c 833 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
340cba60
JH		 834
835 /* set link width speed control register */
f7b7868c 836 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
340cba60 837 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
4b1ced84
JH		 838 switch (pp->lanes) {
839 case 1:
840 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
841 break;
842 case 2:
843 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
844 break;
845 case 4:
846 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
847 break;
848 }
f7b7868c 849 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60
JH		 850
851 /* setup RC BARs */
f7b7868c 852 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
dbffdd68 853 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
340cba60
JH		 854
855 /* setup interrupt pins */
f7b7868c 856 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
340cba60
JH		 857 val &= 0xffff00ff;
858 val |= 0x00000100;
f7b7868c 859 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
340cba60
JH		 860
861 /* setup bus numbers */
f7b7868c 862 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
340cba60
JH		 863 val &= 0xff000000;
864 val |= 0x00010100;
f7b7868c 865 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
340cba60
JH		 866
867 /* setup memory base, memory limit */
868 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
869 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
870 val = memlimit | membase;
f7b7868c 871 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
340cba60
JH		 872
873 /* setup command register */
f7b7868c 874 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
340cba60
JH		 875 val &= 0xffff0000;
876 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
877 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
f7b7868c 878 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
340cba60 879}
340cba60
JH		 880
881MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
4b1ced84 882MODULE_DESCRIPTION("Designware PCIe host controller driver");
340cba60 883MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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