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ARM/PCI: Replace pci_sys_data->align_resource with global function pointer
[deliverable/linux.git] / drivers / pci / host / pcie-designware.c
CommitLineData
340cba60 1/*
4b1ced84 2 * Synopsys Designware PCIe host controller driver
340cba60
JH		 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
f342d940
JH		 14#include <linux/irq.h>
15#include <linux/irqdomain.h>
340cba60 16#include <linux/kernel.h>
340cba60 17#include <linux/module.h>
f342d940 18#include <linux/msi.h>
340cba60 19#include <linux/of_address.h>
804f57b1 20#include <linux/of_pci.h>
340cba60
JH		 21#include <linux/pci.h>
22#include <linux/pci_regs.h>
4dd964df 23#include <linux/platform_device.h>
340cba60
JH		 24#include <linux/types.h>
25
4b1ced84 26#include "pcie-designware.h"
340cba60
JH		 27
28/* Synopsis specific PCIE configuration registers */
29#define PCIE_PORT_LINK_CONTROL 0x710
30#define PORT_LINK_MODE_MASK (0x3f << 16)
4b1ced84
JH		 31#define PORT_LINK_MODE_1_LANES (0x1 << 16)
32#define PORT_LINK_MODE_2_LANES (0x3 << 16)
340cba60 33#define PORT_LINK_MODE_4_LANES (0x7 << 16)
5b0f0738 34#define PORT_LINK_MODE_8_LANES (0xf << 16)
340cba60
JH		 35
36#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
37#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
ed8b472d 38#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
4b1ced84
JH		 39#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
40#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
41#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
5b0f0738 42#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
340cba60
JH		 43
44#define PCIE_MSI_ADDR_LO 0x820
45#define PCIE_MSI_ADDR_HI 0x824
46#define PCIE_MSI_INTR0_ENABLE 0x828
47#define PCIE_MSI_INTR0_MASK 0x82C
48#define PCIE_MSI_INTR0_STATUS 0x830
49
50#define PCIE_ATU_VIEWPORT 0x900
51#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
52#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
53#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
54#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
55#define PCIE_ATU_CR1 0x904
56#define PCIE_ATU_TYPE_MEM (0x0 << 0)
57#define PCIE_ATU_TYPE_IO (0x2 << 0)
58#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
59#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
60#define PCIE_ATU_CR2 0x908
61#define PCIE_ATU_ENABLE (0x1 << 31)
62#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
63#define PCIE_ATU_LOWER_BASE 0x90C
64#define PCIE_ATU_UPPER_BASE 0x910
65#define PCIE_ATU_LIMIT 0x914
66#define PCIE_ATU_LOWER_TARGET 0x918
67#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
68#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
69#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
70#define PCIE_ATU_UPPER_TARGET 0x91C
71
4b1ced84
JH		 72static struct hw_pci dw_pci;
73
73e40850 74static unsigned long global_io_offset;
340cba60
JH		 75
76static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
77{
84a263f3
LS		 78 BUG_ON(!sys->private_data);
79
340cba60
JH		 80 return sys->private_data;
81}
82
4c45852f 83int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
340cba60 84{
b6b18f58
GP		 85 if ((uintptr_t)addr & (size - 1)) {
86 *val = 0;
87 return PCIBIOS_BAD_REGISTER_NUMBER;
88 }
89
c003ca99
GP		 90 if (size == 4)
91 *val = readl(addr);
340cba60 92 else if (size == 2)
4c45852f 93 *val = readw(addr);
c003ca99 94 else if (size == 1)
4c45852f 95 *val = readb(addr);
c003ca99
GP		 96 else {
97 *val = 0;
340cba60 98 return PCIBIOS_BAD_REGISTER_NUMBER;
c003ca99 99 }
340cba60
JH		 100
101 return PCIBIOS_SUCCESSFUL;
102}
103
4c45852f 104int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
340cba60 105{
b6b18f58
GP		 106 if ((uintptr_t)addr & (size - 1))
107 return PCIBIOS_BAD_REGISTER_NUMBER;
108
340cba60
JH		 109 if (size == 4)
110 writel(val, addr);
111 else if (size == 2)
4c45852f 112 writew(val, addr);
340cba60 113 else if (size == 1)
4c45852f 114 writeb(val, addr);
340cba60
JH		 115 else
116 return PCIBIOS_BAD_REGISTER_NUMBER;
117
118 return PCIBIOS_SUCCESSFUL;
119}
120
f7b7868c 121static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
340cba60 122{
4b1ced84 123 if (pp->ops->readl_rc)
f7b7868c 124 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
4b1ced84 125 else
f7b7868c 126 *val = readl(pp->dbi_base + reg);
340cba60
JH		 127}
128
f7b7868c 129static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
340cba60 130{
4b1ced84 131 if (pp->ops->writel_rc)
f7b7868c 132 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
4b1ced84 133 else
f7b7868c 134 writel(val, pp->dbi_base + reg);
340cba60
JH		 135}
136
73e40850
BH		 137static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
138 u32 *val)
340cba60
JH		 139{
140 int ret;
141
4b1ced84
JH		 142 if (pp->ops->rd_own_conf)
143 ret = pp->ops->rd_own_conf(pp, where, size, val);
144 else
4c45852f 145 ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
4b1ced84 146
340cba60
JH		 147 return ret;
148}
149
73e40850
BH		 150static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
151 u32 val)
340cba60
JH		 152{
153 int ret;
154
4b1ced84
JH		 155 if (pp->ops->wr_own_conf)
156 ret = pp->ops->wr_own_conf(pp, where, size, val);
157 else
4c45852f 158 ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
4b1ced84 159
340cba60
JH		 160 return ret;
161}
162
63503c87
JZ		 163static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
164 int type, u64 cpu_addr, u64 pci_addr, u32 size)
165{
166 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
167 PCIE_ATU_VIEWPORT);
168 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
169 dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
170 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
171 PCIE_ATU_LIMIT);
172 dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
173 dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
174 dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
175 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
176}
177
f342d940
JH		 178static struct irq_chip dw_msi_irq_chip = {
179 .name = "PCI-MSI",
280510f1
TG		 180 .irq_enable = pci_msi_unmask_irq,
181 .irq_disable = pci_msi_mask_irq,
182 .irq_mask = pci_msi_mask_irq,
183 .irq_unmask = pci_msi_unmask_irq,
f342d940
JH		 184};
185
186/* MSI int handler */
7f4f16ee 187irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
f342d940
JH		 188{
189 unsigned long val;
904d0e78 190 int i, pos, irq;
7f4f16ee 191 irqreturn_t ret = IRQ_NONE;
f342d940
JH		 192
193 for (i = 0; i < MAX_MSI_CTRLS; i++) {
194 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
195 (u32 *)&val);
196 if (val) {
7f4f16ee 197 ret = IRQ_HANDLED;
f342d940
JH		 198 pos = 0;
199 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
904d0e78
PA		 200 irq = irq_find_mapping(pp->irq_domain,
201 i * 32 + pos);
ca165892
HH		 202 dw_pcie_wr_own_conf(pp,
203 PCIE_MSI_INTR0_STATUS + i * 12,
204 4, 1 << pos);
904d0e78 205 generic_handle_irq(irq);
f342d940
JH		 206 pos++;
207 }
208 }
f342d940 209 }
7f4f16ee
LS		 210
211 return ret;
f342d940
JH		 212}
213
214void dw_pcie_msi_init(struct pcie_port *pp)
215{
c8947fbb
LS		 216 u64 msi_target;
217
f342d940 218 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
c8947fbb 219 msi_target = virt_to_phys((void *)pp->msi_data);
f342d940
JH		 220
221 /* program the msi_data */
222 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
c8947fbb
LS		 223 (u32)(msi_target & 0xffffffff));
224 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
225 (u32)(msi_target >> 32 & 0xffffffff));
f342d940
JH		 226}
227
2f37c5a8
MK		 228static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
229{
230 unsigned int res, bit, val;
231
232 res = (irq / 32) * 12;
233 bit = irq % 32;
234 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
235 val &= ~(1 << bit);
236 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
237}
238
be3f48cb 239static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
58275f2f 240 unsigned int nvec, unsigned int pos)
be3f48cb 241{
2f37c5a8 242 unsigned int i;
be3f48cb 243
0b8cfb6a 244 for (i = 0; i < nvec; i++) {
be3f48cb 245 irq_set_msi_desc_off(irq_base, i, NULL);
58275f2f 246 /* Disable corresponding interrupt on MSI controller */
2f37c5a8
MK		 247 if (pp->ops->msi_clear_irq)
248 pp->ops->msi_clear_irq(pp, pos + i);
249 else
250 dw_pcie_msi_clear_irq(pp, pos + i);
be3f48cb 251 }
c8df6ac9
LS		 252
253 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
be3f48cb
BEN		 254}
255
2f37c5a8
MK		 256static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
257{
258 unsigned int res, bit, val;
259
260 res = (irq / 32) * 12;
261 bit = irq % 32;
262 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
263 val |= 1 << bit;
264 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
265}
266
f342d940
JH		 267static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
268{
c8df6ac9 269 int irq, pos0, i;
e39758e0 270 struct pcie_port *pp = sys_to_pcie(msi_desc_to_pci_sysdata(desc));
f342d940 271
c8df6ac9
LS		 272 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
273 order_base_2(no_irqs));
274 if (pos0 < 0)
275 goto no_valid_irq;
f342d940 276
904d0e78
PA		 277 irq = irq_find_mapping(pp->irq_domain, pos0);
278 if (!irq)
f342d940
JH		 279 goto no_valid_irq;
280
be3f48cb
BEN		 281 /*
282 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
283 * descs so there is no need to allocate descs here. We can therefore
284 * assume that if irq_find_mapping above returns non-zero, then the
285 * descs are also successfully allocated.
286 */
287
0b8cfb6a 288 for (i = 0; i < no_irqs; i++) {
be3f48cb
BEN		 289 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
290 clear_irq_range(pp, irq, i, pos0);
291 goto no_valid_irq;
292 }
f342d940 293 /*Enable corresponding interrupt in MSI interrupt controller */
2f37c5a8
MK		 294 if (pp->ops->msi_set_irq)
295 pp->ops->msi_set_irq(pp, pos0 + i);
296 else
297 dw_pcie_msi_set_irq(pp, pos0 + i);
f342d940
JH		 298 }
299
300 *pos = pos0;
79707374
LS		 301 desc->nvec_used = no_irqs;
302 desc->msi_attrib.multiple = order_base_2(no_irqs);
303
f342d940
JH		 304 return irq;
305
306no_valid_irq:
307 *pos = pos0;
308 return -ENOSPC;
309}
310
ea643e1a 311static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
f342d940 312{
f342d940 313 struct msi_msg msg;
c8947fbb 314 u64 msi_target;
f342d940 315
450e344e 316 if (pp->ops->get_msi_addr)
c8947fbb 317 msi_target = pp->ops->get_msi_addr(pp);
2f37c5a8 318 else
c8947fbb
LS		 319 msi_target = virt_to_phys((void *)pp->msi_data);
320
321 msg.address_lo = (u32)(msi_target & 0xffffffff);
322 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
24832b4d
ML		 323
324 if (pp->ops->get_msi_data)
325 msg.data = pp->ops->get_msi_data(pp, pos);
326 else
327 msg.data = pos;
328
83a18912 329 pci_write_msi_msg(irq, &msg);
ea643e1a
LS		 330}
331
332static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
333 struct msi_desc *desc)
334{
335 int irq, pos;
336 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
337
338 if (desc->msi_attrib.is_msix)
339 return -EINVAL;
340
341 irq = assign_irq(1, desc, &pos);
342 if (irq < 0)
343 return irq;
344
345 dw_msi_setup_msg(pp, irq, pos);
f342d940
JH		 346
347 return 0;
348}
349
79707374
LS		 350static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
351 int nvec, int type)
352{
353#ifdef CONFIG_PCI_MSI
354 int irq, pos;
355 struct msi_desc *desc;
356 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
357
358 /* MSI-X interrupts are not supported */
359 if (type == PCI_CAP_ID_MSIX)
360 return -EINVAL;
361
362 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
363 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
364
365 irq = assign_irq(nvec, desc, &pos);
366 if (irq < 0)
367 return irq;
368
369 dw_msi_setup_msg(pp, irq, pos);
370
371 return 0;
372#else
373 return -EINVAL;
374#endif
375}
376
c2791b80 377static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
f342d940 378{
91f8ae82 379 struct irq_data *data = irq_get_irq_data(irq);
c391f262 380 struct msi_desc *msi = irq_data_get_msi_desc(data);
e39758e0 381 struct pcie_port *pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
91f8ae82
LS		 382
383 clear_irq_range(pp, irq, 1, data->hwirq);
f342d940
JH		 384}
385
c2791b80 386static struct msi_controller dw_pcie_msi_chip = {
f342d940 387 .setup_irq = dw_msi_setup_irq,
79707374 388 .setup_irqs = dw_msi_setup_irqs,
f342d940
JH		 389 .teardown_irq = dw_msi_teardown_irq,
390};
391
4b1ced84
JH		 392int dw_pcie_link_up(struct pcie_port *pp)
393{
394 if (pp->ops->link_up)
395 return pp->ops->link_up(pp);
396 else
397 return 0;
398}
399
f342d940
JH		 400static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
401 irq_hw_number_t hwirq)
402{
403 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
404 irq_set_chip_data(irq, domain->host_data);
f342d940
JH		 405
406 return 0;
407}
408
409static const struct irq_domain_ops msi_domain_ops = {
410 .map = dw_pcie_msi_map,
411};
412
a43f32d6 413int dw_pcie_host_init(struct pcie_port *pp)
4b1ced84
JH		 414{
415 struct device_node *np = pp->dev->of_node;
4dd964df 416 struct platform_device *pdev = to_platform_device(pp->dev);
4dd964df 417 struct resource *cfg_res;
9cdce1cd
ZW		 418 u32 val;
419 int i, ret;
0021d22b
ZW		 420 LIST_HEAD(res);
421 struct resource_entry *win;
f342d940 422
4dd964df
KVA		 423 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
424 if (cfg_res) {
adf70fc0
PA		 425 pp->cfg0_size = resource_size(cfg_res)/2;
426 pp->cfg1_size = resource_size(cfg_res)/2;
4dd964df 427 pp->cfg0_base = cfg_res->start;
adf70fc0 428 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
0f414212 429 } else if (!pp->va_cfg0_base) {
4dd964df
KVA		 430 dev_err(pp->dev, "missing *config* reg space\n");
431 }
432
0021d22b
ZW		 433 ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
434 if (ret)
435 return ret;
4b1ced84
JH		 436
437 /* Get the I/O and memory ranges from DT */
0021d22b
ZW		 438 resource_list_for_each_entry(win, &res) {
439 switch (resource_type(win->res)) {
440 case IORESOURCE_IO:
441 pp->io = win->res;
442 pp->io->name = "I/O";
443 pp->io_size = resource_size(pp->io);
444 pp->io_bus_addr = pp->io->start - win->offset;
445 pp->io->start = max_t(resource_size_t, PCIBIOS_MIN_IO,
446 pp->io_bus_addr +
447 global_io_offset);
448 pp->io->end = min_t(resource_size_t, IO_SPACE_LIMIT,
449 pp->io_bus_addr + pp->io_size +
450 global_io_offset - 1);
451 pp->io_base = pp->io->start;
452 pp->io_base_tmp = pp->io->start;
453 break;
454 case IORESOURCE_MEM:
455 pp->mem = win->res;
456 pp->mem->name = "MEM";
457 pp->mem_size = resource_size(pp->mem);
458 pp->mem_bus_addr = pp->mem->start - win->offset;
459 break;
460 case 0:
461 pp->cfg = win->res;
462 pp->cfg0_size = resource_size(pp->cfg)/2;
463 pp->cfg1_size = resource_size(pp->cfg)/2;
464 pp->cfg0_base = pp->cfg->start;
465 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
466 break;
467 case IORESOURCE_BUS:
468 pp->busn = win->res;
469 break;
470 default:
471 continue;
4b1ced84 472 }
4f2ebe00
LS		 473 }
474
4b1ced84 475 if (!pp->dbi_base) {
0021d22b
ZW		 476 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
477 resource_size(pp->cfg));
4b1ced84
JH		 478 if (!pp->dbi_base) {
479 dev_err(pp->dev, "error with ioremap\n");
480 return -ENOMEM;
481 }
482 }
483
0021d22b 484 pp->mem_base = pp->mem->start;
4b1ced84 485
4b1ced84 486 if (!pp->va_cfg0_base) {
b14a3d17 487 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
adf70fc0 488 pp->cfg0_size);
b14a3d17
MK		 489 if (!pp->va_cfg0_base) {
490 dev_err(pp->dev, "error with ioremap in function\n");
491 return -ENOMEM;
492 }
4b1ced84 493 }
b14a3d17 494
4b1ced84 495 if (!pp->va_cfg1_base) {
b14a3d17 496 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
adf70fc0 497 pp->cfg1_size);
b14a3d17
MK		 498 if (!pp->va_cfg1_base) {
499 dev_err(pp->dev, "error with ioremap\n");
500 return -ENOMEM;
501 }
4b1ced84
JH		 502 }
503
907fce09
GP		 504 ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
505 if (ret)
506 pp->lanes = 0;
4b1ced84 507
f342d940 508 if (IS_ENABLED(CONFIG_PCI_MSI)) {
b14a3d17
MK		 509 if (!pp->ops->msi_host_init) {
510 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
511 MAX_MSI_IRQS, &msi_domain_ops,
512 &dw_pcie_msi_chip);
513 if (!pp->irq_domain) {
514 dev_err(pp->dev, "irq domain init failed\n");
515 return -ENXIO;
516 }
f342d940 517
b14a3d17
MK		 518 for (i = 0; i < MAX_MSI_IRQS; i++)
519 irq_create_mapping(pp->irq_domain, i);
520 } else {
521 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
522 if (ret < 0)
523 return ret;
524 }
f342d940
JH		 525 }
526
4b1ced84
JH		 527 if (pp->ops->host_init)
528 pp->ops->host_init(pp);
529
2d91b491
JZ		 530 if (!pp->ops->rd_other_conf)
531 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
9cdce1cd 532 PCIE_ATU_TYPE_MEM, pp->mem_base,
2d91b491
JZ		 533 pp->mem_bus_addr, pp->mem_size);
534
4b1ced84
JH		 535 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
536
537 /* program correct class for RC */
538 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
539
540 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
541 val |= PORT_LOGIC_SPEED_CHANGE;
542 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
543
0815f957
YW		 544#ifdef CONFIG_PCI_MSI
545 dw_pcie_msi_chip.dev = pp->dev;
0815f957
YW		 546#endif
547
4b1ced84
JH		 548 dw_pci.nr_controllers = 1;
549 dw_pci.private_data = (void **)&pp;
550
804f57b1 551 pci_common_init_dev(pp->dev, &dw_pci);
4b1ced84
JH		 552
553 return 0;
554}
555
4b1ced84 556static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 557 u32 devfn, int where, int size, u32 *val)
558{
2d91b491 559 int ret, type;
4c45852f 560 u32 busdev, cfg_size;
2d91b491
JZ		 561 u64 cpu_addr;
562 void __iomem *va_cfg_base;
340cba60
JH		 563
564 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
565 PCIE_ATU_FUNC(PCI_FUNC(devfn));
340cba60
JH		 566
567 if (bus->parent->number == pp->root_bus_nr) {
2d91b491 568 type = PCIE_ATU_TYPE_CFG0;
9cdce1cd 569 cpu_addr = pp->cfg0_base;
2d91b491
JZ		 570 cfg_size = pp->cfg0_size;
571 va_cfg_base = pp->va_cfg0_base;
340cba60 572 } else {
2d91b491 573 type = PCIE_ATU_TYPE_CFG1;
9cdce1cd 574 cpu_addr = pp->cfg1_base;
2d91b491
JZ		 575 cfg_size = pp->cfg1_size;
576 va_cfg_base = pp->va_cfg1_base;
340cba60
JH		 577 }
578
2d91b491
JZ		 579 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
580 type, cpu_addr,
581 busdev, cfg_size);
4c45852f 582 ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
2d91b491 583 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
9cdce1cd 584 PCIE_ATU_TYPE_IO, pp->io_base,
2d91b491
JZ		 585 pp->io_bus_addr, pp->io_size);
586
340cba60
JH		 587 return ret;
588}
589
4b1ced84 590static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 591 u32 devfn, int where, int size, u32 val)
592{
2d91b491 593 int ret, type;
4c45852f 594 u32 busdev, cfg_size;
2d91b491
JZ		 595 u64 cpu_addr;
596 void __iomem *va_cfg_base;
340cba60
JH		 597
598 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
599 PCIE_ATU_FUNC(PCI_FUNC(devfn));
340cba60
JH		 600
601 if (bus->parent->number == pp->root_bus_nr) {
2d91b491 602 type = PCIE_ATU_TYPE_CFG0;
9cdce1cd 603 cpu_addr = pp->cfg0_base;
2d91b491
JZ		 604 cfg_size = pp->cfg0_size;
605 va_cfg_base = pp->va_cfg0_base;
340cba60 606 } else {
2d91b491 607 type = PCIE_ATU_TYPE_CFG1;
9cdce1cd 608 cpu_addr = pp->cfg1_base;
2d91b491
JZ		 609 cfg_size = pp->cfg1_size;
610 va_cfg_base = pp->va_cfg1_base;
340cba60
JH		 611 }
612
2d91b491
JZ		 613 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
614 type, cpu_addr,
615 busdev, cfg_size);
4c45852f 616 ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
2d91b491 617 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
9cdce1cd 618 PCIE_ATU_TYPE_IO, pp->io_base,
2d91b491
JZ		 619 pp->io_bus_addr, pp->io_size);
620
340cba60
JH		 621 return ret;
622}
623
4b1ced84 624static int dw_pcie_valid_config(struct pcie_port *pp,
340cba60
JH		 625 struct pci_bus *bus, int dev)
626{
627 /* If there is no link, then there is no device */
628 if (bus->number != pp->root_bus_nr) {
4b1ced84 629 if (!dw_pcie_link_up(pp))
340cba60
JH		 630 return 0;
631 }
632
633 /* access only one slot on each root port */
634 if (bus->number == pp->root_bus_nr && dev > 0)
635 return 0;
636
637 /*
638 * do not read more than one device on the bus directly attached
639 * to RC's (Virtual Bridge's) DS side.
640 */
641 if (bus->primary == pp->root_bus_nr && dev > 0)
642 return 0;
643
644 return 1;
645}
646
4b1ced84 647static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
340cba60
JH		 648 int size, u32 *val)
649{
650 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 651 int ret;
652
4b1ced84 653 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
340cba60
JH		 654 *val = 0xffffffff;
655 return PCIBIOS_DEVICE_NOT_FOUND;
656 }
657
340cba60 658 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 659 if (pp->ops->rd_other_conf)
660 ret = pp->ops->rd_other_conf(pp, bus, devfn,
661 where, size, val);
662 else
663 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
340cba60
JH		 664 where, size, val);
665 else
4b1ced84 666 ret = dw_pcie_rd_own_conf(pp, where, size, val);
340cba60
JH		 667
668 return ret;
669}
670
4b1ced84 671static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
340cba60
JH		 672 int where, int size, u32 val)
673{
674 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
340cba60
JH		 675 int ret;
676
4b1ced84 677 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
340cba60
JH		 678 return PCIBIOS_DEVICE_NOT_FOUND;
679
340cba60 680 if (bus->number != pp->root_bus_nr)
a1c0ae9c
MK		 681 if (pp->ops->wr_other_conf)
682 ret = pp->ops->wr_other_conf(pp, bus, devfn,
683 where, size, val);
684 else
685 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
340cba60
JH		 686 where, size, val);
687 else
4b1ced84 688 ret = dw_pcie_wr_own_conf(pp, where, size, val);
340cba60
JH		 689
690 return ret;
691}
692
4b1ced84
JH		 693static struct pci_ops dw_pcie_ops = {
694 .read = dw_pcie_rd_conf,
695 .write = dw_pcie_wr_conf,
340cba60
JH		 696};
697
73e40850 698static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
4b1ced84
JH		 699{
700 struct pcie_port *pp;
701
702 pp = sys_to_pcie(sys);
703
adf70fc0
PA		 704 if (global_io_offset < SZ_1M && pp->io_size > 0) {
705 sys->io_offset = global_io_offset - pp->io_bus_addr;
9cdce1cd 706 pci_ioremap_io(global_io_offset, pp->io_base_tmp);
4b1ced84 707 global_io_offset += SZ_64K;
0021d22b 708 pci_add_resource_offset(&sys->resources, pp->io,
4b1ced84
JH		 709 sys->io_offset);
710 }
711
0021d22b
ZW		 712 sys->mem_offset = pp->mem->start - pp->mem_bus_addr;
713 pci_add_resource_offset(&sys->resources, pp->mem, sys->mem_offset);
714 pci_add_resource(&sys->resources, pp->busn);
4b1ced84
JH		 715
716 return 1;
717}
718
73e40850 719static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
340cba60
JH		 720{
721 struct pci_bus *bus;
722 struct pcie_port *pp = sys_to_pcie(sys);
723
92483df2 724 pp->root_bus_nr = sys->busnr;
8953aab1
LP		 725
726 if (IS_ENABLED(CONFIG_PCI_MSI))
727 bus = pci_scan_root_bus_msi(pp->dev, sys->busnr, &dw_pcie_ops,
728 sys, &sys->resources,
729 &dw_pcie_msi_chip);
730 else
731 bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
732 sys, &sys->resources);
733
92483df2
LS		 734 if (!bus)
735 return NULL;
736
b14a3d17
MK		 737 if (bus && pp->ops->scan_bus)
738 pp->ops->scan_bus(pp);
739
340cba60
JH		 740 return bus;
741}
742
73e40850 743static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
340cba60
JH		 744{
745 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
804f57b1 746 int irq;
340cba60 747
804f57b1
LS		 748 irq = of_irq_parse_and_map_pci(dev, slot, pin);
749 if (!irq)
750 irq = pp->irq;
340cba60 751
804f57b1 752 return irq;
340cba60
JH		 753}
754
4b1ced84
JH		 755static struct hw_pci dw_pci = {
756 .setup = dw_pcie_setup,
757 .scan = dw_pcie_scan_bus,
758 .map_irq = dw_pcie_map_irq,
340cba60
JH		 759};
760
4b1ced84 761void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60 762{
340cba60
JH		 763 u32 val;
764 u32 membase;
765 u32 memlimit;
766
66c5c34b 767 /* set the number of lanes */
f7b7868c 768 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
340cba60 769 val &= ~PORT_LINK_MODE_MASK;
4b1ced84
JH		 770 switch (pp->lanes) {
771 case 1:
772 val |= PORT_LINK_MODE_1_LANES;
773 break;
774 case 2:
775 val |= PORT_LINK_MODE_2_LANES;
776 break;
777 case 4:
778 val |= PORT_LINK_MODE_4_LANES;
779 break;
5b0f0738
ZW		 780 case 8:
781 val |= PORT_LINK_MODE_8_LANES;
782 break;
907fce09
GP		 783 default:
784 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
785 return;
4b1ced84 786 }
f7b7868c 787 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
340cba60
JH		 788
789 /* set link width speed control register */
f7b7868c 790 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
340cba60 791 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
4b1ced84
JH		 792 switch (pp->lanes) {
793 case 1:
794 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
795 break;
796 case 2:
797 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
798 break;
799 case 4:
800 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
801 break;
5b0f0738
ZW		 802 case 8:
803 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
804 break;
4b1ced84 805 }
f7b7868c 806 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60
JH		 807
808 /* setup RC BARs */
f7b7868c 809 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
dbffdd68 810 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
340cba60
JH		 811
812 /* setup interrupt pins */
f7b7868c 813 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
340cba60
JH		 814 val &= 0xffff00ff;
815 val |= 0x00000100;
f7b7868c 816 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
340cba60
JH		 817
818 /* setup bus numbers */
f7b7868c 819 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
340cba60
JH		 820 val &= 0xff000000;
821 val |= 0x00010100;
f7b7868c 822 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
340cba60
JH		 823
824 /* setup memory base, memory limit */
825 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
adf70fc0 826 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
340cba60 827 val = memlimit | membase;
f7b7868c 828 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
340cba60
JH		 829
830 /* setup command register */
f7b7868c 831 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
340cba60
JH		 832 val &= 0xffff0000;
833 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
834 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
f7b7868c 835 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
340cba60 836}
340cba60
JH		 837
838MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
4b1ced84 839MODULE_DESCRIPTION("Designware PCIe host controller driver");
340cba60 840MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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